Sensor data fusion chiplet architecture

Abstract

An electronic circuit package for data fusion includes a substrate, an interposer disposed on the substrate, and one or more first chiplets disposed on the interposer, the one or more first chiplets operable to perform a first operation. The circuit electronic package includes one or more memory chiplets disposed on an interposer, the one or more memory chiplets being operable to store data. The circuit electronic package includes one or more second chiplets disposed on the interposer, the one or more second chiplets operable to perform a second operation.

Description

Technical Field

[0001] The present invention relates to an electronic circuit package for data fusion, a system for electronic circuit packaging, and a vehicle having an electronic circuit package. Background Technology

[0002] The demand for high-performance computer chips (including integrated circuits (ICs), printed circuit boards (PCBs), and electronic circuit packages) in consumer electronics is increasing. It is common for a single computer chip to perform multiple operations within a computing device. The number of transistors in each computer chip has increased dramatically to provide increasingly higher performance for such complex chips. Current technology prevents transistor size from shrinking further. Therefore, the increase in the number of transistors has resulted in very large computer chips. Typically, this means that modern complex computer chips require two (sometimes even three or four times) the physical space usually allocated to such chips in computer devices. These excessively large and complex computer chips are often more fragile than their simpler counterparts due to the added weight and size they impose on standard electrical connectors and physical fasteners (e.g., screws on a computer device). Therefore, there are physical limitations to how complex computer chips can grow. Further improvements in the capabilities of computer devices and such computer chips remain necessary.

[0003] In the automotive industry, the demands on vehicle processing are also growing exponentially. Current vehicles are expected to capture data from multiple sources, compile this data, and use it to assist the driving experience. This can include adaptive driving features (such as adaptive cruise control, adaptive lighting, automatic windshield wipers, etc.), detection features for autonomous driving, music and other content playback, automatic seat adjustment, and so on. Currently, this is achieved by providing the vehicle with multiple independent computer units, each dedicated to a single task. Current systems are difficult to manage, complex to manufacture, expensive, and require a relatively large amount of power to operate. These problems are exacerbated as vehicles adopt artificial intelligence (AI) models to improve their functionality. To address these issues, vehicle manufacturers are attempting to provide a single computer unit (as described above) using complex computer chips to perform all vehicle functions. However, due to the customized nature of vehicle functions, current complex computer chips cannot provide the expected performance required by next-generation vehicles, partly because of their high power requirements and the limitations on performance improvement due to the complexity of current computer chips.

[0004] Therefore, the industry needs computing means that can efficiently perform the various functions required by next-generation vehicles. The purpose of this invention is to solve the above-mentioned problems. Summary of the Invention

[0005] To achieve the above objectives, the present invention provides an electronic circuit device, system, and vehicle for data fusion, as described in the appended claims.

[0006] In a preferred embodiment, an electronic circuit package for data fusion is provided. The electronic circuit package for data fusion includes a substrate, an interposer disposed on the substrate, and one or more first chips disposed on the interposer, the one or more first chips operable to perform a first operation. The package includes one or more memory chips disposed on the interposer, the one or more memory chips operable to store data. The package includes one or more second chips disposed on the interposer, the one or more second chips operable to perform a second operation. By separating multiple operations of a complex chip (e.g., first and second operations) into separate chips dedicated to specific operations, the computing power of each chip can be fully dedicated to its dedicated operation. The advantage of this architecture is that several chips can be combined in a package to avoid poor yield due to the excessive size of a large chip (i.e., a complex chip). Therefore, a chip assembly (or chiplet) is not limited by the computational requirements of multiple operations. This is particularly advantageous in the automotive field, where a vehicle is expected to perform multiple operations, which are typically performed by multiple different complex chips, electronic control units (ECUs), etc. For example, a first-type chiplet can be dedicated to receiving data, while a second-type chiplet can be dedicated to processing data (e.g., sorting data, assigning data to actions, and / or any other processing operations). A first-type chiplet can be manufactured to receive data efficiently (e.g., quickly and with low power consumption). However, a first-type chiplet may have sufficient hardware to process the data. A second-type chiplet can be manufactured to process data efficiently, but may not be efficient at receiving data. Therefore, specific hardware can be dedicated to each type of chiplet to ensure that each chiplet type is as efficient as possible. Because such chipsets need to perform fewer functions, they require fewer resources to manufacture. Therefore, they are easier and cheaper to manufacture, while ensuring that the overall processing system is faster and more efficient. Electronic circuit packages that include multiple chiplet types (i.e., first-type, second-type, and memory chiplets) are advantageous because such packages are not limited by the traditional size requirements of complex chips (e.g., graphics cards, motherboards, and other types of complex chips). Therefore, electronic circuit packages with greater overall processing power than current complex chips can be provided. Integrating data fusion within electronic circuit packaging is advantageous because it allows the fusion of multiple data sources to produce more consistent, accurate, and useful information than that provided by one or more individual (raw) data sources. Fused data is more informative than the original input because it more accurately represents what is happening around the vehicle.

[0007] In one embodiment, the electronic circuit package further includes a first communication infrastructure that couples one or more first chipsets and one or more memory chipsets. The one or more first chipsets may be coupled to the first communication infrastructure in parallel. Alternatively, the one or more first chipsets may be coupled to the first communication infrastructure in series. Advantageously, by placing the first chipsets in parallel with the communication infrastructure, operations performed by the first chipsets (e.g., receiving data) can be performed simultaneously by multiple first chipsets, thus increasing the speed of performing the first operation. Parallel communication with the memory chipsets provides the advantage of unimpeded access to store the actions of the first operation on memory with low latency. By placing the chipsets in series, multiple first chipsets can be arranged such that each operation is performed in series through each of the first chipsets before being stored on the one or more memory chipsets. This provides an arrangement where storage is performed only after the operation is complete, thus reducing the amount of storage required for the entire package.

[0008] In one embodiment, the electronic circuit package further includes a second communication infrastructure that couples one or more memory chips and one or more second chips. The one or more second chips may be coupled to the first communication infrastructure in parallel. Alternatively, the one or more second chips may be coupled to the first communication infrastructure in series. Advantageously, by placing the second chips in parallel with the communication infrastructure data, operations performed by the second chips (e.g., data processing) can be performed simultaneously by providing data from the one or more memory chips to each of the second chips. This reduces overall latency. By placing the second chips in series, multiple second chips can be arranged such that each individual operation is performed in series through each of the second chips before performing a final operation. This is particularly advantageous in scenarios where multiple different types of second operations must be performed consecutively before taking a final action (e.g., sorting multiple different types of data before issuing a request to send a message or activate a device), and it is advantageous to separate each of the second operations into a separate chip to ensure that each of the second chips is manufactured to efficiently perform its dedicated operation.

[0009] In one embodiment, the one or more first chiplets may each include a first processor operable to perform a first operation, wherein the first operation includes receiving data. In one embodiment, it is advantageous that the provided electronic circuit package has dedicated circuitry (one or more first chiplets) to receive data (e.g., raw data, preprocessed data, or a combination thereof) from the automotive system and feed the data into the memory of the electronic circuit package.

[0010] In one embodiment, the data may include internal sensor data captured by the vehicle (e.g., data captured by cameras, radar, microphones, temperature, motion sensors, or any other type of sensor within the vehicle's cabin). The data may include external sensor data captured by the vehicle (e.g., data captured by cameras, radar, LiDAR, infrared, motion, temperature sensors, microphones, or any other type of sensor that captures data from outside the vehicle). The data may include data captured by the vehicle (e.g., not limited to sensor data and including data of sound, video, text, or any other type of information received by the vehicle). The data may include data received from external devices (e.g., data received from user equipment, networks, servers, or any combination thereof communicating with the vehicle). The data may include any combination as described above.

[0011] In one embodiment, sensor data may include video data, radar data, LiDAR data, or any combination thereof. Advantageously, the provided electronic circuitry package can receive a large volume of diverse sensor data. This data is typically continuously collected by the vehicle, and the provided electronic circuitry package, by using one or more dedicated first chips to receive the sensor data, can quickly and efficiently store the data in memory for processing by other circuits or chips. By being able to process this data quickly and efficiently, safe driving is ensured because less data is lost during collection due to system lag.

[0012] In one embodiment, one or more second chips may each include a second processor operable to perform a second operation. The second operation may include classifying received data into one or more categories, one or more data types, or a combination thereof. Advantageously, the provided electronic circuit package can handle large amounts of sensor data because one or more second chips are specifically designed to process (i.e., classify) this data. Therefore, safe driving can be ensured because any actions that may need to be taken due to the received sensor data can be processed more quickly.

[0013] In one implementation, one or more data types may include video data, audio data, text data, radar data, LiDAR data, or any combination thereof. Advantageously, the data can be sorted to determine specific actions the vehicle may need to take. In a non-limiting example, video, radar, and / or LiDAR data may be related to avoiding a vehicle collision due to sensed external conditions. Audio and / or text data may be related to determining whether the vehicle driver is in control of the vehicle.

[0014] In one implementation, one or more categories may include: data including information about the vehicle's user (e.g., personal data, medical data); data including information about the vehicle's status (e.g., speed, location); detection of one or more moving objects outside the vehicle (e.g., other vehicles, pedestrians, animals); detection of one or more fixed objects outside the vehicle (e.g., lampposts, parked vehicles); detection of one or more moving objects inside the vehicle (e.g., users, passengers, user body parts (in case of a medical event / seizure, etc.)); detection of one or more fixed objects inside the vehicle (e.g., detecting when components detach); or any combination of the above. Advantageously, various collisions or other malfunctions can be efficiently and quickly identified to avoid, for example, vehicle collisions.

[0015] In one embodiment, the electronic circuit package may further include one or more third chiplets disposed on an interposer and coupled to a second communication infrastructure. Each of the one or more third chiplets may include a processor operable to perform a third operation. The third operation may include receiving classified data, determining, based on the classified data, the action the package needs to take, and instructing the vehicle to perform that action. Advantageously, providing a separate chiplet with dedicated processing capabilities to determine the required action type allows for more efficient determination of the action to be performed and the type of action to be performed based on the classified data. This further enhances vehicle safety by ensuring no system lag occurs because each operation uses a separate and dedicated chiplet.

[0016] In one implementation, the action includes displaying a message on a user interface, activating or deactivating a mechanical device, activating or deactivating an electrical device, requesting data from a network (e.g., personal data related to the vehicle's driver, such as whether the driver is taking any medications and / or has any specific illness or other medical condition), or any combination thereof. Advantageously, the provided vehicle responds faster than vehicles equipped with multiple complex chips. Furthermore, the provided vehicle can perform multiple operations efficiently and effectively (i.e., a lower failure rate due to the resolution of time lag and therefore the inability to quickly receive and / or process data).

[0017] In one embodiment, the interposer layer may include at least one universal socket operable to receive pins from at least one of one or more first chips, one or more second chips, one or more third chips, and one or more memory chips. At least one of the one or more first chips, one or more second chips, one or more third chips, and one or more memory chips may include pins operable to engage with at least one universal socket. This provides a simplified method for replacing damaged components in electronic circuitry packages compared to current complex chips, in which multiple chips and circuits are soldered onto a circuit board, and therefore the entire chip must be replaced when a component fails. This is advantageous because the replacement costs of complex chips, which typically have higher processing requirements and are vehicle-specific tasks / operations, particularly those in the automotive industry, are high. Therefore, having a universal socket to allow replacement of individual damaged chips rather than the entire circuit is advantageous. Furthermore, the supplied electronic circuitry package can be easily upgraded by replacing chips in the system with newer chips using a "plug-and-play" arrangement. This extends the on-road life of vehicles by allowing older vehicles using previous-generation chips to be easily upgraded to include the most modern chips. By providing a universal socket, small chips from multiple manufacturers can be used in the same electronic circuit package, thereby improving the availability of electronic circuit packages.

[0018] In a preferred embodiment, a system is provided. The system includes a second substrate, a second interposer disposed on the second substrate, and a plurality of electronic circuit packages as defined above. Each of the plurality of electronic circuit packages includes a substrate, an interposer disposed on the substrate, and one or more first chips disposed on the interposer, the one or more first chips operable to perform a first operation. The package includes one or more memory chips disposed on the interposer, the one or more memory chips operable to store data. The package includes one or more second chips disposed on the interposer, the one or more second chips operable to perform a second operation. Advantageously, the plurality of electronic circuit packages can be electronically coupled together and can be separated to perform individual tasks. For example, one electronic circuit package may include the chip type and memory as described above to receive and process sensor data. A second electronic circuit package may include chip types and memory dedicated to different operations. Therefore, each electronic circuit package can be manufactured to efficiently perform its dedicated task. Thus, a system with overall processing power far exceeding that of current complex chips and current computer systems can be provided.

[0019] In a preferred embodiment, a vehicle is provided. The vehicle includes sensors and electronic circuitry packages or systems as defined above. Advantageously, the vehicle can detect more information more quickly (i.e., without hysteresis) and process that data more quickly (i.e., with less hysteresis) to determine what actions need to be taken (if necessary). Therefore, the provided vehicle is more likely to avoid collisions and any other types of accidents and / or malfunctions.

[0020] In one implementation, the sensor includes a radar sensor, a LiDAR sensor, a camera sensor for advanced driver assistance systems (ADAS), or any combination thereof. Attached Figure Description

[0021] The features, aspects and advantages of this disclosure may become more apparent from the following detailed description set forth in conjunction with the accompanying drawings, throughout which the same reference numerals refer to similar elements.

[0022] Figure 1a A top view of a plurality of small chips on a substrate according to the present invention is depicted;

[0023] Figure 1b A side view of a chiplet package on a substrate (chiplet package) according to the present invention is depicted;

[0024] Figure 2 It shows Figure 1a and Figure 1b A detailed top view of multiple chips on a substrate (chiplet package);

[0025] Figure 3 A top view of a chiplet package system according to the present invention is shown; and

[0026] Figure 4 The invention includes Figure 1a , Figure 1b and Figure 2 Chippackaging and Figure 3 Vehicles with small chip packaging systems. Detailed Implementation

[0027] This invention relates to a combination of chiplet packaging (referred to herein as electronic circuit packaging) and data fusion technology, which can provide computing means to efficiently perform a variety of functions required by next-generation automobiles. Figure 1a and Figure 1b A top view and a side view of the chiplet package (electronic circuit package) 100 are depicted. The electronic circuit package 100 is used for data fusion as described below, and can also be a data fusion electronic circuit package. Figure 1aThe substrate 102, the interposer 104, and a plurality of small chips 106a, 106b, 106c, 106d (106a-d) are depicted.

[0028] The substrate 102 is the base material of the electronic circuit package 100. The substrate 102 may be made of a non-conductive material and provides mechanical support and electrical insulation for the interposer 104 and the plurality of chiplets 106a-d. In some embodiments, the substrate 102 may include one or more electrical connectors (e.g., electrically coupling the electronic circuit package 100 to an electronic control unit (ECU) of a vehicle).

[0029] Interposer 104 may be electrical interface wiring between a plurality of chiplets 106a-d, and may also provide electrical interface wiring from electrical components outside the electronic circuit package 100 to the plurality of chiplets 106a-d and from the plurality of chiplets 106a-d to electrical components outside the electronic circuit package 100. Interposer 104 may alternatively or additionally provide electrical interface wiring to one or more electrical connections to substrate 102.

[0030] Each of the chiplets 106a-d is a small integrated circuit (IC), each chiplet including one or more processors, and each chiplet operable to perform a well-defined subset of functions. Each of the chiplets 106a-d is designed to perform a different well-defined subset of functions. Together, the group of chiplets 106a-d performs a complete task typically performed by a single (complex) integrated circuit operable to perform a whole set of functions. For example, a complex integrated circuit can be operated to receive data, store data, receive instructions, and perform actions based on the received data and instructions. An electronic circuit package 100 including chiplets 106a-d can perform the same functions, but instead of performing these functions on a single integrated circuit, it breaks these functions down to individual chiplets 106a. For example, chiplet 106a can be configured to receive data, chiplet 106b can be configured to receive instructions, chiplet 106c can be configured to determine (based on data and instructions) what action needs to be taken, and chiplet 106d can be configured to perform that action. Although... Figure 1a The figure shows four small chips 106a-d, but the present invention is not limited to four small chips, but may include two small chips, three small chips or any number of small chips.

[0031] Electronic circuit package 100 may include multiple small chips corresponding to the number of operations required by the data fusion model. Data fusion is the process of integrating multiple data sources to produce more consistent, accurate, and useful information than that provided by any single (raw) data source. A data fusion model is an arrangement utilizing one or more data fusion processes. Depending on the processing stage at which the fusion occurs, data fusion processes can be classified as low-level, intermediate, or high-level. Low-level data fusion combines several data sources (e.g., sensor data captured by a vehicle, such as video and audio data) to produce new intermediate-level data (e.g., a combination of video details and audio data) that has been fused from the low-level data. The data combined by low-level data fusion can be raw data captured by the vehicle, pre-processed data (e.g., raw data processed by digital signal processing (DSP) operations, text data, any other type of pre-processed data, or any combination thereof). Intermediate data can be fused again to produce new high-level data (e.g., showing only specific colors and specific sound frequency ranges of the fused video and audio data). The fused data can be more informative than the original input because it more accurately represents what is happening around the vehicle. Although three levels (low, medium, and high) are described, the data fusion model can include any number of levels. Electronic circuit package 100 can include at least one chiplet 106a-d for each level. Electronic circuit package 100 can include additional chipslets 106a-d for storage functions (e.g., memory chipslets for storing data and / or instructions).

[0032] In one embodiment, the data collected by one or more first chips 106 may include internal sensor data captured by the vehicle (e.g., data captured by cameras, radar, microphones, temperature, motion sensors, or any other type of sensor within the vehicle's cabin). Data may include external sensor data captured by the vehicle (e.g., data captured by cameras, radar, LiDAR, infrared, motion, temperature sensors, microphones, or any other type of sensor capturing data from outside the vehicle). Data may include data captured by the vehicle (e.g., not limited to sensor data and including data of sound, video, text, or any other type of information received by the vehicle). Data may include data received from external devices (e.g., data received from user equipment, networks, servers, or any combination thereof communicating with the vehicle). Data may include any combination as described above.

[0033] Data fusion processes can be categorized by numerical levels, with lower numbers corresponding to lower-level processing stages and higher numbers corresponding to higher-level processing stages. For example, a level 0 (zero) processing stage might be the source (pre)processing stage. This could be the initial stage (level) for capturing input data (e.g., sensor data captured by a vehicle as described herein). At level 0, preliminary filtering of the input data can be provided. This could include classifying data from multiple sensors (e.g., video sensors, audio sensors, and any other type of sensor) by observation time, reported location, data or sensor type, and consistency of data units. This could also be called signal-level fusion. A level 1 processing stage (i.e., stages higher than level 0) could be an object refinement processing stage. This stage can combine location and identity information from multiple sensors and build a refined attribute database (e.g., identified entities / objects inside or outside the vehicle), (vehicle's) location, (vehicle's) speed, and target trajectory (e.g., where the vehicle should be). This stage could also be called feature-level fusion. A level 2 processing stage (i.e., stages higher than level 1 and level 0) could be context refinement. This stage can filter data to understand the context of detected objects, focusing on relationships between objects and between objects and their environment. This stage can also be called decision-level fusion. The Level 3 processing stage (i.e., stages above Levels 2, 1, and 0) can be threat refinement. At this stage, the current situation (e.g., object / environment) can be extended to the future to describe inferences about threats and weaknesses (e.g., identifying potential collisions or other hazards). At this stage, actions that need to be taken can be determined (as described in more detail herein). This stage can also be called decision-level fusion. The Level 4 processing stage (i.e., stages above Levels 3, 2, 1, and 0) can be process refinement. At this stage, additional processes (e.g., actions or filtering) can be performed to achieve the goal of optimizing the ongoing data fusion process. Electronic circuit package 100 does not necessarily need to employ all of the above levels. Instead, electronic circuit package 100 may utilize two or more levels. If not needed, intermediate levels can be skipped or excluded (e.g., electronic circuit package 100 may utilize only Levels 0 and 3). In one example, the data fusion model could be the JDL (Joint Laboratory Director) model, the DFIG (Data Fusion Information Group) model, or any other suitable data fusion model.

[0034] Interchange layer 104 may be disposed on substrate 102. Electrical connections coupling the interchange layer 104 to substrate 102 may be made by one or more fixed electrical connections (as depicted in 108) or any other suitable type of soldering. This provides a strong physical and electrical bond, ensuring that the interchange layer 104 and substrate 102 are physically stable components. Alternatively, electrical connections coupling the interchange layer 104 and substrate 102 may be made by one or more pins and corresponding sockets as depicted in 110. Pins may form part of the interchange layer 104 and may protrude from the bottom side of the interchange layer to interact with sockets on the top side of substrate 102. Alternatively, the interchange layer 104 may include sockets located on the bottom side of the interchange layer to interact with multiple pins protruding from the top side of substrate 102. Sockets on the bottom side of substrate 102 or interchange layer 104 may be universal sockets operable to receive pins from multiple different arrangements. Compared to current complex chips, this provides a simplified method for replacing components in electronic circuitry packages, where multiple chips and circuits are soldered onto a circuit board, and therefore the entire chip must be replaced when a component fails. This is advantageous because replacing complex chips, especially those in the automotive industry, which typically have higher processing requirements and are vehicle-specific for their tasks / operations, is very costly. Therefore, having a universal socket to allow replacement of individual damaged chips rather than the entire circuit is advantageous. Furthermore, the supplied electronic circuitry package can be easily upgraded by replacing the chips in the system with newer ones using a "plug-and-play" arrangement. This extends the on-road life of vehicles by allowing older vehicles using previous-generation chips to be easily upgraded to include the most modern chips.

[0035] Multiple chips 106a-d may be disposed on the interposer 104. Electrical connections coupling the chips 106a-d to the interposer 104 (and thus to each other and to the substrate 102) may be made of one or more fixed electrical connections (e.g., any suitable type of solder or other type of fixed electrical connection) as depicted in 108. This provides a strong physical and electrical bond, ensuring that the interposer 104 and the one or more chips 106a-d are physically stable components. Alternatively, the electrical connections coupling the chips 106a-d and the interposer 104 may be made of one or more pins and corresponding sockets as depicted in 110. Pins may form part of the interposer 104 and may protrude from the top side of the interposer to interact with sockets on the bottom side of the one or more chips 106a-d. Alternatively, the interposer 104 may include sockets located on the top side of the interposer 104 to interact with multiple pins protruding from the bottom side of the one or more chips 106a-d. The sockets on the top side of the interposer 104 or the bottom side of one or more microchips 106a-d can be universal sockets operable to receive pins from multiple different arrangements. As described above, this provides a simplified method for replacing damaged components in electronic circuit packages compared to current complex chips, in which multiple chips and circuits are soldered onto a circuit board, and therefore the entire chip must be replaced when a component fails. This is advantageous because the replacement costs of complex chips, which typically have higher processing requirements and are vehicle-specific tasks / operations, particularly those in the automotive industry, are very high. Therefore, having universal sockets to allow replacement of individual damaged microchips rather than the entire circuit is advantageous. Furthermore, the supplied electronic circuit package can be easily upgraded by replacing the microchips on the system with newer microchips using a "plug-and-play" arrangement. This extends the on-road life of vehicles by allowing older vehicles using previous-generation microchips to be easily upgraded to include the most modern microchips.

[0036] In one embodiment, each of the chiplets (e.g., 106a and 106b) may include a fixed electrical connection or similar connection as depicted in 108. One or more other chiplets (e.g., 106c and 106d) may include socket and pin-type connections as depicted in 110.

[0037] Figure 2 A detailed top view of an electronic circuit package 200, which is similar to... Figure 1a and Figure 1b Electronic circuit package 100. Electronic circuit package 200 is used for data fusion as described below, and can also be a data fusion electronic circuit package. Electronic circuit package 200 includes substrate 202 (similar to...) Figure 1a and Figure 1b substrate 102), to be referenced above Figure 1a and Figure 1b An interposer 204 disposed on substrate 202 in a manner similar to that described above (similar to...) Figure 1a and Figure 1b Intermediate layer 104). Electronic circuit package 200 includes one or more first chips 206a, 206b, ..., 206n (referred to herein as 206) operable to perform a first operation, one or more memory chips 208a, 208b, ..., 208n (referred to herein as 208) operable to store memory, and one or more second chips 210a, 210b, ..., 210n (referred to herein as 210) operable to perform a second operation different from the first operation. Although a plurality of first chips 206, a plurality of memory chips 208, and a plurality of second chips 210 are shown, the invention is not limited to a plurality of such chips. The invention may include any number (including only one) of first chips 206, memory chips 208, and second chips 210, and any combination thereof. One or more first chips 206 and one or more second chips 210 are similar to the plurality of chips 106a-d described above. Similarly, one or more memory chips 208 described are similar to the plurality of chips 106a-d described above. One or more first chiplets 206, one or more memory chiplets 208, and one or more second chiplets 210 are disposed on the interposer layer 204, as described above. Figure 1a and Figure 1b The one or more second chips 210 may include a second chip 210a operable to perform intermediate operations, a different second chip 210b operable to perform advanced operations, yet another different second chip 210n operable to perform even more advanced operations, or any combination thereof. Thus, the one or more first chips 206 may be a first predefined type, while the one or more second chips 210 may be a second predefined type. However, the one or more second chips may also be different predefined types (e.g., second chip 210a may be a second predefined type, second chip 210b may be a third predefined type, and second chip 210n may be a second, third, fourth, or nth predefined type).

[0038] The electronic circuit package 200 can be configured to perform the operation of the data fusion model as described above. The first operation performed by one or more first chips 206 may include performing low-level operations such as receiving / collecting data (e.g., sensor data collected by sensors of the vehicle). In one embodiment, the data may include internal sensor data captured by the vehicle (e.g., data captured by cameras, radar, microphones, temperature, motion sensors, or any other type of sensor in the vehicle's cabin). The data may include external sensor data captured by the vehicle (e.g., data captured by cameras, radar, LiDAR, infrared, motion, temperature sensors, microphones, or any other type of sensor that captures data outside the vehicle). The data may include data captured by the vehicle (e.g., data not limited to sensor data and including sound, video, text, or any other type of information received by the vehicle). The data may include data received from external devices (e.g., data received from user equipment, networks, servers, or any combination thereof communicating with the vehicle). The data may include any combination as described above. This may include raw data, preprocessed data, or a combination thereof.

[0039] The first operation can be a level 0 processing stage as described above. One or more memory chips 208 can store data. The second operation performed by one or more second chips 210 can include performing intermediate-level and / or high-level operations, as described above. This can include processing data and determining what actions need to be taken. By separating multiple operations of a complex chip (e.g., the first and second operations) into separate chips 206, 208, 210 each dedicated to a specific operation, the computing power of each chip can be fully dedicated to its dedicated operation. The second operation can be a level 1, level 2, level 3, or level 4 processing stage as described above. In one embodiment, one of the multiple second chips 210 can perform a level 1 operation, another of the multiple second chips 210 can subsequently perform a level 2 operation, and different second chips among the multiple second chips 210 can perform a level 3 operation as described above after a level 2 operation. The advantage of this architecture is that several chips 206, 208, 210 can be combined in a package 200 to avoid poor yield due to the excessive size of a large chip (i.e., a complex chip). Therefore, a chip component (or chiplet) 206, 208, 210 is not limited by the computational requirements of multiple operations. For example, a first-type chiplet 206 can be dedicated to receiving data, while a second-type chiplet 210 can be dedicated to processing data (e.g., sorting data, assigning data to actions, and / or any other processing operation). The first-type chiplet 206 can be manufactured to receive data efficiently (e.g., fast and low-power). However, the first-type chiplet 206 may have sufficient hardware to process data. The second-type chiplet 210 can be manufactured to process data efficiently, but may not be able to receive data efficiently. Therefore, specific hardware can be dedicated to each type of chiplet 206, 208, 210 to ensure that each chiplet type 206, 208, 210 is as efficient as possible. Because such chipsets need to perform fewer functions, they require fewer resources to manufacture. Therefore, they are easier and cheaper to manufacture, while ensuring that the overall processing system is faster and more efficient. An electronic circuit package 200 that includes multiple chiplet types (i.e., first chiplet 206, second chiplet 210, and memory chiplet 208) is advantageous because such a package is not limited to the traditional size requirements of complex chips (e.g., graphics cards, motherboards, and other types of complex chips). Therefore, an electronic circuit package 200 with greater overall processing power than current complex chips can be provided.

[0040] Figure 2A first communication infrastructure 212 and a second communication infrastructure 214 are shown. The first communication infrastructure 212 and the second communication infrastructure 214 provide inter-chip communication (e.g., communication between one or more first chipsets 206, one or more memory chipsets 208, one or more second chipsets, and / or any other component portion of system 200). Inter-chip communication may include wiring harnesses, bus connectors, electrical couplings, etched electrical connections on interposer 204, vias in interposer 204 (which couple to etched electrical connections on substrate 202), or any other suitable electrical connection.

[0041] The first communication infrastructure 212 may couple one or more first chipsets 206 and one or more memory chipsets 208. In one embodiment, the one or more first chipsets 206 represent level 0 chipsets (or low-level chipsets) of a data fusion system and are operable to receive and / or collect (raw) data (e.g., sensor data from a vehicle). In one embodiment, the number of first chipsets 206 may be related to the number of sensor inputs required by the system. For example, a system receiving sensor data from three sensors may include three first chipsets 206, each dedicated to a single first chipet 206 for each of the three sensors. The one or more first chipsets 206 may be coupled to the first communication infrastructure 212 in parallel. Advantageously, by placing the first chipsets 206 in parallel with the first communication infrastructure 212, operations performed by the first chipsets 206 (e.g., receiving data) can be performed simultaneously by multiple first chipsets 206, thus increasing the speed of performing the first operation. Parallel communication with memory chip 208 provides unimpeded access to store the actions of a first operation (e.g., receiving data from one or more first chips 206) on memory 208 with low latency. This also provides the option for each of the multiple first chips 206 to be dedicated to collecting a specific type of data (e.g., sensor data) and to allow all data to be stored simultaneously on one or more memory chips 208 (thus ensuring that each of the first chips 206 can perfectly receive the data it is pre-programmed to receive, and that all data is stored with low data corruption).

[0042] Alternatively, one or more first chipsets 206 may be coupled in series to a first communication infrastructure. By placing the first chipsets 206 in series, a plurality of first chipsets 206 can be arranged such that each operation is performed in series through each of the first chipsets 206 before being individually stored on one or more memory chipsets 208. This provides an arrangement where storage is performed only after the operation is complete, thus reducing the amount of storage required for the entire package. This can be advantageous when the plurality of first chipsets 206 each perform early processing (such as digital signal processing) on ​​the collected data. Advantageously, the data stored on one or more memory chipsets 208 is preprocessed to free up processing power for one or more second chipsets 210 to perform their processing operations.

[0043] In one embodiment, the second communication infrastructure 214 can couple one or more memory chips 208 and one or more second chips 210. The one or more second chips 210 can be coupled in parallel to the first communication infrastructure. Advantageously, by placing the second chips 210 in parallel with the second communication infrastructure 214, operations performed by the second chips 210 (e.g., data processing) can be performed simultaneously by providing data from the one or more memory chips 208 to each of the second chips 210. This reduces overall latency.

[0044] Alternatively, one or more second chips 210 may be coupled in series to the first communication infrastructure 212. By placing the second chips 210 in series, multiple second chips 210 can be arranged such that each performs a separate operation (e.g., the second, third, fourth, nth, or any combination thereof as described above) in series through each of the second chips 210 before performing the final operation. This is particularly advantageous in scenarios where multiple different types of second operations (e.g., the second, third, fourth, nth, or any combination thereof as described above) must be performed consecutively before taking a final action (e.g., sorting multiple different types of data before issuing a request to send a message or activate a device), and it is advantageous to separate each of the second operations into a separate chip to ensure that each of the second chips is manufactured to perform its dedicated operation efficiently.

[0045] One or more memory chips 208 are electrically coupled to each other to form a single memory group dedicated to storing data provided by one or more first chips 206 and providing that data to one or more second chips 210. The number of memory chips 208 is determined based on system requirements and may include a single memory chip 208 or any number of memory chips 208.

[0046] One or more first chips 206 may each include a processor (e.g., a microcontroller unit (MCU) or any other suitable type of processor) to perform a first operation. The first operation may include receiving data as described above (e.g., sensor data captured by a vehicle). The first operation may be a level 0 processing stage as described above. In one embodiment, the data may include data received by the vehicle (e.g., sensor data captured by a vehicle). Figure 4 The sensor data captured by the vehicle 400 described herein. Advantageously, the provided electronic circuit packages 100, 200 have dedicated circuitry (one or more first chips 206) to receive data from the vehicle system and feed the data to the memory (one or more memory chips 208) of the electronic circuit packages 100, 200.

[0047] In one implementation, sensor data may include data from the vehicle (e.g., such as...). Figure 4 The sensor data includes sensor data from external sensors of the vehicle (400) described herein. These external sensors may record video data, radar data, light detection and ranging (LiDAR) data, or any combination thereof. The sensor data may additionally or alternatively include sensor data from internal sensors of the vehicle (e.g., in-cabin sensors that can view the vehicle's passengers, radar detectors, one or more cameras, temperature sensors, sound sensors, or any other in-cabin sensors). Advantageously, the provided electronic circuit packages 100, 200 can receive a large amount of diverse sensor data. This data is typically generated by the vehicle (e.g., as described herein). Figure 4 The vehicle 400 continuously collects sensor data, and the provided electronic circuit packages 100, 200 receive sensor data using one or more dedicated first chips 206, which can quickly and efficiently store the data in memory for processing by other circuits or chips (e.g., one or more second chips 210). This ability to process the data quickly and efficiently ensures safe driving because less data is lost during collection due to system lag. Furthermore, all sensor data recorded by the vehicle can be received, stored, and processed by a single system (i.e., electronic circuit packages 100, 200). This provides a simple solution for the automotive industry where the perception and processing of data requires less computational resources (i.e., fewer processing units). Moreover, by combining all sensor data in a single system, multiple actions (e.g., accident prevention actions) can be efficiently processed to more accurately determine the current situation of the vehicle (and / or the vehicle's driver). This is more efficient than using multiple systems for each sensor type to collect and process sensor data.

[0048] The one or more first chips 206 can be coupled to the first communication infrastructure 208 in parallel or in series. By placing one or more first chips 206 in parallel, different types of sensor data (e.g., video data, radar data, LiDAR data, and / or any other type of data as described above) can be captured simultaneously. By placing one or more first chips 206 in series, different types of sensor data (e.g., video data, radar data, LiDAR data, and / or any other type of data as described above) can be captured in a specific order.

[0049] In one implementation, one or more first chiplets 206 may perform preprocessing on the captured data. For example, this may include a digital signal processing (DSP) stage, in which the captured sensor signals (e.g., voice, audio, temperature, pressure, position, video, and / or any other type of data or combinations thereof) are preprocessed and filtered into separate components stored in one or more memory chiplets 208.

[0050] One or more second chiplets 210 may each include a processor (e.g., a microcontroller unit (MCU) or any other suitable type of processor) operable to perform a second operation. The second operation may include classifying received data into one or more datasets. The dataset may include one or more categories, one or more data types, or a combination thereof. Classifying the data may include one or more of the first-level processing stage, second-level processing stage, and intermediate processing stage as described above. This may include receiving data from one or more memory chiplets 208, then processing and merging that data. Advantageously, the provided electronic circuit packages 100, 200 can handle large amounts of sensor data because one or more second chiplets 210 are specifically designed to process (i.e., classify) this data. Therefore, safe driving can be ensured because any actions that may need to be taken due to the received sensor data can be processed more quickly.

[0051] In one implementation, the Level 1 processing stage (and the corresponding second chip 210 operable to perform the Level 1 processing stage) can perform digital signal processing (DSP) operations.

[0052] In one implementation, one or more data types may include video data, audio data, text data, radar data, LiDAR data, or any combination thereof. Advantageously, the data can be sorted to determine specific actions the vehicle may need to take. In a non-limiting example, video, radar, and / or LiDAR data may be related to avoiding a vehicle collision due to sensed external conditions. Audio and / or text data may be related to determining whether the vehicle driver is in control of the vehicle.

[0053] In one implementation, one or more categories may include: data including information about the vehicle's user (e.g., personal data, medical data), data including information about the vehicle's status (e.g., speed, location), detection of one or more moving objects outside the vehicle (e.g., other vehicles, pedestrians, animals), detection of one or more fixed objects outside the vehicle (e.g., lampposts, parked vehicles), detection of one or more moving objects inside the vehicle (e.g., users, passengers, user body parts (in case of a medical event / seizure, etc.)), detection of one or more fixed objects inside the vehicle (e.g., detecting when components detach), or any combination thereof. Advantageously, various collisions or other malfunctions can be efficiently and quickly identified to avoid, for example, vehicle (such as...) Figure 4 The aforementioned vehicle 400) collided.

[0054] In one embodiment, the electronic circuit packages 100, 200 may further include one or more third chips 210b, 210c, ..., 210n, which are disposed on the interposer 204 and coupled to the second communication infrastructure 214. The one or more third chips may be physically similar to one or more second chips 210 and may be coupled to the second communication infrastructure 214 in a similar manner to the one or more second chips 210 (e.g., in parallel with one or more second chips 210, or in series with one or more second chips 210 and after one or more second chips 210). The one or more third chips may be a subset of the one or more second chips 210 and may be a third predetermined type as described above. Each of the one or more third chips may include a processor (e.g., an MCU or any other suitable processor) operable to perform a third operation. The third operation may include receiving classified data, determining the action that the package needs to take based on the classified data, and instructing the vehicle to perform that action. Advantageously, providing a separate chip with dedicated processing capabilities to determine the required action type, which can more efficiently determine the action to be performed and the type of action to be performed based on the classified data. This further improves vehicle performance by ensuring no system lag due to the use of a separate and dedicated small chip for each operation (e.g., ...). Figure 4 The safety of the vehicle (400) mentioned above.

[0055] In the example use case, vehicles (such as...) Figure 4The vehicle 400 can receive sensor data. The sensor data can be external sensor data, including radar (e.g., short-wave radar, mid-range radar, long-range radar, or any other type of radar), LiDAR data, and data captured from one or more camera sensors (e.g., for ADAS). All such sensor data is captured by one or more first chips 206 (e.g., a first chip 206a for radar, a different first chip 206b for LiDAR, and yet another different first chip 206c for the camera) and then stored on one or more memory chips 208. The radar sensor can detect objects (e.g., obstacles on the road), and this data, after being collected and stored, is fed into one or more second chips 210. One or more second chips 210n can track data associated with the object (e.g., at level 1). When an object enters the range of the LiDAR, the LiDAR sensor data is captured by the first chip 206b and stored in one or more memory chips 208. Data related to object detection performed by LiDAR is then fed into one or more second chips 210n (e.g., in Level 1). Different chips in the one or more second chips (e.g., a third predetermined type as described above) can receive data related to objects detected by LiDAR and radar and then classify the objects. This may include determining whether the object is moving or stationary, determining the speed at which the object is moving toward the vehicle (or the amount of time remaining before the vehicle collides with the object). This determination may be fed into another second chip (e.g., a chip operable to perform a Level 2 processing phase) to classify the object and its motion relative to the vehicle as threatening (or non-threatening). When an object enters the camera's range, the camera's sensor data is captured by a first chip 206c and stored in one or more memory chips 208. Data related to object detection performed by the camera is then also fed into one or more second chips 210n (e.g., in Level 1), which is then used for further classification of the object. This may include determining whether the object is dangerously close to the vehicle. This determination may also be fed into another second chip (i.e., a second chip operable to perform a Level 2 processing phase). At this stage, a higher-level second chip is required (e.g., a second chip operable to perform the Level 3 processing stage), where actions are taken. These actions could include instructing the vehicle user to issue a warning, applying the vehicle's brakes and / or steering, etc.

[0056] Another example could include from vehicles (such as...) Figure 4The vehicle 400 described herein captures sensor data within its passenger compartment. This may include using in-cabin cameras, radar, a connection to the driver's smartwatch, or any combination thereof to capture various types of data. The camera may first detect abnormal head movements by the driver. This is performed through the following steps: continuously capturing photographic and / or continuous video feeds of the driver; feeding this data to one or more first chips 206 (e.g., operable to perform a first operation that can be level 0); storing the data in one or more memory chips 208; and determining whether the head movement is abnormal by a first of one or more second chips 210 (e.g., chip 210a operable to perform a second operation that can be level 1). A second chip 210b (operable to perform a level 2 operation) may then receive the data and determine that data from the radar must also be accessed. Radar data is captured using one or more first chips 206 and processed using one or more different second chips (e.g., second chip 210c). A second chip 210b, operable to perform Level 2 operations, can detect whether the driver's heart rate is abnormal (based on data received in Level 1 operations for radar data). Finally, another first chip can receive the driver's medical data from the smartwatch and input it into a memory chip 208, which can be retrieved by one or more second chips 210 (e.g., second chip 210d). In Level 1 operations, second chip 210d can determine that the driver is currently taking a medication with rare side effects such as increased blood pressure (e.g., by retrieving medical records and / or data fed into the smartwatch). The Level 2 operations performed by second chip 210b can integrate these three pieces of information—abnormal head movements (from second chip 210a), abnormal heart rate (from second chip 210c), and the driver taking a medication with rare side effects (from second chip 210d)—and send it to another second chip (e.g., second chip 210e) operable to perform Level 3 operations. Second chip 210e can combine all such data and conclude that action is required. This action leads to the conclusion that all the captured data combined constitutes the current threat, and thus triggers a call to emergency services.

[0057] Advantageously, a single device can be implemented in a vehicle to detect multiple scenarios and adjust the vehicle's driving to ensure safety or other purposes. Each of the second small chips 210 can include predetermined thresholds to determine a specific scenario and identify each scenario as requiring or not requiring a specific trigger. By providing electronic circuit packages 100, 200 as described herein, each chip can be easily replaced if the predetermined thresholds need to be updated. This is much simpler and cheaper than replacing or updating the entire computer system.

[0058] In one implementation, the action may include displaying a message on a user interface (e.g., displaying a safety message that the vehicle is approaching an object, indicating that emergency services will be called, etc.), activating mechanical devices (e.g., activating brakes, steering, accelerator, or any other component to operate the vehicle; and / or activating in-cabin components to soothe a distressed driver, such as seat massage), and / or deactivating one or more mechanical devices to operate the vehicle and / or soothe the driver. The action may include activating and / or deactivating electrical devices (e.g., activating and / or deactivating interior or exterior lighting of the vehicle to draw attention to the vehicle, activating and / or deactivating electronic driving controls of the vehicle to take over driving operations and thus avoid collisions, etc.). The action may include requesting data from a network (e.g., personal data related to the driver of the vehicle, such as whether the driver is taking any medications and / or has any specific illnesses or other medical conditions). The action may include any combination of the above. Advantageously, the provided vehicle (e.g., such as...) Figure 4 The vehicle 400 described above can react faster than a vehicle equipped with multiple complex chips. Furthermore, the provided vehicle can perform multiple operations efficiently and effectively (i.e., it has a lower failure rate due to the resolution of time lag and therefore the inability to quickly receive and / or process data).

[0059] Electronic circuit packages 100 and 200 may further include one or more fourth chiplets, one or more fifth chiplets, or up to one or more nth chiplets. Each of the fourth, fifth, and nth chiplets may be of a fourth predetermined type, a fifth predetermined type, and an nth predetermined type, respectively. Each of the fourth, fifth, and nth chiplets may each include a processor (e.g., an MCU or any other suitable processor) operable to perform a corresponding fourth, fifth, and nth operation.

[0060] In one embodiment, the intermediary layer 204 may include at least one socket operable to receive pins from at least one of one or more first chips 206, one or more second chips 210, one or more third chips, and one or more memory chips 208 (as described above with reference to FIG. 1). In one embodiment, the at least one socket may be a general-purpose socket. The intermediary layer 204 may have a general-purpose socket operable to receive multiple chips (e.g., one or more first chips 206, one or more second chips 210, one or more third chips, one or more memory chips 208, or any combination thereof). The intermediary layer 204 may have a general-purpose socket for each type of chip (e.g., a general-purpose socket for one or more first chips 206, a general-purpose socket for one or more second chips 210, a general-purpose socket for one or more third chips, a general-purpose socket for one or more memory chips 208, or any combination thereof). The intermediary layer may have a general-purpose socket for each chip. At least one of one or more first chips 206, one or more second chips 210, one or more third chips, and one or more memory chips 208 may include pins operable to engage with at least one universal socket. This provides a simplified method for replacing damaged components of electronic circuit packages 100, 200, compared to current complex chips where multiple chips and circuits are soldered onto a circuit board, and therefore the entire chip must be replaced when a component fails. This is advantageous because replacing complex chips, particularly those in the automotive industry, which typically have higher processing requirements and are vehicle-specific for their tasks / operations, is very costly. Therefore, having a universal socket to allow replacement of individual damaged chips rather than the entire circuit is advantageous. Furthermore, the supplied electronic circuit packages 100, 200 can be easily upgraded by replacing chips in the system with newer chips using a "plug-and-play" arrangement. This extends the on-road life of vehicles by allowing older vehicles using previous-generation chips to be easily upgraded to include the most modern chips. By providing a universal socket, chips from multiple manufacturers can be used in the same electronic circuit package 100, 200 (provided that multiple manufacturers use the same socket and pin arrangement). This increases the availability of electronic circuit packages 100, 200 and provides increased manufacturing flexibility for vehicle manufacturers and automotive component suppliers.

[0061] In one embodiment, the at least one socket is not universal but specifically designed for each type of chiplet (i.e., one or more first chipsets 206, one or more second chipsets 210, one or more third chipsets, one or more memory chipsets 208, or any combination thereof). Therefore, a chiplet requiring replacement can only be replaced with a chiplet of the same type. Advantageously, the fit between the pins and the socket can be manufactured to be very small, ensuring a stronger fit compared to universal systems. Consequently, the risk of one or more chipslets detaching from the interposer 204 (e.g., during harsh driving conditions) is reduced, and thus the reliability of the electronic integrated circuit packages 100, 200 is improved.

[0062] Figure 3 The electronic circuit package is depicted (e.g., in Figure 1 and Figure 2 respectively). Figure 2 The system 300 comprises electronic circuit packages 100 and 200 described herein. System 300 includes a substrate 302, an interposer 304 disposed on the substrate 302, and a plurality of electronic circuit packages 202a, 202b, ..., 202n disposed on the interposer 304. Each of the plurality of electronic circuit packages 202a, 202b, ..., 202n can be coupled to the electronic circuit packages 202a, 202b, ..., 202n as described above with reference to FIG1 and ... Figure 2 The electronic circuit packages 100 and 200 described are basically similar. The interposer 304 can be coupled to the substrate 102 in a manner similar to that described above with reference to Figure 1, or in a manner similar to that described above with reference to... Figure 2 The interposer 204 is coupled to the substrate 302 in a manner similar to that of the substrate 202. Each of the plurality of electronic circuit packages 202a, 202b, ..., 202n can be coupled to the interposer 104 in a manner similar to that of the chiplet 106 as described with reference to FIG. 1, or in a manner similar to that described with reference to FIG. 1. Figure 2 The chiplets (first chiplet 206, second chiplet 210, memory chiplet 208, and third chiplet) are coupled to the interposer 304 in a manner that couples to the interposer 204. The coupling from the interposer 304 to the substrate 302 may include the universal socket described above. The coupling of one or more of the plurality of electronic circuit packages 202a, 202b, ..., 202n may include the universal socket.

[0063] Therefore, each of the plurality of electronic circuit packages 202a, 202b, ..., 202n includes a substrate 202, an interposer 204 disposed on the substrate 202, and one or more first chips 206 disposed on the interposer 204, the one or more first chips 206 being operable to perform a first operation. Each of the plurality of electronic circuit packages 202a, 202b, ..., 202n includes one or more memory chips 208 disposed on the interposer 204, the one or more memory chips 208 being operable to store data. Each of the plurality of electronic circuit packages 202a, 202b, ..., 202n includes one or more second chips 210 disposed on the interposer 204, the one or more second chips 210 being operable to perform a second operation.

[0064] although Figure 3 The invention describes three electronic circuit packages 202a, 202b, ..., 202n, but the invention is not limited to three electronic circuit packages, but may include any number of electronic circuit packages.

[0065] Advantageously, multiple electronic circuit packages 202a, 202b, ..., 202n can be electronically coupled together and can be separated to perform individual tasks. For example, one electronic circuit package may include the chip type and memory described above to receive and process sensor data. A second electronic circuit package may include chip types and memory dedicated to different operations. Thus, each electronic circuit package can be manufactured to efficiently perform its dedicated task. Therefore, a system with overall processing power far exceeding that of current complex chips and current computer systems can be provided. Current vehicles require multiple electronic control units (ECUs) to operate a variety of different vehicle operations. The number of operations required by future vehicles is expected to increase, and therefore, more processing power is expected to be needed to accommodate all operations. With current technology, this is expected to require vehicles to be equipped with more ECUs. ECUs are expensive to manufacture, and increasing the number of ECUs will increase the cost of the vehicle. Furthermore, additional ECUs will further increase the weight of the vehicle, thereby reducing vehicle efficiency. Additional ECUs also require more power to operate, which further reduces vehicle efficiency. By providing the system 300 described above, multiple types of operations (typically performed by different ECUs) can be combined into a single unit. This can be achieved by providing an electronic circuit package for each operation (e.g., as shown in Figure 1 above and...). Figure 2 The above is achieved by providing a substrate 302 and an interposer 304 as described above to accommodate each of the electronic circuit packages. Therefore, a central control unit (CCU) is provided that occupies less physical space in the vehicle, requires less power to operate, and is operable by the vehicle (e.g., Figure 4The vehicle 400 described in the text has all the functions. Furthermore, any faulty component can be easily located (because the CCU is located in one area of ​​the vehicle, rather than multiple different areas), and can be easily replaced due to its small chip-based architecture.

[0066] Figure 4 A vehicle 400 is depicted, including at least one sensor (not shown) and an electronic circuit package 402. The vehicle 400 can be a road vehicle, off-road vehicle, aerial vehicle, amphibious vehicle, or any other suitable type of vehicle. The electronic circuit package 402 can be as shown in Figure 1 above. Figure 2 The electronic circuit packages 100 and 200 are described above. Alternatively, the electronic circuit package 402 can be as described above. Figure 3 The electronic circuitry packaged in the system 300. Advantageously, the vehicle 400 can detect more information faster (i.e., without lag) and process that data faster (i.e., with less lag) to determine what actions need to be taken (if necessary). Therefore, the provided vehicle 400 is more likely to avoid collisions and any other types of accidents and / or malfunctions, as described above. In one embodiment, the sensor may include a radar sensor, a LiDAR sensor, a camera sensor for advanced driver assistance systems (ADAS), or any combination thereof.

Claims

1. An electronic circuit package for data fusion, comprising: a substrate; an interposer disposed on the substrate; one or more first chiplets disposed on the interposer, the one or more first chiplets operable to perform a first operation; one or more memory chiplets disposed on the interposer, the one or more memory chiplets operable to store data; and one or more second chiplets disposed on the interposer, the one or more second chiplets operable to perform a second operation.

2. The package of claim 1, further comprising: a first communication infrastructure coupling the one or more first chiplets and the one or more memory chiplets, wherein: the one or more first chiplets are coupled in parallel to the first communication infrastructure, or the one or more first chiplets are coupled in series to the first communication infrastructure.

3. The package of claim 1 or 2, further comprising: a second communication infrastructure coupling the one or more memory chiplets and the one or more second chiplets, wherein: the one or more second chiplets are coupled in parallel to the first communication infrastructure; or the one or more second chiplets are coupled in series to the first communication infrastructure.

4. The package of any of claims 1-3, wherein the one or more first chiplets each comprise a first processor operable to perform the first operation, wherein the first operation comprises receiving data.

5. The package of claim 4, wherein the data comprises: internal sensor data captured by a vehicle; external sensor data captured by the vehicle; data captured by the vehicle; data received from an external device; or any combination thereof.

6. The package of claim 5, wherein the sensor data comprises: video data; radar data; LiDAR data; or any combination thereof.

7. The package of any of claims 3-6, wherein the one or more second chiplets each comprise a second processor operable to perform the second operation, wherein the second operation comprises classifying the received data into: one or more categories; one or more data types; or a combination thereof.

8. The package of claim 7, wherein the one or more data types comprise: video data; sound data; text data; radar data; LiDAR data; or any combination thereof.

9. The package of claim 7 or 8, wherein the one or more categories comprise: data comprising information about a user of a vehicle; data comprising information about a state of the vehicle; a detection of one or more moving objects outside the vehicle; a detection of one or more stationary objects outside the vehicle; a detection of one or more moving objects inside the vehicle; a detection of one or more stationary objects inside the vehicle; or any combination thereof. ​ 10. The package of any of claims 7-9, further comprising: one or more third chiplets disposed on the interposer and coupled to the second communication infrastructure, the one or more third chiplets each comprising a processor operable to perform a third operation, and the third operation comprising: receiving the classified data; determining, from the classified data, that the package needs to take an action; and directing a vehicle to perform the action.

11. The package of claim 10, wherein the action comprises: displaying a message on a user interface; activating a mechanical device; deactivating a mechanical device; activating an electrical device; deactivating an electrical device; requesting data from a network; or any combination thereof.

12. The package of any of the above claims, wherein: the interposer comprises at least one universal socket operable to receive a socket from at least one of the one or more first chiplets, the one or more second chiplets, the one or more third chiplets, and the one or more memory chiplets; and at least one of the one or more first chiplets, the one or more second chiplets, the one or more third chiplets, and the one or more memory chiplets comprises a pin operable to engage with the at least one universal socket.

13. A system comprising: a second substrate; a second interposer disposed on the second substrate; and a plurality of packages as claimed in claims 1-12 disposed on the second interposer.

14. A vehicle comprising: a sensor; and a package as claimed in claims 1-12 or a system as claimed in claim 13.

15. The vehicle of claim 14, wherein the sensor comprises: a radar sensor; a LiDAR sensor a camera sensor for advanced driver assistance systems (ADAS); or any combination of the above. ​ ​

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