PCB Layout layout method of digital-to-analog conversion board of CX9261 chip

Abstract

The invention discloses a PCB (Printed Circuit Board) Layout layout method of a digital-to-analog conversion board of a CX9261 chip. Shielding processing is carried out between the CX9261 and other circuit modules, so that the interference of other chips on the CX9261 is effectively reduced, and the integrity of related signals of the chip is ensured; through equal-length and equal-distance processing of high-speed signal and differential signal wiring, signal reflection, crosstalk and attenuation are effectively reduced, the integrity and stability of signal transmission are remarkably improved, and the communication quality and data processing efficiency of the electronic equipment in a high-frequency and high-speed working scene are greatly improved.

Description

TECHNICAL FIELD

[0001] The application relates to a PCB Layout layout method of a digital-to-analog conversion board of a CX9261 chip. BACKGROUND

[0002] The core advantage of the digital-to-analog conversion board lies in that discrete instructions of a digital system can be accurately converted into continuous analog signals, high reliability, high compatibility and scene adaptation are realized through hardware optimization, and the problem of signal discontinuity between digital control and analog actuators is solved. In terms of signal conversion, high precision and low distortion can be achieved. In terms of hardware adaptation characteristics, high compatibility and flexibility are achieved. In terms of environmental adaptation, high stability and anti-interference are achieved. In terms of cost and efficiency, low power consumption and easy maintenance are achieved.

[0003] The CX9261 chip is a wideband, high-performance and low-power multi-channel RF transceiver designed based on the software radio concept. The RF transceiver integrates RF, ADC / DAC and digital up / down conversion circuits required by the RF transceiver, greatly reducing the complexity of RF link design, and the system integration is high.

[0004] At present, the PCB layout of the digital-to-analog conversion board of the CX9261 chip has the defects that the transmission process is easily disturbed by other circuits, the signal quality is reduced, the RF signal is obviously attenuated, and the electromagnetic interference on other external circuits is more serious. SUMMARY

[0005] The purpose of the application is to solve the problem that the existing digital-to-analog conversion board of the CX9261 chip is easily disturbed. A PCB Layout layout method of a digital-to-analog conversion board based on a CX9261 chip realizes the effects of improving signal integrity and signal quality and quickly performing digital-to-analog conversion.

[0006] The technical scheme of the application is as follows: A PCB Layout layout method of a digital-to-analog conversion board of a CX9261 chip, comprising the following steps: Step 1: draw a schematic diagram and add correct packaging by using AltiumDesigner20 software; Step 2: after checking that the schematic diagram and the device packaging are correct, import the packaging and the schematic diagram into the PCB in the DXF or DWG format according to the 1:1 metric scale; Step 3: design the layer structure in combination with the number of devices, the size of the board frame, the functional requirements and the principle of low cost and high utilization rate; Step four: first, classify the device by function, then layout according to signal and power flow, and separate the digital and analog signal related devices; only the dedicated power supply chip and circuit for CX9261 chip is placed near the chip, and other power supply chips are away from the chip; a ≥2mm blank space is reserved around the CX9261 related circuit for setting a shielding slot; Step five: the reserved blank is used to open a shielding slot with a width of ≥1.5mm on the surface layer of the PCB, and a safety distance is reserved from the surrounding devices to avoid interference, and the shielding slot needs to be grounded; Step six: PCB wiring is performed; Step seven: after wiring is completed, electrical rule checking is performed and errors are modified, and manual checking is performed to ensure that there are no vias and traces at the shielding slot window; Step eight: export the PCB assembly data; Step nine: after the PCB is produced, self-checking is performed first, then it is installed into the physical product for testing, the experimental data is verified with the reference data, and defects are iteratively corrected until the error is within the standard.

[0007] In step three, a ground plane layer is inserted between adjacent trace layers, and SI / 9000 software is used for layered impedance design to calculate the optimal line width to suppress signal reflection.

[0008] The specific steps of PCB wiring are as follows: Step six one: special signals such as radio frequency signals, high-speed signals, differential signals, and power signals are classified and wiring rules are set, and other signals are set according to process requirements and actual effects; Step six two: CX9261 related radio frequency signals are wired on the surface layer and shielded, and the radio frequency signal is a layer reference, and the actual reference plane is determined by cutting the plane at the corresponding position of the adjacent plane layer; Step six four: clock signals are preferably wired on the surface layer and directly connected, and a ground network is laid around to prevent interference; Step six three: high-frequency signals are wired in a serpentine shape on the same layer, and differential signals are wired in a differential form, and both groups of signals are processed to be equal in length; Step six four: adjacent layer traces are avoided to be relatively parallel to reduce interlayer crosstalk; Step six five: the surface layer trace and the shielding slot window position maintain a safety distance and do not directly contact.

[0009] The allowable range of the error within the two groups of signals is ±2.5mil, and the signal trace meets the 3W rule, the loop area is minimized according to the formula S=L*(W+M), and the trace is in an arc shape to avoid sharp electromagnetic interference; Where S is the minimum loop area, L is the total length of the signal line, W is the line width, and M is the line spacing; The shielding slot is a structure for reducing electromagnetic interference, and the window width is at least 1.5mm, and there is no interference with the surrounding devices.

[0010] In step six, the equal length processing of the high frequency signal and the differential signal needs to ensure the consistency of the signal transmission delay in the group, so as to reduce the signal crosstalk and attenuation.

[0011] The test of step nine includes the PCB board itself quality detection and the entity product adaptation test, and the data needs to be verified again after the defect correction, so as to ensure that the product performance meets the requirements.

[0012] The beneficial effects of the application are that: by shielding between CX9261 and other circuit modules, the interference of other chips on CX9261 is effectively reduced, and the integrity of the chip related signals is ensured; by equal length and equal distance processing of high speed signal and differential signal wiring, signal reflection, crosstalk and attenuation are effectively reduced, the integrity and stability of signal transmission are significantly improved, and the communication quality and data processing efficiency of electronic equipment in high frequency and high speed working scene are greatly improved.

[0013] By optimizing the layout of components and more reasonable wiring connection mode, the space utilization of the PCB is greatly improved under the premise of ensuring performance and heat dissipation, at the same time, unnecessary via, copper and wiring are avoided, and the manufacturing cost of the PCB is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a structure diagram of PCB board lamination layout.

[0015] Figure 2 is a structure diagram of the PCB board after setting a shielding groove.

[0016] Figure 3 is a structure diagram of the radio frequency signal shielding structure.

[0017] Figure 4 is a differential signal wiring diagram.

[0018] Figure 5 is a CX9261 chip related signal wiring diagram. DETAILED DESCRIPTION

[0019] Embodiment: This embodiment aims at the demand of high frequency digital to analog conversion module in communication equipment, the target is to realize signal transmission rate 1.2Gbps, signal distortion degree ≤0.01%, PCB board size ≤100mm×80mm, the adopted CX9261 chip is a wideband multi-channel radio frequency transceiver, the supporting AltiumDesigner20 drawing software, SI / 9000 impedance matching software, the PCB substrate selects FR-4 epoxy resin board, and the copper foil thickness is 18μm.

[0020] Specific design steps: (1) schematic diagram import implementation Using AltiumDesigner20 software, draw the circuit schematic diagram according to the digital-analog conversion function requirements, including CX9261 chip, power supply chip, filter capacitor, radio frequency interface and other devices, wherein the CX9261 chip package selects BGA289, the size is 14.5*14.5, and the power supply chip selects TPS7A4700 package SOT-223.

[0021] Through the software "package library check" function, check the correspondence between all device packages and schematic diagram pins, confirm that there is no wrong welding and missing welding logic, and then execute the "Design→UpdatePCBDocument" command to synchronize the schematic diagram and the package into the PCB file.

[0022] (2) Structure diagram import implementation Draw the board frame outline drawing using AutoCAD, set the board frame size to 170MM*160MM, reserve 10 mounting holes with a diameter of 3mm (hole center distance from board edge 5mm), and save as.DXF format file.

[0023] In the PCB interface of AltiumDesigner20, execute the "File→Import" command, select the above.DXF file, set the import scale to 1:1 and the unit to mm, and after completing the board frame import, check the board frame size and mounting hole position.

[0024] (3) PCB layer structure design implementation According to the number of devices (a total of 1827 components) and signal rate requirements, design a 10-layer PCB layer structure, from top to bottom: L1 (top layer): signal layer (copper 18 μm); L2: ground plane layer (copper foil 18 μm); L3: signal layer (copper foil 18 μm); L4: ground plane layer (copper foil 18 μm); L5: power layer (3.3V, copper foil 18 μm); L6: power layer (5V, copper foil 18 μm); L7: ground plane layer (copper foil 18 μm); L8: signal layer (copper foil 18 μm); L9: ground plane layer (copper foil 18 μm); L10 (bottom layer): signal layer (copper foil 18 μm); The interlayer medium thickness is set to 0.2 mm (S1000-2 material), the SI / 9000 software is used to input the lamination parameters, and the calculation shows that the wiring width corresponding to 50Ω impedance is 0.296 mm, and the wiring width corresponding to 100Ω differential impedance is 0.2 mm and the line spacing is 0.3 mm, which are used as the wiring basis.

[0025] (IV) Modular layout implementation The device is divided into three categories according to function: digital module (including logic control chip, interface chip), analog module (including CX9261 chip, radio frequency filter device), and power module (including TPS7A4700, filter capacitor).

[0026] According to the signal flow direction: radio frequency input interface→filter device→CX9261 chip→digital signal output interface, the power module is close to the CX9261 chip but does not overlap.

[0027] The digital module and the analog module are separated by the center line of the board frame, and the CX9261 chip is placed in the center. Only the dedicated 3.3V power supply chip TPS7A4700 and the filter capacitor C1-C4 are arranged around the CX9261 chip, and other 5V power supply chips are away from the CX9261 chip by ≥15 mm. A 2 mm annular blank space is reserved around the CX9261 chip.

[0028] (V) Shielding groove setting implementation In the 2 mm blank area reserved around the CX9261 chip, the surface layer (L1) is processed to open a 1.5 mm wide annular shielding groove. The shielding groove is spaced apart from the CX9261 chip pin by ≥0.8 mm and spaced apart from the surrounding devices by ≥1 mm to avoid interference.

[0029] The shielding groove opening window parameters are set through "Design→Rules→Manufacturing→SolderMaskExpansion", the shielding groove is connected with the ground plane layer (L2) through 10 diameter 0.3 mm vias, and grounding is achieved.

[0030] (VI) PCB wiring implementation Prioritize wiring special signals: Radio frequency signal (CX9261's RF_IN, RF_OUT): wiring on the L1 layer surface, length controlled within 50 mm, 2 mm wide isolation area cut at the corresponding position of the adjacent plane layer (L2) to ensure the reference of the separation layer.

[0031] Clock signal (CX9261's CLK_IN): L1 layer direct wiring, length 30 mm, surrounding ground network, ground network and clock line spacing ≥3W (W=0.8 mm, i.e. ≥2.4 mm).

[0032] High-speed differential signal (DATA + / - of CX9261): L3 layer is wired in differential form, with a line width of 0.2 mm, a line spacing of 0.3 mm, a total length of 30 mm, an equal length error controlled within ±2.5 mil, an arc-shaped wiring, and a loop area calculated by the formula S = L * (W + M) controlled within 30 * (0.2 + 0.3) = 15 mm².

[0033] General signal wiring: adjacent layers (such as L1 and L3) are wired vertically to avoid parallelism; the distance between surface wiring and shielding slot is ≥1 mm, and all wiring avoids sharp corners (corner ≥45°).

[0034] (Seven) DRC inspection implementation Perform "Tools→DesignRuleCheck" to perform electrical rule checking, set the check items to include line width, line spacing, via spacing, impedance matching, etc., and correct 3 line spacing deficiencies (0.2 mm→0.3 mm) and 2 via overlapping problems.

[0035] Manually check the shielding slot windowed area to confirm that there are no vias and wiring across, ensuring that the shielding slot function is effective.

[0036] (Eight) Implementation of assembly drawing export Perform "File→FabricationOutputs→GerberFiles" to export top / bottom copper foil, silk screen, solder mask, steel mesh, etc. Gerber files, set the precision to 2000 dpi.

[0037] Export BOM table (bill of materials), device location map, mark CX9261 chip, shielding slot, mounting hole, etc. Key position size for assembly process.

[0038] (Nine) Test and correction implementation After the PCB board is produced, use a multimeter to detect the connectivity of the power network and the insulation resistance (≥10 MΩ), and use a network analyzer to measure the RF signal transmission loss (≤0.5 dB @ 1 GHz).

[0039] Install the PCB board into the communication equipment and perform digital-to-analog conversion testing: input digital signal (0-1.2 Gbps), measure the output analog signal distortion as 0.008%, meeting the design requirements; detect electromagnetic interference (EMI) value as 38 dBμV / m, lower than the industry standard 40 dBμV / m.

Claims

1. A PCB layout method of a digital-to-analog conversion board of a CX9261 chip, comprising the following steps: Step one: draw a schematic diagram and add correct packaging using AltiumDesigner20 software; Step two: after verifying that the schematic diagram and device packaging are correct, import the packaging and schematic diagram in DXF or DWG format into the PCB at a 1:1 metric scale; Step three: design a layering structure in combination with the number of devices, the size of the board frame, functional requirements, and the principle of low cost and high utilization; Step four: first, classify devices by function, then layout according to signal and power flow, and separate digital and analog signal-related devices; only place exclusive power supply chips and circuits near the CX9261 chip, and keep other power supply chips away from the chip; reserve ≥2mm of blank space around the CX9261-related circuit for setting a shielding slot; Step five: open a shielding slot with a width of ≥1.5mm in the reserved blank area of the PCB board surface, and reserve a safe distance from surrounding devices to avoid interference, and the shielding slot needs to be grounded; Step six: perform PCB wiring; Step seven: after wiring is completed, perform electrical rule checks and modify errors, manually check that there are no vias and traces in the shielding slot window; Step eight: export PCB assembly data; Step nine: after PCB production, first self-check, then install into the physical product for testing, verify the experimental data with the reference data, and iteratively correct defects until the error is within the acceptable range.

2. The method of claim 1, wherein the PCB layout of the CX9261 chip's digital-to-analog conversion board is configured to: In step three, insert a ground plane layer between adjacent trace layers, and use SI / 9000 software to design layering impedance, and calculate the optimal line width to suppress signal reflection.

3. The method of claim 1, wherein the PCB layout of the CX9261 chip's DAC board is as follows: The specific steps of PCB wiring are as follows: Step six one: prioritize special signals such as radio frequency signals, high-speed signals, differential signals, and power signals, and set wiring rules, and set rules for other signals according to process requirements and actual effects; Step six two: use surface layer wiring and shielding for CX9261-related radio frequency signals, and radio frequency signals are separated layers of reference, and cut the plane at the corresponding position of adjacent plane layers to determine the actual reference plane; Step six four: try to connect clock signals directly on the surface layer, and lay a ground network around to prevent interference; Step six three: high-frequency signals are serpentine on the same layer, and differential signals are wired in differential form, and both groups of signals are processed to be equal in length; Step six four: avoid relative parallelism between adjacent layers to reduce crosstalk between layers; Step six five: maintain a safe distance between surface layer wiring and shielding slot window position, and do not directly contact.

4. The method of claim 3, wherein the PCB layout of the CX9261 chip's DAC board is as follows: The allowable range of intra-group error for the two groups of signals is ±2.5mil, and the signal traces meet the 3W rule, the loop area is minimized according to the formula S=L*(W+M), and the traces are arc-shaped to avoid sharp electromagnetic interference; where S is the minimum loop area, L is the total length of the signal line, W is the line width, and M is the line spacing.

5. The method of claim 1, wherein the PCB layout of the CX9261 chip's DAC board is as follows: The shielding slot is a structure for reducing electromagnetic interference, and the minimum window width is 1.5mm, and there is no interference with surrounding devices.

6. The method of claim 1, wherein the PCB layout of the CX9261 chip's digital-to-analog conversion board is configured to: In step six, the equal length processing of high-frequency signals and differential signals needs to ensure that the signal transmission delay within the group is consistent to reduce signal crosstalk and attenuation.

7. The method of claim 1, wherein the PCB layout of the CX9261 chip's DAC board is as follows: The step nine test includes PCB board self quality detection and entity product adaptation test, and the data needs to be checked again after defect correction to ensure that the product performance meets the requirements.

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