Chip verification method, system and platform

Abstract

The invention provides a chip verification method, system and platform, and the method comprises the steps: obtaining a test request, and determining a target function based on the test request; determining whether a target function module is connected to the chip verification system based on the target function, and determining whether the logic resource satisfies verification of the target function of the target chip; in response to the fact that the chip verification system does not have the target function module, adding the target function module, and / or in response to verification that the logic resource of the chip verification system does not meet the target function, carrying out board card expansion on the chip verification system; and based on the test request, verifying the target function of the target chip through the chip verification system. According to the technical scheme, the target function module needing to be added and the board card needing to be expanded are determined through the target function needing to be verified, and the chip verification system is changed, so that compared with a non-modular verification system in the prior art, a new verification system does not need to be rebuilt for each time of verification, the verification cost is reduced, and the verification efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to the fields of chip technology and digital signal processing, and in particular to a chip verification method, system, and platform. Background Technology

[0002] Chip prototyping is an essential technique in chip design and manufacturing. It's a necessary verification process used before chip tape-out to check if the chip's functionality and interfaces match the expected design, ensuring that the terminal device's functions and performance meet specifications. Currently, large-scale field-programmable gate array (FPGA) prototyping platforms are widely used for terminal chip verification, simulating various signal and communication scenarios in real-world environments to effectively test and verify the terminal chip's functionality and performance. In the field of low-Earth orbit satellite communication, the digital signal processing functions performed by chips are becoming increasingly complex and demanding, requiring more and more resources for verification platforms. The resources of a single FPGA chip are often insufficient to handle such high overhead. This necessitates cascading multiple FPGA chips. However, existing large-scale FPGA prototyping platforms face challenges in inter-chip communication, including communication bandwidth bottlenecks, timing synchronization issues, and insufficient scalability.

[0003] Commonly used inter-chip communication technologies for FPGAs include high-speed serial communication, parallel communication, and network communication. Parallel communication is a technology that transmits multiple bits of data simultaneously, such as bus protocols like AXI (Advanced Extensible Interface). Network communication is a technology that uses network protocols for data transmission, employing Ethernet or other network protocols to enable communication between FPGA chips. High-speed serial communication transmits data through differential signals, providing high bandwidth and low latency data transmission, suitable for applications requiring high-speed data transfer. However, the design and implementation of high-speed serial communication protocols are relatively complex, requiring consideration of timing, synchronization, and protocol requirements. Furthermore, the high hardware resources and circuit design complexity required for high-speed serial communication increase the difficulty of design and development. Summary of the Invention

[0004] This disclosure aims to at least partially address one of the technical problems in the related art.

[0005] Therefore, one objective of this disclosure is to propose a chip verification method.

[0006] The second objective of this disclosure is to propose a chip verification system.

[0007] The third objective of this disclosure is to propose a chip verification platform.

[0008] To achieve the above objectives, a first aspect of this disclosure provides a chip verification method, comprising: acquiring a test request; determining, based on the test request, a target function of a target chip to be verified; determining, based on the target function, whether a target function module is connected to a chip verification system, and determining whether the logic resources of the chip verification system satisfy the verification of the target function of the target chip, wherein the target function module is used to verify the target function of the target chip; in response to the absence of the target function module in the chip verification system, adding the target function module to the chip verification system, and / or in response to the logic resources of the chip verification system not satisfying the verification of the target function, expanding the chip verification system with additional boards; until the target function module is added to the chip verification system and the logic resources of the chip verification system satisfy the verification of the target function, verifying the target function of the target chip through the chip verification system based on the test request.

[0009] According to one embodiment of this disclosure, expanding the chip verification system includes: determining the number of expansion boards that the logic verification unit needs to cascade based on the size of the target chip; and connecting the required number of expansion boards via an FMC connector.

[0010] According to one embodiment of this disclosure, the chip verification system performs board expansion, including: cascading expansion boards that need to be expanded via Chip2Chip IP cores.

[0011] According to one embodiment of this disclosure, the Aurora protocol is used as the inter-chip communication protocol between any two boards connected in the chip verification system, and the Aurora IP core is used as the data transmission protocol for the Chip2Chip IP core.

[0012] To achieve the above objectives, a second aspect of this disclosure provides a chip verification system, comprising: an application processing unit, a logic verification unit, and a peripheral unit, wherein the application processing unit, the logic verification unit, and the peripheral unit are connected in pairs; the application processing unit is connected to a host computer, and the logic verification unit is connected to a target chip; the application processing unit is used to receive test stimulus sources sent by the host computer, preprocess the test stimulus sources, and then send them to the logic verification unit; the logic verification unit includes at least one development board, which provides logic resources for the target chip through a Chip2Chip IP core cascade expansion board to realize the design of the target chip; the peripheral unit is connected to at least one functional module, and the peripheral unit is used to cooperate with the functional module to provide input or output; the logic verification unit is also used to perform functional verification of the target chip based on the functional module and the test stimulus sources; the application processing unit is also used to receive verification data generated during the verification of the target chip by the logic verification unit, preprocess the verification data, and send it to the host computer for analysis and processing.

[0013] According to one embodiment of this disclosure, the system further includes: determining the number of expansion boards that the logic verification unit needs to be cascaded based on the size of the target chip.

[0014] According to one embodiment of this disclosure, the logic verification unit further includes: connecting the board to be connected via an FMC connector.

[0015] According to one embodiment of this disclosure, the logic verification unit further includes: using the Aurora protocol as the inter-chip communication protocol between any two boards connected in the chip verification system, and using the Aurora IP core as the data transmission protocol between Chip2Chip IP cores.

[0016] According to one embodiment of this disclosure, the peripheral unit includes: a plurality of general interfaces for connecting to functional modules that need to be verified.

[0017] According to one embodiment of this disclosure, the general interface supports a bus protocol, and the functional module is provided with a connection port adapted to the general interface.

[0018] According to one embodiment of this disclosure, the chip verification system is further configured to: receive a test request sent by the host computer; determine the target functional module to be verified based on the test request; and delete or add a new target functional module based on the target functional module to the functional modules already connected to the peripheral unit.

[0019] According to one embodiment of this disclosure, the application processing unit uses a ZC706 board, and the development board and expansion board of the logic verification unit are VU13P boards.

[0020] To achieve the above objectives, a third aspect of this disclosure provides a chip verification platform, comprising: a host computer, a chip verification system as described in the first aspect embodiment, and a peripheral system. The host computer is connected to the chip verification system, the chip verification system is connected to the peripheral system, and the chip verification system is connected to a target chip. The host computer generates test stimulus sources and test requests, and sends them to the chip verification system. The chip verification system verifies the target chip based on the test stimulus sources and test requests, and feeds back the verification data to the host computer. The host computer is also used to determine the correctness of the corresponding detection function of the target chip based on the verification data. The peripheral system includes multiple detection devices, used to display reference sources and observation data of the target chip during the verification process in the chip verification system.

[0021] Therefore, by identifying the target functional modules to be added and the boards to be expanded based on the target functions to be verified, and by modifying the chip verification system, compared with the non-modular verification systems in the current technology, it is not necessary to rebuild a new verification system for each verification, which reduces verification costs and improves verification efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a chip verification method according to one embodiment of the present disclosure.

[0023] Figure 2 This is a schematic diagram of the structure of a chip verification system according to one embodiment of the present disclosure;

[0024] Figure 3 This is a schematic diagram illustrating the connection principle of the Chip2Chip IP core disclosed in this publication;

[0025] Figure 4 This is a schematic diagram of the structure of a chip verification platform according to one embodiment of the present disclosure. Detailed Implementation

[0026] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0027] The acquisition, storage, use, and processing of data in this disclosed technical solution all comply with the relevant provisions of relevant laws and regulations.

[0028] Figure 1 This is a schematic diagram of a chip verification method according to one embodiment of the present disclosure, the method including:

[0029] S101, Obtain the test request, and determine the target function of the target chip that needs to be verified based on the test request.

[0030] It should be noted that the test requests in this disclosure can be manually entered by testers or automatically generated based on actual test requirements; no restrictions are imposed here.

[0031] It should be noted that the functional modules in this embodiment are functional modules that need to be verified. The chip verification system may have multiple functional modules, and pre-designed functional modules may be connected to the chip verification system based on design needs.

[0032] Each functional module can be designed, verified, and debugged independently, allowing the entire chip verification system to be customized and adjusted according to needs. When new functions need to be added or the verification process needs to be adjusted, only the corresponding modules need to be modified or replaced, without requiring a complete overhaul of the entire chip verification system. For example, when it is necessary to verify the chip's ability to read memory cards, the functional module corresponding to verifying memory card reading can be connected to the chip verification system to realize the verification of the chip's ability to read memory cards.

[0033] S102, based on the target function, determine whether the target function module is connected to the chip verification system, and determine whether the logic resources of the chip verification system meet the verification of the target function of the target chip, wherein the target function module is used to verify the target function of the target chip.

[0034] It should be noted that the chip verification system proposed in this disclosure is a type that can cascade boards and functional modules. Compared with the non-modular verification systems in the current technology, it does not require rebuilding a new verification system for each verification, thereby reducing verification costs and improving verification efficiency.

[0035] It should be noted that logical resources refer to abstract resources used in computer science, software engineering, and information technology to describe and implement logical functions. These resources differ from physical resources (such as CPU, memory, and disk space); they focus on describing non-physical components such as functional modules, algorithms, protocols, data structures, and interfaces in a system or program.

[0036] In this embodiment of the disclosure, the logic resources of the board are limited, and the existing logic resources of the chip verification system may not be able to meet the verification of the target function. In this case, it is necessary to expand the logic resources of the chip verification system by expanding the board.

[0037] S103, in response to the absence of the target functional module in the chip verification system, add the target functional module to the chip verification system, and / or in response to the inability of the logic resources of the chip verification system to meet the verification of the target function, expand the board of the chip verification system.

[0038] S104, until the target function module is added to the chip verification system and the logic resources of the chip verification system meet the verification of the target function, the target function of the target chip is verified through the chip verification system based on the test request.

[0039] In this embodiment, a test request is first obtained. Based on the test request, the target function of the target chip to be verified is determined. Then, based on the target function, it is determined whether a target function module is connected to the chip verification system, and whether the logic resources of the chip verification system meet the verification requirements of the target function of the target chip. The target function module is used to verify the target function of the target chip. If the target function module is not present in the chip verification system, it is added to the chip verification system. And / or if the logic resources of the chip verification system do not meet the verification requirements of the target function, the chip verification system is expanded with additional boards until a target function module is added to the chip verification system and the logic resources of the chip verification system meet the verification requirements of the target function. Based on the test request, the target function of the target chip is verified through the chip verification system. Therefore, by determining the target function to be added and the boards to be expanded based on the target function to be verified, and by modifying the chip verification system, compared to the non-modular verification systems in the current technology, it is not necessary to rebuild a new verification system for each verification, thus reducing verification costs and improving chip verification efficiency.

[0040] In this embodiment of the disclosure, the chip verification system is expanded by first determining the number of expansion boards that need to be cascaded for the logic verification unit based on the size of the target chip, and then connecting the required number of boards through the expansion board standard (FPGA Mezzanine Card, FMC) connector.

[0041] In this embodiment of the disclosure, the Aurora protocol can be used as the inter-chip communication protocol between any two boards connected in the chip verification system, and the Aurora IP core can be used as the data transmission protocol of the Chip2Chip Internet Protocol (IP) core.

[0042] It's important to note that the Aurora protocol is a scalable, lightweight link-layer protocol for moving data between point-to-point serial links. This provides a transparent interface to the physical layer, allowing proprietary or industry-standard protocols to easily utilize high-speed transceivers. Despite using very few logical resources, Aurora offers low latency, high bandwidth, and a highly configurable feature set. Therefore, by using the Aurora protocol as the inter-chip communication protocol for connected boards, and by using the Aurora IP core as the data transmission protocol for Chip2Chip IP cores, the format and order of data transmission can be standardized. Furthermore, data transmission based on the Aurora protocol can significantly improve transmission speed.

[0043] Figure 2 This is a schematic diagram of the structure of a chip verification system according to one embodiment of the present disclosure, as shown below. Figure 2 As shown, the chip verification system includes an application processing unit 210, a logic verification unit 220, and a peripheral unit 230. The application processing unit 210, the logic verification unit 220, and the peripheral unit 230 are connected in pairs. The application processing unit 210 is connected to the host computer, and the logic verification unit 220 is connected to the chip to be verified.

[0044] The application processing unit 210 is used to receive the test stimulus source sent by the host computer, and after preprocessing the test stimulus source, send it to the logic verification unit 220.

[0045] It should be noted that preprocessing can take many forms, and no specific limitations are made here. For example, filtering and compensation can be performed on the test excitation source.

[0046] The logic verification unit 220 includes at least one development board. The development board is cascaded with a Chip2Chip IP core to provide logic resources for the chip to be verified, so as to realize the design of the chip to be verified.

[0047] It's important to note that an Intellectual Property Core (IP core) incorporates commonly used but complex functional blocks in digital circuits, such as fine-tuned impulse responses (FIRs), synchronous dynamic random-access memory (SDRAM) controllers, and peripheral component interconnect (PCI) interfaces, into modules with modifiable parameters. As complex programmable logic devices (CPLDs) / FPGAs become increasingly larger and more complex, designers' primary task is to complete these complex designs within a specified timeframe. Utilizing IP cores avoids repetitive work, significantly reducing the burden on engineers. Therefore, using IP cores is a growing trend, and the reuse of IP cores greatly shortens time-to-market.

[0048] It should be noted that the Chip2Chip IP core in this embodiment is the IP core proposed in this disclosure for realizing the interconnection between chips.

[0049] like Figure 3 As shown, the Chip2Chip IP core functions as a bridge, seamlessly connecting board 1 and board 2 via an AXI interface. The core transparently connects transactions conforming to the AXI protocol specification. The bridging function between board 1 and board 2 allows all AXI channels to operate independently, ensuring a valid AXI handshake for each channel by forwarding data and control information.

[0050] The Chip2Chip IP core enables data transfer between two connected boards, meeting the chip's demand for large-scale logic resources.

[0051] In this embodiment of the disclosure, the number of expansion boards that the logic verification unit 220 needs to be cascaded can be determined based on the size of the chip to be verified.

[0052] In one possible implementation, the application processing unit 210 uses a ZC706 board, and the development board and expansion board of the logic verification unit 220 are VU13P boards.

[0053] The chip verification system may include one ZC706 board, two VU13P development boards, and simultaneously support three expandable VU13P expansion boards. This allows for the increase of logic resources based on verification requirements, meeting the verification needs of large-scale chips and enhancing the practicality of the chip verification system disclosed herein.

[0054] In this embodiment of the disclosure, the boards to be connected are connected through the FMC connector, wherein the boards to be connected include development boards and expansion boards, expansion boards and expansion boards, or development boards and development boards.

[0055] In this embodiment of the disclosure, the Aurora protocol is used as the inter-chip communication protocol of the boards that need to be connected, and the Aurora IP core is used as the data transmission protocol of the Chip2Chip IP core. The boards that need to be connected include development boards and expansion boards, expansion boards and expansion boards, and development boards and development boards.

[0056] In this embodiment, the peripheral unit 230 is connected to at least one functional module. The peripheral unit is used to cooperate with the functional module to provide input or output. The peripheral unit 230 mainly includes an external RF daughter card and an interface expansion daughter card. By connecting to the functional module, the correctness of the chip's functional design can be verified through the functional unit.

[0057] It should be noted that the functional modules in this embodiment are functional modules that need to be verified. The chip verification system may have multiple functional modules, and the designed functional modules may be connected to the peripheral unit 230 according to the design requirements.

[0058] Each functional module can be designed, verified, and debugged independently, allowing the entire platform to be customized and adjusted according to needs. When new functions need to be added or the verification process needs to be adjusted, only the corresponding modules need to be modified or replaced, without having to completely change the entire platform. For example, when it is necessary to verify the chip's ability to read memory cards, the functional module corresponding to verifying the reading of memory cards can be connected to the peripheral unit 230 to realize the verification of the chip's ability to read memory cards.

[0059] Meanwhile, by dividing the various functions of the massive chip verification system into modules with unified interfaces, the verification platform's functions are modularized. Clearly defined and standardized interfaces between modules help reduce errors and conflicts during the integration process, thereby improving the overall system's reliability and stability.

[0060] In this embodiment of the disclosure, a test request sent by a host computer can be received, and then the target functional module that needs to be verified can be determined based on the test request. Based on the target functional module, the functional modules that have been connected to the peripheral unit 230 can be deleted, or a new target functional module can be added.

[0061] The universal interface supports bus protocols, and functional modules are equipped with connection ports adapted to this universal interface. This bus protocol can be various, such as Advanced High-performance Bus (AHB) or Advanced Peripheral Bus (APB). This allows the large-scale System-on-a-Chip (SoC) verification platform to be divided into modules with a unified interface, thus achieving modularity. Various functional modules can be quickly and easily connected to the verification platform through this unified interface, enabling comprehensive verification of all modules of the terminal chip, including functional testing, performance testing, and communication testing. Flexible connection and routing configurations are possible, allowing for the construction of suitable communication topologies based on specific application requirements to meet the communication needs between different modules. This modular design makes the system easier to expand and maintain, while also improving system reusability.

[0062] Therefore, the chip verification system in this disclosure can achieve high-speed serial communication and high-speed data transmission between multiple boards through the Chip2Chi p IP core. It provides a reliable data transmission mechanism, can cope with high-speed and complex communication requirements, has a high data transmission rate and low latency, and is suitable for chip verification with high bandwidth and real-time requirements. By cascading multiple boards, the logic resources can be multiplied to meet the verification of large-scale chips. At the same time, the peripheral unit 230 supports the free addition and deletion of various functional modules, which can meet different verification requirements and increase the practicality of the chip verification system.

[0063] It should be noted that the development tool for the chip verification system in this disclosure can be the Vivado design kit. The Vivado design kit adopts Electronic System Level (ESL) design for rapid synthesis and verification of C language algorithm IP, realizes reusable standard algorithms and Register Transfer Level (RTL) IP packaging technology, standard IP packaging and system integration of various system building blocks, improves the simulation speed of module and system verification, and also greatly improves hardware co-simulation performance.

[0064] Vivado employs a hierarchical device editor and place planner, and provides SystemVerilog with supported logic synthesis tools, a highly deterministic place-and-route engine, and a "cost" function that minimizes multiple variables such as timing, trace length, and routing congestion through analysis techniques. Furthermore, its incremental workflow allows any modifications to engineering change orders to be processed quickly by reimplementing only a small portion of the design, ensuring no performance impact. By leveraging the latest shared scalable data models, Vivado can estimate power consumption, timing, and footprint at various stages of the design flow, enabling pre-analysis and subsequent optimization of integration functions such as automated clock gates.

[0065] Figure 4 This is a schematic diagram of the structure of a chip verification platform according to one embodiment of the present disclosure, as shown below. Figure 4 As shown, the chip verification platform includes: a host computer 410, a chip verification system 420, and a peripheral system 430. The host computer 410 is connected to the chip verification system 420, the chip verification system 420 is connected to the peripheral system 430, and the chip verification system 420 is connected to the chip to be verified.

[0066] Among them, the chip verification system 420 is as follows Figure 1 The chip verification system 420 shown is shown.

[0067] In this embodiment of the disclosure, the host computer 410 is used to generate test stimulus sources and test requests, and send them to the chip verification system 420.

[0068] It should be noted that the host computer 410 can be of various types, without any limitation here. For example, it can be a personal computer, mobile phone, server, etc. The host computer 410 can develop and test applications, or it can receive pre-developed test applications; there are no limitations here.

[0069] In one possible implementation, the host computer 410 communicates with the chip verification system 420 via a Joint Test Action Group (JTAG) or a Universal Asynchronous Receiver / Transmitter (UART) to load programs and issue commands.

[0070] The chip verification system 420 is used to verify the chip to be verified based on the test stimulus source and test request, and to feed back the verification data to the host computer 410.

[0071] The host computer 410 is also used to determine the correctness of the detection function corresponding to the chip to be verified based on the verification data.

[0072] Peripheral system 430 includes multiple detection devices used to display reference sources and observation data during the verification process of the chip to be verified in chip verification system 420. It should be noted that the detection devices are responsible for capturing and analyzing the output signals and can include various types, without any limitation here. For example, detection devices may include spectrum analyzers, oscilloscopes, bit error rate analyzers, and other test instruments.

[0073] After receiving the verification request, the number of expansion boards that need to be cascaded for the logic verification unit of the chip verification system 420 and the target functional modules that need to be verified can be determined based on the test request. Then, the chip verification system 420 is configured based on the number of expansion boards that need to be cascaded and the target functional modules that need to be verified.

[0074] To implement the above embodiments, this disclosure also proposes a non-transitory computer-readable storage medium storing computer instructions, which is used to store, for example... Figure 2 The verification data of the chip verification system shown, or stored as such Figure 4 The observation data and verification data of the chip verification platform shown are presented.

[0075] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program that, when executed by a processor, implements a test program for a chip verification platform as described in Embodiment 4 of this disclosure.

[0076] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0077] This application is intended to provide an implementation scheme for users to selectively prevent the use or access to their personal information data. Specifically, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information is de-identified to protect user privacy.

[0078] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0079] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0080] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0081] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0082] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0083] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0084] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each unit can exist physically separately, or two or more units can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0085] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A chip verification method characterized by, The method comprises the following steps: acquiring a test request, and determining a target function of a target chip that needs to be verified based on the test request; determining whether a target function module is connected on a chip verification system based on the target function, and determining whether logical resources of the chip verification system meet verification of the target function of the target chip, wherein the target function module is used for verifying the target function of the target chip; in response to the chip verification system not having the target function module, adding the target function module on the chip verification system, and / or in response to the logical resources of the chip verification system not meeting the verification of the target function, performing board card expansion on the chip verification system; until the target function module is added on the chip verification system and the logical resources of the chip verification system meet the verification of the target function, verifying the target function of the target chip based on the test request through the chip verification system.

2. The method of claim 1, wherein, The board card expansion on the chip verification system comprises the following steps: determining the number of board cards that need to be connected based on the scale of the target chip; connecting the board cards through an FMC connector.

3. The method of claim 1, wherein, The board card expansion on the chip verification system comprises the following steps: cascading the expansion board cards that need to be expanded through a Chip2Chip IP core.

4. The method of claim 3, wherein, An Aurora protocol is used as an inter-chip communication protocol of any two board cards connected in the chip verification system, and an Aurora IP core is used as a data transmission protocol of the Chip2Chip IP core.

5. A chip verification system characterized by comprising: The system comprises the following steps: an application processing unit, a logic verification unit and a peripheral unit, wherein the application processing unit, the logic verification unit and the peripheral unit are connected in pairs, the application processing unit is connected with a host computer, and the logic verification unit is connected with a target chip; the application processing unit is used for receiving a test stimulus source sent by the host computer, and sending the test stimulus source to the logic verification unit after preprocessing the test stimulus source; the logic verification unit comprises at least one development board card, the development board card is cascaded with an expansion board card through a Chip2Chip IP core, and provides logical resources for the target chip to realize design of the target chip; the peripheral unit is connected with at least one function module, and the peripheral unit is used for providing input or output in cooperation with the function module; the logic verification unit is further used for performing function verification on the target chip based on the function module and the test stimulus source; the application processing unit is further used for receiving verification data generated in the process of verifying the target chip by the logic verification unit, preprocessing the verification data, and sending the verification data to the host computer for analysis and processing.

6. The chip verification system of claim 5, wherein, The system further comprises the following steps: determining the number of expansion board cards that need to be cascaded by the logic verification unit based on the scale of the target chip.

7. The chip verification system of claim 6, wherein, The logic verification unit further comprises the following steps: connecting the board cards through an FMC connector.

8. The chip verification system of claim 6, wherein, The logic verification unit further comprises the following steps: The Aurora protocol is used as an inter-chip communication protocol for any two board cards connected in the chip verification system, and the Aurora IP core is used as a data transmission protocol of the Chip2Chip IP core.

9. The chip verification system of claim 5, wherein, The peripheral unit comprises: A plurality of general interfaces are configured to connect the functional modules to be verified.

10. The chip verification system of claim 9, wherein, The general interface supports a bus protocol, and the functional module is provided with a connection port adapted to the general interface.

11. The chip verification system of claim 9, wherein, The chip verification system is further configured to: receive a test request sent by the host computer; determine a target functional module to be verified based on the test request, delete the functional modules already connected to the peripheral unit based on the target functional module, or add a new target functional module.

12. The chip verification system of claim 5, wherein, The application processing unit is a ZC706 board card, and the development board card and the expansion board card of the logic verification unit are VU13P board cards.

13. A chip verification platform, characterized by Comprise: a host computer, the chip verification system and the peripheral system as claimed in any one of claims 5-12, the host computer being connected to the chip verification system, the chip verification system being connected to the peripheral system, and the chip verification system being connected to a target chip; wherein the host computer is configured to generate a test stimulus source and a test request, and deliver them to the chip verification system; the chip verification system is configured to verify the target chip based on the test stimulus source and the test request, and feed back verification data to the host computer; the host computer is further configured to determine the correctness of the detection function corresponding to the target chip based on the verification data; the peripheral system comprises a plurality of detection devices, and is configured to display reference sources and observation data of the target chip in the process of verification in the chip verification system through the detection devices.

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