Field programmable gate array (FPGA)-based one-by-one market information back-stepping real-time order system

Abstract

The invention relates to the technical field of back-stepping real-time orders of market-by-market information, in particular to a back-stepping real-time order system of market-by-market information based on an FPGA (Field Programmable Gate Array). The method comprises the following steps: a network protocol processing unit receives original market information data packets of an exchange for parallel processing, and adopts an order-preserving processing mechanism on the market information data packets; the market information analysis unit analyzes the piece-by-piece market information data based on the market information data packet of the network protocol processing unit, and extracts key information required for constructing an order queue; the order construction unit constructs an order queue model of the buyer and the seller based on the information extracted by the market information analysis unit; and the data control unit provides customized data index, frequency and gear control through the order queue model of the order construction unit, and pushes the processed high-quality order data in real time. According to the design of the invention, an FPGA + software heterogeneous model architecture is utilized, and nanosecond delay is formed in a full link.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of real-time order system based on FPGA, and particularly relates to a real-time order system based on FPGA. BACKGROUND

[0002] In financial market transactions, data processing speed is crucial. Traditional CPU-based systems may have latency issues when processing large amounts of high-frequency data, making it difficult to meet nanosecond or microsecond level low latency requirements, which will affect the speed and accuracy of trading decisions, especially in the field of high-frequency trading, where data throughput is extremely large, and traditional server architecture may have difficulty handling such large data streams; different investors and institutions have different needs, including data indicators, update frequency and market position, and traditional systems may not support custom configurations; market data in the financial market changes very quickly and needs to be processed in real time to seize the best trading opportunities. Therefore, a real-time order system based on FPGA is designed. SUMMARY

[0003] The purpose of the present application is to provide a real-time order system based on FPGA, to solve the low latency requirement, high throughput, real-time low, and inability to support configuration problems raised in the background.

[0004] To achieve the above purpose, the present application provides a real-time order system based on FPGA, which comprises a network protocol processing unit, which receives raw market data packets from the exchange for parallel processing, and uses a sequence-preserving processing mechanism for market data packets; a market analysis unit, which analyzes the market data based on the network protocol processing unit and extracts the key information required to build the order queue; an order construction unit, which constructs the order queue model of the buyer and seller based on the information extracted by the market analysis unit; a data control unit, which provides custom data indicators, frequency and position control through the order queue model of the order construction unit, and pushes the processed high-quality order data in real time.

[0005] As a further improvement of the present technical solution, the key information required to build the order queue includes the following steps: S1.1, analyze the fields in the market data packet, including timestamp, security code, price, quantity, and buy / sell direction, each field corresponds to different market activities, including new quotes, order modifications and cancellations; S1.2, extracting the key information required for constructing the order queue based on the field parsing algorithm, the key information including market type, tick type, order direction, current tick sequence number, channel number, order quantity and price, time; S1.3, verifying the checksum of the data through the Fletcher checksum algorithm, for ensuring the consistency and validity of the data; S1.4, encapsulating the extracted key information into an event object and passing it to the order construction unit.

[0006] As a further improvement of the technical solution, in S1.4, the Fletcher checksum algorithm is specifically: ; ; ; wherein Checksum is the value calculated by the Fletcher checksum algorithm; each field in the market data packet; n represents the number of fields contained in a market data packet; m is 255; the sum of all fields in the market data packet after being mod m; represents plus each data segment , and the sum of the results of mod m.

[0007] As a further improvement of the technical solution, the order queue model of the buying and selling parties is constructed, including the following steps: S2.1, creating an empty order book structure for storing orders of the buying and selling parties, and defining a state machine to manage the state of the order book, including insertion, deletion, and update; S2.2, receiving the sent tick order and tick transaction data output from the market parsing unit; S2.3, classifying orders according to order type and buying and selling direction and introducing a price cage mechanism; S2.4, arranging the buy orders in descending order of price and the sell orders in ascending order of price, using the interpolation search algorithm to find the correct position of the new order, inserting the new order at the found position, and updating the order book; S2.5, when receiving an order modification event, updating the corresponding order in the order book according to the new information in the event; S2.6, updating the state of the order book according to the tick transaction data, reducing the number of matched orders, and deleting the order if the number is zero; S2.7, continuously maintaining the state of the order queue, to ensure that the state of the order queue is always up-to-date.

[0008] As a further improvement of the technical solution, in S2.3, the price cage mechanism is specifically: ; ; ; Wherein, minPrice represents the minimum bid price; maxPrice represents the maximum bid price; bidPrice represents the bid price; lastPrice represents the previous transaction price.

[0009] As a further improvement of the technical solution, in S2.4, the interpolation search algorithm is specifically: ; Wherein, pos represents the predicted position of the new order insertion; represents the starting index of the current search interval; high represents the end index of the current search interval; represents the price of the new order; represents the sorted order array.

[0010] As a further improvement of the technical solution, the data control unit includes a data padding module, a data pushing module, a custom data index module, an output frequency control module, an output gear control module, and an abnormal data management module. Wherein, the data padding module is used to judge whether there is data loss, if there is data loss, a retransmission request is initiated to the market gateway, and the data recovered is used to ensure the integrity of the constructed order; The data pushing module is used to send the processed order data to the receiving end in the form of UDP multicast; The custom data index module provides user-defined data index options, and pushes the corresponding data index according to the user's configuration; The output frequency control module allows users to customize the data pushing frequency, to support real-time pushing and interval pushing; The output gear control module is used to support user-defined order queue gear range for pushing; The abnormal data management module introduces an exception handling mechanism to mark abnormal data and alarm in time.

[0011] As a further improvement of the technical solution, the output gear control module is used to support user-defined order queue gear range for pushing, including the following steps: S3.1, initialize the state of the system, including the order book and other related variables; S3.2, allowing the user to set the frequency of interval packet sending through an external interface, if the frequency set by the user is not within the valid range, the default value is used; S3.3, check whether the frequency set by the user is within the valid range, and enable the interval push function; S3.4, start a timer according to the frequency set by the user, and push data every time the timer triggers; S3.5, receive and process the data of each order and transaction, and update the state of the order book; S3.6, update the state of the order book according to the data of each order and transaction, and continuously maintain the state of the order book to ensure that the data is up-to-date.

[0012] As a further improvement of the technical solution, the S3.2 allows the user to set the frequency of interval packet sending through an external interface, comprising the following steps: S3.21, determine the valid frequency range that the system can accept; S3.22, allow the user to input the set packet sending frequency through API call; S3.23, when the user tries to set a new packet sending frequency, the system receives the new packet sending frequency input; S3.24, verify the frequency input by the user, check whether the frequency falls within the defined valid range; S3.25, if the frequency input by the user is within the valid range, apply the new setting and update the packet sending interval of the system, if the frequency input by the user is out of the valid range, ignore the setting and use the preset default frequency; S3.26, return the corresponding status code and message after the user completes the setting.

[0013] As a further improvement of the technical solution, the abnormal data is marked and an alarm is generated in time, comprising the following steps: S4.1, initialize the internal state of FPGA, including the current sequence number and the abnormal flag; S4.2, allow the user to set whether to continue receiving suspicious data through an external interface; S4.3, receive the data of each order and transaction, and extract the sequence number therefrom; S4.4, compare the current sequence number with the previous sequence number to determine whether they are consecutive; S4.5, if data loss is found, mark the abnormal data; S4.6, generate an abnormal message and distribute it in real time; S4.7, decide whether to continue forwarding suspicious data according to the user configuration.

[0014] Compared with the prior art, the present application has the following advantages: 1. This FPGA-based real-time order system for reverse-engineering market data uses FPGA hardware acceleration technology. Especially in the decoding and processing stage of market data packets, it utilizes the parallel processing capability of FPGA, enabling the system to complete the decoding and parsing of large amounts of data in a very short time. It uses a heterogeneous model architecture of FPGA + software, achieving nanosecond-level latency across the entire link. In addition, the Fletcher checksum algorithm ensures data consistency and validity, reducing processing delays and resource waste caused by data errors, thereby improving the overall system response speed and reliability.

[0015] 2. In this FPGA-based real-time order system that uses tick-by-tick market data to deduce orders, the built-in data control unit provides a variety of functional modules, such as customizable data indicators, frequency, and level control. This not only allows users to adjust the data push method and content according to their own needs, but also adapts to the data processing requirements under different market conditions. For example, users can select different data push frequencies and order queue display levels according to their trading strategies. At the same time, the abnormal data management module can promptly detect and process abnormal data, ensuring the accuracy and timeliness of trading decisions. Attached Figure Description

[0016] Figure 1 This is an overall flowchart of the present invention; The meanings of the labels in the diagram are as follows: 1. Network protocol processing unit; 2. Market data analysis unit; 3. Order building unit; 4. Data control unit. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example

[0018] Please see Figure 1 As shown, a real-time order derivation system based on FPGA-based tick-by-tick market data is provided, including... Network protocol processing unit 1 receives raw market data packets from the exchange and processes them in parallel, and adopts an order-preserving processing mechanism for the market data packets; In this embodiment, the market data packet includes a MAC header, an IP header, a transport protocol header, a data packet portion, and a trailer. The data packet portion includes market data categories such as order placement, trade execution (trade execution, after-hours fixed-price trade execution), and snapshot data (market overview data, index data, auction data, after-hours fixed-price trading data). The order preservation mechanism is used to ensure that although data packets may be out of order during network transmission (due to network congestion, latency differences between different paths, etc.), the data ultimately delivered to the application is still arranged in the order of transmission. The process involves decoding the received ordered data packets, which may contain binary data that needs to be converted into readable information. First, a portion of the data is filtered based on the IP address. Then, the order and transaction data are extracted based on the market data category MsgType. The parallel processing capability of the FPGA is used to accelerate the decoding process and ensure that the data packets are processed in order.

[0019] Market data parsing unit 2 parses tick-by-tick market data based on the market data packets of network protocol processing unit 1, and extracts the key information required to construct the order queue; In this embodiment, the key information required to construct the order queue is extracted, including the following steps: S1.1 Parse the fields in the data packet. The fields include timestamp, security code, price, quantity, and buy / sell direction. Each field corresponds to different market activities, including new quotes, order modifications, and cancellations. S1.2 Extract the key information required to construct the order queue based on the field parsing algorithm. The key information includes market type (main board, growth enterprise board), tick data type (market order, limit order, best order, executed, cancelled order), buy / sell direction of the order, current tick number (if it is executed or cancelled, the original tick number of the execution or cancellation will also exist), channel number, order, quantity and price of the executed order, and time. The field parsing algorithm first needs to receive raw market data from exchanges or other data providers. This data is usually provided via API interfaces and may be in text format (such as JSON or XML) or binary format. If the data is transmitted in encoded form, it needs to be decoded and converted into a readable format. Next, the algorithm extracts the required fields according to the data format definition. The data is then validated to ensure that the extracted fields conform to the expected format. Finally, the extracted information is stored in a data structure for further processing and analysis. S1.3 The checksum of the data is verified using the Fletcher checksum algorithm to ensure the consistency and validity of the data, including checking whether the price is reasonable and whether the quantity is within the allowable range. The Fletcher checksum algorithm is relatively simple to compute, easy to understand and implement. This allows it to run efficiently in resource-constrained environments (such as embedded systems or FPGAs). It uses two independent accumulators, increasing the probability of detecting errors. In FPGA-based environments, the Fletcher checksum algorithm is well-suited for parallel processing. FPGAs can implement multiple accumulators to work simultaneously through hardware logic, thereby accelerating the checksum calculation process. This is particularly important for real-time systems, as they need to process large amounts of data in a very short time. The Fletcher checksum algorithm is as follows: ; ; ; The Checksum, calculated using the Fletcher checksum algorithm, is used to ensure that the data packets received from the network protocol processing unit are free from errors during transmission. This represents each field in the data packet; n represents the number of fields contained in a data packet; m is 255, which is a modulus used to limit the size of intermediate calculation results; The result modulo m after summing all fields in the data packet; express Add each data segment The sum of the results modulo m further improves the ability to detect sudden errors.

[0020] S1.4. The extracted key information is encapsulated into event objects and passed to the order building unit (3). These objects contain all the necessary information for the next step of processing.

[0021] Order building unit 3 constructs an order queue model for both buyers and sellers based on the information extracted by market analysis unit 2; In this embodiment, constructing an order queue model for both buyers and sellers includes the following steps: S2.1 Create an empty order book structure to store orders from both buyers and sellers. Define a state machine to manage the state of the order book, including insertion, deletion, and update. S2.2 Receive the order and transaction data sent from the market data analysis unit (2); S2.3 Classify orders according to order type (limit order or market order) and buy / sell direction (buy order or sell order) and introduce a price collar mechanism; The price collar mechanism is a system used to limit the range of price fluctuations in orders, designed to prevent market manipulation and excessive volatility. Specifically, the price collar mechanism sets a price range for each order; only price movements within this range are valid. The price collar mechanism helps stabilize market prices and reduces drastic price fluctuations caused by sudden large orders or market sentiment. By limiting the range of price fluctuations, the price collar mechanism can prevent investors from suffering losses due to irrational price movements under extreme market conditions. The price collar mechanism is specifically as follows: ; ; ; In the formula, minPrice represents the lowest bid price; maxPrice represents the highest bid price; bidPrice represents the bid price; and lastPrice represents the previous transaction price.

[0022] S2.4 Buyer orders are sorted in descending order of price, and seller orders are sorted in ascending order of price. An interpolation search algorithm is used to find the correct position of a new order, the new order is inserted at the found position, and the order book is updated. Interpolation search algorithm is an improved search algorithm that utilizes the distribution relationship between the search value and the elements in the array for searching. For large datasets, interpolation search algorithm can significantly reduce the number of comparisons required for searching, improving search efficiency. In FPGA environments, memory access is often a bottleneck; interpolation search algorithm can reduce memory access by reducing the number of comparisons, thereby improving overall performance. FPGAs can utilize hardware parallelism to implement multiple interpolation search operations, further accelerating the search process. In multi-core or multi-threaded environments, interpolation search can be executed in parallel, further improving performance. The specific interpolation search algorithm is as follows: ; Where pos represents the predicted position where the new order will be inserted; `high` indicates the starting index of the current search interval; `high` indicates the ending index of the current search interval. This indicates the price of the new order, i.e., the value being searched for; This represents a sorted array of orders.

[0023] S2.5 When an order modification event is received, update the corresponding order in the order book according to the new information in the event; S2.6. Based on the transaction data, update the status of the order book and reduce the number of matched orders. If the number is zero, delete the order. S2.7 Continuously maintain the state of the order queue to ensure that the state of the order queue is always up-to-date.

[0024] The data control unit 4 provides customized data metrics, frequency, and level control through the order queue model of the order building unit 3, and pushes high-quality processed order data in real time; In this embodiment, the data control unit 4 includes a data completion module, a data push module, a custom data indicator module, an output frequency control module, an output gear control module, and an abnormal data management module. The data completion module is used to determine whether there is any data loss. If there is data loss, it sends a retransmission request to the market data gateway to obtain the replenished data to ensure the integrity of the constructed order. Furthermore, the FPGA obtains the business sequence number of each data entry and compares it with the previous sequence number. It determines whether there is data loss based on whether the sequence numbers are consecutive. If there is data loss, it sends a retransmission request to the market data gateway to obtain the supplementary data to ensure the integrity of the constructed order. The data push module is used to send the processed order data to the receiving end via UDP multicast; Furthermore, the FPGA sends the processed data out in the form of UDP multicast and pushes it to the switch to provide the receiving end's strategy program with order data that restores market conditions; The custom data metrics module provides users with options for custom data metrics, including the latest price and transaction volume statistics, and pushes the corresponding data metrics according to the user's configuration; Furthermore, the custom data indicator module introduces various indicators such as the latest price and trading volume statistics. Users can customize and select the data indicators they need for delivery, eliminating the need for complex basic processing of individual data. FPGA order data can be directly applied to market review, strategy construction, strategy backtesting, and trade execution, improving the efficiency of user data utilization. The output frequency control module allows users to customize the frequency of data push, supporting real-time push and interval push. Furthermore, the output gear control module is used to support user-defined order queue gear ranges, including the following steps: S3.1 Initialize the system state, including the order book and other relevant variables; S3.2 Allow users to set the frequency of packet transmission intervals through an external interface. If the frequency set by the user is not within the valid range, the default value will be used. The interval packet sending setting ranges from 100ms to 3s, allowing users to customize the output frequency within this range. If the setting is less than 100ms, the interval push function will not be enabled, and the FPGA will push orders in real time according to individual messages. After the interval packet sending function is enabled, the system will not immediately push packets; it will only begin pushing packets at the set interval once market data is entered at the opening bell. Users can set the interval packet sending frequency via an external interface, including the following steps: S3.21 Determine the effective frequency range that the system can accept. If the system requires a minimum packet interval of 1 second and a maximum of 60 seconds, then the effective range is between 1 and 60 seconds. S3.22. Allow users to input and set the packet sending frequency via API calls; S3.23 When a user attempts to set a new packet transmission frequency, the system receives the new packet transmission frequency input; S3.24. Validate the frequency of user input, check whether the frequency falls within the defined valid range, and use conditional statements to determine whether the value of user input is between 1 and 60 seconds. The conditional statement is specifically as follows: def validate_frequency(user_input): # Define the effective frequency range min_freq = 1 # Minimum packet interval is 1 second max_freq = 60 # Maximum packet sending interval is 60 seconds # Check if the frequency of user input is within the valid range if min_freq<= user_input<= max_freq: return True, "Frequency is valid." else: return False, "Frequency is out of range (must be between 1and 60 seconds)." user_frequency = 10 # User-input frequency value # Verification frequency is_valid, message = validate_frequency(user_frequency) if is_valid: print("Setting new frequency:", user_frequency, "seconds.") else: print(message) S3.25. If the frequency entered by the user is within the valid range, apply this new setting and update the system's packet sending interval; if the frequency entered by the user exceeds the valid range, ignore the setting and use the preset default frequency. S3.26. After the user completes the settings, the corresponding status code and message are returned.

[0025] S3.3 Check if the frequency set by the user is within the valid range (100ms to 3000ms) and enable the interval push function; S3.4 Start the timer according to the frequency set by the user, and push data each time the timer is triggered; S3.5 Receive and process each order and transaction data, and update the status of the order book; S3.6 Update the status of the order book based on each piece of data and continuously maintain the status of the order book to ensure that the data is up-to-date.

[0026] The output gear control module is used to support user-defined gear ranges for pushed order queues; Furthermore, users can customize the range of price levels to be pushed. Once the setting is successful, the FPGA will push the corresponding order queues according to the set price levels. The abnormal data management module introduces an abnormal handling mechanism to mark abnormal data and issue timely alerts; Furthermore, the FPGA compares the seqnum in the received message with the previous message, determines whether data loss has occurred based on the sequence number, marks abnormal data for each lost message, and distributes anomaly messages (including error channel, time, sequence number, etc.) to downstream devices in real time. Alternatively, users can choose whether to continue receiving suspicious data via an anomaly data switch. The process for marking abnormal data and providing timely alarms includes the following steps: S4.1 Initialize the FPGA internal state, including the current serial number and exception flags; S4.2 Allow users to configure whether to continue receiving suspicious data via an external interface; S4.3 Receive each message individually and extract the sequence number from it; S4.4 Compare the current sequence number with the previous sequence number to determine if they are consecutive; S4.5 If data loss is detected, mark the data as abnormal; S4.6 Generate exception messages and distribute them in real time; S4.7. Decide whether to continue forwarding questionable data based on user configuration.

[0027] The system software has been programmed to complete other auxiliary functions: Overall monitoring: The content that can be monitored includes: Availability monitoring, such as primary / standby failover, latency, etc.; Machine performance monitoring, such as CPU utilization, network connection count, system load, etc. Data monitoring: Regularly collect data on changes in market inflows and outflows, and detect abnormal values. Log analysis includes collecting error logs and performing periodic analysis.

[0028] The entire lifecycle of an order is restored: the order records of the Shanghai Stock Exchange and Shenzhen Stock Exchange are restored in real time, depicting the overall picture of the market at any point in time with a frame-by-frame update frequency (related information of all price levels, including order price, order volume, etc.). The entire lifecycle of each order can be recorded through dynamic tracking.

[0029] Personalized subscription: Users can subscribe to all or part of the target data according to their needs, allowing them to receive only the order data they need, reducing the data pressure on the receiving side and improving the latency of the entire link.

[0030] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. An FPGA-based real-time order system based on the line-by-line market reverse, characterized in that: The application relates to a network protocol processing unit (1) which receives original market data packets of a transaction market for parallel processing and adopts a sequence-preserving processing mechanism for the market data packets. A market analysis unit (2) analyzes tick-by-tick market data based on the market data packets of the network protocol processing unit (1) and extracts key information required for constructing an order queue. An order construction unit (3) constructs a buy-sell order queue model based on the information extracted by the market analysis unit (2). A data control unit (4) provides customized data indexes, frequencies and gear controls through the order queue model of the order construction unit (3) and pushes real-time processed high-quality order data. The key information required for constructing the order queue comprises the following steps: 2.The FPGA-based real-time order system for single-pen transaction reverse deduction according to claim 1, characterized in that: S1.1, fields in the market data packet are analyzed, the fields include a timestamp, a security code, a price, a quantity, a buy-sell direction, each field corresponds to different market activities, the market activities include a new quotation, order modification and cancellation; S1.2, key information required for constructing the order queue is extracted based on a field analysis algorithm, the key information includes a market type, a tick-by-tick market type, a buy-sell direction of a commission order, a current tick-by-tick serial number, a channel number, a commission quantity and a price, and a time; S1.3, checksum of the data is verified through a Fletcher checksum algorithm, which is used to ensure the consistency and validity of the data; S1.4, the extracted key information is encapsulated into an event object and delivered to the order construction unit (3). In S1.3, the Fletcher checksum algorithm is specifically as follows: 3.The FPGA-based real-time order system for single-pen transaction reverse deduction according to claim 2, characterized in that: The order queue model of the buy-sell side comprises the following steps: ； ； ； Checksum is a value calculated by Fletcher checksum algorithm; represents each field in the data packet; n represents the number of fields contained in a market data packet; m is 255; the sum of all fields in the market data packet after being taken modulo m; represents each data segment , and the sum of the results after being taken modulo m.

4. The FPGA-based real-time order system of claim 1, wherein: S2.1, an empty order book structure is created and used for storing buy-sell orders, a state machine is defined to manage the state of the order book, and the management state includes insertion, deletion and update; S2.2, received tick-by-tick commission and tick-by-tick transaction data are output from the market analysis unit (2); S2.3, orders are classified according to order types and buy-sell directions and a price cage mechanism is introduced; S2.4, buy-side orders are arranged in descending order of price, sell-side orders are arranged in ascending order of price, an interpolation search algorithm is used to find the correct position of a new order, the new order is inserted into the found position, and the order book is updated; S2.5, when an order modification event is received, corresponding orders in the order book are updated according to new information in the event; S2.6, according to the tick-by-tick transaction data, the state of the order book is updated, the number of matched orders is reduced, and if the number is zero, the order is deleted; S2.7, the state of the order queue is continuously maintained, which is used to ensure that the state of the order queue is always the latest. In S2.3, the price cage mechanism is specifically as follows:

5. The FPGA-based real-time order system of claim 4, wherein: Wherein, minPrice represents the lowest bid price; maxPrice represents the highest bid price; bidPrice represents the bid price; and lastPrice represents the previous transaction price. ； ； ； ​ 6.The FPGA-based real-time order system of single-pen transaction reverse deduction according to claim 4, characterized in that: In S2.4, the interpolation lookup algorithm is specifically as follows: ； wherein pos represents the predicted position of insertion of the new order; represents the start index of the current search interval; high represents the end index of the current search interval; represents the price of the new order; represents the sorted array of orders.

7. The FPGA-based real-time order system of claim 1, wherein: The data control unit (4) comprises a data padding module, a data pushing module, a custom data index module, an output frequency control module, an output gear control module, and an abnormal data management module. The data padding module is configured to determine whether there is data loss, and if so, to initiate a retransmission request to the market gateway to obtain the backfilled data to ensure the integrity of the constructed order. The data pushing module is configured to send the processed order data to the receiving end in the form of UDP multicast. The custom data index module provides user-defined data index options, and pushes the corresponding data index according to the user's configuration. The output frequency control module allows the user to customize the data pushing frequency, supporting real-time pushing and interval pushing. The output gear control module is configured to support user-defined order queue gear range for pushing. The abnormal data management module introduces an exception handling mechanism to mark abnormal data and alarm in a timely manner. 8.The FPGA-based real-time order system of single-pen transaction reverse deduction according to claim 7, characterized in that: The output gear control module is configured to support user-defined order queue gear range for pushing, comprising the following steps: S3.1, initialize the state of the system, including the order book and other related variables; S3.2, allow the user to set the interval packet sending frequency through an external interface, and if the user-set frequency is not within the valid range, use the default value; S3.3, check whether the user-set frequency is within the valid range, and enable the interval pushing function; S3.4, start the timer according to the user-set frequency, and push data at each timer trigger; S3.5, receive and process the individual orders and transaction data, and update the state of the order book; S3.6, update the state of the order book according to the individual data and continuously maintain the state of the order book to ensure that the data is up-to-date. 9.The FPGA-based real-time order system of single-pen transaction reverse deduction according to claim 8, characterized in that: S3.2 allows the user to set the interval packet sending frequency through an external interface, comprising the following steps: S3.21, determine the valid frequency range that the system can accept; S3.22, allow the user to input the set packet sending frequency through API call; S3.23, when the user attempts to set a new packet sending frequency, the system receives the new packet sending frequency input; S3.24, verify the user-input frequency, and check whether the frequency falls within the defined valid range; S3.25, if the user-input frequency is within the valid range, apply the new setting and update the system packet sending interval, and if the user-input frequency exceeds the valid range, ignore the setting and use the pre-set default frequency; S3.26, return the corresponding status code and message after the user completes the setting.

10. The FPGA-based real-time order system of claim 7, wherein: The introduction of the exception handling mechanism for marking abnormal data and timely alarm comprises the following steps: S4.1, initialize the FPGA internal state, including the current sequence number and the exception flag; S4.2, allow the user to set whether to continue receiving suspicious data through an external interface; S4.3, receive individual messages and extract the sequence number therefrom; S4.4, compare the current sequence number with the previous sequence number to determine whether they are consecutive; S4.5, if data loss is found, mark the abnormal data; S4.6, generate an exception message and distribute it in real time. S4.

7. Decide whether to continue forwarding suspect data based on user configuration.

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