Printing visual identification positioning system and method based on dynamic part reconfiguration

Abstract

The invention discloses a printing visual identification positioning system and method based on dynamic part reconfiguration, and belongs to the technical field of industrial machine vision. The system comprises a task management unit, an FPGA chip and a configuration memory. The interior of the FPGA is divided into a static system area and a dynamic reconfigurable function area. Basic services such as image acquisition, data scheduling, reconfiguration control, real-time communication and the like are realized through static region solidification; the dynamic area serves as an algorithm container, and corresponding special visual processing algorithm hardware modules can be dynamically loaded on line according to different printing tasks (different materials and different marks). According to the method, rapid online switching of algorithms is realized by receiving a task instruction, deciding and executing dynamic reconfiguration and switching a data processing path. According to the method, the inherent deterministic processing delay of a hardware pipeline is strictly kept, meanwhile, millisecond-level online reconstruction of the core vision algorithm is successfully realized, and the long-standing technical problem that determinacy and flexibility cannot be achieved at the same time in a high-speed printing vision system is solved.

Description

Technical Field

[0001] This invention relates to the fields of industrial machine vision and embedded programmable logic systems, specifically to a system and method for online visual inspection and positioning of high-speed printing equipment, and in particular to a visual processing system and method capable of dynamically switching processing algorithms online to adapt to printing scenarios with multiple materials and markings. Background Technology

[0002] On high-speed precision packaging and printing production lines, the core task of a vision positioning system is to perform real-time, high-precision identification and positioning of pre-printed micro-positioning marks (such as crosshairs, squares, and dots, typically smaller than 2mm) on the substrate, thereby guiding subsequent precision processing steps such as die-cutting, hot stamping, and embossing. This application scenario places three extremely stringent technical requirements on the vision system: first, extremely high real-time performance, where the total delay from image acquisition to outputting correction commands must be consistently less than one production cycle; second, absolute determinism, where there can be no jitter in the processing delay to ensure precise synchronization with the high-speed motion axis; and third, strong environmental adaptability, requiring the system to stably handle complex and varied substrate materials, including highly reflective gold / silver cardboard, laser paper with diffraction textures, and translucent films, and to identify diverse mark shapes.

[0003] Currently, to meet the first two requirements, the industry generally adopts a fully hardware pipelined solution based on FPGAs. This solution embeds algorithms such as image preprocessing, feature extraction, and coordinate calculation into the FPGA logic, forming a direct channel from the sensor to the actuator, achieving near-physical processing speeds and nanosecond-level timing determinism. However, the fatal flaw of this "fully hardened" solution lies in its extremely rigid algorithms. A fixed algorithm pipeline typically performs optimally only for specific combinations of materials and markings. When the production line switches products, facing new optical characteristics or new marking shapes, the existing system often experiences performance degradation or even failure due to algorithm mismatch. At this point, time-consuming offline algorithm modifications, FPGA logic resynthesis, placement and routing, and overall programming updates are necessary, a process that can take several hours to several days, causing production interruptions and completely failing to meet the demands of modern flexible manufacturing.

[0004] To improve adaptability, another common approach is to use an "industrial computer + image acquisition card" architecture, relying on a general-purpose CPU to run variable software algorithms. While this architecture offers high flexibility, it inevitably introduces uncertainties such as operating system scheduling, memory access, and inter-process communication, resulting in unpredictable fluctuations in overall system latency of tens or even hundreds of milliseconds. This makes it completely unacceptable for the deterministic real-time requirements of high-speed printing. In effect, this approach sacrifices key performance indicators for flexibility.

[0005] Therefore, existing technologies have long faced an irreconcilable core contradiction: how to ensure hardware-level determinism and real-time performance while endowing the system with the algorithmic adaptability to quickly respond to different production tasks. This contradiction has become a key bottleneck restricting the upgrading of high-end printing equipment towards intelligence and flexibility. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] This invention aims to resolve the aforementioned technical contradictions by providing a printing visual recognition and positioning system and method based on dynamic partial reconfiguration. The core concept of this invention lies in innovatively utilizing the dynamic partial reconfiguration characteristics of FPGA chips to construct a heterogeneous architecture of "static platform + dynamic algorithm module" within a single chip. By physically dividing the chip's logic resources into a static system area with permanently fixed functions and one or more online programmable dynamic functional areas, the system can dynamically load complete algorithm hardware modules optimized for different printing scenarios (specific materials and specific markings) into designated areas within milliseconds. This achieves seamless online switching of the core recognition and positioning algorithm without interrupting basic system services or sacrificing processing speed and determinism.

[0008] (II) Technical Solution

[0009] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0010] In a first aspect, the present invention provides a printing visual recognition and positioning system based on dynamic partial reconfiguration.

[0011] S1. Task Parsing and Scheduling Unit: This unit receives production task instructions from the upper-level control system. The instructions include target material type and marker type codes. Based on a preset strategy mapping table, this unit parses out the corresponding target algorithm module identifier and configuration parameter set, and generates dynamic reconfiguration trigger instructions and data flow control instructions.

[0012] S2. Static System Area: Located inside the FPGA chip, its logic functions are permanently fixed after the initial overall configuration, forming a stable and unchangeable operating platform for the system. This area integrates at least:

[0013] High-speed image acquisition interface: Implements the underlying communication protocol with industrial cameras and is responsible for receiving raw image data streams.

[0014] Data Stream Scheduling and Cache Manager: As the central control unit for the internal data path of the system, it guides image data to the currently active processing module according to scheduling instructions, and manages data buffering and bypassing during reconfiguration.

[0015] Dynamic reconfiguration controller: The core hardware logic for performing partial reconfiguration operations. It receives instructions from the task parsing unit and drives the logic reconfiguration of the specified dynamic functional area through the dedicated configuration port inside the FPGA.

[0016] System service and communication core: Provides industrial fieldbus protocol encapsulation and transmission functions for internal chip bus interconnection, external memory access control, and final positioning results.

[0017] S3. At least one dynamically reconfigurable functional area: This is an independent logic region pre-defined and reserved in the FPGA layout plan. This area itself is an "empty socket" and does not possess specific processing functions. When a reconfiguration operation is performed, the reconfiguration controller loads the pre-synthesized and verified local configuration bitstream file corresponding to the target algorithm into this area, instantly instantiating a complete hardware processing pipeline optimized for a specific scenario. This pipeline typically integrates an adaptive image preprocessing submodule and an intelligent marker recognition and localization submodule.

[0018] S4. Non-volatile configuration memory: used to store multiple different local configuration bitstream files, as well as the set of initialization parameters associated with each algorithm module.

[0019] Secondly, the present invention provides a visual recognition and positioning method applicable to the above-mentioned system.

[0020] The method includes the following steps:

[0021] S1. Task Reception and Decision-Making: During continuous operation, the system receives new production task instructions. The task parsing unit compares these instructions with the algorithm identifiers already loaded in the current dynamic functional area. If the identifiers match, the current processing path is maintained; if they do not match, it is determined that an algorithm switch is needed, and the dynamic reconfiguration process is immediately initiated.

[0022] S2. Handling safe switching and dynamic reconfiguration of the pipeline:

[0023] S2a. Safe pause and emptying: The scheduling unit instructs the data stream manager to immediately stop sending new image frames to the dynamic functional area to be reconstructed, and ensures that the data that has entered the pipeline of this area has been completely processed, thus ensuring the integrity of data processing.

[0024] S2b. Local Logic Reconfiguration: Based on the target algorithm identifier, the dynamic reconfiguration controller reads the corresponding local bitstream file from the external configuration memory and precisely erases and reprograms the logic functions of the specified dynamically reconfigurable functional area through the chip's internal configuration channel. This process is strictly limited to the dynamic area, while the static system area continues to operate normally.

[0025] S2c. New Module Initialization: After the logic reconstruction is completed, the task parsing unit writes the corresponding algorithm parameter set (such as filter coefficients, feature extraction thresholds, neural network weight pointers, etc.) into the configuration register of the newly instantiated algorithm module through the system service bus, thus completing its working state initialization.

[0026] S3. Data Path Redirection and Recovery: The data stream scheduling manager updates the internal routing configuration, seamlessly switching subsequent high-speed image data streams to the dynamic functional area loaded with the new algorithm. The system enters the ready state.

[0027] S4. Deterministic Real-Time Identification and Positioning: The motion encoder on the production line generates synchronous trigger pulses. Image data is input via a high-speed interface in the static system area and routed to a dedicated hardware pipeline in the dynamic area. Image enhancement, feature extraction, marker matching, and sub-pixel coordinate calculation are performed sequentially in pure hardware. The final positioning result is sent to the motion controller via the industrial network interface in the static area within a fixed and deterministic time delay (e.g., less than 10 milliseconds).

[0028] S5. Forward-looking preloading: As an optimization extension, the system can prefetch the algorithm bitstream required for the next expected production task into the FPGA's configuration cache in advance, either during the idle interval of processing the current task or through a background thread, based on the production schedule. This reduces the effective reconfiguration time during task switching to the millisecond level.

[0029] (III) Beneficial Effects

[0030] Compared with the closest existing technology, the technical solution provided by this invention can produce the following significant beneficial effects:

[0031] 1. This invention integrates two traditionally mutually exclusive characteristics in the field of high-speed visual positioning, which has extremely stringent real-time requirements. The main body of the system maintains the essence of the FPGA full hardware pipeline architecture, thereby ensuring that the end-to-end processing latency is consistently less than 12 milliseconds, meeting the fundamental requirements of high-speed synchronous control. At the same time, its core identification and positioning algorithm can achieve online, dynamic, and disturbance-free switching within a few hundred milliseconds, achieving scene adaptability and flexibility comparable to software solutions.

[0032] 2. The time required for algorithm switching has been reduced from several hours (involving development, synthesis, routing, and overall updates) in traditional FPGA solutions to within hundreds of milliseconds, enabling near-in-line switching between different printing tasks. This reduces equipment debugging and downtime, improves overall production line efficiency and capacity utilization, and provides key technological enablement for flexible production models with small batches and multiple product varieties.

[0033] 3. This invention proposes an open "hardware platform + configurable algorithm IP" architecture. When faced with emerging new materials, processes, or markers, only the corresponding algorithm hardware module needs to be developed and verified offline. This module can then be injected as a new local bitstream into the system resource library, enabling existing devices to acquire new processing capabilities remotely or locally. The entire process requires no replacement of any hardware components or redesign or integration of the main system, thus extending the device's technological lifespan.

[0034] 4. Compared to heterogeneous solutions that require the integration of general-purpose processors and involve complex hardware-software interactions, all real-time processing functions of this invention are implemented through hardware logic within the same FPGA chip. Dynamic reconfiguration is a deterministic hardware behavior at the chip level, strictly managed by a dedicated hardware controller. This architecture completely avoids the additional complexity, performance fluctuations, and potential failure points caused by cross-chip communication, operating system task scheduling, and resource contention. The overall architecture is simple and meets the stringent stability requirements of industrial environments. Attached Figure Description

[0035] Figure 1 A schematic diagram of the overall hardware architecture of the system provided in an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram illustrating the logical division between the static system area and the dynamically reconfigurable functional area within the FPGA chip in an embodiment of the present invention.

[0037] Figure 3 This is a flowchart illustrating the overall process of the visual recognition and positioning method described in this invention.

[0038] Figure 4 This is a detailed timing diagram of the task switching and dynamic reconfiguration process in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples. It should be noted that the described embodiments are intended to facilitate understanding of the present invention and do not constitute a limitation on the scope of protection of the present invention.

[0040] See Figure 1 The hardware platform of this system is a customized industrial processing board, the core of which is a large-scale FPGA chip that supports dynamic partial reconfiguration. This board connects to a high frame rate area scan camera through two CoaXPress interfaces, receives rotary encoder synchronization pulses through a high-speed digital input interface, and communicates in real time with the main control PLC of the printing equipment through an EtherCAT fieldbus.

[0041] The core of this invention lies in the logic resource planning within the FPGA chip (see...) Figure 2 ):

[0042] Static system area: This area accounts for approximately 40% of the chip's total logic and memory resources. Its function is permanently established after the chip powers on and loads the initial complete bitstream. It contains the following key sub-modules:

[0043] Image acquisition engine: Implements CoaXPress protocol decoupling to receive camera data in pixel stream format.

[0044] Data cross-connector and buffer pool: As the core data router, it dynamically distributes the image stream to different processing units according to the instructions of the central scheduler, and has a built-in buffer to handle data temporary storage during reconfiguration.

[0045] Reconfiguration Engine: This is a hardened reconfiguration control logic that directly manages the FPGA's internal configuration access ports and is responsible for decompressing and loading bitstreams.

[0046] System service cluster: integrates microprocessor core, DDR memory controller, gigabit Ethernet and EtherCAT MAC, etc., and is responsible for system control, parameter management and real-time communication.

[0047] The dynamically reconfigurable functional area (RPU) is planned as an independent, clearly defined rectangular region in the chip layout. This region is interconnected with the static area via a high-bandwidth, low-latency AXI-Stream interface. In the default global bitstream, this region may only contain a very simple data pass-through module. The system's external SPI Flash memory stores several rigorously tested local bitstream files, such as algo_gold_cross.bit optimized for "mirror gold cardstock + small cross markers," algo_laser_square.bit optimized for "diffuse reflection laser film + large square markers," and algo_pet_bar.bit optimized for "transparent PET + thin bar markers."

[0048] Combination Figure 3 and Figure 4 The system's workflow from receiving a new task to completing the algorithm switch and putting it into operation is as follows:

[0049] 1. Normal operation: After the system starts, the static system area and the dynamic function area (such as the initial loading of algo_gold_cross) work together to process images from gold cardboard products with a fixed delay.

[0050] 2. Task Trigger: The production management system issues a new instruction, requiring a switch to the production of laser film packaging boxes. The instruction is sent via Ethernet to the processor core in the FPGA's static area.

[0051] 3. Decision-making and triggering: The task parsing software (running on the processor core) analyzes the instructions and matches the target algorithm as algo_laser_square. Upon comparison, it finds that the target algorithm differs from the current algorithm and immediately issues synchronization control commands to the reconfiguration engine and data crossover switch.

[0052] 4. Safe handover and dynamic reconfiguration:

[0053] a. The data cross switch immediately closes the data gate to the RPU and either imports subsequent image frames into the bypass buffer or discards them. Simultaneously, it waits for the RPU's internal pipeline to empty (this process typically lasts several microseconds).

[0054] b. At the same time, the reconfiguration engine is activated, quickly reading the algo_laser_square.bit file from the external SPI Flash.

[0055] c. The reconfiguration engine performs logical reconstruction only on the RPU area through its internal configuration channel. This process is a purely hardware operation, taking approximately 80-150 milliseconds, during which all functions in the static system area (including image reception, communication, etc.) remain completely unaffected.

[0056] 5. Initialization and Recovery:

[0057] a. Refactoring complete, the reconfiguration engine issues an interrupt signal.

[0058] b. The task parsing software on the processor core responds to the interrupt and writes the parameter set specific to the algo_laser_square algorithm (such as the filter kernel coefficients set to suppress laser noise and the template feature values ​​optimized for recognizing squares) into the configuration space of the new RPU module via the system bus.

[0059] c. After the parameters are configured, the processor core notifies the data crossover switch to update the routing table and reopens the data gateway to the RPU.

[0060] 6. Deterministic Processing Recovery: The arrival of the next encoder synchronization pulse marks the official start of the first processing cycle for the new material (laser film). Image data flows through the new algo_laser_square hardware pipeline, undergoes targeted processing, and finally, after a fixed time delay identical to the previous one, the high-precision positioning coordinates are sent out via the EtherCAT network to drive the actuator to complete the correction.

[0061] Through the above mechanism, this invention successfully integrates extreme hardware-level performance with system-level intelligent flexibility, providing an innovative visual solution for high-speed precision printing.

Claims

1. A printed visual identification positioning system based on dynamic partial reconfiguration, characterized in that, Comprise: a task analysis and scheduling unit for receiving and analyzing external production task instructions and generating corresponding algorithm switching control signals; a field programmable gate array chip, whose internal logic resources are physically divided into: a static system area, whose functions are permanently fixed during system operation, and which integrates at least a high-speed image acquisition interface module, a data stream scheduling and cache management module, a dynamic reconfiguration controller, and a system service and communication core module; at least one dynamically reconfigurable functional area, whose logic functions can be dynamically reconfigured at system runtime by loading different local configuration bitstream files; a non-volatile configuration memory connected to the field programmable gate array chip for storing a plurality of local configuration bitstream files corresponding to different printing tasks; wherein the dynamic reconfiguration controller reads a target local configuration bitstream file from the configuration memory in response to the algorithm switching control signal and performs logic reconfiguration on the dynamically reconfigurable functional area to realize online switching of the visual recognition and positioning algorithm.

2. The system of claim 1, wherein, The data stream scheduling and cache management module is configured to: during the logic reconfiguration of the dynamically reconfigurable functional area, pause the input of image data stream to the area, and cache or perform degradation processing on the input data; after the reconfiguration is completed, route the data stream to the reconfigured hardware logic module.

3. The system of claim 1, wherein, The hardware logic module formed after the reconfiguration of the dynamically reconfigurable functional area is a complete processing pipeline integrating an image preprocessing submodule and a mark recognition and positioning submodule, and the processing delay of the pipeline is a fixed value.

4. The system of claim 1, wherein, The system service and communication core module includes an industrial field bus controller; the total processing time from the reception of a frame of image by the high-speed image acquisition interface module to the issuance of the corresponding positioning result by the industrial field bus controller remains constant after the loading of any valid local configuration bitstream on the dynamically reconfigurable functional area, and the constant time is less than 12 milliseconds.

5. The system of claim 1, wherein, The task analysis and scheduling unit is further configured to: after the logic reconfiguration of the dynamically reconfigurable functional area is completed, write a set of initialization parameters matching the current production task to the newly instantiated hardware logic module of the area.

6. A visual recognition positioning method applied to the system of any one of claims 1 to 5, characterized in that, Comprise the following steps: receive a new production task instruction, which contains task identification information; determine whether the visual processing algorithm required by the task identification information is consistent with the algorithm currently loaded on the dynamically reconfigurable functional area; if not, perform a dynamic reconfiguration process: control the pause of data stream input to the dynamically reconfigurable functional area, load a local configuration bitstream file corresponding to the task identification information through the dynamic reconfiguration controller to reconfigure the area, and perform algorithm module initialization on the new area after the reconfiguration is completed; restore the image data stream to the reconfigured dynamically reconfigurable functional area, and process the subsequent images by the hardware logic pipeline of the area and output the positioning results.

7. The method of claim 6, wherein, The total execution time of the dynamic reconfiguration process is less than 500 milliseconds.

8. The method of claim 6, wherein, Further comprise a preloading step: during the processing of the current production task, load the local configuration bitstream file required by the next expected task to the internal configuration cache in advance by the dynamic reconfiguration controller according to the known production plan.

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