Display chip and time sequence control method of display chip

Abstract

The invention discloses a display chip and a time sequence control method of the display chip. The display chip comprises a time sequence detection unit, a control unit and a time sequence compensation unit, the time sequence detection unit receives a pixel clock signal and an input DE signal, performs anomaly detection on the pixel clock signal and the input DE signal based on a preset threshold range, and generates a first indication signal representing that the pixel clock signal is abnormal or the input DE signal is abnormal; the control unit generates a first control signal when receiving the first indication signal; and the time sequence compensation unit is used for judging the corresponding affiliated interval of the abnormal occurrence moment in the display period of the first image frame under the control of the first control signal, performing time sequence compensation based on the judgment result and preset time sequence data, and generating and outputting a DE signal. In a time sequence compensation process, an output DE signal needs to be generated based on an abnormal occurrence moment and preset time sequence data, so that the reliability and the real-time performance of the output DE signal are ensured, and normal display of an image is ensured.

Description

Technical Field

[0001] This invention relates to the field of image display technology, and in particular to a display chip and a timing control method for the display chip. Background Technology

[0002] Display devices typically consist of a system-on-chip (SoC), a timing controller (TCON), and a display panel. The SoC usually generates image data and timing data corresponding to the image frame to be displayed and sends them to the TCON. The TCON parses and processes the received image data and timing data to obtain pixel data and a data enable (DE) signal, and sends the pixel data and DE signal to the display panel. Driven by the DE signal, the display panel displays the image frame to be displayed normally according to the pixel data.

[0003] However, in practical applications, the received signal at the TCON end may switch. For example, when the SoC starts up, switches the frame rate, or switches the image signal source, signal interruption or abnormal signal jump may easily occur on the signal transmission link between the SoC and the TCON. This will cause abnormal timing data transmission on the signal transmission link, resulting in abnormal driving timing on the display panel end, causing screen flickering or distorted display. In severe cases, it may even damage the display panel.

[0004] In the timing processing methods provided by related technologies, when an abnormal DE signal is detected, the DE signal generated by the input timing data is switched to the locally generated DE signal, and after the DE signal is detected to be normal, it is switched back directly. Therefore, the above methods have low reliability, poor real-time performance, and cannot effectively guarantee the normal display of the image. Summary of the Invention

[0005] This invention provides a display chip and a timing control method for the display chip, which generates highly reliable and real-time timing control signals to ensure that the timing drive is performed normally and stably and to optimize the display effect.

[0006] In a first aspect, embodiments of the present invention provide a display chip, including a timing detection unit, a control unit, and a timing compensation unit, wherein:

[0007] The control unit is connected to the timing detection unit and the timing compensation unit respectively, and the timing detection unit is also connected to the timing compensation unit;

[0008] The timing detection unit is used to receive a pixel clock signal and an input DE signal, and to perform anomaly detection on the pixel clock signal and the input DE signal based on a preset threshold range, and generate a first indication signal, wherein the pixel clock signal and the input DE signal are determined according to the image display signal of the first image frame;

[0009] The control unit is configured to generate a first control signal upon receiving the first indication signal, wherein the first indication signal is configured to indicate that the pixel clock signal is abnormal or the input DE signal is abnormal.

[0010] The timing compensation unit is used to determine, under the control of the first control signal, the interval to which the time of the abnormality occurs belongs within the display period of the first image frame, and to perform timing compensation based on the determination result and preset timing data to generate an output DE signal, wherein the display period includes a field effective interval and a field blanking interval.

[0011] In the display chip provided in this embodiment of the invention, when the timing detection unit detects an abnormality in the pixel clock signal or the input DE signal, the control unit controls the timing compensation unit to perform timing compensation operations to ensure the normal generation and output of the output DE signal. During timing compensation, the output DE signal is not simply generated based on preset timing data; instead, the time of the abnormality is first determined, and then the output DE signal is generated based on the determination result and the preset timing data. This ensures the reliability and real-time performance of the output DE signal, thereby guaranteeing the normal display of the image.

[0012] Furthermore, when performing timing anomaly detection, anomalies should be detected for both the pixel clock signal and the input DE signal based on a preset threshold range. Therefore, the determination of timing anomalies not only takes into account the abnormality of the input DE signal, but also the abnormality of the pixel clock signal, thereby improving the accuracy of timing anomaly detection. The improved accuracy of timing anomaly detection leads to the improvement of timing compensation effect, which in turn optimizes the display effect of the image.

[0013] In an optional embodiment, the timing compensation unit includes an input timing compensation subunit, wherein:

[0014] The timing detection unit is further configured to generate a second indication signal based on the input DE signal and a preset threshold, and send the second indication signal to the input timing compensation subunit, wherein the second indication signal is used to indicate the end of the image display signal corresponding to a frame of image;

[0015] The input timing compensation subunit is used for:

[0016] When it is determined that the time of the anomaly occurs corresponds to the effective range of the field, the remaining part of the output DE signal corresponding to the first image frame is generated according to the preset time series data.

[0017] When it is determined that the time of the anomaly occurs corresponds to the blanking interval, after receiving the second indication signal, an output DE signal corresponding to the second image frame is generated according to the preset timing data, wherein the second image frame is the next frame image of the first image frame.

[0018] In the aforementioned display chip, when the input timing compensation subunit in the timing compensation unit detects that the anomaly occurred within the field valid interval, the input timing compensation subunit directly supplements the remaining part of the output DE signal according to preset timing data to achieve timing compensation. When the input timing compensation subunit detects that the anomaly occurred within the field blanking interval, the input timing compensation subunit waits for the arrival of the second indication signal. Upon receiving the second indication signal, it directly generates the output DE signal corresponding to the next frame image according to the preset timing data to achieve timing compensation. Therefore, depending on the time of the anomaly, the input timing compensation subunit adopts different timing compensation methods, thereby ensuring the reliability and effectiveness of the compensated output DE signal, so that the timing drive can proceed normally and stably.

[0019] In one optional embodiment, the timing detection unit is specifically used for:

[0020] Within any period of the input DE signal, the number of reference clock signals is detected to obtain the first quantity value (Htotal) of the input DE signal;

[0021] When the first quantity value is detected to be equal to the preset threshold value, the second indication signal is generated;

[0022] Wherein, one period of the input DE signal is used to characterize the row effective interval and row blanking interval of a row of pixels, and the preset threshold is greater than the maximum value of the first quantity value corresponding to the field effective interval, and less than the number of pixel clock signals corresponding to the field blanking interval.

[0023] In the aforementioned display chip, the timing detection unit also generates a second indication signal based on the input DE signal and a preset threshold. This second indication signal indicates the end of the image display signal corresponding to a frame of image. Through this second indication signal, the boundary between two image frames can be distinguished, and the switching of image display signals between different frames can be identified, which is beneficial for the detection and compensation of timing anomalies.

[0024] In an optional embodiment, the timing compensation unit further includes an internal timing generation subunit, wherein:

[0025] The control unit is further configured to generate a second control signal and a third control signal after the timing compensation of the output DE signal corresponding to a frame of image is completed;

[0026] The input timing compensation subunit is also used to stop working under the control of the second control signal;

[0027] The internal timing generation subunit is used to generate an internal DE signal according to the preset timing signal under the control of the third control signal, and to use the internal DE signal as the output DE signal.

[0028] In the aforementioned display chip, after the input timing compensation subunit completes the timing compensation of the output DE signal corresponding to one frame of image, the internal timing generation subunit in the timing compensation unit starts to work. It generates an internal DE signal according to the preset timing signal and uses the internal DE signal as the output DE signal. This ensures that the output DE signal can still be output normally and stably during the timing anomaly detection of the next frame of image, so that the timing drive can be carried out normally and stably.

[0029] In an optional embodiment, the timing detection unit is further configured to perform anomaly detection on the pixel clock signal and the input DE signal based on the preset threshold range, and generate a third indication signal, wherein the third indication signal is used to indicate that the pixel clock signal is normal and the input DE signal is normal.

[0030] The control unit is further configured to generate a fourth control signal and a fifth control signal when it receives the third indication signal and detects that a preset switching condition is met;

[0031] The input timing compensation subunit is further configured to generate the output DE signal under the control of the fourth control signal, based on the input DE signal and the preset timing data.

[0032] The internal timing generation subunit is also used to stop working under the control of the fifth control signal.

[0033] The aforementioned display chip, after detecting that both the pixel clock signal and the input DE signal corresponding to the next frame image are normal, does not immediately switch back to the input DE signal. Instead, it waits for the preset switching conditions to be met before switching from the internal DE signal to the output DE signal generated by the input DE signal and preset timing data. This ensures a stable frame rate. Furthermore, even when the timing is normal, the input DE signal is not directly used as the output DE signal. Instead, the output DE signal is generated based on the input DE signal and preset timing data. This results in an output DE signal whose waveform is closer to the ideal waveform, improving the reliability of the output DE signal and optimizing the display driving effect.

[0034] In an optional embodiment, under the control of the fourth control signal, the input timing compensation subunit is specifically used for:

[0035] The rising edge time of the input DE signal is taken as the rising edge time of the output DE;

[0036] Based on the preset timing data, determine the effective level duration corresponding to one cycle of the output DE signal, and determine the number of cycles in the output DE signal.

[0037] The aforementioned display chip, even when no pixel clock signal or input DE signal abnormality is detected, will perform timing compensation on the input DE signal according to preset timing data to generate the output DE signal. Compared to directly using the input DE signal as the output DE signal, this method can effectively correct slight distortions in the input DE signal, ensuring that even when the input DE signal experiences slight distortion but does not reach the level of signal abnormality, the waveform of the output DE signal remains close to the ideal waveform. This improves the effectiveness of timing-driven operation and enhances the display driving effect.

[0038] In one optional embodiment, the preset switching condition is:

[0039] The first rising edge of the input DE signal is no later than the first rising edge of the internal DE signal, and the first rising edge of the input DE signal is no earlier than the time corresponding to the lower limit of the first threshold range on the internal DE signal.

[0040] The preset threshold range includes the first threshold range, which is used to detect a second quantity value of the input DE signal. The second quantity value is the number of reference clock signals detected during the period from the first rising edge of the input DE signal corresponding to the first frame image to the first rising edge of the input DE signal corresponding to the next frame image of the first frame image.

[0041] When the aforementioned display chip detects that the timing is normal and needs to switch from the internal DE signal to the output DE signal generated by the input DE signal, the positional relationship between the internal DE signal and the input DE signal is uncertain. Directly switching the signal would cause frame rate chaos and affect the display effect. Therefore, in this embodiment of the invention, by setting the above-mentioned preset switching conditions, the signal switching is only performed when the timing is detected to be normal and the preset switching conditions are met. This ensures that the output DE signal always meets the set requirements and that the frame rate is stable, thereby ensuring the normal display of the image.

[0042] In an optional embodiment, the display chip further includes a timing path switching unit and a data path switching unit, wherein:

[0043] The control unit is further configured to generate a first switching control signal upon receiving the first indication signal, or upon receiving the third indication signal and satisfying the preset switching condition; and to generate a second switching control signal after timing compensation of the output DE signal corresponding to a frame of image is completed.

[0044] Upon receiving the first indication signal, a third switching control signal is generated; upon receiving the third indication signal and satisfying the preset switching condition, a fourth switching control signal is generated.

[0045] The timing path switching unit is used to output the output DE signal generated by the input timing compensation subunit under the control of the first switching control signal, and to output the output DE signal generated by the internal timing generation subunit under the control of the second switching control signal.

[0046] The data path switching unit is used to output preset blackout data under the control of the third switching signal, and to output image data under the control of the fourth switching control signal, wherein the image data is generated based on the image display signal.

[0047] The aforementioned display chip also includes a timing path switching unit and a data path switching unit. The timing path switching unit is used, under the control of the control unit, to select the output path of the input timing compensation subunit or the output path of the internal timing generation subunit to ensure the normal and stable output of the DE signal. The data path switching unit is used, under the control of the control unit, to select the output of preset blackout data or output image data. This allows the display panel to display a normal image frame when normal timing is detected, and to display a preset pattern when abnormal timing is detected, thus avoiding screen flickering, screen distortion, and other phenomena that could delay the lifespan of the display panel.

[0048] In one optional embodiment, the timing detection unit includes an input clock detection subunit and an input timing detection subunit, and the preset threshold range further includes a second threshold range, a third threshold range, a fourth threshold range, and a fifth threshold range, wherein:

[0049] The input clock detection subunit is used to identify the frequency information of the pixel clock signal, and to perform anomaly detection on the frequency information based on the second threshold range to generate a first detection result;

[0050] The input timing detection subunit is used to identify multiple feature information of the input DE signal, and perform anomaly detection on the feature information based on the threshold range corresponding to each feature information to generate a second detection result. The multiple feature information includes the first quantity value, the second quantity value, the third quantity value and the fourth quantity value.

[0051] Wherein, the third threshold range is used to detect the first quantity value, the fourth threshold range is used to detect the third quantity value, the third quantity value is the number of pixel clock signals detected within the effective level range of one cycle of the input DE signal, and the fifth threshold range is used to detect the fourth quantity value, the fourth quantity value is the number of rising edges of the input DE signal detected within the display cycle of one frame of image.

[0052] The aforementioned display chip uses the input clock detection subunit in the timing detection unit to detect frequency anomalies in the pixel clock signal, and uses the input timing detection subunit in the timing detection unit to detect anomalies in multiple feature information of the input DE signal. This not only detects pulse missingness in the input DE signal, but also detects other anomalies in the input DE signal, such as signal distortion, thus improving the accuracy of timing anomaly detection.

[0053] In a second aspect, embodiments of the present invention provide a timing control method for a display chip, applied to a display chip as described in any of the embodiments of the first aspect above, the method comprising:

[0054] The timing detection unit receives a pixel clock signal and an input DE signal, and performs anomaly detection on the pixel clock signal and the input DE signal based on a preset threshold range to generate a first indication signal. The pixel clock signal and the input DE signal are determined based on the image display signal of the first image frame.

[0055] When the control unit receives the first indication signal, it generates a first control signal, wherein the first indication signal is used to indicate that the pixel clock signal is abnormal or the input DE signal is abnormal.

[0056] Under the control of the first control signal, the timing compensation unit determines the interval within the display period of the first image frame corresponding to the time of the abnormality occurrence, and performs timing compensation based on the determination result and preset timing data to generate an output DE signal. The display period includes a field effective interval and a field blanking interval.

[0057] For the technical effects that the timing control method for the display chip disclosed in the second aspect above may achieve, please refer to the above description of the technical effects that may be achieved for the first aspect or various possible solutions in the first aspect, and will not be repeated here. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 A schematic diagram of the structure of a display device provided for related technologies;

[0060] Figure 2 This is a schematic diagram illustrating an application scenario of a display chip provided by an embodiment of the present invention;

[0061] Figure 3 This is a schematic diagram of the internal module structure of a display chip provided in an embodiment of the present invention;

[0062] Figure 4 This is a schematic diagram of the structure of a timing processing module in a display chip provided by an embodiment of the present invention;

[0063] Figure 5 This is a schematic diagram of the structure of a timing detection unit in a timing processing module provided in an embodiment of the present invention;

[0064] Figure 6 A schematic diagram of the signal waveforms of an input DE signal and a second indication signal provided in an embodiment of the present invention;

[0065] Figure 7 This is a schematic diagram of a signal waveform for detecting a third quantity value, provided by an embodiment of the present invention.

[0066] Figure 8 This is a schematic diagram of a signal waveform for detecting a fourth quantity value, provided by an embodiment of the present invention.

[0067] Figure 9 This is a schematic diagram of a signal waveform for detecting a first quantity value, provided by an embodiment of the present invention.

[0068] Figure 10 This is a schematic diagram of a signal waveform for detecting a second quantity value, provided as an embodiment of the present invention.

[0069] Figure 11 This is a schematic diagram of the structure of a timing compensation unit in a timing processing module provided in an embodiment of the present invention;

[0070] Figure 12 This invention provides a schematic diagram of a signal waveform for generating an output DE signal based on an input DE signal and preset timing data.

[0071] Figure 13 This is a schematic diagram of another signal waveform for generating an output DE signal based on an input DE signal and preset timing data, provided by an embodiment of the present invention.

[0072] Figure 14 This invention provides a schematic diagram of a signal waveform for generating an output DE signal under an abnormal Htotal Min condition.

[0073] Figure 15 This invention provides a schematic diagram of a signal waveform for generating an output DE signal under an abnormal Htotal Max condition.

[0074] Figure 16 A schematic diagram of a signal waveform for switching windows provided in an embodiment of the present invention;

[0075] Figure 17 A schematic diagram of a signal waveform for signal switching provided in an embodiment of the present invention;

[0076] Figure 18 This is a schematic diagram of the interaction process of various units in a display chip provided in an embodiment of the present invention;

[0077] Figure 19 This invention provides a schematic diagram of the internal working path of a timing processing module in both free and adjusted states, as provided in an embodiment of the invention.

[0078] Figure 20 This is a schematic diagram of the internal working path of a timing processing module under normal conditions, provided by an embodiment of the present invention.

[0079] Figure 21 This is a schematic diagram of the internal working path of a timing processing module in a compensated state, provided by an embodiment of the present invention.

[0080] Figure 22 This is a schematic diagram illustrating the complete workflow of a display chip according to an embodiment of the present invention;

[0081] Figure 23This is a schematic diagram illustrating the workflow of a timing control method for a display chip provided in an embodiment of the present invention. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0083] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0084] Figure 1 A schematic diagram of the structure of a display device provided by related technologies is shown. For example... Figure 1 As shown, the display device 10 includes a SoC 11, a TCON 12, and a display panel 13. The TCON 12 internally houses an RX (Receive) module 121, a Datapath module 122, and a TX (Transmit) module 123, wherein:

[0085] TCON 12 communicates with SoC 11 via RX module 121. This communication link is generally a signal transmission link using V-by-one protocol, eDP protocol or MIPIDSI protocol. TCON 12 communicates with display panel 13 via TX module 123. This communication link is generally a signal transmission link using mini-LVDS protocol or P2P protocol.

[0086] In practical applications, SoC 11 generates image data and timing data corresponding to the image frame to be displayed, and sends the image data and timing data to TCON 12 through the corresponding communication link; TCON 12 receives the image data and timing data through RX module 121, and parses the received timing data through RX module 121 to obtain pixel clock signal and DE signal; then, the image data is processed through Datapath module 122 to generate pixel data; then, the DE signal and pixel data are sent to display panel 13 through TX module 123 to drive display panel 13 to display the image normally.

[0087] Therefore, during image display, only by ensuring the normal and stable transmission of timing data can the TCON12 drive the display panel 13 to display images normally. However, the communication link between the SoC 11 and the RX module 121 of the TCON 12 may experience signal interruption or abnormal transitions during the switching of the TCON received signal. For example, during the startup of the SoC 11 and the switching of the frame rate or image signal source of the display device 10, signal interruption or abnormal transitions may occur, causing the DE signal sent by the TCON 12 to the display panel 13 to become abnormal. Consequently, the timing drive control of the display panel 13 also becomes abnormal, resulting in screen flickering or distorted images. In severe cases, it may even damage the display panel.

[0088] In related technologies, there are generally two methods to ensure normal display timing: hardware processing and software processing.

[0089] One processing method uses hardware design to detect the presence of a DE signal and, based on the detection result, switches between a DE signal generated from the input timing data and a locally generated DE signal to address the issue of timing data transmission interruption. However, this method can only detect interruptions in timing data and cannot detect other anomalies. Therefore, its timing processing function is weak, it cannot effectively guarantee the normal display of the image, and the reliability of the generated DE signal is low.

[0090] Another approach involves using software to correct abnormal timing signals to obtain normal timing control signals. However, this method consumes significant processing resources and has poor real-time performance, failing to meet the display requirements of high-performance display devices.

[0091] Based on this, embodiments of the present invention provide a display chip and a timing control method for the display chip, which is used to detect anomalies in the timing control signal and perform timing compensation to generate a highly reliable and real-time timing control signal, ensuring that the timing drive is normal and stable, optimizing the display effect. In addition, when a timing anomaly is detected, the display panel is blacked out to avoid abnormal images appearing on the display panel, ensuring that the display panel is not damaged and extending the service life of the display panel.

[0092] The objectives, functional features, and advantages of this invention will be further explained in conjunction with the embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0093] The application scenarios of the display chip provided by the present invention will be described below with reference to the accompanying drawings:

[0094] like Figure 2 As shown, the application scenario includes a display 21 and a server 22. The display chip provided in this embodiment of the invention is integrated in the display 21, and the display 21 and the server 22 are connected via Internet communication.

[0095] In a specific implementation, server 22 sends an image display signal corresponding to an image frame to display 21. The display chip in display 21 generates an output DE signal and pixel data according to the received image display signal and using the method provided in this embodiment of the invention, and sends the generated output DE signal and pixel data to the display panel of display 21. Driven by the output DE signal, the display panel displays the image frame according to the pixel data.

[0096] Of course, the methods provided in the embodiments of the present invention are not limited to those described above. Figure 2 The application scenarios shown can also be used in other possible application scenarios, and the embodiments of the present invention do not impose any limitations.

[0097] After introducing the application scenarios of the embodiments of the present invention, the preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. Furthermore, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0098] The display chip provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings:

[0099] Figure 3 A schematic diagram of the internal module structure of a display chip is shown. Figure 3As shown, the display chip 30 includes a receiving module 31, a timing processing module 32, a data processing module 33, and a transmitting module 34; the receiving module 31, the timing processing module 32, the data processing module 33, and the transmitting module 34 are connected in sequence, wherein:

[0100] The receiving module 31 is used to receive the image display signal sent by the previous stage frame by frame, parse the received image display signal to obtain the pixel clock signal, input DE signal and image data, and send the generated pixel clock signal, input DE signal and image data to the timing processing module 32.

[0101] The timing processing module 32 is used to perform timing compensation processing on the received pixel clock signal and the input DE signal according to the method provided in the embodiment of the present invention (see the following embodiments for details), generate an output DE signal, and send the output DE signal and image data to the data processing module 33;

[0102] Data processing module 33 is used to perform data conversion processing on the received image data to obtain pixel data, and send the pixel data and the output DE signal to the sending module 34;

[0103] The transmitting module 34 is used to transmit pixel data and output DE signal to the subsequent stage.

[0104] It should be noted that the display chip 30 in this embodiment of the invention can be a TCON chip, a Scaler chip, or other general-purpose display chip, and this embodiment of the invention does not impose any limitations on it. Furthermore, other essential components of this display chip are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limitations on the invention.

[0105] Figure 4 A schematic diagram of the module structure of a timing processing module in a display chip is shown. Figure 4 As shown, the timing processing module 32 includes a timing detection unit 321, a control unit 322, and a timing compensation unit 323; the control unit 322 is connected to both the timing detection unit 321 and the timing compensation unit 323, and the timing detection unit 321 is also connected to the timing compensation unit 323; wherein:

[0106] The timing detection unit 321 is used to receive the pixel clock signal and the input DE signal, and to perform anomaly detection on the pixel clock signal and the input DE signal based on a preset threshold range, and generate a first indication signal. The pixel clock signal and the input DE signal are determined according to the image display signal of the first image frame, and the first indication signal is used to indicate that the pixel clock signal or the input DE signal is abnormal.

[0107] In some embodiments, the timing detection unit 321 may also generate a third indication signal, wherein the third indication signal is used to indicate that the pixel clock signal is normal and the input DE signal is normal.

[0108] In a specific implementation, when the timing detection unit 321 detects an abnormality in at least one of the pixel clock signal and the input DE signal, it generates a first indication signal and sends the first indication signal to the control unit 322 to inform the control unit 322 that a timing abnormality has been detected. When the timing detection unit 321 detects that both the pixel clock signal and the input DE signal are normal, it generates a third indication signal and sends the third indication signal to the control unit 322 to inform the control unit 322 that no timing abnormality has been detected.

[0109] The control unit 322 is used to generate a first control signal when it receives a first indication signal.

[0110] The timing compensation unit 323 is used to determine the interval within the display period of the first image frame corresponding to the time of the abnormality under the control of the first control signal, and to perform timing compensation based on the judgment result and preset timing data to generate an output DE signal, wherein the display period includes the field effective interval and the field blanking interval.

[0111] In practical implementation, the display cycle corresponding to an image frame can be divided into a field effective interval and a field blanking interval. Within the field effective interval, the pixel units on the display panel are scanned line by line according to a preset scanning order. Therefore, the field effective interval can be further divided into multiple cycles. One cycle corresponds to the row effective interval and row blanking interval of a row of pixel units. Within the row effective interval, a row of pixel units is scanned and driven so that the row of pixel units displays the image according to the corresponding pixel data.

[0112] In the display chip provided in this embodiment of the invention, when the timing detection unit detects an abnormality in the pixel clock signal or the input DE signal, the control unit controls the timing compensation unit to perform timing compensation operations to ensure the normal generation and output of the output DE signal. During timing compensation, the output DE signal is not simply generated based on preset timing data; instead, the time of the abnormality is first determined, and then the output DE signal is generated based on the determination result and the preset timing data. This ensures the reliability and real-time performance of the output DE signal, thereby guaranteeing the normal display of the image.

[0113] Furthermore, when performing timing anomaly detection, anomalies should be detected for both the pixel clock signal and the input DE signal based on a preset threshold range. Therefore, the determination of timing anomalies not only takes into account the abnormality of the input DE signal, but also the abnormality of the pixel clock signal, thereby improving the accuracy of timing anomaly detection. The improved accuracy of timing anomaly detection leads to the improvement of timing compensation effect, which in turn optimizes the display effect of the image.

[0114] The following is a detailed description of each unit in the timing processing module of the display chip provided in the embodiments of the present invention, with reference to the accompanying drawings:

[0115] Figure 5 A schematic diagram of the internal structure of a timing detection unit in a timing processing module is shown. For example... Figure 5 As shown, the timing detection unit 321 includes an input clock detection subunit 3211 and an input timing detection subunit 3212. The input clock detection subunit 3211 is used to detect anomalies in the pixel clock signal, and the input timing detection subunit 3212 is used to detect anomalies in the input DE signal.

[0116] In some embodiments, the preset threshold range may include multiple ranges, namely a first threshold range, a second threshold range, a third threshold range, a fourth threshold range, and a fifth threshold range. Specifically, the second threshold range may be represented as (clock_F_Min, clock_F_Max); the first threshold range may be represented as (Vttl_Min, Vttl_Max); the third threshold range may be represented as (Httl_Min, Httl_Max); the fourth threshold range may be represented as (Hact_Min, Hact_Max); and the fifth threshold range may be represented as (Vact_Min, Vact_Max).

[0117] In some embodiments, the input clock detection subunit 3211 is specifically used to identify the frequency information of the pixel clock signal, and to perform anomaly detection on the identified frequency information based on a second threshold range to generate a first detection result.

[0118] In specific implementation, the second threshold range (clock_F_Min, clock_F_Max) is used to detect frequency anomalies in the pixel clock signal RX clock. That is, when the input clock detection subunit 3211 detects that the frequency value of the pixel clock signal RX clock is within the second threshold range (clock_F_Min, clock_F_Max), it is determined that the pixel clock signal RX clock is normal. At this time, a first detection result is generated to characterize the normality of the pixel clock signal RX clock.

[0119] When the input clock detection subunit 3211 detects that the frequency value of the pixel clock signal RX clock is outside the second threshold range (clock_F_Min, clock_F_Max), it determines that the pixel clock signal RX clock is abnormal. At this time, a first detection result is generated to characterize the abnormality of the pixel clock signal RX clock. In this case, the frequency value of the pixel clock signal RX clock may be greater than the upper limit value clock_F_Max of the second threshold range (clock_F_Min, clock_F_Max), or it may be less than the lower limit value clock_F_Min of the second threshold range (clock_F_Min, clock_F_Max).

[0120] In some embodiments, the input timing detection subunit 3212 is used to identify multiple feature information of the input DE signal, and to perform anomaly detection on the feature information based on the threshold range corresponding to each feature information, thereby generating a second detection result. The multiple feature information of the input DE signal includes a first quantity value (Htotal), a second quantity value (Vtotal), a third quantity value (Hactive), and a fourth quantity value (Vactive).

[0121] It should be noted that the first quantity value can be represented as Htotal, which is used to represent the total number of clock cycles in the scanning time of a row of pixel units; the second quantity value can be represented as Vtotal, which is used to represent the total number of clock cycles in the display cycle corresponding to a frame of image; the third quantity value can be represented as Hactive, which is used to represent the number of effective points in the horizontal direction; and the fourth quantity value can be represented as Vactive, which is used to represent the number of effective rows in the vertical direction.

[0122] In some embodiments, the input timing detection subunit 3212 is specifically configured to perform anomaly detection on a first quantity value based on a third threshold range, and to perform anomaly detection on a second quantity value based on a first threshold range, and to perform anomaly detection on a third quantity value based on a fourth threshold range, and to perform anomaly detection on a fourth quantity value based on a fifth threshold range; and when it is detected that each quantity value is within the threshold range corresponding to that quantity value, it is determined that the input DE signal is normal; if it is detected that at least one quantity value is outside the threshold range corresponding to that quantity value, it is determined that the input DE signal is abnormal.

[0123] In a specific implementation, the input timing detection subunit 3212 needs to use a second indication signal to identify multiple feature information of the input DE signal. This second indication signal is generated by the input timing detection subunit 3212 based on the input DE signal and a preset threshold, and is used to indicate the end of the image display signal corresponding to a frame of image.

[0124] In some embodiments, the input timing detection subunit 3212 can specifically generate the second indication signal in the following manner:

[0125] Within any cycle of the input DE signal, the number of reference clock signals is detected to obtain the first quantity value of the input DE signal; when the first quantity value is found to be equal to a preset threshold, a second indication signal is generated.

[0126] One period of the input DE signal is used to characterize the row effective interval and row blanking interval of a row of pixels. The preset threshold is greater than the maximum value of the first quantity value corresponding to the field effective interval and less than the number of pixel clock signals corresponding to the field blanking interval.

[0127] Figure 6 A schematic diagram of the signal waveforms of an input DE signal and a second indication signal is shown. Figure 6 As shown, the input DE signal corresponding to an image frame is used to control the display timing of the display cycle of that image frame. Therefore, the input DE signal corresponds to the field active interval and the field blanking interval within the display cycle. For any cycle of the input DE signal, the high-level interval of that cycle is used to drive a row of pixel units on the scanning display panel, corresponding to the row active interval, while the low-level interval of that cycle corresponds to the row blanking interval.

[0128] Since the preset threshold is set to be greater than the maximum value of the first quantity value Htotal corresponding to the field effective interval and less than any value between the number of pixel clock signals RX clock corresponding to the field blanking interval, when the count of the first quantity value Htotal reaches the preset threshold, it can be determined that the display stage of the current image frame has ended. At this time, a second indicator signal Vtrigger is generated, which is a pulse signal.

[0129] In addition, after generating the second indication signal, the input timing detection subunit 3212 will send the second indication signal and the input DE signal to the input timing compensation unit 323.

[0130] The system generates a second indicator signal based on the input DE signal and a preset threshold. This second indicator signal indicates the end of the image display signal corresponding to a frame of image. Through this second indicator signal, the boundary between two image frames can be distinguished, and the switching of image display signals between different frames can be identified, which is beneficial for the detection and compensation of timing anomalies.

[0131] In some embodiments, the input timing detection subunit 3212 may determine the third quantity value Hactive in the following manner:

[0132] Within one cycle of the effective level range of the input DE signal, the number of input clock signals RX clock is counted to obtain the third quantity value Hactive.

[0133] In the following embodiments, the effective level interval of one cycle of the input DE signal is taken as the high level interval (i.e., the input DE signal = 1) for illustration:

[0134] Figure 7 A schematic diagram of a signal waveform for detecting a third quantity value is shown. For example... Figure 7 As shown, at the rising edge of the input DE signal, the count value Hact counter is reset, and counting begins at the rising edge of the input clock signal RX clock. The count value Hact counter corresponding to the falling edge of the input DE signal is used as the third quantity value Hactive (i.e., Figure 7 (C1 in the middle).

[0135] In some embodiments, the input timing detection subunit 3212 can specifically perform anomaly detection on the third quantity value Hactive in the following manner:

[0136] Real-time detection of the relationship between the third quantity value Hactive and the fourth threshold range (Hact_Min, Hact_Max);

[0137] If the third quantity value Hactive is detected to be within the fourth threshold range (Hact_Min, Hact_Max), then the third quantity value Hactive is determined to be normal.

[0138] If the third quantity value Hactive is found to be greater than the upper limit value Hact_Max of the fourth threshold range (Hact_Min, Hact_Max), then the third quantity value Hactive is determined to be abnormal. This abnormal situation can be called Hactive Max abnormality.

[0139] If the third quantity value Hactive is found to be less than the lower limit Hact_Min of the fourth threshold range (Hact_Min, Hact_Max), then the third quantity value Hactive is determined to be abnormal. This abnormal situation can be called Hactive Min abnormal.

[0140] In some embodiments, the input timing detection subunit 3212 may specifically determine the fourth quantity value Vactive in the following manner:

[0141] Within the display cycle of one frame of an image, the number of rising edges of the input DE signal is detected to obtain the fourth quantity value Vactive.

[0142] In a specific implementation, since the second indicator signal V trigger is used to indicate the end of the display cycle corresponding to an image frame, the number of rising edges of the input DE signal can be counted between two adjacent second indicator signals V trigger to obtain the fourth quantity value Vactive.

[0143] Figure 8 A schematic diagram of a signal waveform for detecting a fourth quantity value is shown. For example... Figure 8 As shown, upon receiving a second indicator signal V trigger, the count value Vact counter is cleared to zero. Then, with each rising edge of the subsequent input DE signal, the count value Vact counter is incremented by 1. The count value Vact counter corresponding to the arrival of the next second indicator signal V trigger is used as the fourth quantity value Vactive (i.e., ...). Figure 8 (C2 in the middle).

[0144] In some embodiments, the input timing detection subunit 3212 can specifically perform anomaly detection on the fourth quantity value Vactive in the following manner:

[0145] Real-time detection of the relationship between the fourth quantity value Vactive and the fifth threshold range (Vact_Min, Vact_Max);

[0146] If the fourth quantity value Vactive is found to be within the fifth threshold range (Vact_Min, Vact_Max), then the fourth quantity value Vactive is determined to be normal.

[0147] If the fourth quantity value Vactive is found to be greater than the upper limit value Vact_Max of the fifth threshold range (Vact_Min, Vact_Max), then the fourth quantity value Vactive is determined to be abnormal. This abnormal situation can be called Vactive Max abnormality.

[0148] If the fourth quantity value Vactive is found to be less than the lower limit Vact_Min of the fifth threshold range (Vact_Min, Vact_Max), then the fourth quantity value Vactive is determined to be abnormal. This abnormal situation can be called Vactive Min abnormal.

[0149] In some embodiments, the input timing detection subunit 3212 may determine the first quantity value Htotal in the following manner:

[0150] Within any period of the input DE signal, the number of reference clock signals REF clock is detected to obtain a first quantity value Htotal, where the frequency of the reference clock signal REF clock is a fixed value.

[0151] In practice, since the first period of the input DE signal corresponding to an image frame will span the field blanking interval, determining the count value within the first period of the input DE signal cannot reflect the true first quantity value Htotal. Therefore, in practical applications, the count value corresponding to the first period will be discarded, and the first quantity value Htotal will be determined and anomaly detection will be performed starting from the second period of the input DE signal.

[0152] Figure 9 A schematic diagram of a signal waveform for detecting a first quantity value is shown. For example... Figure 9 As shown, at the rising edge of the input DE signal, the count value Httl counter is reset, and counting of the reference clock signal REF clock begins. Specifically, when the rising edge of the reference clock signal REF clock arrives, the count value Httl counter is incremented by 1, and the count value Httl counter corresponding to the falling edge of the input DE signal is used as the first quantity value Htotal (i.e., ...). Figure 9 (Z1 in the middle).

[0153] Since a fixed-frequency reference clock signal REFclock is used in the determination of the first quantity value Htotal, the line frequency can be accurately determined.

[0154] In some embodiments, the input timing detection subunit 3212 can specifically perform anomaly detection on the first quantity value Htotal in the following manner:

[0155] Real-time detection of the relationship between the first quantity value Htotal and the third threshold range (Httl_Min, Httl_Max);

[0156] If the first quantity value Htotal is detected to be within the third threshold range (Httl_Min, Httl_Max), then the first quantity value Htotal is determined to be normal.

[0157] If the first quantity value Htotal is found to be greater than the upper limit value Httl_Max of the third threshold range (Httl_Min, Httl_Max), then the first quantity value Htotal is determined to be abnormal. This abnormal situation can be called Htotal Max abnormal.

[0158] If the first quantity value Htotal is found to be less than the lower limit Httl_Min of the third threshold range (Httl_Min, Httl_Max), then the first quantity value Htotal is determined to be abnormal. This abnormal situation can be called Htotal Min abnormal.

[0159] In some embodiments, the input timing detection subunit 3212 may determine the second quantity value Vtotal in the following manner:

[0160] During the period from the first rising edge of the input DE signal corresponding to the first frame of the first image to the first rising edge of the input DE signal corresponding to the next frame of the first image, the number of reference clock signals REF clock is detected to obtain the second quantity value Vtotal.

[0161] Figure 10 A schematic diagram of a signal waveform for detecting a second quantity value is shown. For example... Figure 10 As shown, upon receiving a second indicator signal Vtrigger, the counter value Vttlcounter is reset upon detecting the first rising edge of the input DE signal. Subsequently, the counter value Vttlcounter is incremented by 1 with each rising edge of the reference clock signal REF clock. The counter value Vttlcounter corresponding to the first rising edge of the input DE signal in the next image frame after receiving the next second indicator signal Vtrigger is used as the second quantity value Vtotal (i.e., ...). Figure 10 (Z2 in the middle).

[0162] Since a fixed-frequency reference clock signal REFclock is used in the determination of the second quantity value Vtotal, the frame rate can be accurately determined.

[0163] In some embodiments, the input timing detection subunit 3212 can specifically perform anomaly detection on the second quantity value Vtotal in the following manner:

[0164] Real-time detection of the relationship between the second quantity value Vtotal and the first threshold range (Vttl_Min, Vttl_Max);

[0165] If the second quantity value Vtotal is detected to be within the first threshold range (Vttl_Min, Vttl_Max), then the second quantity value Vtotal is determined to be normal.

[0166] If the second quantity value Vtotal is found to be greater than the upper limit value Vttl_Max of the first threshold range (Vttl_Min, Vttl_Max), then the second quantity value Vtotal is determined to be abnormal. This abnormal situation can be called Vtotal Max abnormality.

[0167] If the second quantity value Vtotal is found to be less than the lower limit Vttl_Min of the first threshold range (Vttl_Min, Vttl_Max), then the second quantity value Vtotal is determined to be abnormal. This abnormal situation can be called Vtotal Min abnormal.

[0168] In specific implementation, the input timing detection subunit 3212 performs anomaly detection on the frequency of the pixel clock signal RXclock and the third quantity value Hactive, the fourth quantity value Vactive, the first quantity value Htotal and the second quantity value Vtotal of the input DE signal through the above detection. Only when all the quantity values ​​of the input DE signal are normal can the input DE signal be determined to be normal. Only when there is an abnormal data quantity can the input DE signal be determined to be abnormal.

[0169] The above detection method, on the one hand, considers not only the abnormalities in the input DE signal but also the abnormalities in the pixel clock signal during the timing anomaly determination process, thus improving the accuracy of timing anomaly detection. On the other hand, during the anomaly detection process of the input DE signal, not only pulse loss but also other anomalies such as signal distortion can be detected, thereby improving the accuracy of anomaly detection and enhancing the reliability of subsequent timing compensation.

[0170] Figure 11 A schematic diagram of the internal structure of a timing compensation unit in a timing processing module is shown. Figure 11 As shown, the timing compensation unit 323 includes an input timing compensation subunit 3231 and an internal timing generation subunit 3232, wherein:

[0171] When the timing is normal, that is, when the timing detection unit 321 detects that the pixel clock signal and the input DE signal are normal, the timing detection unit 321 will generate a third indication signal and send the third indication signal to the control unit 322. After receiving the third indication signal, the control unit 322 will control the input timing compensation subunit 3231 to work and control the internal timing generation subunit 3232 to not work. At this time, the input timing compensation subunit 3231 will generate an output DE signal according to the input DE signal and the preset timing data. The specific generation method is as follows:

[0172] In some embodiments, the input timing compensation subunit 3231 can generate the output DE signal by: taking the rising edge time of the input DE signal as the rising edge time of the output DE; determining the effective level duration corresponding to one cycle of the output DE signal and the number of cycles in the output DE signal according to preset timing data.

[0173] It should be noted that the preset timing data includes the settings of parameters Httl0, Vttl0, Hact0, Vact0, Vsync Front Porch, and Vsync Width. Among them, parameters Vsync Front Porch and Vsync Width are used to generate Vsync (Vertical Synchronization) signals.

[0174] In a specific implementation, the input timing compensation subunit 3231 can determine the effective level duration corresponding to one cycle of the output DE signal according to the parameter Hact0 in the preset timing data; and determine the number of cycles in the output DE signal according to the parameter Vact0 in the preset timing data.

[0175] Figure 12 A schematic diagram of a signal waveform is shown, illustrating how an output DE signal is generated based on an input DE signal and preset timing data. For example... Figure 12 As shown, after receiving the second indicator signal V trigger, the waveform of the input DE signal shows that the high-level duration is longer and the low-level duration is shorter in the first cycle of the input DE signal, while the high-level duration is shorter and the low-level duration is longer in the third cycle. However, the third quantity value Hactive detected by the input timing detection subunit 3212 is still within the fourth threshold range (Hact_Min, Hact_Max). In other words, the input timing detection subunit 3212's detection of the third quantity value Hactive is normal and no abnormality has occurred.

[0176] In this situation, if the input DE signal is directly used as the output DE signal, the waveform of the generated output DE signal will obviously be unsatisfactory. Therefore, referring to... Figure 12 As can be seen from the waveform diagram of the output DE signal, in this embodiment of the invention, the rising edge of the output DE signal is triggered by the rising edge of the input DE signal. However, the duration of the high-level state after each rising edge of the output DE signal is triggered is determined by the parameter Hact0 in the preset timing data. Therefore, Figure 12 The waveform of the generated output DE signal is quite ideal.

[0177] Figure 13This diagram illustrates another signal waveform used to generate the output DE signal based on the input DE signal and preset timing data. (See diagram for example.) Figure 13 As shown, after receiving the second indication signal V trigger, the waveform of the input DE signal shows that there are many rising edges in the input DE signal, which means that the fourth quantity value Vactive detected by the input timing detection subunit 3212 is too large. However, the fourth quantity value Vactive is still within the fifth threshold range (Vact_Min, Vact_Max). In other words, the input timing detection subunit 3212 detected the fourth quantity value Vactive normally and no abnormality occurred.

[0178] In this situation, if the input DE signal is directly used as the output DE signal, the waveform of the generated output DE signal will obviously be unsatisfactory. Therefore, referring to... Figure 13 As can be seen from the waveform of the output DE signal in this embodiment of the invention, the number of rising edges included in the output DE signal is determined by the parameter Vact0 in the preset timing data. Therefore, Figure 12 The waveform of the generated output DE signal is quite ideal.

[0179] Under normal timing conditions (i.e., when no abnormalities are detected in the pixel clock signal or the input DE signal), the input DE signal is not directly used as the output DE signal. Instead, timing compensation is performed on the input DE signal based on preset timing data to generate the output DE signal. Compared to directly using the input DE signal as the output DE signal, this method can effectively correct slight distortions in the input DE signal. It ensures that even when slight distortions occur in the input DE signal, but do not reach the level of signal abnormality, the waveform of the output DE signal remains close to the ideal waveform. This improves the reliability of the output DE signal, guarantees the effectiveness of timing-driven operation, and enhances the display driving effect.

[0180] When a timing anomaly is detected, i.e., when the input timing detection subunit 3212 detects an abnormality in the pixel clock signal or the input DE signal, it sends a first indication signal to the control unit 322. After receiving the first indication signal, the control unit 322 generates a first control signal and sends it to the input timing compensation subunit 3231. Under the control of the first control signal, the input timing compensation subunit 3231 determines the interval within the display period of the first image frame corresponding to the time of the anomaly, and performs timing compensation operations based on the determination result, as follows:

[0181] In some embodiments, when it is determined that the time of the anomaly occurs corresponds to the effective range of the field, the input timing compensation subunit 3231 generates the remaining part of the output DE signal corresponding to the first image frame according to the preset timing data.

[0182] In practical implementation, when the time of the anomaly corresponds to the effective range of the field, the input timing compensation subunit 3231 will perform different timing compensation operations according to the specific anomaly situation in order to achieve accurate compensation of the output DE signal.

[0183] In one timing compensation method, when it is determined that the time of an anomaly occurs is within the effective range of the field, and when the input timing compensation subunit 3231 detects the anomaly, if a certain feature information corresponding to the output DE signal is less than or equal to the corresponding preset parameter in the preset timing data, then the input timing compensation subunit 3231 immediately stops following the input DE signal to generate the output DE signal, and waits for the count of the feature information to reach the corresponding preset parameter before generating the subsequent output DE signal according to the preset timing data.

[0184] Among them, Hactive Min anomaly, Hactive Max anomaly, and Htotal Min anomaly are all applicable to the above timing compensation methods. The following is a specific explanation using Htotal Min anomaly as an example:

[0185] Figure 14 A schematic diagram of the signal waveform for generating the output DE signal under the Htotal Min abnormal condition is shown. Figure 14 As shown, the time when the Htotal Min anomaly occurs corresponds to the valid period of presence. When the anomaly occurs, the current Htotal count value of the output DE signal is less than the parameter Httl0 in the preset timing data. Therefore, when timing compensation is enabled, it will immediately stop following the input DE signal to generate the output DE signal, and will wait for the current Htotal count value of the output DE signal to reach the parameter Httl0 before generating the next cycle of the output DE signal and multiple subsequent cycles according to the preset timing data until the end.

[0186] In another timing compensation method, when it is determined that the time of the abnormality occurs is within the effective range of the field, and when the input timing compensation subunit 3231 detects the abnormality, if a certain feature information corresponding to the output DE signal is greater than the preset parameter in the preset timing data, then the input timing compensation subunit 3231 immediately stops following the input DE signal to generate the output DE signal, and immediately generates the subsequent output DE signal according to the preset timing data.

[0187] Both the Htotal Max anomaly and the Vactive Min anomaly are applicable to the timing compensation methods described above. The following explanation uses the Htotal Max anomaly as an example:

[0188] Figure 15 A schematic diagram of the signal waveform for generating the output DE signal under the abnormal condition of Htotal Max is shown. Figure 15As shown, the time when the Htotal Max anomaly occurs corresponds to the valid period of presence. When the anomaly occurs, the current Htotal count value of the output DE signal is greater than the parameter Httl0 in the preset timing data. Therefore, when timing compensation is enabled, it will immediately stop following the input DE signal to generate the output DE signal, and will immediately generate the next cycle of the output DE signal and multiple subsequent cycles according to the preset timing data until the end.

[0189] Thus, for the current image frame, the first half of its corresponding output DE signal (i.e., the part before the time of the anomaly) is generated following the input DE signal, while the second half of the output DE signal (i.e., the part after the time of the anomaly) is generated based on preset timing data.

[0190] In some embodiments, when it is determined that the time of an anomaly occurs is within the field blanking interval, after receiving the second indication signal, the input timing compensation subunit 3231 generates an output DE signal corresponding to the second image frame according to preset timing data, wherein the second image frame is the next frame image of the first image frame.

[0191] In practice, when the time of the anomaly occurs within the blanking interval, the input timing compensation subunit 3231 will perform different timing compensation operations according to the specific anomaly situation in order to achieve accurate compensation of the output DE signal.

[0192] In one timing compensation method, when it is determined that the time of an anomaly occurs is within the field blanking interval, and the input timing compensation subunit 3231 detects the anomaly, if a certain feature information corresponding to the output DE signal is less than or equal to the corresponding preset parameter in the preset timing data, then the input timing compensation subunit 3231 immediately stops following the input DE signal to generate the output DE signal, and waits for the feature information count to reach the corresponding preset parameter before generating the output DE signal corresponding to a complete image frame according to the preset timing data.

[0193] Both the Vactive Max anomaly and the Vtotal Min anomaly are applicable to the aforementioned timing compensation method. Taking the Vtotal Min anomaly as an example, when the Vtotal Min anomaly occurs, it corresponds to the current blanking interval. At the time of the anomaly, the current Vtotal count value of the output DE signal is less than the parameter Vttl0 in the preset timing data. Therefore, when timing compensation is enabled, it will immediately stop following the input DE signal to generate the output DE signal, and will wait until the current Vtotal count value of the output DE signal reaches the parameter Vttl0 before generating the output DE signal corresponding to the next image frame according to the preset timing data.

[0194] In another timing compensation method, when it is determined that the time of the abnormality occurs is within the field blanking interval, and the input timing compensation subunit 3231 detects the abnormality, if a certain feature information corresponding to the output DE signal is greater than the corresponding preset parameter in the preset timing data, then the input timing compensation subunit 3231 immediately stops following the input DE signal to generate the output DE signal, and immediately generates the output DE signal corresponding to a complete image frame according to the preset timing data.

[0195] Among them, the Vtotal Max anomaly is applicable to the timing compensation method described above. Taking the Vtotal Max anomaly as an example, when the Vtotal Max anomaly occurs, it corresponds to the blanking interval. At the time of the anomaly, the current Vtotal count value of the output DE signal is greater than the parameter Vttl0 in the preset timing data. Therefore, when timing compensation is enabled, it will immediately stop following the input DE signal to generate the output DE signal, and will immediately generate the output DE signal corresponding to the next image frame according to the preset timing data.

[0196] In summary, when the timing is normal, the input timing compensation subunit 3231 follows the input DE signal to generate the output DE signal, while maintaining the consistency of the Hactive and Vactive feature information in the output DE signal with the set parameter values ​​in the preset timing data. When the timing is abnormal, the input timing compensation subunit 3231 stops following the input DE signal and instead completes the output DE signal corresponding to one image frame based on the preset timing signal. Furthermore, depending on the timing of the abnormality, the input timing compensation subunit 3231 employs different timing compensation methods, thereby ensuring the reliability and effectiveness of the compensated output DE signal, enabling the timing drive to operate normally and stably.

[0197] In some embodiments, the control unit 322 is further configured to generate a second control signal and a third control signal after timing compensation of the output DE signal corresponding to a frame of image is completed, and send the second control signal to the input timing compensation subunit 3231 and the third control signal to the internal timing generation subunit 3232; the input timing compensation subunit 3231 will stop working under the control of the second control signal; the internal timing generation subunit 3232 will start working under the control of the third control signal, generate an internal DE signal according to a preset timing signal, and use the internal DE signal as the output DE signal.

[0198] In specific implementation, after the input timing compensation subunit 3231 completes the timing compensation operation corresponding to one image frame, the timing detection unit 321 begins to detect the pixel clock signal and input DE signal corresponding to the next image frame. During the period of anomaly detection and before the detection result is obtained, the internal timing generation subunit 3232 generates an internal DE signal according to the preset timing signal and directly uses the internal DE signal as the output DE signal. This ensures that the output DE signal can still be output normally and stably during the timing anomaly detection of the next image frame, so that the timing drive can proceed normally and stably.

[0199] When the timing detection unit 321 detects that both the pixel clock signal and the input DE signal corresponding to the next image frame are normal, directly switching the internal DE signal to the output DE signal generated following the input DE signal would affect the stability of the frame rate. Therefore, in this embodiment of the invention, the following settings are made:

[0200] In some embodiments, the control unit 322 generates a fourth control signal and a fifth control signal when it receives a third indication signal and detects that a preset switching condition is met; the input timing compensation subunit 3231 starts working under the control of the fourth control signal and generates an output DE signal according to the input DE signal and preset timing data; the internal timing generation subunit 3232 stops working under the control of the fifth control signal.

[0201] The preset switching conditions are: the first rising edge of the input DE signal is no later than the first rising edge of the internal DE signal, and the first rising edge of the input DE signal is no earlier than the time corresponding to the lower limit of the first threshold range on the internal DE signal.

[0202] In practical implementation, a switching window can be set. When signal switching occurs within the switching window, the waveform of the output DE signal can always be guaranteed to meet the set requirements. Specifically, Figure 16 A schematic diagram of a signal waveform for switching windows is shown. For example... Figure 16 As shown, the start time of the switching window is the time corresponding to the lower limit value Vttl_Min of the first threshold range (Vttl_Min, Vttl_Max), and the end time of the switching window is the time of the first rising edge of the internal DE signal.

[0203] Figure 17 A schematic diagram of a signal waveform for signal switching is shown. For example... Figure 17As shown, for a period of time after the timing is normal (i.e. the third indicator signal is generated), the internal DE signal is still used as the output DE signal. Only when the switching opportunity arrives, that is, when the first rising edge of the input DE signal is within the switching window, will the output of the internal DE signal stop and the output DE signal be generated following the input DE signal.

[0204] In the above embodiments, when the timing is detected to be normal and it is necessary to switch from the internal DE signal to the output DE signal generated by the input DE signal, the positional relationship between the input DE signal and the internal DE signal is uncertain. Directly switching the signal will cause frame rate disorder and affect the display effect. Therefore, in the embodiments of the present invention, by setting the above-mentioned preset switching conditions, the signal switching is only performed when the timing is detected to be normal and the preset switching conditions are met. This ensures that the output DE signal always meets the set requirements and ensures frame rate stability, thereby ensuring normal image display.

[0205] Furthermore, refer to Figure 4 , Figure 5 and Figure 11 The timing processing module 32 also includes a timing path switching unit 324 and a data path switching unit 325. The timing path switching unit 324 is connected to the control unit 322 and the timing compensation unit 323 respectively. One input terminal of the timing path switching unit 324 is connected to the input timing compensation subunit 3231, and the other input terminal of the timing path switching unit 324 is connected to the internal timing generation subunit 3232. The data path switching unit 325 is connected to the control unit 322. One input of the data path switching unit 325 is used to receive image data, and the other input of the data path switching unit 325 is used to receive preset blackout data.

[0206] In some embodiments, the control unit 322 generates a first switching control signal when it receives a first indication signal, or when it receives a third indication signal and meets a preset switching condition, and sends the first switching control signal to the timing path switching unit 324; the timing path switching unit 324 outputs the output DE signal generated by the input timing compensation subunit 3231 under the control of the first switching control signal.

[0207] In some embodiments, the control unit 322 will also generate a third switching control signal when it receives the first indication signal, and send the third switching control signal to the data path switching unit 325; the data path switching unit 325 will output blackout data under the control of the third switching control signal.

[0208] It should be noted that the black-masking data in the embodiments of the present invention can be data that enables the display panel to display a black image, data that enables the display panel to display a solid color image of other colors, or data that enables the display panel to display a static image. The embodiments of the present invention do not impose any restrictions on this.

[0209] In practical implementation, when the timing detection unit 321 detects an abnormality in the pixel clock signal or the input DE signal, the control unit 322 receives a first indication signal. At this time, the control unit 322 controls the input timing compensation subunit 3231 to operate. The input timing compensation subunit 3231 performs timing compensation according to preset timing data, generates an output DE signal, and controls the timing path switching unit 324 to send the output DE signal to the subsequent stage through a first switching control signal. It also controls the data path switching unit 325 to send the black-masking data as output data to the subsequent stage through a third switching control signal. Thus, when a timing abnormality is detected, the control display panel will display a preset pattern to avoid screen flickering, distorted images, and other issues that could delay the lifespan of the display panel.

[0210] In some embodiments, when the control unit 322 receives a third indication signal and the preset switching conditions are met, it will generate a fourth switching control signal and send the fourth switching control signal to the data path switching unit 325; the data path switching unit 325 will output image data under the control of the fourth switching control signal.

[0211] In practical implementation, when the timing detection unit 321 detects that the pixel clock signal and the input DE signal are normal, the control unit 322 receives a third indication signal. When the control unit 322 detects that the preset switching conditions are met, the control unit 322 controls the input timing compensation subunit 3231 to work. The input timing compensation subunit 3231 generates an output DE signal based on the input DE signal and preset timing data, and controls the timing path switching unit 324 to send the output DE signal to the subsequent stage through the first switching control signal, and controls the data path switching unit 325 to send the image data as output data to the subsequent stage through the fourth switching control signal. In this way, when the timing is detected to be normal, the display panel can display a normal image frame.

[0212] In some embodiments, after the timing compensation of the output DE signal corresponding to a frame of image is completed, the control unit 322 will generate a second switching control signal and send the second switching control signal to the timing path switching unit 324. Under the control of the second switching control signal, the timing path switching unit 324 will output the output DE signal generated by the internal timing generation subunit.

[0213] In practical implementation, after compensating the output DE signal corresponding to one frame of image, the control unit 322 will control the input timing compensation subunit 3231 to stop working and control the internal timing generation subunit 3232 to start working. The internal timing generation subunit 3232 will generate the internal DE signal.

[0214] The control unit 322 also controls the timing path switching unit 324 to send the internal DE signal as the output DE signal to the subsequent stage through the second switching control signal, and controls the data path switching unit 325 to send the blackout data as the output data to the subsequent stage through the third switching control signal.

[0215] In the above embodiments, the timing path switching unit is used to select the output path of the input timing compensation subunit or the output path of the internal timing generation subunit under the control of the control unit, so as to ensure the normal and stable output of the DE signal; the data path switching unit is used to select the output of preset blackout data or output image data under the control of the control unit, so that when the timing is detected to be normal, the display panel can be controlled to display a normal image frame, and when the timing is detected to be abnormal, the display panel can be controlled to display a preset pattern, so as to avoid the display screen from having phenomena such as screen tearing and flickering, and delaying the service life of the display panel.

[0216] In specific implementation, the control unit 322 in this embodiment of the invention can be a state machine. Through transitions between different states, it controls various units in the timing processing module 32. Specifically, the control unit 322 has four states: free state, adjustment state, normal state, and compensation state. The following is a combination of... Figure 11 The structure shown provides a detailed description of the switching control methods between the various states in the control unit 322:

[0217] Figure 18 This diagram illustrates the interaction flow between various units within a display chip. For example... Figure 18 As shown, it includes the following steps:

[0218] Step 1801: Control unit 322 is in a free state at the initial moment;

[0219] The initial time can be either the initial time when the display chip is powered on or the initial time when the display chip is reset.

[0220] Step 1802: Control unit 322 controls internal timing generation subunit 3232 to start working, generates internal DE signal according to preset timing signal, and uses internal DE signal as output DE signal;

[0221] Step 1803: Control unit 322 controls timing path switching unit 324 to output output DE signal generated by internal timing generation subunit 3232;

[0222] Step 1804: Control unit 322 controls data path switching unit 325 to output blackout data;

[0223] Figure 19 A schematic diagram of the internal working path of the timing processing module in both free and adjusted states is shown. Figure 19 As shown, in the free state, the internal timing generation subunit 3232 is working to generate the internal DE signal, while the input timing compensation subunit 3231 is not working; the timing path switching unit 324 is used to output the output DE signal generated by the internal timing generation subunit 3232; and the data path switching unit 325 is used to output the blackout data.

[0224] Step 1805: Timing detection unit 321 detects that the pixel clock signal is normal and the input DE signal is normal;

[0225] Step 1806: Control unit 322 switches from free state to adjustment state;

[0226] Step 1807: Control unit 322 controls input timing compensation subunit 3231 to generate output DE signal following input DE signal;

[0227] Step 1808: Control unit 322 waits for the arrival of preset switching conditions;

[0228] like Figure 19 As shown, in the adjustment state, both the internal timing generation subunit 3232 and the input timing compensation subunit 3231 are working. The internal timing generation subunit 3232 is used to generate the internal DE signal, and the input timing compensation subunit 3231 is used to generate the output DE signal following the input DE signal. However, in this state, the timing path switching unit 324 still outputs the output DE signal generated by the internal timing generation subunit 3232; the data path switching unit 325 still outputs the blackout data.

[0229] Step 1809: Control unit 322 switches from adjustment state to normal state;

[0230] Step 1810: Control unit 322 controls internal timing generation subunit 3232 to stop working;

[0231] Step 1811: Control unit 322 controls timing path switching unit 324 to output the output DE signal generated by input timing compensation subunit 3231;

[0232] Step 1812: Control unit 322 controls data path switching unit 325 to output image data;

[0233] Figure 20 A schematic diagram of the internal working path of a timing processing module under normal conditions is shown. For example... Figure 20 As shown, under normal conditions, the internal timing generation subunit 3232 does not work, while the input timing compensation subunit 3231 works to generate the output DE signal following the input DE signal; the timing path switching unit 324 is used to output the output DE signal generated by the input timing compensation subunit 3231; and the data path switching unit 325 is used to output image data.

[0234] Step 1813: Timing detection unit 321 detects an abnormality in the pixel clock signal or an abnormality in the input DE signal;

[0235] Step 1814: Control unit 322 switches from normal state to compensation state;

[0236] Step 1815: Control unit 322 controls input timing compensation subunit 3231 to stop following input DE signal, and performs timing compensation according to preset timing data and the time of abnormal occurrence to generate output DE signal corresponding to one frame of image;

[0237] Step 1816: Control unit 322 controls timing path switching unit 324 to output the output DE signal generated by input timing compensation subunit 3231;

[0238] Step 1817: Control unit 322 controls data path switching unit 325 to output blackout data;

[0239] Figure 21 A schematic diagram of the internal working path of a timing processing module in a compensated state is shown. For example... Figure 21 As shown, in the compensation state, the internal timing generation subunit 3232 does not work, and the input timing compensation subunit 3231 works to generate the output DE signal according to the preset data and the time of the abnormality; the timing path switching unit 324 is used to output the output DE signal generated by the input timing compensation subunit 3231; and the data path switching unit 325 is used to output the blackout data.

[0240] Step 1818: After the control unit 322 recognizes that the output DE signal corresponding to a frame of image has been compensated, it switches back from the compensation state to the free state.

[0241] Based on the above description of the internal state transition method of control unit 322, the working states of each unit under different states are shown in the following table:

[0242]

[0243] Based on such Figure 11 The structure shown, Figure 22 A schematic diagram illustrating the overall workflow of a display chip is shown. Figure 22 As shown, the specific steps include:

[0244] In step S2201, the control unit 322 is in normal state, and the input timing compensation subunit 3231 follows the input DE signal to generate the output DE signal;

[0245] In step S2202, the timing detection unit 321 detects whether the pixel clock signal or the input DE signal is abnormal. If so, step S2203 is executed; otherwise, step S2201 is executed.

[0246] In step S2203, the control unit 322 switches from the normal state to the compensation state, and the input timing compensation subunit 3231 stops following the input DE signal;

[0247] Step S2204: Input timing compensation subunit 3231 to determine whether the time of the abnormal occurrence corresponds to the present blanking interval. If yes, execute step S2205; otherwise, execute step S2208.

[0248] Step S2205: Input timing compensation subunit 3231 to determine whether the Vtotal characteristic information of the output DE signal meets the preset requirements. If yes, then execute step S2207; otherwise, execute step S2206.

[0249] Step S2206: Wait for the Vtotal characteristic information of the output DE signal to meet the preset requirements;

[0250] Step S2207: The input timing compensation subunit 3231 generates an output DE signal corresponding to the next image frame according to the preset timing data.

[0251] Step S2208: Input timing compensation subunit 3231 completes the remaining part of the output DE signal corresponding to the image frame according to the preset timing data;

[0252] In step S2209, the control unit 322 switches from the compensation state to the free state, the input timing compensation subunit 3231 stops working, and the internal timing generation subunit 3232 generates an internal DE signal according to the preset timing data and uses the internal DE signal as the output DE signal.

[0253] In step S2210, the timing detection unit 321 detects whether the pixel clock signal or the input DE signal is abnormal. If so, step S2209 is executed; otherwise, step S2211 is executed.

[0254] In step S2211, the control unit 322 switches from the free state to the adjustment state, the input timing compensation subunit 3231 starts to follow the input DE signal, and the internal timing generation subunit 3232 continues to use the internal DE signal as the output DE signal.

[0255] In step S2212, the control unit 322 detects whether the preset switching conditions are met. If so, step S2213 is executed; otherwise, step S2211 is executed.

[0256] Step S2213: Wait for the time when the preset switching conditions are met;

[0257] In step S2214, the control unit 322 switches from the adjustment state to the normal state.

[0258] Based on the same concept, this embodiment of the invention also provides a timing control method for a display chip, which is applied to the display chip provided in any of the above embodiments. Since this method is the same method executed by the display chip in this embodiment of the invention, and the principle of solving the problem by this method is similar to that of the display chip, the implementation of this method can refer to the implementation of the display chip, and the repeated parts will not be described again.

[0259] like Figure 23 As shown, the method includes the following steps:

[0260] Step S2301: Receive the pixel clock signal and the input DE signal through the timing detection unit, and perform anomaly detection on the pixel clock signal and the input DE signal based on a preset threshold range to generate a first indication signal. The pixel clock signal and the input DE signal are determined based on the image display signal of the first image frame.

[0261] Step S2302: When the control unit receives the first indication signal, it generates a first control signal, wherein the first indication signal is used to indicate that the pixel clock signal is abnormal or the input DE signal is abnormal.

[0262] Step S2303: Under the control of the first control signal, the timing compensation unit determines the interval within the display period of the first image frame corresponding to the time of the abnormality, and performs timing compensation based on the judgment result and preset timing data to generate an output DE signal. The display period includes the field effective interval and the field blanking interval.

[0263] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0264] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A display chip, characterized by, The timing detection unit, the control unit and the timing compensation unit are connected with each other. The timing detection unit is connected with the control unit and the timing compensation unit. The timing detection unit is configured to receive a pixel clock signal and an input data enable (DE) signal, and perform abnormality detection on the pixel clock signal and the input DE signal based on a preset threshold range to generate a first indication signal, wherein the pixel clock signal and the input DE signal are determined according to image display signals of a first image frame. The control unit is configured to generate a first control signal when the first indication signal is received, wherein the first indication signal is used to indicate that the pixel clock signal is abnormal or the input DE signal is abnormal. The timing compensation unit is configured to determine a belonging interval of an abnormal occurrence time in a display period of the first image frame under the control of the first control signal, and perform timing compensation based on a determination result and preset timing data to generate an output DE signal, wherein the display period includes a field active interval and a field blanking interval.

2. The display chip of claim 1, wherein, The timing compensation unit includes an input timing compensation subunit. The timing detection unit is further configured to generate a second indication signal based on the input DE signal and a preset threshold, and send the second indication signal to the input timing compensation subunit, wherein the second indication signal is used to indicate the end of image display signals corresponding to one frame of image. The input timing compensation subunit is configured to: generate a remaining part of the output DE signal corresponding to the first image frame according to the preset timing data when it is determined that the abnormal occurrence time corresponds to the field active interval; and generate an output DE signal corresponding to a second image frame according to the preset timing data after receiving the second indication signal when it is determined that the abnormal occurrence time corresponds to the field blanking interval, wherein the second image frame is a next frame of image of the first image frame.

3. The display chip of claim 2, wherein, The timing detection unit is specifically configured to: detect the number of reference clock signals in any one period of the input DE signal to obtain a first number value of the input DE signal; generate the second indication signal when it is identified that the first number value is equal to the preset threshold; and wherein one period of the input DE signal is used to represent a row active interval and a row blanking interval of one row of pixels, the preset threshold is greater than the maximum value of the first number value corresponding to the field active interval, and less than the number of pixel clock signals corresponding to the field blanking interval.

4. The display chip of claim 2, wherein, The timing compensation unit further includes an internal timing generation subunit. The control unit is further configured to generate a second control signal and a third control signal after identifying that timing compensation of the output DE signal corresponding to one frame of image is completed. The input timing compensation subunit is further configured to stop working under the control of the second control signal. The internal timing generation subunit is configured to generate an internal DE signal according to the preset timing signal under control of the third control signal, and take the internal DE signal as the output DE signal.

5. The display chip of claim 4, wherein, The timing detection unit is further configured to perform abnormality detection on the pixel clock signal and the input DE signal based on the preset threshold range, and generate a third indication signal, where the third indication signal is used to indicate that the pixel clock signal is normal and the input DE signal is normal. The control unit is further configured to generate a fourth control signal and a fifth control signal when the third indication signal is received and it is detected that a preset switching condition is met. The input timing compensation subunit is further configured to generate the output DE signal according to the input DE signal and the preset timing data under control of the fourth control signal. The internal timing generation subunit is further configured to stop working under control of the fifth control signal.

6. The display chip of claim 5, wherein, Under control of the fourth control signal, the input timing compensation subunit is specifically configured to: take a rising edge moment of the input DE signal as a rising edge moment of the output DE; determine, according to the preset timing data, a valid level duration corresponding to one period of the output DE signal, and determine a number of periods in the output DE signal.

7. The display chip of claim 5, wherein, The preset switching condition is that: a first rising edge moment of the input DE signal is not later than a first rising edge moment of the internal DE signal, and the first rising edge moment of the input DE signal is not earlier than a moment corresponding to a lower limit value of a first threshold range on the internal DE signal. The preset threshold range includes the first threshold range, and the first threshold range is used to detect a second number value of the input DE signal, where the second number value is a number of reference clock signals detected in a period from a first rising edge moment of the input DE signal corresponding to the first frame of image to a first rising edge moment of the input DE signal corresponding to a next frame of image of the first frame of image.

8. The display chip of claim 5, wherein, The timing path switching unit and the data path switching unit are further included, where: The control unit is further configured to generate a first switching control signal when the first indication signal is received, or generate a second switching control signal after identifying that timing compensation of the output DE signal corresponding to one frame of image is completed, and generate a third switching control signal when the first indication signal is received, and generate a fourth switching control signal when the third indication signal is received and the preset switching condition is met. The timing path switching unit is configured to output the output DE signal generated by the input timing compensation subunit under control of the first switching control signal, and output the output DE signal generated by the internal timing generation subunit under control of the second switching control signal. The data path switching unit is configured to output preset black-out data under control of the third switching signal and output image data under control of the fourth switching control signal, wherein the image data is generated according to the image display signal.

9. The display chip of any one of claims 1-8, wherein, The timing detection unit comprises an input clock detection subunit and an input timing detection subunit, and the preset threshold range further comprises a second threshold range, a third threshold range, a fourth threshold range and a fifth threshold range. The input clock detection subunit is configured to identify frequency information of the pixel clock signal and perform abnormality detection on the frequency information based on the second threshold range to generate a first detection result. The input timing detection subunit is configured to identify a plurality of characteristic information of the input DE signal and perform abnormality detection on each characteristic information based on a threshold range corresponding to the characteristic information to generate a second detection result, wherein the plurality of characteristic information comprises the first quantity value, the second quantity value, a third quantity value and a fourth quantity value. The third threshold range is used for detecting the first quantity value, the fourth threshold range is used for detecting the third quantity value, the third quantity value is a number of the pixel clock signals detected in an effective level interval of one period of the input DE signal, the fifth threshold range is used for detecting the fourth quantity value, and the fourth quantity value is a number of rising edges of the input DE signal detected in a display period of one frame of image.

10. A timing control method for a display chip, characterized in that, The method is applied to the display chip according to any one of claims 1-9, and the method comprises: receiving a pixel clock signal and an input data enable (DE) signal through a timing detection unit and performing abnormality detection on the pixel clock signal and the input DE signal based on a preset threshold range to generate a first indication signal, wherein the pixel clock signal and the input DE signal are determined according to an image display signal of a first image frame; generating a first control signal through a control unit when the first indication signal is received, wherein the first indication signal is used to indicate that the pixel clock signal is abnormal or the input DE signal is abnormal; judging, through a timing compensation unit, an interval corresponding to an abnormality occurrence time in a display period of the first image frame under control of the first control signal and performing timing compensation based on a judgment result and preset timing data to generate an output DE signal, wherein the display period comprises a field effective interval and a field blanking interval.

Images