Display panel and display device

Abstract

The invention discloses a display panel and a display device, at least one sub-pixel comprises a pixel electrode, a pixel driving circuit electrically connected between the pixel electrode and a corresponding data line and a first frequency division control module, and the first frequency division control module is configured to perform frequency division control according to a frequency division control signal transmitted by a frequency division control line. And controlling signal transmission between the pixel driving circuit and the pixel electrode or the corresponding data line according to the sub-pixel display content refresh frequency so as to control the frequency of receiving the corresponding data signal by the pixel electrode, so that the sub-pixel display content refresh frequency is controlled, and the power consumption of the display panel is reduced when the sub-pixel display content refresh frequency is controlled to be reduced. Moreover, the orthographic projection of the at least one frequency division control line on the substrate is at least partially overlapped with the orthographic projection of the data line on the substrate, so that the influence of the frequency division control lines on the aperture ratio can be reduced, the demand on electric energy during sub-pixel display can be reduced, and the power consumption of the display panel is further reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] The higher the power consumption of a display panel, the more electrical energy it consumes, and the more heat it generates during operation. This negatively impacts component performance, accelerates component aging, and consequently shortens the display panel's lifespan. Therefore, there remains a need to reduce the power consumption of display panels in practical applications. Summary of the Invention

[0003] This application provides a display panel and a display device for reducing the power consumption of the display panel.

[0004] This application provides a display panel, including a substrate, multiple data lines, at least one frequency division control line, and multiple sub-pixels. The multiple data lines are located on the substrate, and each data line is configured to transmit a data signal. At least one frequency division control line is located on the substrate, and each frequency division control line is configured to transmit a frequency division control signal. Multiple sub-pixels are located on the substrate. At least one sub-pixel includes a pixel electrode, a pixel driving circuit, and a first frequency division control module. The pixel driving circuit and the first frequency division control module are electrically connected between the pixel electrode and the corresponding data line. The first frequency division control module is configured to control the signal transmission between the pixel driving circuit and the pixel electrode or the corresponding data line according to the frequency division control signal transmitted by the frequency division control line, thereby controlling the frequency at which the pixel electrode receives the corresponding data signal. The orthographic projection of the at least one frequency division control line on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

[0005] This application also provides a display device including any of the above-described display panels.

[0006] In the above technical solution, by including at least one sub-pixel with a pixel electrode, a pixel driving circuit electrically connected between the pixel electrode and a corresponding data line, and a first frequency division control module, the first frequency division control module controls the signal transmission between the pixel driving circuit and the pixel electrode or the corresponding data line according to the frequency division control signal transmitted by a frequency division control line. This controls the frequency at which the pixel electrode receives the corresponding data signal, thereby controlling the refresh rate of the sub-pixel display content. This reduces the power consumption of the display panel when the refresh rate of the sub-pixel display content is reduced. Furthermore, by ensuring that the orthographic projection of at least one frequency division control line on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate, the influence of the frequency division control line on the aperture ratio can be reduced, which helps to reduce the power demand during sub-pixel display, further reducing the power consumption of the display panel. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0008] Figures 1A-1B This is a schematic diagram of the structure of the display panel provided in an embodiment of this application; Figure 2 A cross-sectional schematic diagram of the display panel provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a sub-pixel provided in an embodiment of this application; Figure 4 Timing diagram of the frequency division control signal and multiple scanning signals provided in the embodiments of this application; Figure 5 This is a schematic diagram of the gate driving module provided in an embodiment of this application; Figures 6A-6B A circuit diagram of the gate drive circuit provided in an embodiment of this application; Figure 7 Timing diagrams of multiple scanning signals provided in embodiments of this application; Figure 8 Timing diagram of the frequency division control signal, output frequency division signal and multiple scanning signals provided in the embodiments of this application; Figures 9A-9B This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0009] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0011] It should be noted that the electrical connection referred to in this application can include both direct and indirect connections. Indirect connections can include connections between connected modules, devices, and nodes achieved through electrical components, wired or wireless media, etc. An electrical connection can refer to a physically existing connection or a connection established through signals.

[0012] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the various technical features in this application can be applied to achieve different combinations, and are not limited to the technical solutions formed by the combinations listed in the embodiments. Technical solutions between different embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "optionally" and "in some embodiments" used in this application indicate that the technical content they refer to can be selectively configured.

[0013] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention.

[0014] Figures 1A-1B This is a schematic diagram of the structure of the display panel provided in an embodiment of this application. Figure 2 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application. This application provides a display panel including a substrate 100, multiple data lines DL, at least one frequency division control line FL, and multiple sub-pixels Spx.

[0015] The substrate 100 may include at least one of a rigid substrate and a flexible substrate. The rigid substrate may include a glass substrate. The flexible substrate may include polyimide, etc. The substrate 100 may include at least one of a substrate, a barrier layer, and a buffer layer, etc.

[0016] Multiple data lines DL are located on the substrate 100, and each data line DL is configured to transmit data signals.

[0017] At least one frequency divider control line FL is located on the substrate 100, and each frequency divider control line FL is configured to transmit a frequency divider control signal.

[0018] Multiple sub-pixels Spx are located on substrate 100. The multiple sub-pixels Spx are electrically connected to multiple data lines DL. The multiple sub-pixels Spx are configured to display according to the corresponding data signals to realize the display function of the display panel.

[0019] At least one sub-pixel Spx may include a first frequency division control module 20, a pixel driving circuit 30, and a pixel electrode 40. The pixel driving circuit 30 and the first frequency division control module 20 are electrically connected between the pixel electrode 40 and the corresponding data line DL. The first frequency division control module 20 is configured to control the signal transmission between the pixel driving circuit 30 and the pixel electrode 40 or the corresponding data line DL according to the frequency division control signal transmitted by a frequency division control line FL, so as to control the frequency at which the pixel electrode 40 receives the corresponding data signal, thereby controlling the refresh rate of the sub-pixel Spx display content, and thus reducing the power consumption of the display panel when the refresh rate of the sub-pixel Spx display content is reduced.

[0020] For ease of understanding, the sub-pixel Spx, including the first frequency division control module 20, will be referred to as a frequency-divided sub-pixel. Specifically, in a frequency-divided sub-pixel, the first frequency division control module 20 and the pixel driving circuit 30 are disposed between the pixel electrode 40 and the corresponding data line DL. In the frequency-divided sub-pixel, the first frequency division module controls the signal transmission path between the pixel electrode 40 and the corresponding data line DL to be disconnected, thus preventing the pixel electrode 40 from receiving the corresponding data signal. Therefore, the first frequency division control module 20 can be used to control the frequency at which the pixel electrode 40 receives the corresponding data signal, thereby controlling the number of times the sub-pixel Spx displays its content.

[0021] In some embodiments, in a frequency-divided sub-pixel, the pixel driving circuit 30 is electrically connected between the first frequency-dividing control module 20 and the pixel electrode 40, and the first frequency-dividing control module 20 is electrically connected between the pixel driving circuit 30 and the corresponding data line DL. The first frequency-dividing control module 20 is configured to control the signal transmission between the pixel driving circuit 30 and the corresponding data line DL according to the frequency-dividing control signal transmitted by the corresponding frequency-dividing control line FL, so as to control the frequency at which the pixel electrode 40 receives the corresponding data signal.

[0022] In other embodiments, in a frequency-divided sub-pixel, the pixel driving circuit 30 is electrically connected between the corresponding data line DL and the first frequency-dividing control module 20, and the first frequency-dividing control module 20 is electrically connected between the pixel electrode 40 and the pixel driving circuit 30. The first frequency-dividing control module 20 is configured to control the signal transmission between the pixel driving circuit 30 and the pixel electrode 40 according to the frequency-dividing control signal transmitted on the corresponding frequency-dividing control line FL, so as to control the frequency at which the pixel electrode 40 receives the corresponding data signal.

[0023] Optionally, each sub-pixel Spx may include a pixel driving circuit 30 and a pixel electrode 40, so that multiple sub-pixels Spx can realize the display function of the display panel according to the corresponding data signal. At least one frequency-divided sub-pixel is included among the multiple sub-pixels Spx, so that the refresh rate of the frequency-divided sub-pixel display can be reduced by the frequency-dividing control signal and the first frequency-dividing control module 20, thereby reducing the power consumption of the display panel.

[0024] It should be noted that in the display panel, one or more sub-pixels Spx may include the first frequency division control module 20. In some embodiments, depending on the actual application, sub-pixels Spx in a certain area may include the first frequency division control module 20. In other embodiments, each sub-pixel Spx in the display panel may include the first frequency division control module 20.

[0025] Figure 3 This is a schematic diagram of the sub-pixel structure provided in an embodiment of this application. The orthographic projection of at least one frequency division control line FL on the substrate 100 at least partially overlaps with the orthographic projection of the data line DL on the substrate 100, so as to reduce the influence of the frequency division control line FL on the aperture ratio of the sub-pixel Spx, which is beneficial to reduce the power demand of the sub-pixel Spx when it is displayed, and further reduce the power consumption of the display panel.

[0026] In some embodiments, multiple data lines DL are arranged along a first direction Dr1, and each data line DL extends along a second direction Dr2 that intersects the first direction Dr1. The display panel includes a frequency divider control line FL extending along the second direction Dr2, and the orthographic projection of the frequency divider control line FL on the substrate 100 partially overlaps with the orthographic projection of a data line DL on the substrate 100.

[0027] Optionally, the first direction Dr1 can be either the row direction or the column direction, and the second direction Dr2 can be either the row direction or the column direction.

[0028] It should be noted that, in the second direction Dr2, the data line DL can extend in at least one shape, such as a straight line, a curve, or a broken line. The number of frequency division control lines FL that overlap with the orthographic projection of the same data line DL on the substrate 100 can be greater than or equal to 1.

[0029] In some embodiments, a plurality of sub-pixels Spx arranged along the second direction Dr2 are electrically connected to the same data line DL to reduce the number of data lines DL included in the display panel.

[0030] Optionally, to reduce the number of frequency division control lines FL included in the display panel, and further reduce the impact of the frequency division control lines FL on the aperture ratio of sub-pixels Spx, while achieving frequency control of the data signals received by multiple sub-pixels Spx, the display panel may include multiple pixel groups SG, which are arranged along a first direction Dr1. Each pixel group SG includes multiple pixel units SU arranged along a second direction Dr2, and each pixel unit SU includes at least one sub-pixel Spx. A frequency division control line FL is connected to a first frequency division control module 20 of multiple sub-pixels Spx in the same pixel group SG, so that multiple sub-pixels Spx in the same pixel group SG share the frequency division control signal transmitted by the same frequency division control line FL, thereby using the same frequency division control signal to achieve frequency control of the data signals received by multiple sub-pixels Spx in the same pixel group SG.

[0031] In some embodiments, the display panel may include multiple frequency division control lines FL, and each pixel unit SU includes a sub-pixel Spx, such as Figure 1A As shown. Each frequency division control line FL is connected to the first frequency division control module 20 of multiple sub-pixels Spx in the same pixel group SG. The orthographic projection of each frequency division control line FL on the substrate 100 at least partially overlaps with the orthographic projection of a data line DL on the substrate 100. This reduces the impact of the multiple frequency division control lines FL on the aperture ratio of the sub-pixels Spx while simultaneously achieving frequency control of the data signals received by the multiple sub-pixels Spx in the multiple sub-pixel groups SG.

[0032] It should be noted that the frequency division control signals transmitted by multiple frequency division control lines (FL) can be the same or different.

[0033] Optionally, to reduce the winding distance of the frequency division control line FL and reduce the impact of the frequency division control line FL on the aperture ratio, the frequency division control line FL can be overlapped with the data line DL corresponding to the frequency division sub-pixel.

[0034] Taking the first direction Dr1 as the row direction and the second direction Dr2 as the column direction as an example, multiple sub-pixels Spx arranged in the second direction Dr2 are electrically connected to the same data line DL. Multiple sub-pixels Spx located in the s-th column are electrically connected to the s-th data line. The orthographic projection of the frequency division control line FL, which is electrically connected to the frequency division sub-pixel located in the r-th column, on the substrate 100 at least partially overlaps with the orthographic projection of the r-th data line on the substrate 100. Wherein, s≥1, r≥1.

[0035] In some embodiments, each pixel unit SU includes a plurality of sub-pixels Spx arranged along a first direction Dr1, such as Figure 1BAs shown, the display panel includes multiple first connection lines CL1, each first connection line CL1 extending along a first direction Dr1, and each first connection line CL1 connecting multiple sub-pixels Spx in a pixel unit SU and the corresponding frequency division control line FL, so as to realize the electrical connection between multiple sub-pixels Spx in the same pixel unit SU and the corresponding frequency division control line FL.

[0036] Optionally, when multiple adjacent sub-pixels Spx along the first direction Dr1 share the same frequency division control line FL, the frequency division control line FL can be overlapped with the data line DL corresponding to the pixel group SG including the frequency division sub-pixels to reduce the winding distance of the frequency division control line FL and reduce the influence of the frequency division control line FL on the aperture ratio. Taking the first direction Dr1 as the row direction and the second direction Dr2 as the column direction as an example, multiple sub-pixels Spx located in the s-th column are electrically connected to the s-th data line, and the pixel group SG including the frequency division sub-pixels is electrically connected to the r1-r2 data lines. The orthographic projection of the frequency division control line FL corresponding to the pixel group SG including the frequency division sub-pixels on the substrate 100 at least partially overlaps with the orthographic projection of one of the r1-r2 data lines on the substrate 100. Wherein, r1≥1, r2>r1.

[0037] Optionally, in order to achieve display control with different refresh rates in different areas of the display panel, multiple pixel groups SG can be controlled by the same or different frequency division control signals.

[0038] In some embodiments, the display panel includes a first unit group SUG1 and a second unit group SUG2 adjacent along a first direction Dr1, and the first unit group SUG1 and the second unit group SUG2 each include at least one pixel group SG. The display panel includes multiple frequency division control lines FL, including a first frequency division control line FL1 and a second frequency division control line FL2. The first frequency division control line FL1 is connected to a first frequency division control module 20 of multiple sub-pixels Spx in the first unit group SUG1, and the second frequency division control line FL2 is connected to the first frequency division control module 20 of multiple sub-pixels Spx in the second unit group SUG2. The first frequency division control line FL1 is configured to transmit a first frequency division control signal Fd1, and the second frequency division control line FL2 is configured to transmit a second frequency division control signal Fd2. In at least one display cycle of the display panel, the frequency of the first frequency division control signal Fd1 is different from the frequency of the second frequency division control signal Fd2, so that in at least one display cycle, multiple sub-pixels Spx of the first unit group SUG1 and multiple sub-pixels Spx of the second unit group SUG2 can be displayed at different refresh frequencies.

[0039] It should be noted that the first frequency division control line FL1 can be set to one or more. For example, in some embodiments, one first frequency division control line FL1 can be set for each pixel group SG included in the first unit group SUG1, and the orthographic projection of each first frequency division control line FL1 on the substrate 100 partially overlaps with the orthographic projection of a data line DL on the substrate 100. In other embodiments, one first frequency division control line FL1 can be set for multiple pixel groups SG included in the first unit group SUG1, and the orthographic projection of the first frequency division control line FL1 on the substrate 100 partially overlaps with the orthographic projection of one of the multiple data lines DL corresponding to the first unit group SUG1 on the substrate 100. Multiple pixel groups SG adjacent along the first direction Dr1 in the first unit group SUG1 can be connected by a second connecting line connected to the first frequency division control line FL1. Similarly, the second frequency division control line FL2 can also be set to one or more, which will not be elaborated further here.

[0040] In some embodiments, the display panel further includes a third unit group SUG3 located on the side of the second unit group SUG2 away from the first unit group SUG1, the third unit group SUG3 including at least one pixel group SG. Multiple frequency division control lines FL include a third frequency division control line FL3, which is connected to a first frequency division control module 20 of multiple sub-pixels Spx of the third unit group SUG3. The third frequency division control line FL3 is configured to transmit a third frequency division control signal Fd3. During at least one display cycle, at least one of the frequencies of the first frequency division control signal Fd1 and the second frequency division control signal Fd2 is different from the frequency of the third frequency division control signal Fd3, so that during at least one display cycle, the multiple sub-pixels Spx of the third unit group SUG3 are displayed at a different refresh rate than at least one of the multiple sub-pixels Spx of the first unit group SUG1 and the multiple sub-pixels Spx of the second unit group SUG2.

[0041] It should be noted that the display panel can also include only one of the first unit group SUG1, the second unit group SUG2, and the third unit group SUG3, so that the refresh frequency of different areas of the display panel can be controlled by a frequency division control signal. For example, in some embodiments, the display panel only includes the first unit group SUG1, and only the sub-pixels Spx included in the first unit group SUG1 are frequency-divided sub-pixels. The sub-pixels Spx located outside the first unit group SUG1 do not include the first frequency division control module 20. In this case, by controlling the first frequency division control signal Fd1 and the frequency-divided sub-pixels, the refresh frequency of the area of ​​the display panel corresponding to the first unit group SUG1 can still be made different from the refresh frequency of other areas.

[0042] In practical applications of display panels, the area corresponding to the center of the display panel is more likely to receive more attention. Therefore, the area corresponding to the second unit group SUG2 can be displayed at a higher refresh rate. For example, in some embodiments, in one display cycle, multiple sub-pixels Spx of the first unit group SUG1 are displayed at a first refresh rate, multiple sub-pixels Spx of the second unit group SUG2 are displayed at a second refresh rate, and multiple sub-pixels Spx of the third unit group SUG3 are displayed at a third refresh rate; the second refresh rate is greater than the first refresh rate, and the first refresh rate is greater than or equal to the third refresh rate.

[0043] Optionally, the number of frames included in a display cycle and the duration of the display cycle can be determined based on the refresh rate.

[0044] In some embodiments, the second refresh rate is greater than the first refresh rate, and the first refresh rate is greater than or equal to the third refresh rate. The display period includes X frames, where X is equal to the ratio of the second refresh rate to the third refresh rate. The duration of each frame is equal to the reciprocal of the second refresh rate, and the duration of one display period is equal to the reciprocal of the third refresh rate.

[0045] In some embodiments, X ≥ 2. The first refresh rate to the third refresh rate can be equal to 360Hz, 250Hz, 120Hz, 90Hz, 60Hz, 50Hz, 30Hz, 10Hz or 1Hz, respectively.

[0046] It should be understood that the second refresh rate can be less than or equal to the first refresh rate, and the first refresh rate can be less than or equal to the third refresh rate.

[0047] Optionally, when only one frequency division control signal is applied to the display panel, the duration of one display cycle can be equal to the reciprocal of the refresh frequency applied to the area corresponding to the frequency division control signal.

[0048] Please continue reading. Figures 1A-1B The display panel includes multiple scan lines SL, each scan line SL is configured to transmit a scan signal, and each scan line SL is electrically connected to a pixel driving circuit 30 of at least one sub-pixel Spx. In each sub-pixel Spx, the pixel driving circuit 30 is configured to control the frequency at which the pixel electrode 40 receives a corresponding data signal according to the corresponding scan signal.

[0049] Optionally, multiple scan lines SL are arranged along the second direction Dr2, and each scan line SL extends along the first direction Dr1. Each scan line SL is electrically connected to multiple sub-pixels Spx, so that the multiple sub-pixels Spx share the same scan signal. Taking the first direction Dr1 as the row direction and the second direction Dr2 as the column direction as an example, each scan line SL is electrically connected to multiple sub-pixels Spx located in the same row, so that the multiple sub-pixels Spx located in the same row share the same scan signal, and multiple sub-pixels Spx located in different rows apply different scan signals.

[0050] Optionally, the display panel may include a gate driving module 50, which is electrically connected to multiple scan lines SL. The gate driving module 50 includes multiple cascaded gate driving circuits GA, each of which is configured to generate a scan signal to be output to the corresponding scan line SL.

[0051] Optionally, the pixel driving circuit 30 includes a first transistor T1, and the first frequency division control module 20 includes a second transistor T2. The control terminal of the first transistor T1 is electrically connected to the corresponding scan line SL, and the first source-drain terminal of the first transistor T1 is electrically connected to one of the pixel electrode 40 and the corresponding data line DL. The control terminal of the second transistor T2 is electrically connected to the corresponding frequency division control line FL, and the first source-drain terminal of the second transistor T2 is electrically connected to the other of the corresponding data line DL and the pixel electrode 40. The second source-drain terminal of the second transistor T2 is electrically connected to the second source-drain terminal of the first transistor T1. The first transistor T1 is configured to be turned on or off according to the corresponding scan signal. The second transistor T2 is configured to be turned on or off according to the corresponding frequency division control signal.

[0052] It should be noted that the first transistor T1 and the second transistor T2 can be either P-type transistors or N-type transistors, respectively. The first transistor T1 and the second transistor T2 can be implemented as bipolar junction transistors, field-effect transistors, or thin-film transistors, respectively. When the transistors are implemented as field-effect transistors or thin-film transistors, the aforementioned control terminal can be the gate, the first source-drain terminal can be one of the source and drain, and the second source-drain terminal can be the other of the source and drain. When the transistors are implemented as bipolar junction transistors, the aforementioned control terminal can be the base, the first source-drain terminal can be one of the collector and emitter, and the second source-drain terminal can be the other of the collector and emitter. Each transistor can employ a single-gate or dual-gate design. The active layer 107 of each transistor can include silicon semiconductor material or oxide semiconductor material. The silicon semiconductor material includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon, etc. The oxide semiconductor material includes indium gallium zinc oxide or indium zinc oxide, etc.

[0053] Optionally, to allow the frequency division control line FL to overlap with the data line DL, the frequency division control line FL and the data line DL can be located on different layers. To reduce the risk of short circuits between the frequency division control line FL and the scan line SL, the frequency division control line FL and the scan line SL can be located on different layers.

[0054] Please continue reading. Figures 1A-1B and Figures 2-3 The display panel also includes a first metal layer 101, a second metal layer 102 and a third metal layer 103.

[0055] A first metal layer 101 is located on the substrate 100 and includes multiple scan lines SL. A second metal layer 102 is located on the first metal layer 101 and includes multiple data lines DL. A third metal layer 103 is located on the second metal layer 102 and includes at least one frequency division control line FL.

[0056] Optionally, to reduce the risk of short circuits between the frequency division control line FL and the scan line SL and data line DL, the display panel may also include a first insulating layer 104, a second insulating layer 105 and a third insulating layer 106.

[0057] The first insulating layer 104 is located on the first metal layer 101, the second insulating layer 105 is located on the second metal layer 102, and the third insulating layer 106 is located on the third metal layer 103.

[0058] It is understandable that the first metal layer 101 to the third metal layer 103 can be made of conductive materials, and the first insulating layer 104 to the third insulating layer 106 can be made of insulating materials.

[0059] It should be noted that the first insulating layer 104 may be referred to as the gate insulating layer, and the second insulating layer 105 may include at least one of the following: a protective layer 1051, an organic planarization layer 1052, and a buffer layer 1053.

[0060] Optionally, the first metal layer 101 further includes a first electrode Ed1 and a second electrode Ed2 disposed at intervals, the second electrode Ed2 being connected to a corresponding frequency division control line FL. The display panel also includes an active layer 107 and a pixel electrode layer 108. The active layer 107 includes a first active pattern pl1 and a second active pattern pl2, the orthographic projection of the first active pattern pl1 on the substrate 100 partially overlapping the orthographic projection of the first electrode Ed1 on the substrate 100, and the orthographic projection of the second active pattern pl2 on the substrate 100 partially overlapping the orthographic projection of the second electrode Ed2 on the substrate 100. The second metal layer 102 further includes a third electrode Ed3, a fourth electrode Ed4, and a fifth electrode Ed5, the third electrode Ed3 being located on the first active pattern pl1 and disposed at intervals from the fourth electrode Ed4, the fourth electrode Ed4 being located on the first active pattern pl1 and the second active pattern pl2, and the fifth electrode Ed5 being located on the second active pattern pl2 and disposed at intervals from the fourth electrode Ed4. The pixel electrode layer 108 is located on the third insulating layer 106. The pixel electrode layer 108 includes a pixel electrode 40, which is connected to the third electrode Ed3.

[0061] Among them, the first electrode Ed1 can be used as the control terminal of the first transistor T1, the second electrode Ed2 can be used as the control terminal of the second transistor T2, the third electrode Ed3 can be used as the first source-drain terminal of the first transistor T1, the fourth electrode Ed4 can be used as the second source-drain terminal of the first transistor T1 and the second source-drain terminal of the second transistor T2, and the fifth electrode Ed5 can be used as the first source-drain terminal of the second transistor T2.

[0062] Optionally, the pixel electrode layer 108 may include a first connection portion Cn1, which is connected between the second electrode Ed2 and the corresponding frequency division control line FL through a via penetrating the first insulating layer 104, the second insulating layer 105, and the third insulating layer 106. The third electrode Ed3 is connected to the pixel electrode 40 through a via penetrating the second insulating layer 105 and the third insulating layer 106.

[0063] Optionally, the display panel further includes a common electrode layer 109, which is located between the second insulating layer 105 and the third insulating layer 106, and includes a common electrode Ec. The first metal layer 101 may also include a sixth electrode Ed6, which is connected to the common electrode Ec.

[0064] Optionally, the pixel electrode layer 108 may include a second connection portion Cn2, which is connected between the common electrode Ec and the sixth electrode Ed6 through a via penetrating the first insulating layer 104, the second insulating layer 105 and the third insulating layer 106.

[0065] Figure 4This is a timing diagram of the frequency division control signal and multiple scan signals provided in the embodiments of this application. To facilitate understanding of the frequency control of the first frequency division control module 20 on the pixel electrode 40 receiving the corresponding data signal, the first transistor T1 and the second transistor T2 are N-type transistors. The display panel includes F scan lines, each receiving F scan signals. The first direction Dr1 is the row direction, and the second direction Dr2 is the column direction. Figure 1B The design shown is used as an example for illustration. Where F ≥ 1.

[0066] In the first frame of a display cycle, the first-level scan signal Scan(1) to the F-level scan signal Scan(F) sequentially have valid pulses, and the first frequency division control signal Fd1 to the third frequency division control signal Fd3 are at a high level. Therefore, in the first frame, the second transistor T2 included in the multiple sub-pixels Spx in the first unit group SUG1 to the third unit group SUG3 is turned on. When the first-level scan signal Scan(1) has a valid pulse, the first transistor T1 included in the multiple sub-pixels Spx located in the first row is turned on, and the pixel electrode 40 included in the multiple sub-pixels Spx located in the first row receives the corresponding data signal. When the second-level scan signal Scan(2) has a valid pulse, the first transistor T1 included in the multiple sub-pixels Spx located in the second row is turned on, and the pixel electrode 40 included in the multiple sub-pixels Spx located in the second row receives the corresponding data signal. Similarly, when the F-th scan signal Scan(F) has a valid pulse, the first transistor T1 of the multiple sub-pixels Spx located in the F-th row is turned on, and the pixel electrode 40 of the multiple sub-pixels Spx located in the F-th row receives the corresponding data signal. Therefore, in the first frame, the multiple sub-pixels Spx in the first unit group SUG1 to the third unit group SUG3 all receive the corresponding data signal.

[0067] In the second frame of a display cycle, the first-level scan signal Scan(1) to the F-level scan signal Scan(F) sequentially have valid pulses, the first frequency division control signal Fd1 and the third frequency division control signal Fd3 are at low levels, and the second frequency division control signal Fd2 is at a high level. Therefore, in the second frame, the second transistor T2 included in the multiple sub-pixels Spx in the first unit group SUG1 and the third unit group SUG3 is turned off, and the second transistor T2 included in the multiple sub-pixels Spx in the second unit group SUG2 is turned on. When the first-level scan signal Scan(1) has a valid pulse, the first transistor T1 included in the multiple sub-pixels Spx located in the first row is turned on. However, because the second transistor T2 included in the multiple sub-pixels Spx in the first unit group SUG1 and the third unit group SUG3 is turned off, the pixel electrode 40 included in the multiple sub-pixels Spx located in the first row and in the second unit group SUG2 receives the corresponding data signal, while the pixel electrode 40 included in the multiple sub-pixels Spx located in the first row and in the first unit group SUG1 and the third unit group SUG3 does not receive the corresponding data signal. When the second-level scan signal Scan(2) has a valid pulse, because the second transistor T2 included in the multiple sub-pixels Spx in the first unit group SUG1 and the third unit group SUG3 is turned off, the pixel electrode 40 included in the multiple sub-pixels Spx located in the second row and in the second unit group SUG2 receives the corresponding data signal, while the pixel electrode 40 included in the multiple sub-pixels Spx located in the second row and in the first unit group SUG1 and the third unit group SUG3 does not receive the corresponding data signal. Similarly, when the F-th scan signal Scan(F) has a valid pulse, the first transistor T1 of the multiple sub-pixels Spx located in the F-th row is turned on, and the pixel electrode 40 of the multiple sub-pixels Spx located in the F-th row and in the second unit group SUG2 receives the corresponding data signal. The pixel electrode 40 of the multiple sub-pixels Spx located in the F-th row and in the first unit group SUG1 and the third unit group SUG3 does not receive the corresponding data signal. Therefore, in the second frame, the multiple sub-pixels Spx in the first unit group SUG1 and the third unit group SUG3 do not receive the corresponding data signal, while the multiple sub-pixels Spx in the second unit group SUG2 receive the corresponding data signal.

[0068] By analogy, the design of whether the first unit group SUG1 to the third unit group SUG3 receive the corresponding data signals in the remaining frames of a display cycle is obtained.

[0069] Therefore, in one display cycle, multiple sub-pixels Spx of the first unit group SUG1 to the third unit group SUG3 can be displayed at different refresh rates, thus realizing the frequency division design of the display panel.

[0070] exist Figure 4The example described uses the case where the first frequency division control signal Fd1 to the third frequency division control signal Fd3 maintain the same level within one frame. However, in some embodiments, at least one of the first frequency division control signal Fd1 to the third frequency division control signal Fd3 may have a level change within one frame.

[0071] Similarly, corresponding results can be obtained. Figure 1A The frequency division design principle of the display panel corresponding to the design shown will not be elaborated here.

[0072] It should be understood that, Figures 1A-1B The example described uses the arrangement of the first unit group SUG1 to the third unit group SUG3 along the first direction Dr1. However, it should be noted that the first unit group SUG1 to the third unit group SUG3 can also be arranged along the second direction Dr2.

[0073] It should be noted that, Figures 1A-1B This description uses only the example of the pixel driving circuit 30 and the first frequency division control module 20 each including a transistor as an example. However, this does not limit the pixel driving circuit 30 and the first frequency division control module 20 to adopt only the above design. Those skilled in the art can still modify the design of the pixel driving circuit 30 and the first frequency division control module 20 based on the content disclosed in this application, and implement the design of the pixel driving circuit 30 and the first frequency division control module 20 in a simpler or more complex form or with more components. Among them, components include, but are not limited to, transistors, capacitors, resistors, etc.

[0074] In the frequency-divided sub-pixel, since the signal transmission path between the pixel electrode 40 and the corresponding data line DL is controlled by the first frequency-dividing control module 20 and the pixel driving circuit 30, in addition to controlling the frequency of the pixel electrode 40 receiving the corresponding data signal by controlling the first frequency-dividing control module 20, the frequency of the pixel electrode 40 receiving the corresponding data signal can also be controlled by controlling the pixel driving circuit 30. That is, at least one of the first frequency-dividing control module 20 and the pixel driving circuit 30 can be used to control the frequency of the pixel electrode 40 receiving the corresponding data signal, thereby controlling the refresh rate of the sub-pixel Spx display content.

[0075] Optionally, in order to use the pixel driving circuit 30 to achieve frequency control of the data signal received by the pixel electrode 40, the number of effective pulses of the scan signal Scan generated by the gate driving circuit GA can be controlled.

[0076] like Figure 5 This is a schematic diagram of the gate driving module provided in an embodiment of this application. Figures 6A-6B This is a circuit diagram of the gate driving circuit provided in an embodiment of this application. To facilitate understanding of the gate driving module 50 of this application, [the following is a description of the circuit diagram]. Figure 5 and Figures 6A-6B An example is provided. However, it should be understood that... Figure 5 and Figures 6A-6B This is not intended to limit the gate drive module 50 and gate drive circuit GA of this application to only adopt the form shown in the figure. Based on the functions required to be implemented by the gate drive module 50 and gate drive circuit GA of this application, the specific implementation of the gate drive module 50 and gate drive circuit GA can still be changed.

[0077] In some embodiments, at least one gate drive circuit GA includes a pull-up module 501, a gate output module 502, and a second frequency division control module 503, such as Figure 5 and Figures 6A-6B As shown.

[0078] Pull-up module 501 is electrically connected to the first node No1 of the gate drive circuit GA of this stage. Pull-up module 501 is configured to control the signal transmission between the first node No1 and the start signal line STL according to the start signal transmitted by the start signal line STL. The start signal is either a frame start signal or a signal output by the previous stage gate drive circuit GA.

[0079] In some embodiments, the start signal corresponding to the first m gate driving circuits GA(m) in the plurality of gate driving circuits GA is the frame start signal, and the start signal corresponding to the nth gate driving circuit GA(n) is the signal output by the nAth gate driving circuit GA(nA). Wherein, m≥1, n>1, nA>0, A≥1. In some embodiments, A=4.

[0080] Please continue reading. Figures 6A-6B The gate output module 502 is electrically connected to the first node No1 via the second node No2 of the gate drive circuit GA. The gate output module 502 is configured to control the signal transmission between the corresponding clock signal line and the gate output terminal of the gate drive circuit GA according to the signal of the second node No2. The gate output terminal OT1 is configured to output the scan signal Scan of this stage. The clock signal line is used to transmit the clock signal CK.

[0081] The second frequency division control module 503 is electrically connected to the first node No1 and the second node No2. The second frequency division control module 503 is configured to control the formation of a current path between the second node No2 and the first node No1 or the first power supply terminal VSSQ according to the output frequency division signal, so as to control the effective number of scan signals Scan output by the gate drive circuit GA of this stage.

[0082] Optionally, to prevent the first node No1 and the first power supply terminal VSSQ from simultaneously forming a current path with the second node No2, the output frequency division signal may include a first output frequency division signal Fo1 and a second output frequency division signal Fo2, and the second frequency division control module 503 may include a first frequency division unit 5031 and a second frequency division unit 5032, such as... Figures 6A-6B As shown.

[0083] The first frequency divider unit 5031 is electrically connected between the first node No1 and the second node No2. The first frequency divider unit 5031 is configured to control the signal transmission between the first node No1 and the second node No2 according to the first output frequency divider signal Fo1.

[0084] The second frequency divider unit 5032 is electrically connected between the second node No2 and the first power supply terminal VSSQ. The second frequency divider unit 5032 is configured to disconnect the current path between the second node No2 and the first power supply terminal VSSQ according to the first output frequency divider signal Fo1 when the first frequency divider unit 5031 connects the current path between the first node No1 and the second node No2; and is configured to connect the current path between the second node No2 and the first power supply terminal VSSQ according to the first output frequency divider signal Fo1 and the second output frequency divider signal Fo2 when the first frequency divider unit 5031 disconnects the current path between the first node No1 and the second node No2.

[0085] Optionally, to reduce the number of control signals for the application corresponding to the gate drive module 50, the multi-stage gate drive circuit GA can share the same first output divider signal Fo1 and the same second output divider signal Fo2, such as... Figure 5 As shown.

[0086] Optionally, to ensure that the gate output terminal OT1 of the gate drive circuit GA has a relatively stable output state during the invalid level period of the corresponding output scan signal Scan, at least one gate drive circuit GA further includes a pull-down sustaining module 504, a first pull-down module 505, and a second pull-down module 506, such as... Figures 6A-6B As shown.

[0087] The pull-down sustaining module 504 is electrically connected to the first node No1 and the gate output terminal OT1. The pull-down sustaining module 504 is configured to control the signal transmission between the first node No1 and the first power supply terminal VSSQ, and to control the signal transmission between the gate output terminal OT1 and the second power supply terminal VSSG, based on the signal of the first node No1 and the first control signal LC.

[0088] The first pull-down module 505 is electrically connected to the first node No1. The first pull-down module 505 is configured to control the electrical signal transmission between the first node No1 and the first power supply terminal VSSQ according to the first pull-down control signal transmitted by the first pull-down control line DCL1.

[0089] The second pull-down module 506 is electrically connected to the gate output terminal OT1. The second pull-down module 506 is configured to control the signal transmission between the gate output terminal OT1 and the second power supply terminal VSSG according to the second pull-down control signal transmitted by the second pull-down control line DCL2.

[0090] It should be noted that the first control signal LC can also be called the low-frequency clock signal, and the first pull-down control signal and the second pull-down control signal can be the signals output by the subsequent gate drive circuit GA, respectively.

[0091] In some embodiments, the first pull-down control signal corresponding to the nth-stage gate drive circuit GA(n) is the signal output by the (n+B)th-stage gate drive circuit GA(n+B), and the second pull-down control signal corresponding to the nth-stage gate drive circuit GA(n) is the signal output by the (n+C)th-stage gate drive circuit GA(n+C), where C≥1 and B≥C. In some embodiments, B=5 and C=4.

[0092] Optionally, the pull-down sustaining module 504 may include a single inverting unit 5041 and a single pull-down sustaining unit 5042; or, the pull-down sustaining module 504 may include two inverting units 5041 and two pull-down sustaining units 5042.

[0093] In some embodiments, the pull-down sustaining module 504 may include an inverting unit 5041 and a pull-down sustaining unit 5042, such as Figure 6A As shown. The inverting unit 5041 is electrically connected to the first node No1 and the third node No3 of the gate drive circuit GA. The inverting unit 5041 is configured to control the third node No3 to form a time-division multiplexing current path between the first control line and the first power supply terminal VSSQ based on the signal from the first node No1 and the first control signal LC transmitted via the first control line. The pull-down sustaining unit 5042 is electrically connected to the first node No1, the third node No3, and the gate output terminal OT1. The pull-down sustaining unit 5042 is configured to control the signal transmission between the first node No1 and the first power supply terminal VSSQ, and to control the signal transmission between the gate output terminal OT1 and the second power supply terminal VSSG, based on the signal from the third node No3.

[0094] In some embodiments, the first control line transmitting the first control signal LC includes a first sub-control line transmitting the first sub-control signal LC1 and a second sub-control line transmitting the second sub-control signal LC2, wherein the first sub-control signal LC1 and the second sub-control signal LC2 are inverted; the third node No3 includes a first sub-node No31 and a second sub-node No32. The pull-down sustaining module 504 may include a first inverting unit 5041A, a second inverting unit 5041B, a first pull-down sustaining unit 5042A, and a second pull-down sustaining unit 5042B, such as... Figure 6B As shown. The first inverting unit 5041A is electrically connected to the first node No1 and the first sub-node No31. The first inverting unit 5041A is configured to control the first sub-node No31 to form a time-division multiplexing current path between the first sub-node No31, the first sub-control line, and the first power supply terminal VSSQ, based on the signal from the first node No1 and the first sub-control signal LC1. The first pull-down sustaining unit 5042A is electrically connected to the first node No1, the first sub-node No31, and the gate output terminal OT1. The first pull-down sustaining unit 5042A is configured to control the signal transmission between the first node No1 and the first power supply terminal VSSQ, and to control the signal transmission between the gate output terminal OT1 and the second power supply terminal VSSG, based on the signal from the first sub-node No31. The second inverting unit 5041B is electrically connected to the first node No1 and the second sub-node No32. The second inverting unit 5041B is configured to control the second sub-node No32 to form a time-division multiplexing current path between the second sub-node No32, the second sub-control line, and the first power supply terminal VSSQ, based on the signal from the first node No1 and the second sub-control signal LC2. The second pull-down sustaining unit 5042B is electrically connected to the first node No1, the second sub-node No32, and the gate output terminal OT1. The second pull-down sustaining unit 5042B is configured to control the signal transmission between the first node No1 and the first power supply terminal VSSQ, and to control the signal transmission between the gate output terminal OT1 and the second power supply terminal VSSG, based on the signal of the second sub-node No32.

[0095] Optionally, to reduce the impact of the pull-down sustaining module 504 on the potential of the first node No1 and accelerate the potential change rate of the first node No1 during the period when the pull-up module 501 controls the circuit path between the first node No1 and the start signal line STL, at least one gate drive circuit GA further includes at least one node control module 507, such as... Figures 6A-6B As shown.

[0096] Please continue reading. Figure 6A The node control module 507 is electrically connected to the third node No3 of the gate drive circuit GA of this stage. The node control module 507 is configured to control the signal transmission between the first power supply terminal VSSQ and the third node No3 according to the start signal.

[0097] Please continue reading. Figure 6B At least one gate drive circuit (GA) includes two node control modules 507, namely a first node control module 5071 and a second node control module 5072. The first node control module 5071 is electrically connected to the first sub-node No. 31 of the gate drive circuit GA, and is configured to control the signal transmission between the first power supply terminal VSSQ and the first sub-node No. 31 according to a start signal. The second node control module 5072 is electrically connected to the second sub-node No. 32 of the gate drive circuit GA, and is configured to control the signal transmission between the first power supply terminal VSSQ and the second sub-node No. 32 according to a start signal.

[0098] Before the effective pulse of the scan signal Scan output by the gate drive circuit GA, the second frequency division control module 503 of the gate drive circuit GA controls the circuit path between the first node No1 and the second node No2 to be disconnected. Therefore, some gate drive circuits GA lack corresponding pull-down control signals, resulting in inconsistent pulse widths of the effective pulses of the scan signals Scan output by multiple gate drive circuits GA. Furthermore, within a frame, from the moment when the scan signal Scan output by the first-stage gate drive circuit GA has no effective pulse until the end of the frame, even if the output frequency division control signal reconnects the current path between the first node No1 and the second node No2 during this period, from the first-stage gate drive circuit GA where the output scan signal Scan has no effective pulse to the last-stage gate drive circuit GA, because the corresponding start signal has no effective pulse, the scan signals Scan output by all stages from the first-stage gate drive circuit GA where the output scan signal Scan has no effective pulse to the last-stage gate drive circuit GA will have no effective pulses. Correspondingly, the control of the output frequency division control signal of the display panel can achieve frequency reduction display control.

[0099] In some embodiments, the display panel includes a first display area and a second display area adjacent along a second direction Dr2. The first display area includes a plurality of sub-pixels Spx from a first row to a plurality of sub-pixels Spx from a first row to a second display area, and the second display area includes a plurality of sub-pixels Spx from a (E+1)th row to a plurality of sub-pixels Spx from a (F)th row. In at least one frame, in the gate driving module 50, the scan signal Scan output by the gate driving circuit GA electrically connected to the sub-pixels Spx in the E row has a valid pulse, while the scan signal Scan output by the gate driving circuit GA electrically connected to the sub-pixels Spx in the (E+1)th row has no valid pulse. Therefore, the conduction frequency of the first control transistor Tc1 of the sub-pixels Spx in the first display area is greater than the conduction frequency of the first control transistor Tc1 of the sub-pixels Spx in the second display area. Thus, there is a basis for making the refresh frequency of the first display area greater than the refresh frequency of the second display area. Where E ≥ 1.

[0100] It should be noted that the gate driving module 50, in conjunction with the output frequency divider module, can achieve frequency division design at a fixed position on the display panel, or at any position. For example, in some embodiments, the second frequency divider control module 503 is set only in the gate driving circuit GA electrically connected to the sub-pixel Spx in the E+1 row, which can correspondingly enable the display panel to achieve a frequency division design for the first display area and the second display area. In other embodiments, the second frequency divider control module 503 is set in multiple gate driving circuits GA, which can correspondingly achieve a frequency division design in the area formed by the row of the sub-pixel Spx electrically connected to the gate driving circuit GA where the second frequency divider control module 503 is set.

[0101] In some embodiments, to enable the display panel to achieve upsampling under the control of the gate driving module 50, at least one gate driving circuit GA further includes a stage output module 508, such as... Figures 6A-6B As shown.

[0102] The stage transmission output module 508 is electrically connected to the first node No1. The stage transmission output module 508 is configured to control the signal transmission between the corresponding clock signal line and the stage transmission output terminal OT2 of the gate drive circuit GA of this stage according to the signal of the first node No1. The stage transmission output terminal OT2 is configured to output the stage transmission signal St of this stage. Among them, the start signal corresponding to the nth stage gate drive circuit GA(n) is the stage transmission signal St(nA) output by the nAth stage gate drive circuit GA(nA).

[0103] By setting the stage transmission output module 508, even when the scan signal Scan output by part of the gate drive circuit GA has no valid pulse, the stage transmission signal St with valid pulse can still be output. This will enable the start signal corresponding to part of the gate drive circuit GA to have valid pulse. Thus, after the gate drive module 50 outputs a scan signal Scan with no valid pulse, it will output a scan signal Scan with valid pulse again under the action of the output frequency division signal and the stage transmission signal St.

[0104] In some embodiments, in order to ensure that the effective pulses of multiple scan signals Scan have the same pulse width, the first pull-down control signal corresponding to the nth stage gate drive circuit GA(n) is the stage transmission signal St(n+B) or the reset signal Res output by the (n+B)th stage gate drive circuit GA(n+B), and the second pull-down control signal corresponding to the nth stage gate drive circuit GA(n) is the scan signal Scan(n+C) or the reset signal Res output by the (n+C)th stage gate drive circuit GA(n+C).

[0105] In some embodiments, the pull-down sustaining unit 5042 is electrically connected to the stage transmission output terminal OT2, and the pull-down sustaining unit 5042 is configured to control the signal transmission between the stage transmission output terminal OT2 and the first power supply terminal VSSQ according to the signal of the third node No3, such as... Figure 6A As shown.

[0106] In some embodiments, both the first pull-down sustaining unit 5042A and the second pull-down sustaining unit 5042B are electrically connected to the stage transmission output terminal OT2. The first pull-down sustaining unit 5042A is configured to control the signal transmission between the stage transmission output terminal OT2 and the first power supply terminal VSSQ according to the signal of the first sub-node No.31. The second pull-down sustaining unit 5042B is configured to control the signal transmission between the stage transmission output terminal OT2 and the first power supply terminal VSSQ according to the signal of the second sub-node No.32, such as... Figure 6B As shown.

[0107] Optionally, to reduce the power consumption of the display panel, multiple gate drive circuits (GAs) can share clock signals transmitted through multiple clock signal lines.

[0108] In some embodiments, the display panel includes Z clock signal lines configured to transmit Z clock signals that have the same phase difference in sequence. The ZK+Yth stage gate drive circuit GA(ZK+Y) is electrically connected to the Yth clock signal line, where Z > 2, K ≥ 0, and 1 ≤ Y ≤ Z.

[0109] Please continue reading. Figure 5Taking Z=8 as an example, the display panel includes 8 clock signal lines. The first clock signal line CKL1 is configured to transmit the first clock signal CK1, the second clock signal line CKL2 is configured to transmit the second clock signal CK2, the third clock signal line CKL3 is configured to transmit the third clock signal CK3, the fourth clock signal line CKL4 is configured to transmit the fourth clock signal CK4, the fifth clock signal line CKL5 is configured to transmit the fifth clock signal CK5, the sixth clock signal line CKL6 is configured to transmit the sixth clock signal CK6, the seventh clock signal line CKL7 is configured to transmit the seventh clock signal CK7, and the eighth clock signal line CKL8 is configured to transmit the eighth clock signal CK8. Specifically, the 8K+1 level gate drive circuit GA(8K+1) is electrically connected to the first clock signal line CKL1; the 8K+2 level gate drive circuit GA(8K+2) is electrically connected to the second clock signal line CKL2; the 8K+3 level gate drive circuit GA(8K+3) is electrically connected to the third clock signal line CKL3; the 8K+4 level gate drive circuit GA(8K+4) is electrically connected to the fourth clock signal line CKL4; the 8K+5 level gate drive circuit GA(8K+5) is electrically connected to the fifth clock signal line CKL5; the 8K+6 level gate drive circuit GA(8K+6) is electrically connected to the sixth clock signal line CKL6; the 8K+7 level gate drive circuit GA(8K+7) is electrically connected to the seventh clock signal line CKL7; and the 8K+8 level gate drive circuit GA(8K+8) is electrically connected to the eighth clock signal line CKL8.

[0110] In some embodiments, to avoid the problem that the effective pulse width of the scan signal Scan output by part of the gate drive circuit GA becomes narrower when the current path between the first node No1 and the second node No2 is disconnected due to the output frequency division control signal, the effective time periods of the Z clock signals transmitted by the Z clock signal lines do not overlap, and the transition edge of the output frequency division signal corresponds to the time period when all Z clock signals are ineffective.

[0111] In some embodiments, the transition edge of the first output frequency divider signal Fo1 corresponds to a period when all Z clock signals are at invalid levels. The first output frequency divider signal Fo1 and the second output frequency divider signal Fo2 are out of phase. This improves the problem of inconsistent pulse widths of the effective pulses of multiple scan signals Scan. When the first frequency divider unit 5031 disconnects the current path of the first node No1 and the second node No2, the second frequency divider unit 5032 disconnects the current path between the first power supply terminal VSSQ and the second node No2. Conversely, when the first frequency divider unit 5031 connects the current path of the first node No1 and the second node No2, the second frequency divider unit 5032 connects the current path between the first power supply terminal VSSQ and the second node No2.

[0112] In some embodiments, in order to ensure that the gate drive circuit GA has a stable initial state, at least one gate drive circuit GA may further include a reset module 509. The reset module 509 is electrically connected between the first power supply terminal VSSQ and the first node No1. The reset module 509 is configured to control the signal transmission between the first power supply terminal VSSQ and the first node No1 according to the reset signal Res.

[0113] by Figures 6A-6B The gate drive circuit GA of this application will be illustrated using an example.

[0114] Optionally, the pull-up module 501 may include a pull-up transistor Tu, which includes a control terminal and a first source-drain terminal electrically connected to the start signal line STL, and a second source-drain terminal electrically connected to the first node No1. The pull-up transistor Tu is configured to control the signal transmission between the start signal line STL and the first node No1 according to the start signal.

[0115] Optionally, the gate output module 502 includes a first output transistor To1 and a first capacitor C1. The first output transistor To1 includes a control terminal electrically connected to the second node No2, a first source-drain terminal configured to receive the corresponding clock signal CK, and a second source-drain terminal electrically connected to the gate output terminal OT1. The first capacitor C1 is electrically connected between the second node No2 and the gate output terminal OT1.

[0116] Optionally, the first frequency division unit 5031 of the second frequency division control module 503 may include a first frequency division transistor Tf1. The control terminal of the first frequency division transistor Tf1 is configured to receive a first output frequency division signal Fo1. The first source-drain terminal of the first frequency division transistor Tf1 is electrically connected to the first node No1, and the second source-drain terminal of the first frequency division transistor Tf1 is electrically connected to the second node No2.

[0117] Optionally, the second frequency division unit 5032 of the second frequency division control module 503 includes a second frequency division transistor Tf2, a third frequency division transistor Tf3, and a fourth frequency division transistor Tf4. The control terminal of the second frequency division transistor Tf2 is configured to receive a first output frequency division signal Fo1. The first source-drain terminals of the second frequency division transistor Tf2 and the first source-drain terminals of the fourth frequency division transistor Tf4 are electrically connected to the first power supply terminal VSSQ. The second source-drain terminal of the second frequency division transistor Tf2 is electrically connected to the second source-drain terminal of the third frequency division transistor Tf3 and the control terminal of the fourth frequency division transistor Tf4. The control terminal of the third frequency division transistor Tf3 and the first source-drain terminal of the third frequency division transistor Tf3 are configured to receive a second output frequency division signal Fo2. The second source-drain terminal of the fourth frequency division transistor Tf4 is electrically connected to the second node No2.

[0118] In some embodiments, the first frequency divider transistor Tf1 and the second frequency divider transistor Tf2 are both N-type transistors or both P-type transistors, so that the first node No1 is electrically connected to the first power supply terminal VSSQ and the second node No2 in a time-division manner.

[0119] In some embodiments, the second frequency divider transistor Tf2 and the third frequency divider transistor Tf3 are both N-type transistors or both P-type transistors, so that the first power supply signal supplied by the first power supply terminal VSSQ and the second output frequency divider signal Fo2 are transmitted to the control terminal of the fourth frequency divider transistor Tf4 in a time-division manner.

[0120] In some embodiments, the third frequency divider transistor Tf3 and the fourth frequency divider transistor Tf4 are both N-type transistors or both P-type transistors, so that when the third frequency divider transistor Tf3 is turned on according to the second output frequency divider signal Fo2, the fourth frequency divider transistor Tf4 is turned on to connect the current path between the second node No2 and the first power supply terminal VSSQ.

[0121] Optionally, the inverting unit 5041 of the pull-down sustaining module 504 includes a first control transistor Tc1 and a second control transistor Tc2, such as Figure 6A As shown. The first control transistor Tc1 includes a control terminal configured to receive a first control signal, a first source-drain terminal, and a second source-drain terminal electrically connected to the third node No3. The second control transistor Tc2 includes a control terminal electrically connected to the first node No1, a first source-drain terminal electrically connected to the first power supply terminal VSSQ, and a second source-drain terminal electrically connected to the third node No3.

[0122] Optionally, when the pull-down sustaining module 504 includes a first inverting unit 5041A and a second inverting unit 5041B, the second source-drain terminals of the first control transistor Tc1 and the second source-drain terminals of the second control transistor Tc2 in the first inverting unit 5041A are electrically connected to the first sub-node No. 31, and the control terminal and the first source-drain terminal of the first control transistor Tc1 are configured to receive the first sub-control signal LC1. The second source-drain terminals of the first control transistor Tc1 and the second source-drain terminals of the second control transistor Tc2 in the second inverting unit 5041B are electrically connected to the second sub-node No. 32, and the control terminal and the first source-drain terminal of the first control transistor Tc1 are configured to receive the second sub-control signal LC2, such as... Figure 6B As shown.

[0123] Optionally, the pull-down sustaining unit 5042 includes a third control transistor Tc3 and a fourth control transistor Tc4, such as Figure 6AAs shown. The third control transistor Tc3 includes a control terminal electrically connected to the third node No3, a first source-drain terminal electrically connected to the first power supply terminal VSSQ, and a second source-drain terminal electrically connected to the first node No1. The fourth control transistor Tc4 includes a control terminal electrically connected to the third node No3, a first source-drain terminal electrically connected to the second power supply terminal VSSG, and a second source-drain terminal electrically connected to the gate output terminal OT1.

[0124] In some embodiments, the gate drive circuit GA includes a first pull-down sustaining unit 5042A and a second pull-down sustaining unit 5042B. The control terminals of the third control transistor Tc3 and the fourth control transistor Tc4 of the first pull-down sustaining unit 5042A are electrically connected to the first sub-node No. 31. The control terminals of the third control transistor Tc3 and the fourth control transistor Tc4 of the second pull-down sustaining unit 5042B are electrically connected to the second sub-node No. 32, as shown below. Figure 6B As shown.

[0125] Optionally, the first pull-down module 505 includes a first pull-down transistor Td1, which includes a control terminal electrically connected to the first pull-down control line DCL1, a first source-drain terminal electrically connected to the first power supply terminal VSSQ, and a second source-drain terminal electrically connected to the first node No1.

[0126] Optionally, the second pull-down module 506 includes a second pull-down transistor Td2, which includes a control terminal electrically connected to the second pull-down control line DCL2, a first source-drain terminal electrically connected to the second power supply terminal VSSG, and a second source-drain terminal electrically connected to the gate output terminal OT1.

[0127] Optionally, the node control module 507 includes a switching transistor Ts, such as Figure 6A As shown. The switching transistor Ts includes a control terminal configured to receive a start signal, a first source-drain terminal electrically connected to the first power supply terminal VSSQ, and a second source-drain terminal electrically connected to the third node No3.

[0128] Optionally, the first node control module 5071 and the second node control module 5072 each include a switching transistor Ts, such as... Figure 6B As shown. The first source-drain terminal of the switching transistor Ts in the first node control module 5071 is electrically connected to the first child node No.31, and the first source-drain terminal of the switching transistor Ts in the second node control module 5072 is electrically connected to the second child node No.32.

[0129] Optionally, the reset module 509 includes a reset transistor, which includes a control terminal configured to receive a reset signal Res, a first source-drain terminal electrically connected to a first power supply terminal VSSQ, and a second source-drain terminal electrically connected to a first node No1.

[0130] Optionally, the gate drive circuit GA further includes a stage output module 508, which includes a second output transistor To2 and a second capacitor C2. The second output transistor To2 includes a control terminal electrically connected to the first node No1, a first source-drain terminal configured to receive the corresponding clock signal CK, and a second source-drain terminal electrically connected to the stage output terminal OT2. The second capacitor C2 is electrically connected between the first node No1 and the stage output terminal OT2.

[0131] Optionally, the first output transistor To1 and the second output transistor To2 are both N-type transistors or both P-type transistors, so that when the second frequency divider unit 5032 connects the current path between the first node No1 and the second node No2, the operating state of the stage transmission output module 508 of the gate drive circuit GA is synchronized with that of the gate output module 502.

[0132] Optionally, the pull-down sustaining unit 5042 may also include a fifth control transistor Tc5, such as Figure 6A As shown. The fifth control transistor Tc5 includes a control terminal electrically connected to the third node No3, a first source-drain terminal electrically connected to the first power supply terminal VSSQ, and a second source-drain terminal electrically connected to the stage output terminal OT2.

[0133] In some embodiments, the control terminal of the fifth control transistor Tc5 included in the first pull-down sustaining unit 5042A is electrically connected to the first sub-node No. 31, and the control terminal of the fifth control transistor Tc5 included in the second pull-down sustaining unit 5042B is electrically connected to the second sub-node No. 32. Figure 6B As shown.

[0134] It should be noted that the transistors included in the gate drive circuit GA can be either P-type or N-type transistors. The transistors in the gate drive circuit GA can be implemented as bipolar junction transistors (BJTs), field-effect transistors (FETs), or thin-film transistors (TFTs). When the transistors are implemented as FETs or TFTs, the control terminal can be the gate, the first source / drain terminal can be one of the source and drain, and the second source / drain terminal can be the other of the source and drain. When the transistors are implemented as bipolar junction transistors (BJTs), the control terminal can be the base, the first source / drain terminal can be one of the collector and emitter, and the second source / drain terminal can be the other of the collector and emitter. Each transistor can employ a single-gate or dual-gate design. The active layer of each transistor can include silicon semiconductor materials or oxide semiconductor materials. The silicon semiconductor materials include monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The oxide semiconductor materials include indium gallium zinc oxide (IGNOW) or indium zinc oxide (IBO).

[0135] Figure 7 This is a timing diagram of multiple scan signals Scan provided in an embodiment of this application. Taking the gate drive circuit GA as an N-type transistor with A=4, B=5, and C=4, the nth-stage gate drive circuit GA(n) is electrically connected to the fifth clock signal line CKL5. Taking the fifth clock signal CK5 as the clock signal CK corresponding to the nth-stage gate drive circuit GA(n) as an example, combined with... Figure 6A The gate drive circuit GA shown here explains the working principle of the nth stage gate drive circuit GA(n) to the (n+q)th stage gate drive circuit GA(n+q).

[0136] In the first stage t1: the n-4th stage transmission signal St(n-4), the first clock signal CK1, and the first output frequency divider signal Fo1 are at high level, while the second output frequency divider signal Fo2, the second clock signal CK2 to the eighth clock signal CK8 are at low level.

[0137] In the nth-stage gate drive circuit GA(n), the pull-up transistor Tu, the second control transistor Tc2, the switching transistor Ts, the second output transistor To2, the first output transistor To1, the first frequency divider transistor Tf1, and the second frequency divider transistor Tf2 are turned on, while the third control transistor Tc3, the fourth control transistor Tc4, the fifth control transistor Tc5, the third frequency divider transistor Tf3, and the fourth frequency divider transistor Tf4 are turned off. The nth-stage transmission signal St(n) and the nth-stage scan signal Scan(n) are at low levels.

[0138] In the second stage t2: the n-4th stage transmission signal St(n-4) and the second output frequency divider signal Fo2 are at low level, the first output frequency divider signal Fo1 is at high level, the second clock signal CK2 to the fourth clock signal CK4 are at high level in sequence, and the fifth clock signal CK5 to the eighth clock signal CK8 are at low level.

[0139] In the nth-stage gate drive circuit GA(n), the second control transistor Tc2, the second output transistor To2, the first output transistor To1, the first frequency divider transistor Tf1, and the second frequency divider transistor Tf2 are turned on, while the pull-up transistor Tu, the switching transistor Ts, the third control transistor Tc3, the fourth control transistor Tc4, the fifth control transistor Tc5, the third frequency divider transistor Tf3, and the fourth frequency divider transistor Tf4 are turned off. The nth-stage transmission signal St(n) and the nth-stage scan signal Scan(n) are at low levels.

[0140] The (n+1)th stage gate drive circuit GA(n+1) to the (n+3)th stage gate drive circuit GA(n+3) sequentially execute the operation of the nth stage gate drive circuit GA(n) in the first stage t1. The (n+1)th stage pass signal St(n+1) to the (n+3)th stage pass signal St(n+3) and the (n+1)th stage scan signal Scan(n+1) to the (n+3)th stage scan signal Scan(n+3) are at low level.

[0141] In the third stage t3: the n-4th stage transmission signal St(n-4) and the second output frequency divider signal Fo2 are at low level, the first output frequency divider signal Fo1 and the fifth clock signal CK5 are at high level, and the first clock signal CK1 to the fourth clock signal CK4, the sixth clock signal CK6 to the eighth clock signal CK8 are at low level.

[0142] In the nth-stage gate drive circuit GA(n), the second control transistor Tc2, the second output transistor To2, the first output transistor To1, the first frequency divider transistor Tf1, and the second frequency divider transistor Tf2 are turned on, while the pull-up transistor Tu, the switching transistor Ts, the third control transistor Tc3, the fourth control transistor Tc4, the fifth control transistor Tc5, the third frequency divider transistor Tf3, and the fourth frequency divider transistor Tf4 are turned off. The nth-stage transmission signal St(n) and the nth-stage scan signal Scan(n) are at high levels.

[0143] The (n+4)th stage gate drive circuit GA(n+4) performs the operation of the nth stage gate drive circuit GA(n) in the first stage t1. The (n+1)th stage pass signal St(n+1) to the (n+4)th stage pass signal St(n+4) and the (n+1)th stage scan signal Scan(n+1) to the (n+4)th stage scan signal Scan(n+4) are at low level.

[0144] In the fourth stage t4: the n-4th stage transmission signal St(n-4) and the second output frequency divider signal Fo2 are at low level, the first output frequency divider signal Fo1 is at high level, the first clock signal CK1 to the fifth clock signal CK5 are at low level, and the sixth clock signal CK6 to the eighth clock signal CK8 are at high level in sequence.

[0145] In the nth-stage gate drive circuit GA(n), the second control transistor Tc2, the second output transistor To2, the first output transistor To1, the first frequency divider transistor Tf1, and the second frequency divider transistor Tf2 are turned on, while the pull-up transistor Tu, the switching transistor Ts, the third control transistor Tc3, the fourth control transistor Tc4, the fifth control transistor Tc5, the third frequency divider transistor Tf3, and the fourth frequency divider transistor Tf4 are turned off. The nth-stage transmission signal St(n) and the nth-stage scan signal Scan(n) are at low levels.

[0146] The (n+1)th to (n+3)th stage gate drive circuits GA(n+1) and GA(n+3) sequentially execute the operation of the nth stage gate drive circuit GA(n) in the third stage t3. The (n+4)th stage gate drive circuit GA(n+4) executes the operation of the nth stage gate drive circuit GA(n) in the second stage t2. The (n+5)th to (n+7)th stage gate drive circuits GA(n+7) sequentially execute the operation of the nth stage gate drive circuit GA(n) in the first stage t1. The (n+1)th stage pass signal St(n+1) to (n+3)th stage pass signal St(n+3) are sequentially high, and the (n+1)th stage scan signal Scan(n+3) to (n+3)th stage scan signal Scan(n+3) are sequentially high. The (n+4)th stage transmission signal St(n+4) to the (n+7)th stage transmission signal St(n+7) and the (n+4)th stage scan signal Scan(n+4) to the (n+7)th stage scan signal Scan(n+7) are at low level.

[0147] In the fifth stage t5: the n-4th stage transmission signal St(n-4) and the second output frequency divider signal Fo2 are at low level, the first output frequency divider signal Fo1 and the first clock signal CK1 are at high level, and the second clock signal CK2 to the eighth clock signal CK8 are at low level.

[0148] In the nth stage gate drive circuit GA(n), the second pull-down transistor Td2 is turned on, and the nth stage transmission signal St(n) and the nth stage scan signal Scan(n) are at low level.

[0149] The (n+4)th stage gate drive circuit GA(n+4) performs the operation of the nth stage gate drive circuit GA(n) in the third stage t3. The (n+1)th stage pass signal St(n+1) to the (n+3)th stage pass signal St(n+3) are low, and the (n+1)th stage scan signal Scan(n+3) to the (n+3)th stage scan signal Scan(n+3) are low. The (n+4)th stage pass signal St(n+4) and the (n+4)th stage scan signal Scan(n+4) are low. The (n+5)th stage pass signal St(n+5) to the (n+7)th stage pass signal St(n+7) and the (n+5)th stage scan signal Scan(n+5) to the (n+7)th stage scan signal Scan(n+7) are low.

[0150] In stage 6 t6: the (n-4)th stage transmission signal St(n-4) and the second output frequency divider signal Fo2 are at low level, the first output frequency divider signal Fo1 and the second clock signal CK2 are at high level, and the first clock signal CK1, the third clock signal CK3 to the eighth clock signal CK8 are at low level.

[0151] In the nth-stage gate drive circuit GA(n), the first pull-down transistor Td1, the first frequency divider transistor Tf1, the second frequency divider transistor Tf2, the third control transistor Tc3, the fourth control transistor Tc4, and the fifth control transistor Tc5 are turned on, while the second control transistor Tc2, the second output transistor To2, the first output transistor To1, the pull-up transistor Tu, the switching transistor Ts, the third frequency divider transistor Tf3, and the fourth frequency divider transistor Tf4 are turned off.

[0152] The (n+5)th stage gate drive circuit GA(n+5) performs the operation of the nth stage gate drive circuit GA(n) in the third stage t3. The (n+1)th stage pass signal St(n+1) to the (n+4)th stage pass signal St(n+4) are low, and the (n+1)th stage scan signal Scan(n+4) are low. The (n+5)th stage pass signal St(n+5) and the (n+5)th stage scan signal Scan(n+5) are low. The (n+6)th stage pass signal St(n+6) to the (n+7)th stage pass signal St(n+7) and the (n+6)th stage scan signal Scan(n+6) to the (n+7)th stage scan signal Scan(n+7) are low.

[0153] When the first output frequency divider signal Fo1 transitions from a high level to a low level, the second output frequency divider signal Fo2 transitions from a low level to a high level. The first frequency divider transistor Tf1 and the second frequency divider transistor Tf2 in the gate drive circuit GA are turned off, while the third frequency divider transistor Tf3 and the fourth frequency divider transistor Tf4 are turned on, thereby turning off the first output transistor To1 in the gate drive circuit GA. The transition edge of the first output frequency divider signal Fo1 includes a falling edge and a rising edge. The falling edge of the first output frequency divider signal Fo1 corresponds to the transition from a high level to a low level, and the rising edge corresponds to the transition from a low level to a high level.

[0154] Stage 7 t7: The (n-4)th stage transmission signal St(n-4) and the first output frequency divider signal Fo1 are at low level, the second output frequency divider signal Fo2 and the fourth clock signal CK4 are at high level, and the first clock signal CK1 to the third clock signal CK3, the fifth clock signal CK5 to the eighth clock signal CK8 are at low level.

[0155] In the (n+7)th stage gate drive circuit GA(n+7), due to the influence of the output frequency divider signal, the first output transistor To1 is turned off, and the (n+7)th stage scan signal Scan(n+7) is low. Since the first frequency divider transistor Tf1 is turned off, the second output transistor To2 can remain on. Therefore, the (n+7)th stage pass signal St(n+7) is high.

[0156] The nth stage transmission signal St(n) to the (n+6th)th stage transmission signal St(n+6) and the nth stage scan signal Scan(n) to the (n+6th)th stage scan signal Scan(n+6) are at low level.

[0157] Subsequently, during the phase where the first output frequency divider signal Fo1 is low and the second output frequency divider signal Fo2 is high, the (n+8)th stage transmission signal to the (n+q-6)th stage transmission signal St(n+q-6) successively have high levels according to the corresponding clock signals. However, due to the cutoff of the first frequency divider transistor Tf1 and the conduction of the fourth frequency divider transistor Tf4, the (n+8)th stage scan signal to the (n+q-6)th stage scan signal Scan(n+q-6) are low.

[0158] At the moment when the first output frequency divider signal Fo1 transitions from low to high, the second output frequency divider signal Fo2 transitions from high to low. The first frequency divider transistor Tf1 and the second frequency divider transistor Tf2 in the gate drive circuit GA are turned on, while the third frequency divider transistor Tf3 and the fourth frequency divider transistor Tf4 are turned off. This disconnects the current path between the second node No2 in the gate drive circuit GA and the first power supply terminal VSSQ. Subsequently, the (n+q-5)th stage gate drive circuit GA(n+q) to the (n+q)th stage gate drive circuit GA(n+q) sequentially execute the operations of the nth stage gate drive circuit GA(n) in the first stage t1 to the sixth stage t6. This causes the (n+q-5)th stage pass signal St(n+q) to the (n+q)th stage pass signal St(n+q) and the (n+q-5)th stage scan signal Scan(n+q) to the (n+q)th stage scan signal Scan(n+q) sequentially to have a high level according to the corresponding clock signal.

[0159] Therefore, by controlling the level change of the output frequency divider signal, the Scan signal output by the gate drive circuit GA can be made to have or not have a valid pulse.

[0160] In some embodiments, the pixel driving circuit 30 of the sub-pixel Spx is controlled by the corresponding scan signal Scan to realize the electrical connection between the first frequency division control module 20 and the pixel electrode 40 or the corresponding data line DL. Therefore, if the control scan signal Scan has no effective pulse, the current path between the pixel electrode 40 of the sub-pixel Spx and the corresponding data line DL can be disconnected, thereby realizing frequency control of the sub-pixel Spx receiving the corresponding data signal.

[0161] In some embodiments, the pixel driving circuit 30 is located between the first frequency division control module 20 and the pixel electrode 40. When the frequency division control signal disconnects the current path between the pixel driving circuit 30 and the corresponding data line DL, the scan signal Scan corresponding to the sub-pixel Spx is configured to control the pixel driving circuit 30 to disconnect the current path between the pixel electrode 40 and the first frequency division control module 20, so as to reduce the leakage current between the pixel electrode 40 and the corresponding data line DL when the pixel electrode 40 cannot receive the corresponding data signal, thereby enabling the pixel electrode 40 to maintain a stable potential.

[0162] Optionally, frequency division control of the display panel can be achieved by using both the Scan signal and the frequency division control signal.

[0163] like Figure 8This is a timing diagram of the frequency division control signal, the output frequency division signal, and multiple scan signals provided in the embodiments of this application. Still assuming the transistors mentioned above are N-type transistors, the display panel includes F scan lines SL, each SL receiving F scan signals Scan. The first direction Dr1 is the row direction, and the second direction Dr2 is the column direction. Figure 1A The design shown is used as an example for illustration. Where F ≥ 1.

[0164] In the first frame of a display cycle, the first-level scan signal Scan(1) to the F-level scan signal Scan(F) sequentially have valid pulses, the first frequency division control signal Fd1 to the third frequency division control signal Fd3 and the first output frequency division signal Fo1 are at high levels, and the second output frequency division signal Fo2 is at a low level. Therefore, in the first frame, the second transistor T2 included in the multiple sub-pixels Spx in the first unit group SUG1 to the third unit group SUG3 is turned on. When the first-level scan signal Scan(1) has a valid pulse, the first transistor T1 included in the multiple sub-pixels Spx located in the first row is turned on, and the pixel electrode 40 included in the multiple sub-pixels Spx located in the first row receives the corresponding data signal. When the second-level scan signal Scan(2) has a valid pulse, the first transistor T1 included in the multiple sub-pixels Spx located in the second row is turned on, and the pixel electrode 40 included in the multiple sub-pixels Spx located in the second row receives the corresponding data signal. Similarly, when the F-th scan signal Scan(F) has a valid pulse, the first transistor T1 of the multiple sub-pixels Spx located in the F-th row is turned on, and the pixel electrode 40 of the multiple sub-pixels Spx located in the F-th row receives the corresponding data signal. Therefore, in the first frame, the multiple sub-pixels Spx in the first unit group SUG1 to the third unit group SUG3 all receive the corresponding data signal.

[0165] In the first time period tA of the second frame of a display cycle, the first frequency division control signal Fd1 to the third frequency division control signal Fd3 are at a low level, the first output frequency division signal Fo1 is at a low level, the second output frequency division signal Fo2 is at a high level, and the first-level scan signal Scan(1) to the i-th scan signal Scan(i) have no valid pulses. The first transistor T1 and the second transistor T2 included in the multiple sub-pixels Spx in the first row to the multiple sub-pixels Spx in the i-th row are turned off, and the multiple sub-pixels Spx in the first row to the multiple sub-pixels Spx in the i-th row do not receive the corresponding data signals.

[0166] In the second time period tB of the second frame of a display cycle, the first frequency division control signal Fd1 and the third frequency division control signal Fd3 are at low level, the second frequency division control signal Fd2 is at low level, the first output frequency division signal Fo1 is at high level, the second output frequency division signal Fo2 is at low level, and the (i+1)th scan signal Scan(i+1) to the jth scan signal Scan(j) have valid pulses in sequence. The second transistor T2 included in the multiple sub-pixels Spx in the first unit group SUG1 and the third unit group SUG3 is turned off, and the second transistor T2 included in the multiple sub-pixels Spx in the second unit group SUG2 is turned on. The second transistor T2 included in the multiple sub-pixels Spx located in rows i+1 to j and located in the first unit group SUG1 and the third unit group SUG3 is turned off, and the first transistor T1 is turned on in sequence row by row. The first transistor T1 of the multiple sub-pixels Spx located in rows i+1 to j and in the second unit group SUG2 is turned on sequentially row by row, and the second transistor T2 is turned on, so that the pixel electrode 40 of the multiple sub-pixels Spx located in rows i+1 to j and in the second unit group SUG2 receives the corresponding data signal, and the pixel electrode 40 of the multiple sub-pixels Spx located in rows i+1 to j and in the first unit group SUG1 and the third unit group SUG3 does not receive the corresponding data signal.

[0167] During the third time period tC of the second frame in a display cycle, the first frequency division control signal Fd1 to the third frequency division control signal Fd3 are at a low level, the first output frequency division signal Fo1 is at a low level, the second output frequency division signal Fo2 is at a high level, the (j+1)th scan signal Scan(j+1) to the Fth level scan signal Scan(F) are at a low level, the first transistor T1 and the second transistor T2 included in the multiple sub-pixels Spx in the (j+1)th row to the multiple sub-pixels Spx in the Fth row are turned off, and the multiple sub-pixels Spx in the (j+1)th row to the multiple sub-pixels Spx in the Fth row do not receive the corresponding data signals.

[0168] Therefore, in the second frame, multiple sub-pixels Spx in the first unit group SUG1 and the third unit group SUG3 do not receive the corresponding data signals. In the second unit group SUG2, multiple sub-pixels Spx located in the first row to the i-th row and multiple sub-pixels Spx located in the j+1-F-th row do not receive the corresponding data signals, while multiple sub-pixels Spx located in the i+1-j-th row receive the corresponding data signals.

[0169] By analogy, the design of whether the first unit group SUG1 to the third unit group SUG3 receive the corresponding data signals in the remaining frames of a display cycle is obtained.

[0170] Therefore, in one display cycle, multiple sub-pixels Spx in the first unit group SUG1 to the third unit group SUG3 can be displayed at different refresh rates, and multiple sub-pixels Spx in the second unit group SUG2 can also be displayed at different refresh rates. Thus, by coordinating the output frequency division signal and the frequency division control signal, this application can simultaneously implement a frequency division design along the first direction Dr1 and a frequency division design along the second direction Dr2.

[0171] It should be understood that, Figure 8 This explanation uses the example of the second unit group SUG2 comprising multiple sub-pixels Spx forming three refresh rate partitions along the second direction Dr2. In practical applications, the frequency division regions along the second direction Dr2 are not limited to three.

[0172] It should be noted that the timing of the transition edge of the output frequency division signal may be the same or different in different frames of a display cycle. For example, in some embodiments, within a display cycle, in one frame, the output frequency division signal controls the j-th scan signal Scan(j) to the F-th scan signal Scan(F) to have no valid pulses; in another frame, the output frequency division signal controls the i-th scan signal Scan(i) to the c-th scan signal Scan(c) to have no valid pulses.

[0173] Figures 9A-9B This is a schematic diagram of the structure of a display device provided in an embodiment of this application. This application also provides a display device including any of the above-described display panels.

[0174] Optionally, the display device may also include a source driver configured to generate a plurality of data signals for output to the display panel.

[0175] In some embodiments, the display panel may further include a timing controller configured to generate a plurality of clock signals to be output to the display panel.

[0176] Optionally, the display panel may further include a frequency division signal generation module, which is electrically connected to at least one of the first frequency division control module 20 and the second frequency division control module 503. The frequency division signal generation module is configured to generate at least one of an output frequency division signal and a frequency division control signal.

[0177] In some embodiments, the timing controller can be reused as a frequency division signal generation module.

[0178] Optionally, when multiple frequency division control lines FL and data lines DL are arranged in a one-to-one overlapping manner, at least two of the multiple frequency division control lines FL can be connected via connecting lines located in the non-display area of ​​the display panel. The multiple frequency division control lines FL can also be directly connected to the frequency division signal generation module. The signals transmitted by the multiple frequency division control lines FL can be the same or different.

[0179] It should be understood that since the display device of this application includes any of the aforementioned display panels, the display device of this application has all the technical effects corresponding to the aforementioned display panels, which will not be repeated here.

[0180] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a plurality of data lines on the substrate, each of the data lines being configured to transmit a data signal; at least one frequency division control line on the substrate, each of the frequency division control lines being configured to transmit a frequency division control signal; and a plurality of sub-pixels on the substrate, at least one of the sub-pixels comprising a pixel electrode, a pixel driving circuit, and a first frequency division control module, the pixel driving circuit and the first frequency division control module being electrically connected between the pixel electrode and a corresponding data line, the first frequency division control module being configured to control signal transmission between the pixel driving circuit and the pixel electrode or the corresponding data line according to the frequency division control signal transmitted by a frequency division control line, so as to control the frequency at which the pixel electrode receives the corresponding data signal, wherein a projection of at least one of the frequency division control lines on the substrate at least partially overlaps a projection of the data line on the substrate.

2. The display panel of claim 1, wherein: the plurality of data lines are arranged along a first direction, and each of the data lines extends along a second direction intersecting the first direction; the display panel comprises a plurality of pixel groups arranged along the first direction, each of the pixel groups comprises a plurality of pixel units arranged along the second direction, and each of the pixel units comprises at least one of the sub-pixels; wherein the frequency division control line is connected to the first frequency division control modules of the plurality of sub-pixels in the same pixel group.

3. The display panel of claim 2, wherein: the display panel comprises a plurality of frequency division control lines; each of the pixel units comprises one of the sub-pixels; wherein each of the frequency division control lines is connected to the first frequency division control modules of the plurality of sub-pixels in the same pixel group, and a projection of each of the frequency division control lines on the substrate at least partially overlaps a projection of one of the data lines on the substrate.

4. The display panel of claim 2, wherein: each of the pixel units comprises a plurality of the sub-pixels arranged along the first direction; the display panel comprises a plurality of first connection lines, each of the first connection lines extends along the first direction, and each of the first connection lines is connected between the plurality of sub-pixels in one of the pixel units and a corresponding frequency division control line. The display panel comprises:

5. The display panel of claim 2, wherein, a first unit group and a second unit group adjacent along the first direction, the first unit group and the second unit group respectively comprising at least one of the pixel groups; a plurality of frequency division control lines comprising a first frequency division control line and a second frequency division control line, the first frequency division control line being connected to the first frequency division control modules of the plurality of sub-pixels in the first unit group, and the second frequency division control line being connected to the first frequency division control modules of the plurality of sub-pixels in the second unit group, the first frequency division control line being configured to transmit a first frequency division control signal, and the second frequency division control line being configured to transmit a second frequency division control signal; and a plurality of sub-pixels on the substrate, at least one of the sub-pixels comprising a pixel electrode, a pixel driving circuit, and a first frequency division control module, the pixel driving circuit and the first frequency division control module being electrically connected between the pixel electrode and a corresponding data line, the first frequency division control module being configured to control signal transmission between the pixel driving circuit and the pixel electrode or the corresponding data line according to the frequency division control signal transmitted by a frequency division control line, so as to control the frequency at which the pixel electrode receives the corresponding data signal, wherein a projection of at least one of the frequency division control lines on the substrate at least partially overlaps a projection of the data line on the substrate. The frequency of the first frequency division control signal is different from the frequency of the second frequency division control signal in at least one display period of the display panel.

6. The display panel of claim 5, wherein, The display panel further comprises a third unit group located on a side of the second unit group away from the first unit group, and the third unit group comprises at least one pixel group. The plurality of frequency division control lines comprises a third frequency division control line, the third frequency division control line is connected with the first frequency division control module of the plurality of sub-pixels of the third unit group, and the third frequency division control line is configured to transmit a third frequency division control signal. The frequency of at least one of the first frequency division control signal and the second frequency division control signal is different from the frequency of the third frequency division control signal in at least one display period.

7. The display panel of claim 6, wherein, In one display period, the plurality of sub-pixels of the first unit group display at a first refresh frequency, the plurality of sub-pixels of the second unit group display at a second refresh frequency, and the plurality of sub-pixels of the third unit group display at a third refresh frequency; the second refresh frequency is greater than the first refresh frequency, and the first refresh frequency is greater than or equal to the third refresh frequency. The display period comprises X frames, and X is equal to the ratio of the second refresh frequency to the third refresh frequency.

8. The display panel of any one of claims 1-7, wherein, The display panel comprises a plurality of scan lines, each of the scan lines is configured to transmit a scan signal, and each of the scan lines is electrically connected with the pixel driving circuit of at least one sub-pixel. In each of the sub-pixels, the pixel driving circuit is configured to control the frequency of the pixel electrode receiving the corresponding data signal according to the corresponding scan signal.

9. The display panel of claim 8, wherein, The plurality of data lines are arranged along a first direction, and each of the data lines extends along a second direction intersecting the first direction. The plurality of scan lines are arranged along the second direction, and each of the scan lines extends along the first direction. The frequency division control lines, the scan lines, and the data lines are located in different layers.

10. The display panel of claim 9, wherein, Further comprising: a first metal layer located on the substrate and comprising the plurality of scan lines; a second metal layer located on the first metal layer and comprising the plurality of data lines; and a third metal layer located on the second metal layer and comprising at least one frequency division control line.

11. The display panel of claim 8, wherein, The pixel driving circuit comprises a first transistor, a control terminal of the first transistor is electrically connected with the corresponding scan line, and a first source / drain terminal of the first transistor is electrically connected with the pixel electrode. The first frequency division control module comprises a second transistor, a control terminal of the second transistor is electrically connected with the corresponding frequency division control line, a first source / drain terminal of the second transistor is electrically connected with the corresponding data line, and a second source / drain terminal of the second transistor is electrically connected with a second source / drain terminal of the first transistor. ​ 12. The display panel of claim 8, wherein, The display panel further comprises a gate driving module electrically connected with the plurality of scan lines, the gate driving module comprising a plurality of cascaded gate driving circuits; At least one of the gate driving circuits comprises: a pull-up module electrically connected with a first node of the gate driving circuit, configured to control signal transmission between the first node and a start signal line according to a start signal transmitted by the start signal line, wherein the start signal is a frame start signal or a signal output by a previous-stage gate driving circuit; a gate output module electrically connected with the first node through a second node of the gate driving circuit, configured to control signal transmission between a corresponding clock signal line and a gate output end of the gate driving circuit according to a signal of the second node, the gate output end being configured to output the scan signal of the gate driving circuit; and a second frequency division control module electrically connected with the first node and the second node, configured to control a current path formed between the second node and the first node or a first power supply end according to an output frequency division signal, so as to control the number of effective pulses of the scan signal output by the gate driving circuit.

13. The display panel of claim 12, wherein, The output frequency division signal comprises a first output frequency division signal and a second output frequency division signal. The second frequency division control module comprises: a first frequency division unit electrically connected between the first node and the second node, configured to control signal transmission between the first node and the second node according to the first output frequency division signal; a second frequency division unit electrically connected between the second node and the first power supply end, configured to disconnect the current path between the second node and the first power supply end according to the first output frequency division signal when the first frequency division unit connects the current path between the first node and the second node, and configured to connect the current path between the second node and the first power supply end according to the first output frequency division signal and the second output frequency division signal when the first frequency division unit disconnects the current path between the first node and the second node.

14. The display panel of claim 13, wherein the first frequency division unit comprises a first frequency division transistor, a control end of the first frequency division transistor being configured to receive the first output frequency division signal, a first source-drain end of the first frequency division transistor being electrically connected with the first node, and a second source-drain end of the first frequency division transistor being electrically connected with the second node; the second frequency division unit comprises a second frequency division transistor, a third frequency division transistor and a fourth frequency division transistor. A control terminal of the second frequency division transistor is configured to receive the first output frequency division signal, a first source-drain terminal of the second frequency division transistor and a first source-drain terminal of the fourth frequency division transistor are electrically connected with the first power terminal, a second source-drain terminal of the second frequency division transistor is electrically connected with a second source-drain terminal of the third frequency division transistor and a control terminal of the fourth frequency division transistor, a control terminal of the third frequency division transistor and a first source-drain terminal of the third frequency division transistor are configured to receive the second output frequency division signal, and a second source-drain terminal of the fourth frequency division transistor is electrically connected with the second node.

15. The display panel of claim 13, wherein, The display panel includes Z clock signal lines, and the Z clock signal lines are configured to transmit Z clock signals having the same phase difference in sequence. The Zth K+Y-stage gate drive circuit is electrically connected with the Yth clock signal line, Z>2, K≥0, and 1≤Y≤Z.

16. The display panel of claim 15, wherein, The Z clock signals transmitted by the Z clock signal lines do not overlap in time periods of valid levels. The first output frequency division signal has a transition edge corresponding to a time period in which the Z clock signals are all invalid, and the first output frequency division signal is inverted with the second output frequency division signal.

17. The display panel of claim 12, wherein, The at least one gate drive circuit further includes: a pull-down maintenance module electrically connected with the first node and the gate output terminal, and configured to control signal transmission between the first node and the first power terminal and signal transmission between the gate output terminal and a second power terminal according to a signal of the first node and a first control signal; a first pull-down module electrically connected with the first node, and configured to control electrical signal transmission between the first node and the first power terminal according to a first pull-down control signal; and a second pull-down module electrically connected with the gate output terminal, and configured to control signal transmission between the gate output terminal and the second power terminal according to a second pull-down control signal.

18. The display panel of claim 17, wherein, The at least one gate drive circuit further includes: a stage transmission output module electrically connected with the first node, and configured to control signal transmission between a corresponding clock signal line and a stage transmission output terminal of the gate drive circuit of the current stage according to a signal of the first node, and the stage transmission output terminal is configured to output a stage transmission signal of the current stage; The starting signal corresponding to the nth-stage gate drive circuit is a stage transmission signal output by an (n-A)th-stage gate drive circuit, the first pull-down control signal corresponding to the nth-stage gate drive circuit is a stage transmission signal or a reset signal output by an (n+B)th-stage gate drive circuit, and the second pull-down control signal corresponding to the nth-stage gate drive circuit is a scanning signal output by an (n+C)th-stage gate drive circuit or the reset signal, n-A>0, A≥1, C≥1, and B≥C.

19. The display panel of claim 18, The pull-down maintaining module comprises an inverting unit and a pull-down maintaining unit; the inverting unit is electrically connected with the first node and a third node of the gate drive circuit at the current stage, and is configured to control the third node to form a current path with the first control line and the first power supply end in time according to the signal of the first node and the first control signal transmitted by the first control line; the pull-down maintaining unit is electrically connected with the first node, the third node, the stage transmission output end and the gate output end, and is configured to control the signal transmission between each of the first node and the stage transmission output end and the first power supply end, and control the signal transmission between the gate output end and the second power supply end according to the signal of the third node; At least one of the gate drive circuits further comprises a node control module electrically connected with the third node of the gate drive circuit at the current stage, and configured to control the signal transmission between the first power supply end and the third node according to the start signal.

20. A display device comprising: The display panel comprises any one of the display panels as claimed in claims 1-19.

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