Image refreshing method and device

Abstract

The embodiment of the invention provides an image refreshing method and device, and the method comprises the steps: after a value of a first target bit of an image display is set based on a first image, a processor receives an image display instruction, and the image display instruction is used for indicating to display a second image; the first target bit is a first bit in a bit plane corresponding to the image display, each liquid crystal unit in the image display corresponds to M first bits, the image display corresponds to M bit planes, and each bit plane comprises one first bit corresponding to each liquid crystal unit; the processor sets the value of a second target bit of the image display based on the second image, the second target bit is a first bit except the first target bit in M bit planes corresponding to the image display, and the value of the second target bit is not set by the first image. According to the method, the efficiency of switching the image display from the first image to the second image for display can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of optical communication technology, and in particular to an image refreshing method and device. BACKGROUND

[0002] In the field of image display, an image display (such as a liquid crystal on silicon display) can be used to display an image. During the process of displaying an image A by the image display, under some factors, the image display needs to display an image B as soon as possible. At present, the image display displays the image B after completely displaying the image A. It can be seen that the process of switching from the image A to the image B by the image display takes a large amount of time. How to improve the efficiency of switching the image display to display different images is a technical problem to be solved at present. SUMMARY

[0003] The present application provides an image refreshing method and device to solve the problem of a large amount of time taken by the image display to switch to display different images.

[0004] In a first aspect, an image refreshing method is provided. The execution subject of the method is a processor in an image display or a module in the processor or a chip in the processor. Here, the processor is taken as an example for description. The method comprises: after setting a value of a first target bit of the image display based on a first image, receiving an image display instruction, the image display instruction being used to instruct to display a second image; the first target bit is a first bit in a bit plane corresponding to the image display; the image display comprises N liquid crystal units, each of the N liquid crystal units corresponds to M first bits, the image display corresponds to M bit planes, each bit plane comprises a first bit corresponding to each liquid crystal unit; N and M are integers greater than 0; setting a value of a second target bit of the image display based on the second image, the second target bit being a first bit in the M bit planes corresponding to the image display except the first target bit, and the value of the second target bit is not set by the first image.

[0005] In the above method, during the process of displaying the first image by the image display, if there is a second image that needs to be displayed as soon as possible, the second image is directly used to set the value of the first bit corresponding to the image display and not set by the first image, instead of waiting for the image display to completely display the first image and then displaying the second image, which is beneficial to improve the efficiency of switching from the first image to the second image by the image display.

[0006] In a possible design, the M bit planes have a first setting sequence, and each bit in each bit plane has a second setting sequence; after setting values of first target bit positions of the image display based on the first image, the processor receives an image display instruction, which can include: the processor sets the M bit planes based on the first image in the first setting sequence, and sets the first bits in each bit plane in the second setting sequence; after setting values of the i th first bit in the x th bit plane of the image display based on the first image, the processor receives an image display instruction; the first target bit positions include all first bits in bit planes before the x th bit plane in the first setting sequence, first bits before the i th first bit in the x th bit plane in the second setting sequence, and the i th first bit in the x th bit plane, x is any integer between 1 and M, and i is any integer between 1 and N. With this design, after receiving the second image, the processor directly sets bit values of first bits of the image display that are not set by the first image based on the second image, which is beneficial to improving the efficiency of switching the image display from the first image to the second image for display.

[0007] In a possible design, the second target bit positions include all first bits in bit planes after the x th bit plane in the first setting sequence, and first bits after the i th first bit in the x th bit plane in the second setting sequence. This design provides a method for determining the second target bit positions.

[0008] In a possible design, one pixel value in the second image corresponds to M second bit positions, and the one pixel value is determined according to values of the M second bit positions; and the processor sets values of the second target bit positions of the image display based on the second image, which can include: setting values of the second target bit positions of the image display based on values of second bit positions corresponding to pixel values in the second image.

[0009] In a possible design, the method further includes: the processor sets values of the first bit positions of the image display based on the second image. With this design, the processor can quickly display the second image on the image display.

[0010] In a second aspect, the embodiments of the present application further provide an image refreshing apparatus, which includes a device for executing the method provided in the first aspect.

[0011] In a third aspect, the embodiments of the present application further provide an image refreshing apparatus, which includes a memory and a processor, where the memory is configured to store a computer program, and the processor is configured to invoke the computer program and execute the method provided in the first aspect.

[0012] In a fourth aspect, an embodiment of the present application further provides a computing device, comprising a processor and a memory, wherein the processor of the computing device is configured to execute instructions stored in the memory of the computing device, so that the computing device performs the method provided in the first aspect above.

[0013] In a fifth aspect, an embodiment of the present application further provides a computer program product comprising instructions which, when executed by a computing device, cause the computing device to perform the method provided in the first aspect above.

[0014] In a sixth aspect, an embodiment of the present application further provides a computer-readable storage medium comprising computer program instructions, which, when executed by a computing device, cause the computing device to perform the method provided in the first aspect above.

[0015] In a seventh aspect, an embodiment of the present application further provides a chip comprising instructions which, when executed by a computing device, cause the computing device to perform the method provided in the first aspect above.

[0016] In an eighth aspect, an embodiment of the present application provides a chip system comprising instructions which, when executed by a computing device, cause the computing device to perform the method provided in the first aspect above. The chip system can be composed of a chip, or can comprise a chip and other discrete devices. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A structural schematic diagram of a wavelength selective switch device provided by an embodiment of the present application;

[0018] Figure 2A A structural schematic diagram of a light spot array provided by an embodiment of the present application;

[0019] Figure 2B A structural schematic diagram of an image A provided by an embodiment of the present application;

[0020] Figure 2C A structural schematic diagram of an image B provided by an embodiment of the present application;

[0021] Figure 2D A flowchart of updating a light spot array provided by an embodiment of the present application;

[0022] Figure 3 A structural schematic diagram of an arrangement of N liquid crystal units provided by an embodiment of the present application;

[0023] Figure 4 A structural schematic diagram of a bit plane provided by an embodiment of the present application;

[0024] Figure 5A flowchart of an image refreshing method provided by an embodiment of the present application;

[0025] Figure 6 A flowchart of a liquid crystal cell refreshing method provided by an embodiment of the present application;

[0026] Figure 7 A flowchart of an image refreshing method provided by an embodiment of the present application;

[0027] Figure 8 A structural diagram of an image display provided by an embodiment of the present application;

[0028] Figure 9A A flowchart of a liquid crystal cell refreshing method provided by an embodiment of the present application;

[0029] Figure 9B A flowchart of a liquid crystal cell refreshing method provided by an embodiment of the present application;

[0030] Figure 10 A flowchart of an image refreshing method provided by an embodiment of the present application;

[0031] Figure 11 A flowchart of a liquid crystal cell refreshing method provided by an embodiment of the present application;

[0032] Figure 12 A flowchart of an image refreshing method provided by an embodiment of the present application;

[0033] Figure 13 A flowchart of a liquid crystal cell refreshing method provided by an embodiment of the present application;

[0034] Figure 14 A structural diagram of an image refreshing device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0035] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. The terms “first”, “second” and corresponding terms of reference labels and the like in the specification and claims and drawings of the present application are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, which is only a distinguishing way adopted in the description of the embodiments of the present application for the same attribute objects in the description. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion, so that the processes, methods, systems, products or equipment containing a series of units do not have to be limited to those units, but can include other units not clearly listed or inherent to these processes, methods, products or equipment.

[0036] In one possible application scenario, a wavelength selective switch (WSS) device as shown in Figure 1 The WSS device can realize full-optical connection between any pair of input ports and output ports, that is, for any wavelength of optical signal in the S1 input ports, it can be output from any one of the S2 output ports.

[0037] It should be understood that the first and second optical gratings can be two devices in the WSS device, or can be combined into one device according to different optical designs, which is not limited here. The first and second LCOSs can independently deflect the light beams, such as the first LCOS can independently deflect the light beams of different input ports, and the second LCOS can independently deflect the light beams of different output ports.

[0038] In the WSS device as shown in Figure 1 If each input port supports W wavelength channels, an S1*W spot array can be formed, which is the LCOS image of the WSS device. When the output port of the WSS device is switched, the LCOS image will also change accordingly.

[0039] Specifically, for any one wavelength of light signal of any one input port of the WSS device, the wavelength of light signal of the input port can display different LCOS images in the case of outputting from different output ports. For example, the LCOS image displayed by the wavelength of light signal of the s1th input port of the WSS device is image A when the wavelength of light signal of the s1th input port is output from the s2-1th output port. When the wavelength of light signal of the s1th input port is switched to the s2-2th output port, the LCOS image displayed by the wavelength of light signal of the s1th input port is image B. Wherein, the s1th input port is any one input port of the WSS device, the s2-1th output port and the s2-2th output port are any two different output ports of the WSS device, and λ is any one of the W wavelengths supported by the s1th input port.

[0040] When the wavelength of light signal λ is output from the s2-1th output port, the displayed LCOS image is image A, that is, the WSS device needs to update each spot in the S1*W spot array in sequence so that the LCOS image is image A. During the updating process of the S1*W spot array, the wavelength of light signal λ is switched to the s2-2th output port, and the WSS device needs to update each spot in the S1*W spot array in sequence so that the LCOS image is image B. At present, after the S1*W spot array is updated according to the LCOS image A, the S1*W spot array is updated according to the LCOS image B.

[0041] For example, as shown in Figure 2A , the spot array is 2*2 in size. In order to facilitate the description hereinafter, the coordinates of each spot in the spot matrix are (1, 1), (1, 2), (2, 1), (2, 2) in sequence. When the WSS device determines that the wavelength of light signal λ is output from the s2-1th output port, the spot array should display image A, which can be referred to as Figure 2B . Figure 2B The pixel values of the displayed image A are A1, A2, A3 and A4 respectively. When the WSS device determines that the wavelength of light signal λ is switched to the s2-2th output port during the updating of the spot array according to image A to the coordinate (1, 2), the WSS device needs to update the spot array according to image A and then update the spot array according to image B. Image B can be referred to as Figure 2C . Figure 2C The pixel values of the displayed image B are B1, B2, B3 and B4 respectively.

[0042] The specific updating process can be referred to as Figure 2DAfter the WSS device determines that the spot array should display image A, the WSS device updates the spot at coordinate (1, 1) to A1, and updates the spot at coordinate (1, 2) to A2. When updating the spot at coordinate (1, 2), the WSS device determines that the spot array should display image B. Then, the WSS device updates the spot at coordinate (2, 1) to A3, and updates the spot at coordinate (2, 2) to A4. At this time, the spot array completes the display of image A. Then, the WSS device updates the spot at coordinate (1, 1) to B1, updates the spot at coordinate (1, 2) to B2, updates the spot at coordinate (2, 1) to B3, and updates the spot at coordinate (2, 2) to B4. At this time, the spot array completes the display of image B.

[0043] As can be seen from the above updating process of the spot matrix, when the spot array displays image A, if there is image B that needs to be displayed as soon as possible, the spot array needs to display image A completely before displaying image B. Therefore, the process of switching from image A to image B for display will take a lot of time. How the WSS device quickly switches from image A to image B for display is a technical problem that needs to be solved at present.

[0044] In another possible application scenario, when displaying an image, the display can refresh the image in the display at a fixed refresh frequency. For example, in a game scenario, the display can display image A according to the current mouse position of a user. During the display of image A by the display, the user quickly moves the mouse, and the display needs to display image B according to the mouse position after the movement. At present, the display displays image B after completing the display of image A. The specific updating process can refer to the above description, which is not repeated here. Figure 2D

[0045] In the embodiments of the present application, the display can be a twisted nematic (TN) liquid crystal display, a super twisted nematic (STN) liquid crystal display, a dual scantortuosity nomograph (DSTN) liquid crystal display, a thin film transistor (TFT) liquid crystal display, an organic light-emitting diode (OLED) display, and the like, which are not limited here.

[0046] ​As can be seen from the above display process, if there is an image B that needs to be displayed as soon as possible while the monitor is displaying image A, then the monitor needs to display image A completely before displaying image B. Therefore, the process of switching from image A to image B will take a lot of time, which will cause serious lag in game scenes. How to quickly switch the monitor from image A to image B is a technical problem that urgently needs to be solved.

[0047] In order to solve the technical problem of quickly switching from image A to image B for display in WSS devices / displays, this application provides an image refresh method and apparatus.

[0048] Combination Figure 1 The WSS device shown and the display described above, in this application embodiment, provide an image refresh method. This image refresh method can be applied to the refresh of liquid crystal cells in an image display. The image display can be the S1*W light spot array in the WSS device, or it can be the display described above; no limitation is made here. The image display includes N liquid crystal cells, where N is an integer greater than 0. The arrangement of the N liquid crystal cells can be as follows: Figure 3 The matrix form of S1*W is shown, i.e., N = S1*W.

[0049] In this embodiment of the application, each of the N liquid crystal cells is set to correspond to M first bits, and the grayscale value of each liquid crystal cell is determined according to the bit values ​​of the M first bits corresponding to each liquid crystal cell, where M is an integer greater than 0.

[0050] For any liquid crystal cell among N liquid crystal cells, the M first bits corresponding to that liquid crystal cell form a high-low bit sequence. This high-low bit sequence includes the sequence numbers corresponding to the M first bits, with each first bit corresponding to a different sequence number. For example, refer to... Figure 2A The image display shown has a liquid crystal cell at coordinate (1,2) corresponding to four first bits, which are 1-1, 1-2, 1-3 and 1-4 in sequence. The first bit 1-1 corresponds to the number 1, the first bit 1-2 corresponds to the number 2, the first bit 1-3 corresponds to the number 3, and the first bit 1-4 corresponds to the number 4. Therefore, the high and low bit sequence corresponding to the four first bits (i.e., 1-1, 1-2, 1-3 and 1-4) of the liquid crystal cell at coordinate (1,2) is 1234.

[0051] It should be understood that the high and low bit sequences corresponding to the M first bits of each liquid crystal cell can be directly set in each of the first bits of the liquid crystal cell, or other setting methods can be used, which are not limited here.

[0052] Generally speaking, the first bit with the same serial number corresponding to each of the N liquid crystal cells can form a bit plane (BP). Therefore, the M first bits corresponding to each of the N liquid crystal cells can form M bit planes, and each bit plane includes N first bits.

[0053] For example, an image display consists of 2x2 liquid crystal units, and the coordinates of each liquid crystal unit in the image display can be referenced... Figure 2A As shown, they are (1,1), (1,2), (2,1), and (2,2) in sequence. Figure 4 As shown, each liquid crystal cell corresponds to 4 first bits. Specifically, the 4 first bits corresponding to the liquid crystal cell at coordinate (1,1) are 1-1, 1-2, 1-3, and 1-4, and their corresponding numbers are 1, 2, 3, and 4, respectively. Similarly, the 4 first bits corresponding to the liquid crystal cell at coordinate (1,2) are 2-1, 2-2, 2-3, and 2-4, and their corresponding numbers are 1, 2, 3, and 4, respectively. 4; The four first bits corresponding to the liquid crystal cell at coordinate (2,1) are 3-1, 3-2, 3-3 and 3-4 respectively, and the serial numbers corresponding to these four first bits (i.e. 3-1, 3-2, 3-3 and 3-4) are 1, 2, 3 and 4 respectively; The four first bits corresponding to the liquid crystal cell at coordinate (2,2) are 4-1, 4-2, 4-3 and 4-4 respectively, and the serial numbers corresponding to these four first bits (i.e. 4-1, 4-2, 4-3 and 4-4) are 1, 2, 3 and 4 respectively.

[0054] Among them, Figure 4 As can be seen, the first bit of each liquid crystal cell, numbered 1, can form a bit plane, namely, the first bits 1-1, 2-1, 3-1, and 4-1 can form a bit plane, denoted as bit plane 1. The first bit of each liquid crystal cell, numbered 2, can form a bit plane, namely, the first bits 1-2, 2-2, 3-2, and 4-2 can form a bit plane, denoted as bit plane 2. The first bit of each liquid crystal cell, numbered 3, can form a bit plane, namely, the first bits 1-3, 2-3, 3-3, and 4-3 can form a bit plane, denoted as bit plane 3. The first bit of each liquid crystal cell, numbered 4, can form a bit plane, namely, the first bits 1-4, 2-4, 3-4, and 4-4 can form a bit plane, denoted as bit plane 4. Therefore, this image display corresponds to 4 bit planes.

[0055] The process of displaying an image on the image display involves setting the values ​​of the first bits in the M bit planes corresponding to the image display based on the image. During this process, the M bit planes have a setting order; that is, based on the image (such as pixel values ​​in the image), the values ​​of the first bits in each of the M bit planes are set sequentially according to the setting order. For ease of explanation, this setting order of the M bit planes is referred to as the first setting order. Specifically, for any one of the M bit planes, this bit plane includes N first bits, and these N first bits have a setting order. When setting the first bits in this bit plane, based on the image, the values ​​of each first bit in this bit plane are set sequentially according to the setting order of the N first bits. For ease of explanation, this setting order of the N first bits is referred to as the second setting order.

[0056] The embodiments of this application do not limit the specific content of the first setting order and the second setting order, and the second setting order of N first bits in different bit planes may be the same or different, which is not limited here. For ease of explanation later, the second setting order of N first bits in different bit planes is the same.

[0057] In one possible implementation, the first setting order can be determined based on the index of the first bit in the M bit planes. For example, the first setting order can be the ascending order of the indexes of the first bits in the M bit planes. For instance, referring to... Figure 4 As shown, the first bit in bit plane 1 is numbered 1, the first bit in bit plane 2 is numbered 2, the first bit in bit plane 3 is numbered 3, and the first bit in bit plane 4 is numbered 4. Therefore, the first configuration order can be bit plane 1, bit plane 2, bit plane 3, and bit plane 4. According to this first configuration order, bit plane 1 can also be called the first bit plane, bit plane 2 can also be called the second bit plane, bit plane 3 can also be called the third bit plane, and bit plane 4 can also be called the fourth bit plane.

[0058] In one possible implementation, the second setting order can be determined based on the positional relationship of N first bits in a bit plane. For example, the second setting order could be: for first bits with different row coordinates, the first bit with the smaller row coordinate is updated first; for first bits with different column coordinates, the first bit with the smaller column coordinate is updated first. For example, refer to... Figure 4As shown, the bit plane 1 includes 4 first bits, i.e., the first bit 1-1, the first bit 2-1, the first bit 3-1 and the first bit 4-1, and a second setting order of the 4 first bits can be the first bit 1-1, the first bit 2-1, the first bit 3-1 and the first bit 4-1. According to the second setting order, the first bit 1-1 can also be referred to as the 1st first bit, the first bit 2-1 can also be referred to as the 2nd first bit, the first bit 3-1 can also be referred to as the 3rd first bit, and the first bit 4-1 can also be referred to as the 4th first bit.

[0059] It should be understood that the "xth" bit plane mentioned hereinafter in the present application is determined based on the setting order of the first setting order. The "ith" first bit is determined based on the setting order of the second setting order, and details are not described hereinafter.

[0060] According to the image display device described above, the embodiment of the present application provides a method for refreshing an image display device, which can be executed by a processor in the image display device or a module in the processor or a chip in the processor, which is not limited here. For the convenience of description, the following is described by taking the processor in the image display device as the execution subject.

[0061] In the embodiment of the present application, the processor can refresh the image display device by using a first image, wherein the first image includes N pixel values, the length and the width of the first image can be S1 and W respectively, and the size of the first image can be S1*W, i.e., N=S1*W.

[0062] Each pixel value in the first image corresponds to M third bits, and each pixel value is determined according to the values of the M third bits corresponding to each pixel value. For example, in the case that each pixel value in the first image is determined according to the values of 4 third bits, if the values of the 4 third bits are 1, 0, 0 and 1 respectively, the pixel value corresponding thereto is 1001. The M third bits corresponding to each pixel value in the first image correspond to a high-low bit sequence, and the high-low bit sequence includes the serial numbers corresponding to the M third bits respectively, and the serial numbers corresponding to each third bit are different. For example, if the values of the 4 third bits corresponding to a pixel value are 1, 0, 0 and 1 respectively, the serial numbers corresponding to the above 4 third bits are 1, 2, 3 and 4 in turn, i.e., the high-low bit sequence corresponding to the above 4 third bits is 1234.

[0063] It should be understood that the "xth" third bit mentioned hereinafter in the present application is determined based on the order corresponding thereto.

[0064] In a possible implementation, after determining to refresh the image display device with the first image, the processor can set the value of the first bit in the M bit planes corresponding to the image display device according to the N pixel values in the first image, that is, the processor can set the M bit planes corresponding to the image display device according to the first setting sequence based on the N pixel values in the first image, and set the first bit in each bit plane according to the second setting sequence in each bit plane. Specifically, the processor sets the M bit planes according to the first setting sequence based on the values of the M third bits corresponding to the N pixel values in the first image respectively, and sets the first bit in the xth bit plane according to the second setting sequence based on the value of the xth third bit corresponding to the N pixel values in the first image, where the xth bit plane is the setting sequence of the bit plane determined based on the first setting sequence, x is any integer between 1 and M, the serial number of the xth third bit is the same as that of the first bit in the xth bit plane, and the processor repeats the above process until the display of the first image in the image display device is completed. For details, refer to the steps shown in the specific embodiment. Figure 5

[0065] S501, the processor sets a variable z = 1.

[0066] S502, the processor sets a variable k = 1.

[0067] S503, the processor determines whether z is greater than M, if not, the process jumps to S504; if yes, the process ends, that is, S504 to S508 are not executed.

[0068] S504, the processor determines whether k is greater than N, if not, the process jumps to S505; if yes, the process jumps to S508.

[0069] S505, the processor determines the value of the zth third bit corresponding to the kth pixel value in the first image.

[0070] S506, the processor sets the value of the kth first bit in the zth bit plane corresponding to the image display device based on the value of the zth third bit corresponding to the kth pixel value.

[0071] In the application embodiment, the processor directly sets the value of the kth first bit in the zth bit plane corresponding to the image display device to the value of the zth third bit corresponding to the kth pixel value. The kth first bit is the first bit in the zth bit plane in the kth liquid crystal cell.

[0072] S507, the processor sets k++, and then the process jumps to S504. The k++ can be understood as k being incremented by 1.

[0073] ​S508, the processor sets z++, and then jumps to S502. Wherein, z++ can be understood as z is increased by 1.

[0074] The above Figure 5 The steps shown provide a method for quickly displaying a first image in an image display.

[0075] For example, as Figure 6 As shown, after the processor determines that the image A should be displayed, the image A includes 4 pixel values, A1, A2, A3 and A4. Wherein, the values of the 4 third bits corresponding to A1 are A1-1, A1-2, A1-3 and A1-4 in turn, the values of the 4 third bits corresponding to A2 are A2-1, A2-2, A2-3 and A2-4 in turn, the values of the 4 third bits corresponding to A3 are A3-1, A3-2, A3-3 and A3-4 in turn, and the values of the 4 third bits corresponding to A4 are A4-1, A4-2, A4-3 and A4-4 in turn.

[0076] The processor first sets the value of the first bit in the first bit plane corresponding to the image display. Specifically, the processor first sets the value of the first bit in the first bit plane in the liquid crystal cell at coordinate (1, 1) to A1-1, then sets the value of the first bit in the first bit plane in the liquid crystal cell at coordinate (1, 2) to A2-1, then sets the value of the first bit in the first bit plane in the liquid crystal cell at coordinate (2, 1) to A3-1, and then sets the value of the first bit in the first bit plane in the liquid crystal cell at coordinate (2, 2) to A4-1.

[0077] Then, the processor sets the value of the first bit in the second bit plane corresponding to the image display. Wherein, the setting process of the value of the first bit in the second bit plane can refer to the setting process of the value of the first bit in the first bit plane, which will not be repeated here.

[0078] Then, the processor sets the value of the first bit in the third bit plane corresponding to the image display. Wherein, the setting process of the value of the first bit in the third bit plane can refer to the setting process of the value of the first bit in the first bit plane, which will not be repeated here.

[0079] Finally, the processor sets the value of the first bit in the fourth bit plane corresponding to the image display. Wherein, the setting process of the value of the first bit in the fourth bit plane can refer to the setting process of the value of the first bit in the first bit plane, which will not be repeated here.

[0080]

Embodiment One

[0081] In the process that the image display displays the first image, if there is a second image that needs to be displayed as soon as possible, the image display can quickly switch from the first image to the second image for display, which can include the following steps as shown in Figure 7

[0082] S701, after setting the value of the first target bit of the image display based on the first image, the processor receives an image display instruction. Wherein, the first target bit is the first bit in the bit plane corresponding to the image display.

[0083] In embodiment one, when the processor receives the image display instruction, the processor can also receive a second image, wherein the second image is different from the first image, and the image display instruction is used to instruct to display the second image.

[0084] It should be understood that, in the case that the image display instruction includes the second image, the processor can obtain the second image from the image display instruction; in the case that the image display instruction does not include the second image, the processor can obtain the second image in other ways, which will not be described here.

[0085] In embodiment one, the second image includes N pixel values, the length and width of the second image can be S1 and W respectively, and the size of the second image can be S1*W, that is, N=S1*W.

[0086] Each pixel value in the second image corresponds to M second bits, and each pixel value is determined according to the value of the M second bits corresponding to each pixel value. For example, in the case that each pixel value in the second image is determined according to the value of 4 second bits, if the values of the 4 second bits are 1, 0, 0, and 1 respectively, the pixel value corresponding thereto is 1001. The M second bits corresponding to each pixel value in the second image correspond to a high-low bit sequence, which includes the serial numbers corresponding to the M second bits respectively, and the serial numbers corresponding to each second bit are different. For example, if the values of the 4 second bits are 1, 0, 0, and 1 respectively, the serial numbers corresponding to the above 4 second bits are 1, 2, 3, and 4 in turn, that is, the high-low bit sequence corresponding to the above 4 second bits is 1234.

[0087] It should be understood that, in the following of the present application, the "xth" second bit is determined based on the first setting order to determine the order corresponding to the second bit.

[0088] ​In Embodiment 1, the processor can receive an image display instruction through the following implementation: after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, the processor receives the image display instruction; wherein, the first target bit includes all the first bits in the bit planes before the x-th bit plane in the first setting order, the first bit in the second setting order within the x-th bit plane before the i-th first bit, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N].

[0089] It should be understood that all first bits in the bit plane preceding the x-th bit plane in the first setting order can be understood as all first bits from the 1st bit plane to the (x-1)th bit plane; the first bit in the second setting order within the x-th bit plane preceding the ith first bit can be understood as the 1st first bit to the (i-1)th first bit in the x-th bit plane.

[0090] For example, such as Figure 8 As shown, after the processor determines that image A should be displayed, image A can be understood as the first image. Image A includes four pixel values, namely A1, A2, A3, and A4. Specifically, the values ​​of the four third bits corresponding to A1 are A1-1, A1-2, A1-3, and A1-4, respectively; the values ​​of the four third bits corresponding to A2 are A2-1, A2-2, A2-3, and A2-4, respectively; the values ​​of the four third bits corresponding to A3 are A3-1, A3-2, A3-3, and A3-4, respectively; and the values ​​of the four third bits corresponding to A4 are A4-1, A4-2, A4-3, and A4-4, respectively.

[0091] After setting the value of the second first bit in the second bit plane corresponding to the image display based on image A, the processor receives the image display instruction. Specifically, the values ​​of all first bits in the first bit plane are set by image A; that is, the values ​​of first bits 1-1, 2-1, 3-1, and 4-1 in the first bit plane are set to A1-1, A2-1, A3-1, and A4-1, respectively. The values ​​of the first first bits 1-2 and 2-2 in the second bit plane are set to A1-2 and A2-2, respectively.

[0092] S702, the processor sets the value of the second target bit of the image display based on the second image. The second target bit is the first bit in the M bit planes corresponding to the image display, excluding the first target bit, and its value has not been set by the first image.

[0093] In the embodiment one, after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display according to the first image, the processor receives an image display instruction; wherein the first target bit includes all the first bits in the bit planes before the x-th bit plane in the first setting order, the first bits before the i-th first bit in the x-th bit plane in the second setting order, and the i-th first bit in the x-th bit plane, x is any integer between [1, M], i is any integer between [1, N]; the second target bit includes all the first bits in the bit planes after the x-th bit plane in the first setting order, and the first bits after the i-th first bit in the x-th bit plane in the second setting order.

[0094] It should be understood that all the first bits in the bit planes after the x-th bit plane in the first setting order can be understood as all the first bits in the x+1-th bit plane to the M-th bit plane; the first bits after the i-th first bit in the x-th bit plane in the second setting order can be understood as the i-th first bit to the N-th first bit in the x-th bit plane.

[0095] In the embodiment of the present application, the processor can set the value of the second target bit of the image display based on the value of the second bit corresponding to the pixel value in the second image, which can be specifically understood as: the processor can set the second target bit based on the value of the second bit corresponding to the N pixel values in the second image, in combination with the first setting order and the second setting order. Specifically, the processor can set the x-th bit plane to the M-th bit plane based on the value of the x-th second bit to the value of the M-th second bit corresponding to the N pixel values in the second image, according to the first setting order. For any bit plane in the x-th bit plane to the M-th bit plane, taking the x-th bit plane as an example, the processor can set the second target bit in the x-th bit plane based on the value of the x-th third bit corresponding to the N pixel values in the second image, according to the second setting order.

[0096] The following details how the processor sets the value of the second target bit of the image display based on the second image for different value ranges of i, including the following case one and case two.

[0097] In case one, when i is any integer between [1, N-1], the second target bit includes all the first bits in the bit planes after the x-th bit plane in the first setting order, and the i-th first bit to the N-th first bit in the x-th bit plane in the second setting order.

[0098] For example, as shown in FIG. 2, when i is 2, the second target bit includes all the first bits in the bit planes after the x-th bit plane in the first setting order, and the 2-th first bit to the N-th first bit in the x-th bit plane in the second setting order. Figure 9AAs shown, the processor acquires image B when the processor sets the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (1, 2) in the image display according to the value A2-1 of the first third bit corresponding to the pixel value at coordinate (1, 2) in image A. Then, the processor sets the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (2, 1) in the image display according to the value B3-1 of the first second bit corresponding to the pixel value at coordinate (2, 1) in image B. The processor sets the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (2, 2) in the image display according to the value B4-1 of the first second bit corresponding to the pixel value at coordinate (2, 2) in image B.

[0099] Then, the processor sets the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1, 1) in the image display according to the value B1-2 of the second second bit corresponding to the pixel value at coordinate (1, 1) in image B. The processor sets the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1, 2) in the image display according to the value B2-2 of the second second bit corresponding to the pixel value at coordinate (1, 2) in image B. The processor sets the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (2, 1) in the image display according to the value B3-2 of the second second bit corresponding to the pixel value at coordinate (2, 1) in image B. The processor sets the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (2, 2) in the image display according to the value B4-2 of the second second bit corresponding to the pixel value at coordinate (2, 2) in image B.

[0100] Then, the processor sets the value of the first bit in the third bit plane of the image display corresponding to the third target bit, and the setting process of the value of the first bit in the third bit plane can refer to the setting process of the value of the first bit in the second bit plane, which will not be described herein.

[0101] Finally, the processor sets the value of the first bit in the fourth bit plane of the image display corresponding to the fourth target bit, and the setting process of the value of the first bit in the fourth bit plane can refer to the setting process of the value of the first bit in the second bit plane, which will not be described herein.

[0102] In case two, when i is N, the second target bit includes all the first bits in the bit planes after the xth bit plane in the first setting sequence.

[0103] For example, as shown in FIG. 6, the first setting sequence includes the first bit in the first bit plane, the first bit in the second bit plane, the first bit in the third bit plane, and the first bit in the fourth bit plane. Figure 9BAs shown, during the process of displaying image A, the processor sets the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (2, 2) in the image display according to the value A4-1 of the first third bit corresponding to the pixel value at coordinate (2, 2) in image A, and obtains image B.

[0104] Then, the processor sets the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1, 1) in the image display according to the value B1-2 of the second second bit corresponding to the pixel value at coordinate (1, 1) in image B. The processor sets the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1, 2) in the image display according to the value B2-2 of the second second bit corresponding to the pixel value at coordinate (1, 2) in image B. The processor sets the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (2, 1) in the image display according to the value B3-2 of the second second bit corresponding to the pixel value at coordinate (2, 1) in image B. The processor sets the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (2, 2) in the image display according to the value B4-2 of the second second bit corresponding to the pixel value at coordinate (2, 2) in image B.

[0105] Then, the processor sets the value of the first bit in the third bit plane of the image display, and the process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the second bit plane, which will not be repeated here.

[0106] Finally, the processor sets the value of the first bit in the fourth bit plane of the image display, and the process of setting the value of the first bit in the fourth bit plane can refer to the process of setting the value of the first bit in the second bit plane, which will not be repeated here.

[0107] Optionally, the above-mentioned Figure 7 The method shown can further include S703.

[0108] S703, the processor sets the value of the first bit of the image display based on the second image.

[0109] In the above S703, the processor sets the value of the first bit in the M bit planes of the image display according to the second image, which can refer to the process of setting the value of the first bit in the M bit planes of the image display according to the first image, such as the steps shown, which will not be repeated here. Figure 5

[0110] In the above S703, the processor sets the value of the first bit in the M bit planes of the image display according to the second image, which can refer to the process of setting the value of the first bit in the M bit planes of the image display according to the first image, such as the steps shown, which will not be repeated here. Figure 7 ​In the step shown, during the process of displaying the first image by the image display, if there is a second image that needs to be displayed as soon as possible, the second image is directly used to set the value of the first bit of the image display corresponding to the first bit not set by the first image, without waiting for the first image to be completely displayed by the image display, which is beneficial to improve the efficiency of switching from the first image to the second image for display by the image display.

[0111] Embodiment Two

[0112] In the process of displaying the first image by the image display, if there is a second image that needs to be displayed as soon as possible, the image display can quickly switch from the first image to the second image for display, which can include the following steps shown. Figure 10

[0113] S1001, after setting the value of the first target bit of the image display based on the first image, the processor receives an image display instruction. Wherein, the first target bit is the first bit in the bit plane corresponding to the image display.

[0114] The image display instruction in Embodiment Two can refer to the image display instruction in Embodiment One, which will not be repeated here.

[0115] In Embodiment Two, the value of the first target bit of the image display is set by the first image, and the first bit of the first target bit in the image display is not set by the first image.

[0116] The implementation of the processor receiving the image display instruction can refer to the implementation in Embodiment One, which will not be repeated here.

[0117] S1002, the processor sets the value of the first bit of the image display based on the second image.

[0118] In Embodiment Two, the processor sets all the first bits in the M bit planes corresponding to the image display based on the value of the second bit corresponding to the N pixel values in the second image, in combination with the first setting order and the second setting order.

[0119] For example, as shown in the figure, Figure 11 When the processor sets the value of the first bit in the liquid crystal cell of coordinate (1, 2) in the image display corresponding to the first bit in the first bit plane based on the value A2-1 of the first third bit corresponding to the pixel value of coordinate (1, 2) in image A, the processor acquires image B.

[0120] ​Next, the processor refreshes the value of the first bit in the first bit plane of each liquid crystal cell using image B. Specifically, the processor uses the value B1-1 of the first second bit corresponding to the pixel value at coordinate (1,1) in image B to set the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (1,1) in the image display. The processor uses the value B2-1 of the first second bit corresponding to the pixel value at coordinate (1,2) in image B to set the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (1,2) in the image display. The processor uses the value B3-1 of the first second bit corresponding to the pixel value at coordinate (2,1) in image B to set the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (2,1) in the image display. The processor uses the value B4-1 of the first second bit corresponding to the pixel value at coordinate (2,2) in image B to set the value of the first bit in the first bit plane of the liquid crystal unit at coordinate (2,2) in the image display.

[0121] Then, the processor sets the value of the first bit in the second bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be described in detail here.

[0122] Then, the processor sets the value of the first bit in the third bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be repeated here.

[0123] Finally, the processor sets the value of the first bit in the fourth bit plane corresponding to the image display. The process of setting the value of the first bit in the fourth bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be repeated here.

[0124] exist Figure 10 In the steps shown, if there is a second image that needs to be displayed as soon as possible while the image display is displaying the first image, there is no need to wait for the image display to fully display the first image before displaying the second image. Instead, the second image is directly used to refresh the display starting from the value of the first bit in the first bit plane corresponding to the image display. This helps to improve the efficiency of the image display in switching from the first image to the second image.

[0125]

Example 3

[0126] During the display of the first image on the image display, if a second image needs to be displayed as soon as possible, the image display can quickly switch from the first image to the second image for display. This may include, for example: Figure 12The following steps are shown.

[0127] S1201, after setting the value of the first target bit of the image display based on the first image, the processor receives the image display instruction. The first target bit is the first bit in the bit plane corresponding to the image display.

[0128] The image display instructions in Embodiment 3 can refer to the image display instructions in Embodiment 1, and will not be repeated here.

[0129] In Embodiment 3, the values ​​of the first target bits of the image display are all set by the first image, and the first bits of the image display, except for the first target bits, are not set by the first image.

[0130] The implementation method for the processor to receive image display instructions can refer to the implementation method in Embodiment 1, and will not be repeated here.

[0131] S1202, the processor sets the value of the second target bit of the image display based on the second image. The second target bit includes the first bit (excluding the first target bit) and at least one first target bit in the M bit planes corresponding to the image display.

[0132] In Embodiment 3, after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, the processor receives an image display instruction; wherein, the first target bit includes all the first bits in the bit plane before the x-th bit plane in the first setting order, the first bit in the second setting order within the x-th bit plane before the i-th first bit, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N]; the second target bit includes all the first bits in the x-th bit plane in the first setting order and in the bit plane after the x-th bit plane.

[0133] It should be understood that all first bits in the bit planes preceding the x-th bit plane in the first setting order can be understood as all first bits from the 1st bit plane to the (x-1th)th bit plane; the first bits in the second setting order within the x-th bit plane preceding the ith first bit can be understood as the 1st first bit to the (i-1th)th first bit in the x-th bit plane. All first bits in the bit planes following the x-th bit plane in the first setting order can be understood as all first bits from the (x+1th)th bit plane to the Mth bit plane.

[0134] For example, such as Figure 13As shown, during the process of displaying image A, when the processor uses the value A2-2 of the second third bit corresponding to the pixel value at coordinate (1,2) in image A to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (1,2) in the image display, the processor acquires image B.

[0135] Next, the processor uses image B to set the value of the first bit in the second bit plane. Specifically, the processor uses the value B1-2 of the second bit corresponding to the pixel value at coordinate (1,1) in image B to set the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1,1) in the image display. The processor uses the value B2-2 of the second bit corresponding to the pixel value at coordinate (1,2) in image B to set the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1,2) in the image display. The processor uses the value B3-2 of the second bit corresponding to the pixel value at coordinate (2,1) in image B to set the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (2,1) in the image display. The processor uses the value B4-2 of the second bit corresponding to the pixel value at coordinate (2,2) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (2,2) in the image display.

[0136] Then, the processor sets the value of the first bit in the third bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the second bit plane, and will not be described in detail here.

[0137] Finally, the processor sets the value of the first bit in the fourth bit plane corresponding to the image display. The process of setting the value of the first bit in the fourth bit plane can refer to the process of setting the value of the first bit in the second bit plane, and will not be repeated here.

[0138] Optionally, Figure 12 The method shown may also include S1203.

[0139] S1203, the processor sets the value of the first bit of the image display based on the second image.

[0140] In the above S1203, the processor uses the second image to sequentially set the values ​​of the first bits in the M bit planes corresponding to the image display. This can be referenced in the context of the processor using the first image to sequentially set the values ​​of the first bits in the M bit planes corresponding to the image display. Figure 5 The steps shown are not repeated here.

[0141] existFigure 12 In the steps shown, if there is a second image that needs to be displayed as soon as possible while the image display is displaying the first image, there is no need to wait for the image display to fully display the first image before displaying the second image. Instead, the second image is directly used to refresh the bit value of the first bit in the bit plane of the image display that is currently displaying the first image. This helps to improve the efficiency of the image display in switching from the first image to the second image.

[0142] Based on the above embodiments, this application also provides an image refresh device, which is applied to, for example... Figure 1 The WSS device shown and the display described above are used to implement Figure 7 or Figure 10 or Figure 12 The illustrated embodiment provides an image refresh method. See also... Figure 14 As shown, the image refresh device includes: a receiving module 1401 and a refresh module 1402. Wherein:

[0143] The receiving module 1401 is configured to receive an image display instruction after setting the value of the first target bit of the image display based on the first image. The image display instruction is used to instruct the display of a second image. The first target bit is the first bit in the bit plane corresponding to the image display. The image display includes N liquid crystal units, each of the N liquid crystal units corresponds to M first bits, and the image display corresponds to M bit planes. Each bit plane includes one first bit corresponding to each liquid crystal unit. N and M are both integers greater than 0.

[0144] The refresh module 1402 is used to set the value of the second target bit of the image display based on the second image. The second target bit is the first bit in the M bit planes corresponding to the image display, excluding the first target bit. The value of the second target bit is not set by the first image.

[0145] In one possible implementation, the M bit planes have a first setting order, and the first bit in each bit plane has a second setting order;

[0146] The receiving module 1401 is specifically used for: setting M bit planes based on the first image and in a first setting order, setting the first bit in each bit plane in a second setting order; after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, receiving an image display instruction; the first target bit includes all the first bits in the bit planes before the x-th bit plane in the first setting order, the first bit in the x-th bit plane before the i-th first bit in the second setting order, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N].

[0147] In one possible implementation, the second target bit includes all the first bits in the bit plane following the x-th bit plane in the first setting order, and the first bit in the second setting order following the i-th first bit in the x-th bit plane.

[0148] In one possible implementation, a pixel value in the second image corresponds to M second bits, and a pixel value is determined based on the values ​​of the M second bits.

[0149] The refresh module 1402 is specifically used to: set the value of the second target bit of the image display based on the value of the second bit corresponding to the pixel value in the second image.

[0150] In one possible implementation, the refresh module 1402 is also used to: set the value of the first bit of the image display based on the second image.

[0151] In the embodiments of this application, both the receiving module and the refreshing module can be implemented in software or in hardware. For example, the implementation of the refreshing module will be described below. Similarly, the implementation of the receiving module can refer to the implementation of the refreshing module.

[0152] As an example of a software functional unit, a refresh module may include code running on a compute instance. A compute instance may include at least one of a physical host (computing device), a virtual machine, or a container. Furthermore, the aforementioned compute instance may be one or more. For example, a refresh module may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed within the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed within the same availability zone (AZ) or in different AZs, each AZ comprising one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0153] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0154] As an example of a hardware functional unit, a refresh module may include at least one computing device, such as a server. Alternatively, a refresh module may be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0155] The refresh module includes multiple computing devices that can be distributed within the same region or in different regions. Similarly, the refresh module includes multiple computing devices that can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the refresh module includes multiple computing devices that can be distributed within the same Virtual Private Cloud (VPC) or multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0156] It should be noted that, in other embodiments, the receiving module is used to receive an image display instruction after setting the value of the first target bit of the image display based on the first image. The image display instruction is used to instruct the display of the second image. The first target bit is the first bit in the bit plane corresponding to the image display. The image display includes N liquid crystal units, each of the N liquid crystal units corresponds to M first bits, and the image display corresponds to M bit planes. Each bit plane includes one first bit corresponding to each liquid crystal unit. N and M are both integers greater than 0. The refresh module is used to set the value of the second target bit of the image display based on the second image. The second target bit is the first bit in the multiple bit planes corresponding to the image display other than the first target bit. The value of the second target bit has not been set by the first image.

[0157] The steps implemented by the receiving module and the refresh module can be specified as needed. By implementing different steps in the image refresh method through the receiving module and the refresh module, the full functionality of the image refresh device can be achieved.

[0158] This application also provides a computing device, which includes a processor and a memory, wherein the processor of the computing device is used to execute instructions stored in the memory of the computing device to cause the computing device to perform an image refresh method.

[0159] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing system or stored on any usable medium. When the computer program product is run on at least one computing device, it causes the at least one computing device to perform an image refresh method.

[0160] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to perform an image refresh method.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

[0162] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0163] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0164] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0165] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0166] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An image refresh method, characterized by, The method comprises: after setting a value of a first target bit of the image display based on a first image, receiving an image display instruction, the image display instruction being used for instructing to display a second image; the first target bit is a first bit in a bit plane corresponding to the image display, the image display comprises N liquid crystal units, each of the N liquid crystal units corresponds to M first bits, the image display corresponds to M bit planes, each bit plane comprises one first bit corresponding to each liquid crystal unit; N and M are integers greater than 0; setting a value of a second target bit of the image display based on the second image, the second target bit is a first bit in the M bit planes corresponding to the image display except the first target bit, and the value of the second target bit is not set by the first image.

2. The method of claim 1, wherein, The M bit planes have a first setting order, and the first bits in each bit plane have a second setting order; the method further comprises: setting the M bit planes based on the first image in the first setting order, and setting the first bits in each bit plane in the second setting order; after setting a value of an i-th first bit in an x-th bit plane corresponding to the image display based on the first image, receiving the image display instruction; the first target bit comprises all first bits in bit planes before the x-th bit plane in the first setting order, first bits before the i-th first bit in the x-th bit plane in the second setting order, and the i-th first bit in the x-th bit plane, x is any integer between 1 and M, and i is any integer between 1 and N.

3. The method of claim 2, wherein, The second target bit comprises all first bits in bit planes after the x-th bit plane in the first setting order, and first bits after the i-th first bit in the x-th bit plane in the second setting order.

4. The method according to any one of claims 1 to 3, characterized in that, one pixel value in the second image corresponds to M second bits, and the one pixel value is determined according to the values of the M second bits; the method further comprises: setting a value of a first bit of the image display based on the second image.

5. The method according to any one of claims 1 to 4, characterized in that, The method comprises: ​ 6. An image refresh apparatus characterized by comprising: ​ The receiving module is configured to receive an image display instruction after setting a value of a first target bit of the image display device based on the first image, the image display instruction being used to instruct to display a second image, the first target bit being a first bit in a bit plane corresponding to the image display device, the image display device comprising N liquid crystal units, each of the N liquid crystal units corresponding to M first bits, the image display device corresponding to M bit planes, each bit plane comprising one first bit corresponding to each liquid crystal unit, N and M being integers greater than 0; The refreshing module is configured to set a value of a second target bit of the image display device based on the second image, the second target bit being a first bit in the M bit planes corresponding to the image display device except the first target bit, the value of the second target bit not being set by the first image.

7. The apparatus of claim 6, wherein, The M bit planes have a first setting sequence, and the first bits in each bit plane have a second setting sequence; The receiving module is specifically configured to: set the M bit planes in the first setting sequence based on the first image, and set the first bits in each bit plane in the second setting sequence in each bit plane; receive the image display instruction after setting a value of an i-th first bit in an x-th bit plane corresponding to the image display device based on the first image, the first target bit comprising all first bits in bit planes before the x-th bit plane in the first setting sequence, first bits before the i-th first bit in the x-th bit plane in the second setting sequence, and the i-th first bit in the x-th bit plane, x being any integer between 1 and M, and i being any integer between 1 and N.

8. The apparatus of claim 7, wherein, The second target bit comprises all first bits in bit planes after the x-th bit plane in the first setting sequence, and first bits after the i-th first bit in the x-th bit plane in the second setting sequence.

9. The apparatus of claim 8, wherein, One pixel value in the second image corresponds to M second bits, and the one pixel value is determined according to values of the M second bits; The refreshing module is specifically configured to: set the value of the second target bit of the image display device based on values of second bits corresponding to pixel values in the second image.

10. The apparatus of any one of claims 6-9, wherein, The refreshing module is further configured to: set values of first bits of the image display device based on the second image.

11. A computing device, comprising: The computing device comprises a processor and a memory, the memory storing computer executable instructions, and the processor is configured to execute the computer executable instructions stored in the memory, so that the computing device performs the method in any one of claims 1-5.

12. A computer-readable storage medium, characterized in that, The computer program instructions, when executed by a computing system, cause the computing system to perform the method in any one of claims 1-5.

13. A computer program product comprising instructions, characterized in that, The instructions, when executed by a computing system, cause the computing system to perform the method in any one of claims 1-5.

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