Memory system, operating method thereof, and storage medium

Abstract

The embodiment of the invention provides a memory system, an operation method thereof and a storage medium. A memory system includes: a memory device; the memory controller is coupled with the memory device and is configured to perform encoding processing on to-be-written data corresponding to a first programming operation in response to power failure in the process of the first programming operation to obtain encoded data; writing the encoded data to the memory device; wherein the to-be-written data is data to be written into the memory device by the first programming operation; the data size of the coded data is smaller than that of the data to be written; and in response to re-power-on after power failure, decoding the acquired coded data and written data corresponding to the first programming operation to obtain at least part of error recovery data corresponding to the written data.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory system, its operation method, and a storage medium. Background Technology

[0002] With the development of science and technology, the market size of the integrated circuit industry is growing larger and larger. In the entire integrated circuit industry, the process and technology of non-volatile memory devices have made leaps and bounds in recent years. Among them, NAND (Not-And) memory has become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed and retention characteristics.

[0003] Significant progress has been made in the development of NAND flash memory technology, but there is still considerable room for improvement in enhancing the performance of NAND flash memory. Summary of the Invention

[0004] In view of the above, embodiments of this application provide a memory system, its operation method, and a storage medium.

[0005] According to a first aspect of the embodiments of this application, a memory system is provided, comprising: a memory device; and a memory controller coupled to the memory device and configured to: in response to a power failure during a first programming operation, encode data to be written corresponding to the first programming operation to obtain encoded data; write the encoded data into the memory device; wherein the data to be written is the data to be written into the memory device during the first programming operation; the data volume of the encoded data is less than the data volume of the data to be written; and in response to a power-on after the power failure, decode the acquired encoded data and the data already written corresponding to the first programming operation to obtain at least a portion of error recovery data corresponding to the data already written.

[0006] In some embodiments, the memory device includes a plurality of memory cells with N bits each, wherein the N bits of the memory cells correspond to N pages of data, and N is an integer greater than 2; the data to be written includes data to be written to the N pages; the memory controller is specifically configured to perform logical operations on the data of every two pages to be written to obtain the encoded data.

[0007] In some embodiments, the ratio of the amount of data to be written into N pages to the amount of data of the encoded data is N:N-1.

[0008] In some embodiments, the memory controller is specifically configured to: perform OR or AND operations on the data of every two pages to be written to N pages to obtain the encoded data; and perform OR and AND operations on the encoded data and the written data to obtain the at least partial error recovery data.

[0009] In some embodiments, the memory controller includes an error correction encoding module and an error correction decoding module; the memory controller is configured to: disable the error correction encoding module before writing the encoded data into the memory device; and disable the error correction decoding module after retrieving the encoded data from the memory device.

[0010] In some embodiments, the memory device includes a plurality of memory cells with N bits of storage, where N is an integer greater than 2; the memory device includes a first memory area and a second memory area; the memory cells in the first memory area read or write one bit of data in a first mode, and the memory cells in the second memory area read or write the N bits of data in a second mode; the memory controller is configured to: write the encoded data into the memory device using the first mode; and control the memory device to read the encoded data using the first mode before retrieving the encoded data from the memory device.

[0011] In some embodiments, the memory controller is further configured to control the memory device to re-execute the programming operation using the error recovery data.

[0012] In some embodiments, the memory device includes a plurality of memory cells, which are programmed into an intermediate memory state after the first programming operation is performed, and the data in the intermediate memory state is programmed into a target memory state after the second programming operation is performed; the threshold voltage distribution width of the intermediate memory state is greater than the threshold voltage distribution width of the target memory state.

[0013] In some embodiments, the memory controller is configured to: obtain the data to be written from the memory device before encoding the data to be written; and obtain the encoded data and the written data from the memory device before decoding the encoded data and the written data.

[0014] In some embodiments, the memory device includes a page cache; the memory controller includes a cache; the memory controller is configured to: retrieve raw data to be written from the cache before retrieving the data to be written; and send the raw data to be written to the page cache, in which the data to be written corresponding to the first programming operation is generated.

[0015] In some embodiments, the memory controller is configured to: acquire a target reference voltage corresponding to a first programming operation before acquiring the written data; and control the memory device to perform a read operation on the written data using the target reference voltage.

[0016] In some embodiments, the memory controller is configured to: acquire M flip results corresponding to at least one codeword formed by a preset number of memory cells under M reference read voltages; the flip result includes the number of bits that flipped in two read results of at least one codeword under a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; acquire a predicted valley voltage based on the M flip results and the M reference read voltages, combined with a preset function model; the preset function model represents the relationship between the flip results and the reference read voltages; all M flip results are within a preset interval; and determine the target reference voltage based on the predicted valley voltage.

[0017] In some embodiments, the preset function model includes a quadratic function model, which includes the following functional relationships:

[0018] y = a(x + b) 2 +c

[0019] Wherein, y is the flipping result, x is the reference reading voltage, b is used to characterize the prediction parameter, a is the first parameter, and c is the second parameter.

[0020] According to a second aspect of the embodiments of this application, an operation method for a memory system is provided, comprising: in response to a power failure during a first programming operation, encoding data to be written corresponding to the first programming operation to obtain encoded data; writing the encoded data into a memory device of the memory system; wherein the data to be written is the data to be written into the memory device during the first programming operation; the data volume of the encoded data is less than the data volume of the data to be written; and in response to a power-on after the power failure, decoding the acquired encoded data and the data already written corresponding to the first programming operation to obtain at least a portion of error recovery data corresponding to the data already written.

[0021] In some embodiments, the memory device includes a plurality of memory cells with N bits each, wherein the N bits of the memory cells correspond to N pages of data, and N is an integer greater than 2; the data to be written includes data to be written to the N pages; the encoding process of the data to be written to the memory device corresponding to the first programming operation includes: performing logical operations on the data of every two pages to be written to obtain the encoded data.

[0022] In some embodiments, the ratio of the amount of data to be written into N pages to the amount of data of the encoded data is N:N-1.

[0023] In some embodiments, performing logical operations on the data of every two pages to be written to N pages to obtain the encoded data includes: performing OR or AND logical operations on the data of every two pages to be written to N pages to obtain the encoded data; and performing decoding processing on the encoded data obtained from the memory device and the written data corresponding to the first programming operation includes: performing OR and AND logical operations on the encoded data and the written data to obtain the at least partial error recovery data.

[0024] In some embodiments, the method further includes: disabling an error correction encoding module in the memory controller of the memory system before writing the encoded data into the memory device; and disabling an error correction decoding module in the memory controller after obtaining the encoded data from the memory device.

[0025] In some embodiments, the memory device includes a plurality of memory cells with N bits of storage, where N is an integer greater than 2; the memory device includes a first memory area and a second memory area; the memory cells in the first memory area read or write one bit of data in a first mode, and the memory cells in the second memory area read or write the N bits of data in a second mode; writing the encoded data into the memory device of the memory system includes: writing the encoded data into the memory device using the first mode; the method further includes: controlling the memory device to read the encoded data using the first mode before retrieving the encoded data from the memory device.

[0026] In some embodiments, the method further includes controlling the memory device to re-execute the programming operation using the error recovery data.

[0027] In some embodiments, the memory device includes a plurality of memory cells, which are programmed into an intermediate memory state after the first programming operation is performed, and the data in the intermediate memory state is programmed into a target memory state after the second programming operation is performed; the threshold voltage distribution width of the intermediate memory state is greater than the threshold voltage distribution width of the target memory state.

[0028] In some embodiments, the method further includes: obtaining the data to be written from the memory device before encoding the data to be written; and obtaining the encoded data and the written data from the memory device before decoding the encoded data and the written data.

[0029] In some embodiments, the method further includes: obtaining raw data to be written from a cache of the memory controller of the memory system before obtaining the data to be written; and sending the raw data to be written to a page cache of the memory device, wherein data to be written corresponding to the first programming operation is generated in the page cache.

[0030] In some embodiments, the method further includes: acquiring a target reference voltage corresponding to a first programming operation before acquiring the written data; and controlling the memory device to perform a read operation on the written data using the target reference voltage.

[0031] In some embodiments, obtaining the target reference voltage corresponding to the first programming operation includes: obtaining M flip results corresponding to at least one codeword formed by a preset number of the memory cells under M reference read voltages; the flip result includes the number of bits that flipped in two read results of at least one codeword under a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; obtaining a predicted valley voltage based on the M flip results and the M reference read voltages, combined with a preset function model; the preset function model represents the relationship between the flip results and the reference read voltages; all M flip results are within a preset interval; and determining the target reference voltage based on the predicted valley voltage.

[0032] In some embodiments, the preset function model includes a quadratic function model, which includes the following functional relationships:

[0033] y = a(x + b) 2 +c

[0034] Wherein, y is the flipping result, x is the reference reading voltage, b is used to characterize the prediction parameter, a is the first parameter, and c is the second parameter.

[0035] According to a third aspect of this application, a storage medium is provided that stores executable instructions, which, when executed, implement the steps of the operation method as described in any of the second aspects.

[0036] In this embodiment, the data to be written corresponding to the first programming operation is encoded to obtain encoded data. The amount of encoded data is less than the amount of data to be written. The encoded data is written to a memory device to obtain error recovery data required to re-execute the programming operation when power is restored after a power outage. Thus, on the one hand, by reducing the amount of data written to the memory device during power-down protection, the demand for capacitor capacity is effectively reduced. On the other hand, upon power restoration after a power outage, by decoding the encoded data and the data already written corresponding to the first programming operation, at least some error recovery data is obtained. This ensures the data integrity of the first programming operation in the event of a power outage and reduces the risk of overall programming operation failure, thereby improving the reliability of the programming operation. Attached Figure Description

[0037] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0038] Figure 1 A schematic diagram of an exemplary system with a memory system provided in an embodiment of this application;

[0039] Figure 2A A schematic diagram of an exemplary memory card with a memory system provided in an embodiment of this application;

[0040] Figure 2B A schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of this application;

[0041] Figure 3 A schematic diagram of an exemplary memory including peripheral circuitry provided for an embodiment of this application;

[0042] Figure 4 A cross-sectional schematic diagram of a memory cell array including NAND-type memory strings provided for an embodiment of this application;

[0043] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry, provided for an embodiment of this application;

[0044] Figure 6AThis is a schematic diagram of the threshold voltage distribution of a QLC memory cell after performing a first programming operation, according to an embodiment of this application.

[0045] Figure 6B This is a schematic diagram of the threshold voltage distribution of a QLC memory cell after performing a second programming operation, provided in an embodiment of this application.

[0046] Figure 7 This is a schematic diagram of the composition structure of an exemplary system with a memory system provided in an embodiment of this application;

[0047] Figure 8 A schematic diagram of the threshold voltage distribution corresponding to a memory cell with 4 memory bits is provided for an embodiment of this application;

[0048] Figure 9 This is a schematic diagram of the threshold voltage distribution of the storage cell when obtaining the flip result, provided in an embodiment of this application.

[0049] Figure 10 A schematic diagram of a preset function model provided in an embodiment of this application;

[0050] Figure 11 A schematic diagram illustrating the determination of a preset interval according to an embodiment of this application;

[0051] Figure 12 A schematic diagram of obtaining the reference read voltage provided in the embodiments of this application. Figure 1 ;

[0052] Figure 13 Schematic diagram 2 for obtaining the reference read voltage as provided in the embodiments of this application;

[0053] Figure 14 A schematic diagram of obtaining the reference read voltage provided in the embodiments of this application. Figure 3 ;

[0054] Figure 15 A schematic diagram of obtaining the reference read voltage provided in the embodiments of this application. Figure 4 ;

[0055] Figure 16 Flowchart of an operation method for a memory system provided in an embodiment of this application Figure 1 ;

[0056] Figure 17 A second flowchart illustrating an operation method of a memory system provided in an embodiment of this application;

[0057] Figure 18 This is a schematic diagram of the composition structure of a storage medium provided in an embodiment of this application. Detailed Implementation

[0058] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0059] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0060] Furthermore, the accompanying drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0061] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0063] The memory devices in the embodiments of this application include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0064] Figure 1A block diagram of an exemplary system 100 having a memory device according to some aspects of this application is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0065] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0066] In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment in a solid state disk (SSD) or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0067] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory device 104.

[0068] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0069] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0070] In such Figure 2AIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0071] In such Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0072] Figure 3 A schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of this application is shown. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0073] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell, TLC), four bits per cell (also referred to as a quad-level cell, QLC), five bits per cell (also referred to as a penta-level cell, PLC), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0074] It should be noted that the storage state mentioned here is the same as the storage state of the storage cell in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has two storage states (i.e., two memory states), which include one programming state and one erase state. Another example is an MLC type storage cell with four storage states, including one erase state and three programming states. Yet another example is a TLC type storage cell with eight storage states, including one erase state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, including one erase state and fifteen programming states.

[0075] like Figure 3As shown, each memory string 308 may include a lower selection transistor (BSG) 310 (also known as a source-side selection transistor) at its source end and an upper selection transistor (TSG) 312 (also known as a drain-side selection transistor) at its drain end. BSG 310 and TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0076] like Figure 3 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some implementations, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0077] refer to Figure 3 Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0078] Figure 4 A cross-sectional schematic diagram of an exemplary memory cell array 301, including a memory string 308 exemplified by NAND, is shown according to some aspects of this application. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0079] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0080] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0081] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0082] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0083] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory cell array 301 (write data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0084] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0085] Control logic 512 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0086] In some implementations, when performing programming operations on the memory cells in the memory cell array 301, multiple programming operations can be used to improve read margin. Taking a QLC-type memory cell in the memory cell array 301 as an example, when performing two programming operations on the QLC using a 16-16 scheme, after performing the first programming operation on the QLC memory cell, the following can be formed: Figure 6A The threshold voltage distribution width is shown. Further, as... Figure 6B As shown, for Figure 6A After a QLC memory cell that has already undergone the first programming operation performs a second programming operation, the width of the resulting threshold voltage distribution can be finely narrowed. Therefore, the first programming operation can be called a coarse programming operation, and the second programming operation can be called a fine programming operation.

[0087] For example, a first programming operation or a second programming operation can be performed on the QLC memory cell based on Incremental Step Pulse Program (ISPP). For instance, by controlling the step size of the ISPP, the QLC memory cell can be controlled to reach a predetermined threshold voltage range after performing the first programming operation and the second programming operation, respectively. For example, a first verification voltage Vvfy' can be used to verify that the QLC memory cell reaches the target threshold voltage range P1' after the first programming operation, and a second verification voltage Vvfy can be used to verify that the QLC memory cell reaches the target threshold voltage range P1 after the second programming operation. Optionally, the first verification voltage Vvfy' is less than the second verification voltage Vvfy.

[0088] The two programming operations described above, employing a coarse-to-fine programming approach, achieve high-precision voltage regulation, reduce programming errors, and improve data storage reliability. However, in the first programming (coarse programming) stage, the threshold voltage distribution of the memory cells is relatively wide (e.g., Figure 6A As shown in the diagram, accurately reading the coarse programming data written to the storage cell during the first programming operation phase is quite difficult. Furthermore, in data retention scenarios, the threshold voltage of the storage cell may shift over time or due to environmental changes, further increasing the difficulty of accurately reading the coarse programming data. If a power outage occurs during the first programming operation phase, data may not be written in time, leading to data loss.

[0089] To address this issue, power loss protection (PLP) is typically provided using capacitors. Because the amount of data to be written is large and the write time is long, large-capacity capacitors are needed to provide a longer protection time, ensuring that all data is completely written to the NAND flash memory during power loss, thus preventing data loss. However, large-capacity capacitors not only increase physical size and cost but also pose challenges to the overall design of memory devices (referring to memory infrastructure, memory systems, etc.). Therefore, improving the reliability of memory devices without increasing product complexity has become a pressing issue.

[0090] In view of one or more of the above-mentioned problems, in a first aspect, embodiments of this application propose a memory system. For example... Figure 7 As shown, the memory system 102 includes: a memory device 104; and a memory controller 106, coupled to the memory device 104 and configured to: in response to a power failure during a first programming operation, encode the data to be written corresponding to the first programming operation to obtain encoded data; write the encoded data into the memory device; wherein the data to be written is the data to be written into the memory device during the first programming operation; the amount of encoded data is less than the amount of data to be written; and in response to a power-on after the power failure, decode the acquired encoded data and the data already written corresponding to the first programming operation to obtain at least a portion of error recovery data corresponding to the data already written.

[0091] In some embodiments, the memory device includes a plurality of memory cells, which are programmed into an intermediate memory state after the first programming operation is performed, and the data in the intermediate memory state is programmed into a target memory state after the second programming operation is performed; the threshold voltage distribution width of the intermediate memory state is greater than the threshold voltage distribution width of the target memory state.

[0092] Here, the first programming operation can be called the coarse programming operation, and the second programming operation can be called the fine programming operation. Taking a QLC memory cell as an example, the threshold voltage distribution width of the QLC memory cell after the first programming operation is as follows: Figure 6A As shown, the threshold voltage distribution width of the QLC memory cell after performing the second programming operation following the first programming operation is as follows: Figure 6B As shown. For example, as Figure 6A The threshold voltage distribution width of the intermediate storage state shown is greater than Figure 6B The threshold voltage distribution width of the target storage state is shown.

[0093] In some embodiments, the memory controller is further configured to control the memory device to re-execute the programming operation using the error recovery data.

[0094] In this embodiment, the data to be written corresponding to the first programming operation is encoded to obtain encoded data. The amount of encoded data is less than the amount of data to be written. The encoded data is written to a memory device to obtain error recovery data required to re-execute the programming operation when power is restored after a power outage. Thus, on the one hand, by reducing the amount of data written to the memory device during power-down protection, the demand for capacitor capacity is effectively reduced. On the other hand, upon power restoration after a power outage, by decoding the encoded data and the data already written corresponding to the first programming operation, at least some error recovery data is obtained. This ensures the data integrity of the first programming operation in the event of a power outage and reduces the risk of overall programming operation failure, thereby improving the reliability of the programming operation.

[0095] Figure 7 This is a schematic diagram of the composition structure of an exemplary system with a memory system provided in an embodiment of this application. For example... Figure 7 As shown, the memory controller 106 is coupled to the memory device 104 and is used to control the memory device 104 to perform read, write, erase, and other operations. The memory controller 106 may include an interface 1060 and a processor 1063; wherein, the interface 1060 is used for data interaction with external devices, and the processor 1063 is used for overall control of the memory controller 106 and the memory device 104.

[0096] In some specific embodiments, interface 1060 may include host interface (I / F) 1061 and memory interface (I / F) 1062; wherein, host interface 1061 is a connection interface between host 108 and memory controller 106, and host interface 1061 allows the host and memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. Memory interface 1062 is a connection interface between memory controller 106 and memory device 104, and memory interface 1062 is used to implement data transfer between memory controller 106 and memory device 104.

[0097] In some specific embodiments, the processor 1063 may include one or more units with logical operation capabilities, such as a central processing unit (CPU) and / or a microcontroller unit (MCU).

[0098] In some embodiments, the memory controller 106 may further include an error correction module 1064, a cache 1067, a garbage collection (GC) module 1068, and a bus 1069. The error correction module 1064 may further include an error correction encoding module 1065 and an error correction decoding module 1066; the error correction encoding module 1065 is used to encode the data to be stored to obtain verification data, and the error correction decoding module 1066 is used to decode the verification data to detect and correct possible erroneous data during data transmission. The cache 1067 is used to cache data. In some specific embodiments, the cache 1067 may be a volatile memory device with relatively fast read / write speeds, such as Static Random-Access Memory (SRAM) and / or Dynamic Random-Access Memory (DRAM). The garbage collection module 1068 is used to read out valid data from some storage blocks, rewrite it, and then mark these storage blocks to obtain new spare storage blocks after the storage space of the memory device reaches a certain threshold.

[0099] In some embodiments, the memory controller 106 may also include other modules not listed, such as a wear leveling module, a bad block management module, an SLC cache module, etc.

[0100] In some embodiments, the memory device may include NAND flash memory. The structure of the memory device can be referred to the foregoing. Figure 3 This will not be elaborated upon here.

[0101] Generally, power outages are divided into two types: normal power outages and abnormal power outages. A normal power outage occurs when, before the power outage, the host 108 notifies the memory system 102 via a command. The memory system 102 then performs the following tasks: (1) flushing the cached user data in the register to the memory device 104; (2) flushing the mapping table to the memory device 104; and (3) writing the block information of the memory device to the memory device 104 (e.g., which memory device block is being written to, its location within that block, which memory device blocks have already been written to, and which memory device blocks are invalid). The host 108 will only truly stop supplying power to the memory system 102 after the memory system 102 has completed these tasks. Therefore, a normal power outage does not result in data loss. After power is restored, the memory system 102 only needs to reload the relevant information saved before the power outage and can continue operating from its previous state. An abnormal power outage occurs when the memory system 102 is powered off without receiving a power outage notification from the host 108; or when it receives a power outage notification from the host 108 but has not had time to process the aforementioned events before being powered off. Abnormal power outages can be caused by power supply failures, sudden power outages, or battery depletion, and can easily lead to data loss or corruption.

[0102] It should be noted that the power outage in this application embodiment refers to an abnormal power outage.

[0103] In some embodiments, the memory device includes a plurality of memory cells with N bits each, wherein the N bits of the memory cells correspond to N pages of data, and N is an integer greater than 2; the data to be written includes data to be written to the N pages; the memory controller is specifically configured to perform logical operations on the data of every two pages to be written to obtain the encoded data.

[0104] In some embodiments, each memory block may be coupled with multiple word lines, and multiple memory cells coupled to each word line form one or more pages, wherein the number of pages is related to the number of bits of memory contained in the memory cells. For example, multiple MLCs coupled to each word line form two pages, and multiple TLCs coupled to each word line form three pages. In some specific embodiments, multiple QLC memory cells (with four bits of memory) coupled to each word line form four pages.

[0105] For example, the memory device includes a plurality of memory cells with four storage bits, the four storage bits of the memory cells corresponding to four pages of data; the data to be written includes the data to be written to the four pages; the memory controller is specifically configured to: perform logical operations on the data of every two pages to be written to obtain encoded data.

[0106] For example, when the storage bits of a memory cell include four bits, the corresponding storage states include states 0 to 15, refer to... Figure 8 The 16 states are: state 0 (also known as the erase state) P0, state 1 (also known as the first storage state) P1, state 2 (also known as the second storage state) P2...state 15 (also known as the 15th storage state) P15, and the binary data corresponding to these 16 states are 1111, 0111, 0110...1110, respectively. Accordingly, the memory device includes four pages: the lower page (LP), the middle page (MP), the upper page (UP), and the extra page (XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, middle page, upper page, and extra page, respectively.

[0107] by Figure 8 Taking the shown memory cell as an example, a four-bit memory cell uses 15 levels of read voltage ( Figure 8 The reading voltages L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15 shown in the figure read their four-bit sixteen-state stored data.

[0108] For example, each page corresponds to multiple levels of read voltage, such as Figure 8 As shown, the binary data corresponding to the next page is 1100000011111100, and reading the next page requires the corresponding second-level reading voltage L2, eighth-level reading voltage L8, and fourteenth-level reading voltage L14. The binary data corresponding to the middle page is 1110000110000111, and reading the middle page requires the corresponding third-level reading voltage L3, seventh-level reading voltage L7, ninth-level reading voltage L9, and thirteenth-level reading voltage L13. The binary data corresponding to the previous page is 1111100000110001, and reading the previous page requires the corresponding fifth-level reading voltage L5, tenth-level reading voltage L10, twelfth-level reading voltage L12, and fifteenth-level reading voltage L15. The binary data corresponding to the extra page is 1000110000011111, and reading the extra page requires the corresponding first-level reading voltage L1, fourth-level reading voltage L4, sixth-level reading voltage L6, and eleventh-level reading voltage L11.

[0109] In some embodiments, the ratio of the amount of data to be written to N pages to the amount of data encoded is N:N-1.

[0110] Taking N=4 as an example, the ratio of the amount of data to be written to the four pages to the amount of encoded data is 4:3.

[0111] In some specific implementations, the memory controller is specifically configured to perform logical operations on the data of every two pages among the four pages to be written (LP, MP, UP, and XP) to obtain encoded data. For example, logical operations are performed on the data to be written to LP and the data to be written to MP to obtain first encoded data Parity1; logical operations are performed on the data to be written to MP and the data to be written to UP to obtain second encoded data Parity2; and logical operations are performed on the data to be written to UP and the data to be written to XP to obtain third encoded data Parity3. It can be understood that after the logical operations on the data in the four pages to be written, three encoded data (first encoded data Parity1, second encoded data Parity2, and third encoded data Parity3) are obtained.

[0112] In other embodiments, the data to be written to LP and the data to be written to MP are processed by logical operations to obtain first encoded data, the data to be written to LP and the data to be written to UP are processed by logical operations to obtain second encoded data, and the data to be written to UP and the data to be written to XP are processed by logical operations to obtain third encoded data.

[0113] In some embodiments, taking QLC as an example, the amount of data to be written to each page is 16k bytes, and the amount of data for each encoded data is 16k bytes. Therefore, the ratio of the amount of data to be written to the four pages to the amount of encoded data is (4×16k):(3×16k)=4:3.

[0114] It should be noted that the amount of data to be written to each page is merely an example, and this should not unduly limit the scope of protection of this disclosure.

[0115] In some embodiments, the logical operation can be an OR logical operation or an AND logical operation.

[0116] In some embodiments, combined with Figure 5 and Figure 7 The memory device 104 includes a page cache (see [link]). Figure 5 Page cache 504 shown); memory controller 106 includes cache 1067 (see page cache 504 shown); Figure 7The memory controller 106 is configured to: obtain the original data to be written from the cache 1067 before obtaining the data to be written; and send the original data to be written to the page cache 504, in which the data to be written corresponding to the first programming operation is generated.

[0117] Here, we take QLC as an example for explanation. The register 1067 of the memory controller 106 stores the original data to be written. The original data to be written corresponding to LP is denoted as LP0, the original data to be written corresponding to MP is denoted as MP0, the original data to be written corresponding to UP is denoted as UP0, and the original data to be written corresponding to XP is denoted as XP0.

[0118] For example, the memory controller 106 is configured to: obtain original data to be written, LP0, MP0, UP0, and XP0, from the cache 1067 before obtaining the data to be written; send the original data to be written, LP0, MP0, UP0, and XP0, to the page cache 504; and read the original data to be written stored in the page cache 504. That is, the data to be written obtained by the memory controller in the above process refers to the read results LP0_r, MP0_r, UP0_r, and XP0_r corresponding to the original data to be written, read from the page cache 504 by the memory controller. By sending the original data to be written to the page cache and then reading the read results corresponding to the original data to be written from the page cache as the data to be written, the process of writing original data to be written to the storage cells of the memory device and reading the read results corresponding to the original data to be written from the storage cells of the memory device as coarse programming data is simulated.

[0119] In some embodiments, the memory controller is configured to: obtain the data to be written from the memory device before encoding the data to be written. For example, taking a QLC as an example, the memory controller is configured to: obtain data (LP0_r, MP0_r, UP0_r, and XP0_r) to be written from the page cache of the memory device, and perform logical operations on the data (LP0_r, MP0_r, UP0_r, and XP0_r) to obtain three encoded data (first encoded data Parity1, second encoded data Parity2, and third encoded data Parity3).

[0120] By sending and reading raw data to be written to the page buffer, the complete process of writing and reading data into the memory cell of the memory device can be simulated. It is possible to simulate whether errors or data corruption occur during the writing and reading process. The accuracy is higher when the data to be written obtained by the memory controller represents the reading result corresponding to the data actually written to the memory device in the first programming operation. In addition, the speed of writing and reading data into the page buffer is fast and the power consumption is very low, so it will not occupy too many resources for power-down protection.

[0121] In some embodiments, the memory controller includes an error correction encoding module and an error correction decoding module; the memory controller is configured to: disable the error correction encoding module before writing the encoded data into the memory device; and disable the error correction decoding module after retrieving the encoded data from the memory device.

[0122] In some implementations, such as Figure 7 As shown, the memory controller 106 includes an error correction encoding module 1065 and an error correction decoding module 1066. The error correction encoding module 1065 is used to encode the data to be stored to obtain verification data, and the error correction decoding module 1066 is used to decode the verification data to detect and correct possible erroneous data during data transmission.

[0123] For example, the memory controller 106 is configured to disable the error correction encoding module 1065 before writing the encoded data into the memory device 104. Since the algorithm used by the error correction encoding module (e.g., ECC error correction algorithm) is different from the principle of the logical operation used to process the data to be written into the encoded data, re-encoding the encoded data generated by the logical operation may damage the data structure of the encoded data originally intended for obtaining error recovery data, potentially leading to the inability to successfully obtain the error recovery data required to re-execute the programming operation upon power-up after a power outage. To ensure the accuracy of the encoded data when used to obtain the error recovery data required to re-execute the programming operation upon power-up after a power outage, error correction encoding is not required here.

[0124] In some embodiments, the memory controller 106 is configured to disable the error correction decoding module 1066 after retrieving encoded data from the memory device 104. Similarly, to ensure the accuracy of the encoded data when retrieving error recovery data required to re-execute the programming operation upon power-up after a power failure, error correction decoding of the encoded data is not required here.

[0125] In some embodiments, the memory device includes a plurality of memory cells with a storage bit width of N bits, where N is an integer greater than 2; such as Figure 7As shown, the memory device 104 includes a first storage area 1041 and a second storage area 1042; the storage cells in the first storage area 1041 read or write one bit of data in a first mode, and the storage cells in the second storage area 1042 read or write the N bits of data in a second mode; the memory controller 106 is configured to: write the encoded data into the memory device 104 using the first mode; and control the memory device 104 to read the encoded data using the first mode before retrieving the encoded data from the memory device 104.

[0126] In some embodiments, the first mode can be understood as Single Level Read (SLR) or Single Level Write (SLW). The second mode can be understood as Multi-Level Read (MLR) or Multi-Level Write (MLW).

[0127] For example, in single-level write mode, a write operation writes one bit of stored data to a page. In single-level read mode, a read operation reads one bit of stored data from a page. For example, in read... Figure 8 When reading the middle page MP as shown, the first-level read voltage between P6 and P7 is used to read whether the corresponding bit of stored data in the middle page MP is 0 or 1.

[0128] In some implementations, the memory controller 106 is configured to write encoded data into the memory device 104 in a single-level write mode.

[0129] In some implementations, the memory controller 106 is configured to control the memory device 104 to read the encoded data in a single-level read mode before retrieving the encoded data from the memory device 104.

[0130] In this embodiment, the first mode is fast and simple to operate. When power is lost, using the first mode to write the encoded data to the memory device ensures timely and secure storage of the encoded data, reducing the risk of data loss. Upon power-up after a power outage, controlling the memory device to read the encoded data in the first mode before retrieving it from the memory device helps to accelerate the acquisition of error recovery data required for re-executing the programming operation, reducing the overall programming time.

[0131] Furthermore, by dividing the storage area of ​​the memory device into a first storage area and a second storage area, wherein the first storage area is used to store coded data with high reliability requirements and the second storage area is used to store regular data with high capacity requirements, and by using different modes (first mode and second mode) for write and read operations in the first and second storage areas, the storage space can be fully utilized and the performance of the storage device can be effectively optimized.

[0132] In some embodiments, the encoded data and the written data are obtained from the memory device before decoding the encoded data and the written data.

[0133] In some embodiments, the memory controller is configured to: acquire a target reference voltage corresponding to a first programming operation before acquiring the written data; and control the memory device to perform a read operation on the written data using the target reference voltage.

[0134] It should be noted that the target reference voltage here is the optimal read voltage found through the method in the embodiments of this application. Using the target reference voltage allows for more accurate reading of the written data, improving the accuracy of the read result (written data). The specific method for obtaining the target reference voltage will be further described later.

[0135] In some embodiments, the memory controller is specifically configured to: perform OR or AND operations on the data of every two pages to be written to N pages to obtain the encoded data; and perform OR and AND operations on the encoded data and the written data to obtain the at least partial error recovery data.

[0136] The following will use QLC as an example to explain in detail the specific operation process of obtaining encoded data and obtaining at least partial error recovery based on the encoded data in this embodiment. Specifically:

[0137] Step a1: When a power failure occurs during the first programming operation, the original data to be written, LP0, MP0, UP0 and XP0, are retrieved from the buffer. LP0 represents the original data to be written corresponding to LP, MP0 represents the original data to be written corresponding to MP, UP0 represents the original data to be written corresponding to UP, and XP0 represents the original data to be written corresponding to XP.

[0138] Step a2: Send the original data to be written, LP0, MP0, UP0 and XP0, to the page cache of the memory device.

[0139] Step a3: Read the original data to be written, LP0, MP0, UP0, and XP0, from the page cache of the memory device to obtain the read results LP0_r, MP0_r, UP0_r, and XP0_r corresponding to the original data to be written, LP0_r, MP0_r, UP0_r, and XP0_r. Here, LP0_r, MP0_r, UP0_r, and XP0_r are also referred to as data to be written in this application. Specifically, LP0_r represents the data to be written corresponding to LP, MP_r represents the data to be written corresponding to MP, UP_r represents the data to be written corresponding to UP, and XP_r represents the data to be written corresponding to XP.

[0140] Step a4: Perform an AND operation on every two pages of data to be written, including LP0_r, MP0_r, UP0_r, and XP0_r, to obtain encoded data. Specifically, perform an AND operation on LP0_r and MP0_r to obtain the first encoded data Parity1, perform an AND operation on MP0_r and LP0_r to obtain the second encoded data Parity2, and perform an AND operation on LP0_r and XP0_r to obtain the third encoded data Parity3.

[0141] Step a5: Using the first mode, write the encoded data (first encoded data Parity1, second encoded data Parity2, and third encoded data Parity3) into the memory device. It should be noted that the error correction encoding module is disabled before writing the encoded data into the memory device. 。

[0142] Step a6: Upon power-on after a power outage, retrieve the encoded data and written data from the memory device.

[0143] Specifically, on the one hand, the control memory device reads encoded data (first encoded data Parity1, second encoded data Parity2, and third encoded data Parity3) using a first mode, obtaining read results Parity1_r, second encoded data Parity2_r, and third encoded data Parity3_r corresponding to the first encoded data Parity1, second encoded data Parity2, and third encoded data Parity3, respectively. It should be noted that after obtaining the encoded data from the memory device, the error correction decoding module is disabled.

[0144] On the other hand, the target reference voltage corresponding to the first programming operation is obtained; and the memory device is controlled to perform a read operation on the written data using the target reference voltage, and the read results LP_raw, MP_raw, UP_raw and XP_raw corresponding to the written data are obtained, wherein LP_raw represents the read result corresponding to the written data corresponding to LP, MP_raw represents the read result corresponding to the written data corresponding to MP, UP_raw represents the read result corresponding to the written data corresponding to UP, and XP_raw represents the read result corresponding to the written data corresponding to XP.

[0145] Step a7: Decode the acquired encoded data and the written data corresponding to the first programming operation to obtain at least part of the error recovery data corresponding to the written data.

[0146] For example, the read results Parity1_r and LP_raw and MP_raw corresponding to the acquired first encoded data Parity1 are processed by OR logic operation to complete the first step of recovery (flipping the detected 0 to 1), and the first error recovery data LP1 and the second error recovery data MP1 are obtained respectively.

[0147] For example, the read results Parity2_r and MP1 and UPraw corresponding to the acquired second encoded data Parity2 are processed by OR logic operation to complete the second step of recovery (flipping the detected 0 to 1), and the third error recovery data MP2 and the fourth error recovery data UP1 are obtained respectively.

[0148] For example, the read results Parity3_r and UP1 and XPraw corresponding to the acquired third encoded data Parity3 are processed by OR logic operation to complete the third step of recovery (flipping the detected 0 to 1), and the fifth error recovery data UP2 and the sixth error recovery data XP1 are obtained respectively.

[0149] For example, after performing a non-logical operation on the reading result Parity2_r corresponding to the acquired second encoded data Parity2, a logical AND operation is performed with the fifth error recovery data UP2 to obtain the first intermediate data. After performing a non-logical operation on the first intermediate data, a logical AND operation is performed with the third error recovery data MP2 to obtain the seventh error recovery data MP3.

[0150] For example, after performing a non-logical operation on the reading result Parity2_r corresponding to the acquired second encoded data Parity2, a logical AND operation is performed with the seventh error recovery data MP3 to obtain the second intermediate data. After performing a non-logical operation on the second intermediate data, a logical AND operation is performed with the fifth error recovery data UP2 to obtain the eighth error recovery data UP3.

[0151] For example, after performing a non-logical operation on the reading result Parity1_r corresponding to the first encoded data Parity1, a logical AND operation is performed with the seventh error recovery data MP3 to obtain the third intermediate data. After performing a non-logical operation on the third intermediate data, a logical AND operation is performed with the first error recovery data LP1 to obtain the ninth error recovery data LP2.

[0152] For example, after performing a non-logical operation on the reading result Parity3_r corresponding to the acquired third encoded data Parity3, a logical AND operation is performed with the eighth error recovery data UP3 to obtain the fourth intermediate data. After performing a non-logical operation on the fourth intermediate data, a logical AND operation is performed with the sixth error recovery data XP1 to obtain the tenth error recovery data XP2.

[0153] At this point, the decoding process for the acquired encoded data and the written data corresponding to the first programming operation is complete. Among them, the ninth error recovery data LP2 is the error recovery data of the written data corresponding to the first programming operation and LP, the seventh error recovery data MP3 is the error recovery data of the written data corresponding to the first programming operation and MP, the eighth error recovery data UP3 is the error recovery data of the written data corresponding to the first programming operation and UP, and the tenth error recovery data XP2 is the error recovery data of the written data corresponding to the first programming operation and XP.

[0154] It should be noted that there is a corresponding relationship between the logical operation processing method used to obtain the encoded data through encoding and the logical operation processing method used to decode the acquired encoded data and the written data. This is so that data recovery can be performed by decoding the acquired encoded data when power is restored after a power outage.

[0155] In some embodiments, the memory controller is further configured to control the memory device to re-execute the programming operation using the error recovery data.

[0156] In some embodiments, by decoding the encoded data and the written data corresponding to the first programming operation to obtain at least some error recovery data, the data integrity in the event of a power outage during the first programming operation can be ensured. Re-executing the programming operation using the error recovery data can reduce the risk of overall programming operation failure and improve the reliability of the programming operation.

[0157] It should be noted that the execution entity of the specific implementation process of each step in steps a1 to a7 can be the memory controller, and more specifically, the execution entity of the specific implementation process of each step in steps a1 to a7 can be the processor in the memory controller.

[0158] The following section describes the specific method for obtaining the target reference voltage.

[0159] In some embodiments, the memory controller is configured to: acquire M flip results corresponding to at least one codeword formed by a preset number of memory cells under M reference read voltages; the flip result includes the number of bits that flipped in two read results of at least one codeword under a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; acquire a predicted valley voltage based on the M flip results and the M reference read voltages, combined with a preset function model; the preset function model represents the relationship between the flip results and the reference read voltages; all M flip results are within a preset interval; and determine the target reference voltage based on the predicted valley voltage.

[0160] It should be noted that the predicted reference voltage here can be directly used as the target reference voltage to perform the read operation on the data to be read, or it can be obtained after further processing. The specific method for obtaining the predicted reference voltage will be described in more detail later.

[0161] The process of obtaining the target reference voltage based on the preset function model and its first parameter will be described in detail below.

[0162] First, we will explain the meaning of the flipped result and the specific methods for obtaining the flipped result.

[0163] Here, the flip result represents the number of bits that are flipped in the two read results under the first read voltage and the second read voltage of at least one codeword to be read.

[0164] In some embodiments, a predetermined number of storage units form a codeword (CW). A page includes one or more codewords. Exemplarily, a codeword contains the same number of storage units as a single error correction encoding or decoding operation. In some specific embodiments, the number of storage units in a codeword may be less than or equal to the number of storage units coupled to a page, such as a codeword containing 1 / 4 of the number of storage units coupled to a page.

[0165] In general, different memory systems may choose different codeword sizes to meet their performance, reliability, and storage requirements. Different types of memory devices (e.g., MLC, TLC, or QLC) can store different numbers of bits per memory cell. Understandably, a codeword can include multiple memory cells, and the number of memory cells in a codeword can be adjusted according to specific needs. Here, the first read voltage and the second read voltage are generic concepts, and the difference between the first read voltage and the second read voltage is less than a preset voltage.

[0166] In some specific embodiments, the second read voltage is greater than the first read voltage, and the difference between the first and second read voltages is set to a range of 5mV to 20mV. For example, the difference between the first and second read voltages can be 5mV, 10mV, 15mV, or 20mV. In other specific embodiments, the second read voltage is less than the first read voltage, and the difference between the first and second read voltages is set to a range of -5mV to -20mV. For example, the difference between the first and second read voltages can be -5mV, -10mV, -15mV, or -20mV.

[0167] In some embodiments, the memory device is configured to: read at least one codeword of stored data under a first read voltage to obtain a first result; read at least one codeword of stored data under a second read voltage to obtain a second result; perform logical operations on the first result and the second result to obtain a third result; and count the number of bits in the third result that represent the second result being flipped compared to the first result to obtain the flipping result.

[0168] In some embodiments, the memory device includes: a first latch, a second latch, and a third latch; the first latch is configured to store a first result; the second latch is configured to store a second result; and the third latch is configured to store a third result.

[0169] Here, the first and second reading voltages are correlated; that is, the second reading voltage is obtained by making a third adjustment based on the first reading voltage. Therefore, the voltage difference between the first and second reading voltages is the third step size. In some specific embodiments, the range of the third step size is 5mV to 20mV; for example, the third step size can be 5mV, 10mV, 15mV, or 20mV. The preset voltage is related to the third step size and can be a voltage slightly larger than the third step size. In some specific embodiments, the range of the preset voltage is set to 6mV to 21mV; for example, the preset voltage can be 6mV, 11mV, 16mV, or 21mV. In other specific embodiments, the range of the preset voltage is set to -6mV to -21mV; for example, the preset voltage can be -6mV, -10mV, -16mV, or -21mV.

[0170] As previously mentioned, both the first reading voltage and the second reading voltage are general concepts. The target reading voltage, as well as the reading voltage obtained after the first and second adjustments to the target reading voltage, can all be referred to as the first reading voltage. The reading voltage obtained after the third adjustment to the first reading voltage can all be referred to as the second reading voltage. In other words, the first reading voltage is a general concept and can be understood as the target reading voltage or the target adjusted reading voltage (the voltage obtained after adjusting the target reading voltage with a target step size, wherein the target step size can be set to 20mV to 40mV. For example, the first step size of the first adjustment can be 20mV, 30mV, or 40mV, and the target step size can also be set to 50mV to 150mV. For example, the second step size of the second adjustment can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV).

[0171] In various embodiments of this application, at a specific voltage (e.g.) Figure 9 The flip result corresponding to the first read voltage V0 shown can be understood as: a third adjustment to a specific voltage, that is, a specific voltage and a specific voltage after the third adjustment (e.g., Figure 9 The second read voltage V1 shown has a first voltage difference ΔV1. The number of bits that flip in the two read results of at least one codeword under a certain specific voltage and under a third adjusted certain specific voltage can be used as the corresponding flip result under a certain specific voltage.

[0172] In some embodiments, the read mode of the memory device is set to a first mode before acquiring the flip result corresponding to at least one codeword at the target read voltage.

[0173] In some specific embodiments, at least one codeword of stored data is read under a first read voltage to obtain a first result; the first result is then stored in a first latch of the memory device. For example, as shown... Figure 9 As shown, at least one codeword of stored data is read under a first read voltage V0 to obtain a first result. Specifically, storage cells with threshold voltages lower than the target read voltage V0 are marked as bit 1, and storage cells with threshold voltages higher than the target read voltage V0 are marked as bit 0 to obtain the first result. The first result is then stored in a first latch of the memory device.

[0174] Next, the first read voltage is adjusted a third time to obtain a second read voltage. At least one codeword of stored data is read under this second read voltage to obtain a second result. The second result is then stored in a second latch of the memory device. For example, as... Figure 9 As shown, a third adjustment is made to the first read voltage V0, and at least one codeword of stored data is read under the adjusted second read voltage V1 to obtain a third result. Specifically, storage cells with threshold voltages lower than the second read voltage V1 are marked as bit 1, and storage cells with threshold voltages higher than the second read voltage V1 are marked as bit 0 to obtain a second result. The second result is then stored in the second latch of the memory device.

[0175] Next, logical operations are performed on the first and second results to obtain the third result; the third result is then stored in a third latch of the memory device. For example, as shown... Figure 9 As shown, the first result and the second result are XORed to obtain the third result; the third result is stored in the third latch of the memory device.

[0176] It should be noted that the XOR operation is one of the basic logical operations. In binary, if two binary numbers in the same position are the same, the result is "0"; if two binary numbers in the same position are different, the result is "1" (i.e., the same is 0, and different is 1).

[0177] Next, the number of bits in the third result that represent the flipping of the second result compared to the first result is counted to obtain the flipping result. For example, as shown... Figure 9 As shown, the part of the third result with a bit of 1 represents the number of memory cells where the threshold voltage differs between the first read voltage V0 and the second read voltage V1. In other words, the part of the third result with a bit of 1 represents the number of bits that are flipped in the two read results under the first read voltage V0 and the second read voltage V1. This number is recorded as the first result Y1 corresponding to the first read voltage V0.

[0178] In some embodiments, the preset function model is a quadratic function model, and the preset interval represents the range between a first threshold and a second threshold of the curve containing the quadratic function model; the first threshold is greater than the second threshold.

[0179] In some embodiments, the memory controller is configured to: acquire a first result corresponding to at least one codeword at a target read voltage; and, based on the fact that the first result corresponding to at least one codeword at the target read voltage is within a preset range, use the target read voltage as a reference read voltage and use the flip result within the preset range as the flip result corresponding to the reference read voltage.

[0180] In some embodiments, the memory controller is configured to: obtain prediction parameters of a quadratic function model based on M flip results and M reference read voltages, combined with the quadratic function model; the prediction parameters are the reference read voltages corresponding to the minimum flip results on the curve of the quadratic function model; obtain a predicted reference voltage based on the prediction parameters; and determine a target reference voltage based on the predicted reference voltage.

[0181] In some specific implementations, the functional relationship in the fitted preset function model includes relevant parameters. When obtaining the predicted reference voltage, the values ​​of the relevant parameters can be obtained based on the M flip results, M reference reading voltages and the functional relationship. Furthermore, the reference reading voltage corresponding to the minimum flip result on the curve where the preset function model is located can be obtained, and the reference reading voltage corresponding to the minimum flip result on the curve where the preset function model is located can be used as the predicted reference voltage.

[0182] In some embodiments, the preset function model includes a quadratic function model, which includes the following functional relationships:

[0183] y = a(x + b) 2 +c

[0184] Wherein, y is the flipping result, x is the reference reading voltage, b is used to characterize the prediction parameter, a is the first parameter, and c is the second parameter.

[0185] like Figure 10 As shown, based on the functional relationships included in the above quadratic function model, it can be seen that the extreme value of the curve containing this quadratic function model is located at the position where the axis of symmetry is x = -b, that is, at the position where the derivative of the curve containing this quadratic function model is 0. For example, when the first parameter is greater than 0, the y-value (reversed result) corresponding to x = -b is the minimum value of the curve containing this quadratic function model, and this extreme point ( Figure 10 The coordinates of point A in the diagram are (-b, c).

[0186] In some implementations, the prediction parameter is the opposite of b, meaning the prediction parameter represents the x-coordinate of the curve containing the minimum value of the quadratic function model.

[0187] like Figure 10 As shown, the axis of symmetry of the curve containing the quadratic function model (at x = -b) is offset from the y-axis (at x = 0) by -b. That is, the distance between the axis of symmetry of the curve containing the quadratic function model and the y-axis is the absolute value of b, |b|.

[0188] Here, x = 0 can be understood as the position of the default reading voltage. In this application, the term "flipping result corresponding to the default reading voltage" can be simply referred to as "default flipping result". Figure 10 The coordinates of point B shown are (0, ab). 2 +c). The default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to the moment of writing, at which point the corresponding offset value is 0. It can be understood that when the offset of the target read voltage relative to the default read voltage (x=0) is -b, the corresponding topping result under that target read voltage is the minimum value. It can be understood that using the target read voltage corresponding to the minimum topping result (equivalent to the prediction parameter here) as the prediction reference voltage, and determining the target reference voltage based on the prediction reference voltage, results in a low error rate and high reliability in the read results.

[0189] It should be noted that the target read voltage (equivalent to the prediction parameter) corresponding to the minimum value of the flip result is used as the prediction reference voltage, that is, -b is used as the prediction reference voltage. This represents the offset of the prediction reference voltage relative to the default read voltage by -b, not that the prediction reference voltage is negative. When -b is greater than 0, it means that the prediction reference voltage is offset to the right by |b| relative to the default read voltage; when -b is less than 0, it means that the prediction reference voltage is offset to the right by |b| relative to the default read voltage. In other words, the relationship between the actual voltage of the prediction reference voltage (denoted as Vpre) and the actual voltage of the default read voltage (denoted as Vdefault) is as follows:

[0190] Vpre = Vdefault + (-b)

[0191] Similarly, after determining the target reference voltage based on the predicted reference voltage, using the target reference voltage to perform a read operation on at least one codeword means using the actual voltage of the target reference voltage to perform the read operation on at least one codeword. It should be noted that when there is only one set of prediction parameters, it is directly used as the predicted reference voltage. However, when there are multiple sets of prediction parameters, the predicted reference voltage needs to be determined based on all sets of prediction parameters.

[0192] In some embodiments, such as Figure 10 As shown, the preset interval represents the range between the first threshold and the second threshold of the curve containing the quadratic function model; the first threshold (Th1) is greater than the second threshold (Th2).

[0193] Figure 11 This is a schematic diagram illustrating the determination of a preset interval according to an embodiment of this application. In some embodiments, Figure 11 The multiple solid dots shown represent a large amount of data (multiple target read voltages and multiple toggling results corresponding to the multiple target read voltages) collected through extensive experiments before the memory device leaves the factory. Figure 11 When fitting the data shown to a preset function model, the selection of data directly affects the accuracy of the resulting preset function model. For example, when the selected data has an excessively high flip value (e.g., ...), ... Figure 11 As shown in the dashed box region A1 or dashed box region A2, the solid dots in the dashed box region A1 or dashed box region A2 will result in a pre-fitted function model that does not match the actual threshold voltage distribution curve. Specifically, the pre-fitted function model obtained by selecting the solid dots in dashed box region A1 or dashed box region A2 is a quadratic function model with the opening facing downwards, which does not match the actual threshold voltage distribution curve (a quadratic function model with the opening facing upwards). When the selected data's flip result is too low (e.g., Figure 11 The error of the preset function model obtained by fitting the data (the solid dots in the dashed box area A3 shown in the figure) is too large, which causes the target reference voltage obtained according to the preset function model to deviate too much from the position of the actual reading voltage.

[0194] In some implementations, the preset range is from 50 to 200.

[0195] It should be noted that the range of the preset interval provided in the embodiments of this application is only an example. The range of the preset interval is related to the characteristics of the memory device and should not excessively limit the scope of protection of this application.

[0196] In some embodiments, the memory controller is configured to: acquire the toggle result corresponding to the at least one codeword at a target read voltage; and, based on the toggle result corresponding to the at least one codeword at the target read voltage being within the preset range, use the target read voltage as a reference read voltage; and, based on the toggle result corresponding to the at least one codeword at the target read voltage being outside the preset range, acquire at least one new target read voltage, acquire the toggle result corresponding to the at least one new target read voltage, until the toggle result corresponding to the latest target read voltage is within the preset range.

[0197] Here, the first and second parameters can be obtained when fitting a preset function model and stored in a memory device.

[0198] For example, the preset function model includes a quadratic function model, and the quadratic function model includes the following functional relation (1):

[0199] y = a(x + b) 2 +c

[0200] The first and second parameters in a functional relationship can be optimized using, but are not limited to, least squares, gradient descent, Bayesian optimization, Newton's method, and quasi-Newton methods, and the optimal first and second parameters can be stored in a memory device. Least squares is a parameter estimation method that estimates parameters by minimizing the sum of squared residuals between the actual collected data and the predicted values ​​of the quadratic function model. Gradient descent uses the parameters of the quadratic function model as the optimization objective, using gradient descent to find the parameter values ​​that minimize the fitting error of the quadratic function model. It calculates the gradient of the loss function with respect to the first and second parameters, and then updates the values ​​of the first and second parameters in the opposite direction of the gradient until convergence is achieved.

[0201] In some embodiments, such as Figure 12 As shown, the memory controller is configured to: acquire the toggling result of at least one codeword at the target read voltage, i.e., acquire... Figure 12 Point C (x) shown c ,y c ); The flip result corresponding to point C (y c If the target voltage (x) at point C is within the preset range, then the target voltage (x) at point C will be read. c This serves as a reference reading voltage.

[0202] It should be noted that, Figure 12 The example uses the default flip result as point C and should not unduly limit the scope of protection of this application. Furthermore, point C is the point corresponding to the flip result obtained under the default reading voltage according to the method of obtaining the flip result in the foregoing embodiments. Therefore, point C is an actual value, which may or may not lie on the curve of the quadratic function model.

[0203] In some embodiments, such as Figure 13 As shown, the memory controller is configured to: based on point C (x c ,y c The corresponding flip result (y) c If the target voltage is outside the preset range, acquire at least one new target reading voltage and acquire the corresponding flip result under the new target reading voltage until the flip result under the latest target reading voltage is within the preset range.

[0204] Understandably, the target reading voltage can only be used as a reference reading voltage to obtain the predicted reference voltage when the corresponding flip result at the target reading voltage is within a preset range. This enhances the accuracy and reliability of obtaining the predicted reference voltage based on multiple reference reading voltages and multiple flip results.

[0205] In some embodiments, at least two of the M reference read voltages are located on opposite sides of the axis of symmetry of the curve containing the quadratic function model; the memory controller is configured to: when acquiring the reference read voltage, acquire the reference read voltage located on a first side of the axis of symmetry of the curve containing the quadratic function model; and determine the reference read voltage located on a second side of the axis of symmetry based on the reference read voltage located on the first side.

[0206] In some implementations, the first and second parameters can be obtained when fitting a preset function model and stored in a memory device. According to... Figure 12 or Figure 13 From the coordinates of point C, the functional relationship of the quadratic function model, and the first and second parameters, an initial value of b can be obtained. Based on this initial value of b, the axis of symmetry x = -b of the curve containing the quadratic function model can be obtained.

[0207] It should be noted that the first side refers to the axis of symmetry of the curve containing the quadratic function model (e.g., the axis of symmetry of the curve containing the quadratic function model). Figure 13 and Figure 14 The first side (where x = -b) refers to one side of the curve containing the quadratic function model, while the second side refers to the other side of the axis of symmetry. When the first side is to the right of the axis of symmetry, the second side is to the left of the axis of symmetry.

[0208] For example, Figure 12 The target reading voltage (x) corresponding to point C in the diagram. c ) is the reference reading voltage on the first side of the axis of symmetry of the curve containing the quadratic function model.

[0209] The following will detail the process of obtaining the reference reading voltage on the first side of the curve containing the quadratic function model and the reference reading voltage on the second side of the curve containing the quadratic function model.

[0210] In some implementations, the method of obtaining at least one new target read voltage based on the fact that the flip result corresponding to at least one codeword at the target read voltage is outside a preset range includes, but is not limited to, using the read voltage obtained by adjusting the target read voltage by a target step size as the new target read voltage. For example, as... Figure 13 As shown, the target reading voltage (x) c The reading voltage (x) obtained after adjustment with the target step sized Using this as the new target read voltage, obtain at least one codeword's corresponding flip result (y) under the new target read voltage. e ), that is, to obtain Figure 13 Point E (x) shown d ,y e At this point, point E is an actual value, and the flip result (y) corresponding to point E is... e When the value is within the preset range, the new target reading voltage (x) corresponding to point E will be... d This serves as a reference reading voltage. The target step size can be set from 20mV to 40mV. For example, the first adjustment step size can be 20mV, 30mV, or 40mV. The target step size can also be set from 50mV to 150mV. For example, the second adjustment step size can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV.

[0211] In some implementations, the memory controller is configured to: based on the target read voltage, the corresponding flip result under the target read voltage, the target flip result, the target flip result, and a third mapping function, obtain a fitted read voltage on the first side corresponding to the target flip result, since at least one codeword's flip result at the target read voltage is outside a preset range; the third mapping function is obtained based on a quadratic function model, a first parameter, and a second parameter; the target flip result is within a reference preset range, and the preset range is within the range of the reference preset range.

[0212] For example, such as Figure 13 As shown, the memory controller is configured to: based on point C (x c ,y c The corresponding flip result (y) c If the value is outside the preset range, based on the target reading voltage (x) c ), the corresponding flip-flop result (y) under the target reading voltage c ), target flip result (y d And the third mapping function, to obtain the result of flipping the target (y) d The corresponding fitted reading voltage (x) on the first side d That is, based on the coordinates of point C and the target flipping result (y d ) and the third mapping function, to obtain point D (x d ,y d The third mapping function includes the following relation (2):

[0213]

[0214] Where x1 and y1 represent the x and y coordinates of the acquired actual point, respectively; y2 represents the target flipping result, which is an randomly selected value within the reference preset interval; and x2 represents the fitted reading voltage. The third mapping function aims to obtain the fitted reading voltage (e.g., based on a value within the reference preset interval and the acquired actual point (e.g., point C)). Figure 13 The x shown d The preset interval is located within the range of the reference preset interval. Optionally, the range of the reference preset interval is 30 to 220.

[0215] The coordinates of point C and the result of flipping the target (y) d By substituting the first and second parameters into the relational expression (2) of the first mapping function, point D (x) can be obtained. d ,y d ).

[0216] It should be noted that, Figure 13 The third mapping function is explained with the first side as the axis of symmetry and point C located on the first side.

[0217] At this time, point D (x d ,y d Let D be a fitted point, and let x be the x-coordinate of point D. d That is, the fitted read voltage on the first side. The memory controller is configured to: use this fitted read voltage as the new target read voltage, and obtain the fitted read voltage (x) of at least one codeword on the first side using the method of obtaining the flip result in the aforementioned embodiment. d The corresponding flipped result (y) under ) e That is, to obtain point E (x) d ,y e Point E is the actual point; based on the fitting reading of the voltage on the first side, the corresponding flip result (the ordinate y of point E) is read. e If the voltage is within the preset range, the fitted reading voltage (x) on the first side will be used. d This serves as a reference reading voltage for the first side.

[0218] In some embodiments, the fitted reading voltage on the first side (the x-coordinate corresponding to point D) is used to... d As the new target readout voltage, the fitted readout voltage (x) of at least one codeword on the first side is obtained using the method of obtaining the flipping result in the aforementioned embodiment. d The corresponding flipped result (y) under ) f That is, to obtain point F (x) d ,y f The memory controller is also configured to: based on the flip result corresponding to the fitted read voltage on the first side (the y-coordinate of point F). fIf the value is outside the preset range, based on the previous fitted reading voltage on the first side, the corresponding flip result under the previous fitted reading voltage on the first side, the target flip result, and the third mapping function, obtain the next fitted reading voltage on the first side corresponding to the target flip result, until the flip result corresponding to the latest fitted reading voltage on the first side is within the preset range. The latest fitted reading voltage on the first side is then used as a reference reading voltage for the first side. It can be understood that this is based on the previous known actual point F (x...). d ,y f ), target flip result (refer to any one selected within the preset range and y) d Different values) and the third mapping function (relationship (2)) are used to obtain the next fitted reading voltage on the first side corresponding to the target flipping result, until the flipping result corresponding to the latest fitted reading voltage on the first side is within the preset range, and the latest fitted reading voltage on the first side is used as a reference reading voltage on the first side.

[0219] In some embodiments, the memory controller is configured to: adjust the value of a first parameter and adjust a third mapping function accordingly, based on the number of times the latest fitting read voltage on the first side corresponds to a flip result outside a preset range being greater than or equal to a preset number; and obtain the next adjusted fitting read voltage on the first side corresponding to the target flip result based on the previous fitting read voltage on the first side, the previous flip result corresponding to the fitting read voltage on the first side, the target flip result, and the adjusted third mapping function, until the latest adjusted fitting read voltage on the first side corresponds to a flip result within a preset range.

[0220] Here, the preset number of attempts represents the upper limit of the number of trials and errors using the preset function model. If, after the preset number of attempts, the corresponding flipping results under the fitted reading voltage of the first side obtained using the preset function model are all outside the preset range, it means that the selected preset function model may not meet the actual needs and more in-depth parameter adjustments are required. The preset number of attempts can be adjusted according to the actual situation. In some embodiments, the preset number of attempts is 3-7 times. For example, the preset number of attempts can be 3, 5, or 7 times.

[0221] In some implementations, when the number of times the number of times the corresponding flip result of the fitted reading voltage on the first side obtained by the method in the aforementioned embodiments is outside the preset range is greater than or equal to the preset number, it indicates that multiple actual points have been obtained. Based on the multiple actual points obtained, combined with the functional relationship (1) of the quadratic function model and the second parameter (constant), the value of the adjusted first parameter can be obtained. It is understood that in actual use, adjusting the first parameter of the quadratic function model in combination with actual points can improve the accuracy and reliability of the quadratic function model, and make the adjusted first parameter infinitely close to the first parameter corresponding to the actual reading voltage distribution curve. In this way, it can better reflect the actual situation and can be flexibly applied to changes in actual use scenarios, thereby improving the practicality of the quadratic function model.

[0222] For example, the preset number of times is 3. The number of times the flipping result corresponding to the fitting reading voltage of the first side obtained by the method in the above embodiment is outside the preset range is equal to 3. That is, at least 3 actual points are obtained at this time. The coordinates of the 3 actual points are recorded as (x3,y3) and (x4,y4), and (x5,y5) respectively. Based on any 2 actual points among the 3 actual points obtained, such as (x3,y3) and (x4,y4), combined with the functional relationship (1) of the quadratic function model, the calculation formula (1) of b can be obtained as follows:

[0223]

[0224] Based on the calculation formula (1) for b, and according to the functional relationship of the quadratic function model and the fact that the second parameter is constant, the calculation formula (2) for the first parameter can be obtained as follows:

[0225]

[0226] It can be understood that the first parameter obtained here can be used as the first parameter in the parameter table of the N+1th update.

[0227] For example, based on the three actual points already obtained, and combined with the functional relationship (1) of the quadratic function model, the calculation formula (3) for b can be obtained as follows:

[0228]

[0229] Based on the calculation formula (3) for b, and according to the functional relationship (1) of the quadratic function model and the fact that the second parameter is a constant, the calculation formula (4) for the first parameter can be obtained as follows:

[0230]

[0231] Thus, the value of the adjusted first parameter is obtained, and the value of the adjusted first parameter is substituted into the functional relationship (2) of the third mapping function to adjust the third mapping function accordingly.

[0232] In some embodiments, the memory controller is configured to: obtain a fitted read voltage on the second side corresponding to the target flip result based on a reference read voltage on the first side, a flip result corresponding to the reference read voltage on the first side, a target flip result, and a fourth mapping function; the fourth mapping function is obtained according to a quadratic function model, a first parameter / adjusted first parameter, and a second parameter; obtain a flip result corresponding to at least one codeword at the fitted read voltage on the second side; and, based on the fact that the flip result corresponding to the fitted read voltage on the second side is within a preset range, use the fitted read voltage on the second side as a reference read voltage on the second side.

[0233] For example, such as Figure 14 As shown, the memory controller is configured to: based on a reference read voltage on the first side (the x-coordinate corresponding to point G). g The flip result corresponding to a reference reading voltage on the first side (the y-coordinate of point G). g ), target flip result (y h ) and the fourth mapping function, to obtain the result of flipping the target (y h The corresponding fitted reading voltage (x) on the second side h That is, based on the coordinates of point G, obtain the result of flipping with the target (y). h The corresponding fitted reading voltage (x) on the second side h Specifically, based on the coordinates of point G and the target flipping result (y... h ) and the fourth mapping function, to obtain point H(x) h ,y h ).

[0234] The fourth mapping function includes the following relation (3):

[0235]

[0236] Where x1 and y1 represent the x and y coordinates of the acquired actual point, respectively; y2 represents the target flipping result, which is an randomly selected value within the reference preset interval; and x2 represents the fitted reading voltage. The fourth mapping function aims to obtain the fitted reading voltage (e.g., based on a value within the reference preset interval and the acquired actual point (e.g., point G)). Figure 14 The x shown h ).

[0237] The coordinates of point G and the result of the target flip (y) hBy substituting the first parameter / adjusted first parameter and second parameter into the relational expression (3) of the fourth mapping function, point H (x) can be obtained. h ,y h ).

[0238] At this time, point H (x h ,y h H is a fitted point, and the x-coordinate of the point H is... h This refers to the fitted read voltage on the second side. The memory controller is configured to: use this fitted read voltage as the new target read voltage, and obtain the fitted read voltage (x) of at least one codeword on the second side using the method for obtaining the flipping result in the aforementioned embodiment. h The corresponding flipped result (y) under ) i That is, to obtain point I (x) h ,y i Point I is the actual point; based on the fitting data on the second side, the corresponding flip result under the voltage is read (the ordinate y of point I). i If the voltage is within the preset range, the fitted reading voltage (x) on the second side will be used. h This serves as a reference reading voltage for the second side.

[0239] In some embodiments, the memory controller is configured to: based on the previous fitted read voltage on the second side, the previous fitted read voltage on the second side corresponding to the flip result, the target flip result, and the fifth mapping function, obtain the next fitted read voltage on the second side corresponding to the target flip result, until the latest fitted read voltage on the second side corresponds to the flip result within the preset range, and use the latest fitted read voltage on the second side as a reference read voltage on the second side; the fifth mapping function is obtained based on a quadratic function model, the first parameter / adjusted first parameter, and the second parameter.

[0240] In some embodiments, such as Figure 14 and Figure 15 As shown, the fitted reading voltage on the second side (the horizontal coordinate x corresponding to point H) is... h As the new target readout voltage, the fitted readout voltage (x) of at least one codeword on the second side is obtained using the method of obtaining the flipping result in the aforementioned embodiment. h The corresponding flipped result (y) under ) j That is, to obtain point J (x) h ,y j The peripheral circuitry is also configured to: read the corresponding flip result (the ordinate y of point J) based on the fitted voltage on the second side. jThe voltage is outside the preset range, based on the previous fitted reading voltage (x-coordinate of point J) on the second side. h The previous fitting reading voltage on the second side corresponds to the flipping result (the y-coordinate of point J). j ), target flip result (y k And the fifth mapping function, to obtain the result of flipping the target (y). k The next fitted read voltage (x) corresponding to the second side k ), that is, to obtain Figure 15 Point K (x) shown k ,y k ), until the latest fitted read voltage (x) on the second side k The corresponding flipped result (y) under ) l It is within the preset range, that is Figure 15 Point L (x) shown k ,y l The corresponding ordinate is within a preset range, and the latest fitted reading voltage (x) on the second side is used. k The fifth mapping function is obtained based on a quadratic function model, the first parameter / adjusted first parameter, and the second parameter. The fifth mapping function includes the following relationship (4):

[0241]

[0242] Where x1 and y1 represent the x and y coordinates of the acquired actual point, respectively; y2 represents the target flipping result, which is an randomly selected value within the reference preset interval; and x2 represents the fitted reading voltage. The third mapping function aims to obtain the fitted reading voltage (e.g., point J) based on a value within the reference preset interval and the acquired actual point (e.g., point J). Figure 15 The x shown k ).

[0243] The coordinates of point J and the result of the target flip (y) k By substituting the first parameter / adjusted first parameter and second parameter into the relational expression (4) of the fifth mapping function, the K point (x) can be obtained. k ,y k ).

[0244] At this time, point K (x) k ,y k K is a fitted point, and the x-coordinate of point K is... k This refers to the fitted read voltage on the second side. The memory controller is configured to: use this fitted read voltage as the new target read voltage, and obtain the fitted read voltage (x) of at least one codeword on the second side using the method for obtaining the flipping result in the aforementioned embodiment. kThe corresponding flipped result (y) under ) l That is, to obtain point L (x k ,y l ), where point L is the actual point; based on the latest fitted reading on the second side, the corresponding flip result under the voltage (the ordinate y of point L) is read. l If the value is within the preset range, the latest fitted reading voltage (x) on the second side will be used. k This serves as a reference reading voltage for the second side.

[0245] It should be noted that in the embodiments of this application, points A, B, D, H, and K are all fitted points, located on the curve of the quadratic function model. Points C, E, F, G, I, J, and L are all actual points, which may or may not be located on the curve of the quadratic function model.

[0246] In this embodiment of the application, the method of obtaining the reference reading voltage of the first side / second side in the aforementioned embodiment can be used to obtain M reference reading voltages and the corresponding flip results under the M reference readings, and the prediction parameters can be obtained based on the M reference reading voltages and the M flip results.

[0247] In some embodiments, the first parameter is a variable and the second parameter is a constant; the memory controller is configured to: obtain prediction parameters based on the M flip results and the M reference read voltages, combined with a quadratic function model; and use the prediction parameters as prediction reference voltages.

[0248] For example, based on M flip results, M reference readout voltages, a quadratic function model, and a second parameter, N sets of prediction parameters are obtained, where N equals

[0249] Here, the second parameter can be obtained when fitting a preset function model and stored in a memory device.

[0250] In some implementations, M equals 2, then N equals 1. Substituting the coordinates corresponding to the two reference reading voltages and the two flip results into the calculation formula (1) of b, b can be calculated, and a set of prediction parameters can be obtained. These prediction parameters are then used as the prediction reference voltage.

[0251] In some implementations, M is greater than 2, and N is equal to Based on M reference read voltages and M flip results, we can obtain A combination of two reference read voltages and their corresponding two flip results, based on By combining the various combinations with the calculation formula (1) for b, we can obtain... Group prediction parameters. Determine. Outliers in group prediction parameters; based on The median and standard deviation of the group prediction parameters are used to identify outliers or to... The maximum and minimum values ​​in the group prediction parameters are both taken as outliers. The median or average of the remaining prediction parameters after removing outliers is used as the prediction reference voltage.

[0252] In this way, by identifying and removing outliers from multiple sets of prediction parameters, the accuracy and reliability of the remaining prediction parameters when used to determine the predicted reference voltage are ensured.

[0253] In some embodiments, the first parameter and the second parameter are both variables; the memory controller is configured to: obtain prediction parameters based on M flip results and M reference read voltages, combined with a quadratic function model; use the prediction parameters as the target read voltage to obtain the flip result of at least one codeword corresponding to the prediction parameters as the target read voltage; obtain new prediction parameters based on the M flip results, M reference read voltages, prediction parameters, and the flip results corresponding to the prediction parameters as the target read voltage, combined with a quadratic function model; and use the new prediction parameters as the prediction reference voltage.

[0254] In some implementations, the second parameter is a variable, but the second parameter can be given an initial value when fitting a preset function model and stored in a memory device.

[0255] For example, based on M flip results, M reference reading voltages, a quadratic function model, and the initial value of the second parameter, combined with the calculation formula (1) for b, N sets of prediction parameters are obtained, where N equals

[0256] In some implementations, M equals 2, then N equals 1. Substituting the coordinates of the two reference read voltages and the two flip results into the calculation formula (1) of b, b can be calculated, and a set of prediction parameters can be obtained. The prediction parameters are used as the target read voltage to obtain at least one codeword with the prediction parameters as the target read voltage, that is, another actual point is obtained. Next, the coordinates of the three actual points (the two reference read voltages and their corresponding two flip results, the prediction parameters and the flip results with the prediction parameters as the target read voltage) are substituted into the calculation formula (3) of b to calculate b, and a new set of prediction parameters can be obtained. The new prediction parameters are used as the prediction reference voltage.

[0257] Thus, by using the predicted parameters and the corresponding flip-flop results under the read voltage to obtain new predicted parameters, the accuracy of the obtained predicted reference voltage can be improved.

[0258] In some implementations, the M reference reading voltages are located on the same side of the axis of symmetry of the curve containing the quadratic function model. For example, all M reference reading voltages are located on the first side of the axis of symmetry of the curve containing the quadratic function model, or all M reference reading voltages are located on the second side of the axis of symmetry of the curve containing the quadratic function model.

[0259] In some implementations, at least two of the M reference read voltages lie on either side of the axis of symmetry of the curve containing the quadratic function model. Points located on either side of the axis of symmetry of the curve containing the quadratic function model are more representative, covering a wider data range, and can improve the accuracy and reliability of determining prediction parameters based on the reference read voltages to further obtain the predicted reference voltage.

[0260] It should be noted that the target read voltage (first read voltage) used for the first time can refer to the preset read voltage that can distinguish two adjacent intermediate memory states of the memory cell after the first programming operation in previous read processes. The preset read voltage can be an empirical value or a default value configured at the time of manufacture of the memory device. This default value is obtained through a large number of simulation experiments before the memory device leaves the factory.

[0261] The process described above for obtaining the target reference voltage of at least one codeword is applicable to any one of the N pages.

[0262] In this embodiment, the transmission of the flip result (which can be several bytes) is performed instead of transmitting at least one codeword (e.g., the codeword size can be 4KB), thus reducing the amount of data transmitted. The process of obtaining the flip result converges within the memory device, without occupying space such as the memory controller, and thus has a low dependence on the memory controller. Based on a finite number of reference read voltages and a finite number of flip results within a preset interval, the process of obtaining the target reference voltage by combining a preset function model is completed in the memory device. Since the preset interval is a reasonable interval determined when fitting the preset function model, selecting data within the preset interval to determine the target reference voltage not only improves the accuracy of determining the target reference voltage but also reduces the impact of data noise to a certain extent, improving reliability. At the same time, it can reduce the number of iterations and speed up the determination of the target reference voltage when power is restored after a power outage. Then, the target reference voltage is used to perform a read operation on the written data, thus speeding up the re-execution of the programming operation.

[0263] Firstly, in this embodiment, the data to be written corresponding to the first programming operation is encoded to obtain encoded data, wherein the amount of encoded data is less than the amount of data to be written. The encoded data is written to a memory device to obtain error recovery data required to re-execute the programming operation when power is restored after a power outage. Thus, on the one hand, by reducing the amount of data written to the memory device during power-down protection, the demand for capacitor capacity is effectively reduced; on the other hand, when power is restored after a power outage, by decoding the encoded data and the data already written corresponding to the first programming operation to obtain at least some error recovery data, the data integrity during the power outage in the first programming operation process can be ensured, and the risk of overall programming operation failure can be reduced, thereby improving the reliability of the programming operation.

[0264] Secondly, embodiments of this application provide an operation method for a memory system. Figure 16 Flowchart of an operation method for a memory system provided in an embodiment of this application Figure 1 ,like Figure 16 As shown, the operation method of the memory system includes:

[0265] Step S10: In response to a power failure during the first programming operation, the data to be written corresponding to the first programming operation is encoded to obtain encoded data; the encoded data is written to the memory device of the memory system; wherein, the data to be written is the data to be written to the memory device during the first programming operation; the amount of encoded data is less than the amount of data to be written.

[0266] Step S20: In response to the power-on after the power failure, the acquired encoded data and the written data corresponding to the first programming operation are decoded to obtain at least part of the error recovery data corresponding to the written data.

[0267] In some embodiments, the memory device includes a plurality of memory cells with N bits each, wherein the N bits of the memory cells correspond to N pages of data, and N is an integer greater than 2; the data to be written includes data to be written to the N pages; the encoding process of the data to be written to the memory device corresponding to the first programming operation includes: performing logical operations on the data of every two pages to be written to obtain the encoded data.

[0268] In some embodiments, the ratio of the amount of data to be written into N pages to the amount of data of the encoded data is N:N-1.

[0269] In some embodiments, performing logical operations on the data of every two pages to be written to N pages to obtain the encoded data includes: performing OR or AND logical operations on the data of every two pages to be written to N pages to obtain the encoded data; and performing decoding processing on the encoded data obtained from the memory device and the written data corresponding to the first programming operation includes: performing OR and AND logical operations on the encoded data and the written data to obtain the at least partial error recovery data.

[0270] For example, the memory device includes multiple four-bit memory cells, where each four bit corresponds to four pages of data; the data to be written includes data to be written to the four pages; the memory controller is specifically configured to perform logical operations on the data of every two pages to be written to obtain encoded data. Taking N=4 as an example, the ratio of the amount of data to be written to the amount of encoded data is 4:3.

[0271] Logical operations are performed on every two pages of the four pages to be written (LP, MP, UP, and XP) to obtain encoded data. For example, logical operations are performed on the data to be written to LP and MP to obtain the first encoded data Parity1, on the data to be written to MP and UP to obtain the second encoded data Parity2, and on the data to be written to UP and XP to obtain the third encoded data Parity3. It can be understood that after logical operations on the data to be written to the four pages, three encoded data (first encoded data Parity1, second encoded data Parity2, and third encoded data Parity3) are obtained.

[0272] In other embodiments, the data to be written to LP and the data to be written to MP are processed by logical operations to obtain first encoded data, the data to be written to LP and the data to be written to UP are processed by logical operations to obtain second encoded data, and the data to be written to UP and the data to be written to XP are processed by logical operations to obtain third encoded data.

[0273] In some embodiments, the method further includes: disabling an error correction encoding module in the memory controller of the memory system before writing the encoded data into the memory device; and disabling an error correction decoding module in the memory controller after obtaining the encoded data from the memory device.

[0274] In some implementations, such as Figure 7As shown, the memory controller 106 includes an error correction encoding module 1065 and an error correction decoding module 1066. The error correction encoding module 1065 is used to encode the data to be stored to obtain verification data, and the error correction decoding module 1066 is used to decode the verification data to detect and correct possible erroneous data during data transmission.

[0275] For example, the operation method of the memory system further includes disabling the error correction encoding module 1065 before writing the encoded data into the memory device 104. Since the algorithm used by the error correction encoding module (e.g., the ECC error correction algorithm) is different from the principle of the logical operation used to process the data to be written into the encoded data, re-encoding the encoded data generated by the logical operation may damage the data structure of the encoded data originally intended for obtaining error recovery data, potentially leading to the inability to successfully obtain the error recovery data required to re-execute the programming operation upon power-up after a power outage. To ensure the accuracy of the encoded data when used to obtain the error recovery data required to re-execute the programming operation upon power-up after a power outage, error correction encoding is not required here.

[0276] In some embodiments, the method of operating the memory system further includes: after retrieving encoded data from the memory device 104, controlling the disable of the error correction decoding module 1066. Similarly, to ensure the accuracy of the encoded data when used to retrieve error recovery data required to re-execute the programming operation upon power-up after a power failure, error correction decoding of the encoded data is not required here.

[0277] In some embodiments, the memory device includes a plurality of memory cells with N bits of storage, where N is an integer greater than 2; the memory device includes a first memory area and a second memory area; the memory cells in the first memory area read or write one bit of data in a first mode, and the memory cells in the second memory area read or write the N bits of data in a second mode; writing the encoded data into the memory device of the memory system includes: writing the encoded data into the memory device using the first mode; the method further includes: controlling the memory device to read the encoded data using the first mode before retrieving the encoded data from the memory device.

[0278] In some embodiments, the first mode can be understood as a single-level read mode or a single-level write mode. The second mode can be understood as a multi-level read mode or a multi-level write mode.

[0279] In some embodiments, writing the encoded data into the memory device of the memory system includes: writing the encoded data into the memory device 104 using a single-level write mode.

[0280] In some embodiments, writing the encoded data into the memory device of the memory system includes: controlling the memory device 104 to read the encoded data in a single-level read mode before retrieving the encoded data from the memory device 104.

[0281] In this embodiment, the first mode is fast and simple to operate. When power is lost, using the first mode to write the encoded data to the memory device ensures timely and secure storage of the encoded data, reducing the risk of data loss. Upon power-up after a power outage, controlling the memory device to read the encoded data in the first mode before retrieving it from the memory device helps to accelerate the acquisition of error recovery data required for re-executing the programming operation, reducing the overall programming time.

[0282] Furthermore, by dividing the storage area of ​​the memory device into a first storage area and a second storage area, wherein the first storage area is used to store coded data with high reliability requirements and the second storage area is used to store regular data with high capacity requirements, and by using different modes (first mode and second mode) for write and read operations in the first and second storage areas, the storage space can be fully utilized and the performance of the storage device can be effectively optimized.

[0283] In some embodiments, the method further includes controlling the memory device to re-execute the programming operation using the error recovery data.

[0284] By decoding the encoded data and the written data corresponding to the first programming operation, at least some error recovery data can be obtained. This ensures the data integrity in the event of a power outage during the first programming operation. Re-executing the programming operation using this error recovery data can reduce the risk of overall programming operation failure and improve the reliability of the programming operation.

[0285] In some embodiments, the memory device includes a plurality of memory cells, which are programmed into an intermediate memory state after the first programming operation is performed, and the data in the intermediate memory state is programmed into a target memory state after the second programming operation is performed; the threshold voltage distribution width of the intermediate memory state is greater than the threshold voltage distribution width of the target memory state.

[0286] Here, the first programming operation can be called the coarse programming operation, and the second programming operation can be called the fine programming operation. Taking a QLC memory cell as an example, the threshold voltage distribution width of the QLC memory cell after the first programming operation is as follows: Figure 6A As shown, the threshold voltage distribution width of the QLC memory cell after performing the second programming operation following the first programming operation is as follows: Figure 6B As shown. For example, as Figure 6AThe threshold voltage distribution width of the intermediate storage state shown is greater than Figure 6B The threshold voltage distribution width of the target storage state is shown.

[0287] In some embodiments, the method further includes: obtaining the data to be written from the memory device before encoding the data to be written; and obtaining the encoded data and the written data from the memory device before decoding the encoded data and the written data.

[0288] In some embodiments, the method further includes: obtaining raw data to be written from a cache of the memory controller of the memory system before obtaining the data to be written; and sending the raw data to be written to a page cache of the memory device, wherein data to be written corresponding to the first programming operation is generated in the page cache.

[0289] By sending and reading raw data to be written to the page buffer, the complete process of writing and reading data into the memory cell of the memory device can be simulated. It is possible to simulate whether errors or data corruption occur during the writing and reading process. The accuracy is higher when the data to be written obtained by the memory controller represents the reading result corresponding to the data actually written to the memory device in the first programming operation. In addition, the speed of writing and reading data into the page buffer is fast and the power consumption is very low, so it will not occupy too many resources for power-down protection.

[0290] In some embodiments, the method further includes: acquiring a target read voltage corresponding to a first programming operation before acquiring the written data; and controlling the memory device to perform a read operation on the written data using the target read voltage.

[0291] It should be noted that the target reference voltage here is the optimal read voltage found through the method in the embodiments of this application. Using the target reference voltage allows for more accurate reading of the written data, improving the accuracy of the read result (written data). The specific method for obtaining the target reference voltage will be further described later.

[0292] In some embodiments, obtaining the target read voltage corresponding to the first programming operation includes: obtaining M flip results corresponding to at least one codeword formed by a preset number of the memory cells under M reference read voltages; the flip result includes the number of bits that flipped in two read results of at least one codeword under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; obtaining a predicted valley voltage based on the M flip results and the M reference read voltages, combined with a preset function model; the preset function model represents the relationship between the flip results and the reference read voltages; all M flip results are within a preset interval; and determining the target read voltage based on the predicted valley voltage.

[0293] In some embodiments, the preset function model includes a quadratic function model, which includes the following functional relationships:

[0294] y = a(x + b) 2 +c

[0295] Wherein, y is the flipping result, x is the reference reading voltage, b is used to characterize the prediction parameter, a is the first parameter, and c is the second parameter.

[0296] For details on how to obtain the target reference voltage, please refer to [link / reference]. Figures 10 to 15 The relevant descriptions will not be repeated here.

[0297] Figure 17 A flowchart of an operation method for a memory system provided in an embodiment of this application is shown in Figure 2. Figure 17 As shown, the operation method of the memory system provided in this application embodiment verifies the power-down protection process after a power failure during the first programming operation and the data recovery process after power failure and power-on. Figure 17 As shown, perform the following steps:

[0298] Step S1701: Power off. Here, power off can be understood as suddenly cutting off power to the memory system during the first programming operation, such as unplugging the power supply.

[0299] Step S1702: First check of the log (Trace). Here, the check log can be understood as the event log of the tracker at least during the power-down protection period.

[0300] In step S1702, it can be detected that during the entire process, the first mode (e.g., single-level write mode) was enabled, and data equivalent to (N-1) pages was written to the memory device. Here, N is the number of bits in the memory cell.

[0301] Step S1703: Powering on again after a power outage. Here, powering on can be understood as powering on the memory system.

[0302] Step S1704: Second check log. Here, the check log can be understood as the tracker's event log at least during the data inspection operation.

[0303] In step S1704, the detection process reveals the following: 1. The target reference voltage was queried; 2. The target reference voltage was used to perform a read operation on the written data corresponding to the first programming operation, and the read result was obtained; 3. Based on the read result of the written data, erroneous data recovery was performed.

[0304] Thirdly, embodiments of this application provide a storage medium storing executable instructions, which, when executed, implement the steps of the operation method provided in embodiments of this application.

[0305] In some specific embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0306] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0307] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0308] As an example, executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located in one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0309] Figure 18 This is a block diagram of a storage medium provided in an embodiment of this application. This application provides a storage medium 1800 storing executable instructions 1801. When executed by a processor, the executable instructions 1801 can implement the operation method of the memory system as described above. The operation method includes: in response to a power outage during a first programming operation, encoding the data to be written corresponding to the first programming operation to obtain encoded data; writing the encoded data into the memory device of the memory system; wherein the data to be written is the data to be written into the memory device during the first programming operation; the amount of encoded data is less than the amount of data to be written; and in response to a power-on re-energization after the power outage, decoding the acquired encoded data and the written data corresponding to the first programming operation to obtain at least partial error recovery data corresponding to the written data.

[0310] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0311] The above are merely preferred embodiments of this application and do not limit the scope of this patent application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of this application.

Claims

1. A memory system, characterized by, Comprise: a memory device; a memory controller coupled with the memory device and configured to: in response to a power-off during a first programming operation, encode data to be written corresponding to the first programming operation to obtain encoded data; write the encoded data into the memory device; wherein the data to be written is data to be written into the memory device by the first programming operation; a data amount of the encoded data is less than a data amount of the data to be written; in response to a power-on again after the power-off, decode the encoded data obtained and written data corresponding to the first programming operation to obtain at least part of error recovery data corresponding to the written data.

2. The memory system of claim 1, wherein, The memory device comprises a plurality of storage units with N-bit storage, N storage bits of the storage unit correspond to data of N pages, N is an integer greater than 2; the data to be written includes data to be written in N pages; The memory controller is specifically configured to: perform logical operation processing on data of every two pages in N pages to be written to obtain the encoded data.

3. The memory system of claim 2, wherein, The ratio of the data amount of the data to be written in N pages to the data amount of the encoded data is N:N-1.

4. The memory system of claim 2, wherein, The memory controller is specifically configured to: perform or logical operation or and logical operation on data of every two pages in N pages to be written to obtain the encoded data; perform or logical operation and and logical operation on the encoded data and the written data to obtain the at least part of error recovery data.

5. The memory system of claim 1, wherein, The memory controller comprises an error correction encoding module and an error correction decoding module; The memory controller is configured to: before writing the encoded data into the memory device, control to disable the error correction encoding module; after obtaining the encoded data from the memory device, control to disable the error correction decoding module.

6. The memory system of claim 1, wherein, The memory device comprises a plurality of storage units with N-bit storage, N is an integer greater than 2; the memory device comprises a first storage area and a second storage area; the storage units in the first storage area read or write one-bit data in a first mode, and the storage units in the second storage area read or write N-bit data in a second mode; The memory controller is configured to: write the encoded data into the memory device in the first mode; before obtaining the encoded data from the memory device, control the memory device to read the encoded data in the first mode.

7. The memory system of claim 1, wherein, The memory controller is further configured to: control the memory device to re-execute a programming operation using the error recovery data.

8. The memory system according to any one of claims 1 to 7, wherein The memory device comprises a plurality of storage units, the storage units are programmed to an intermediate storage state after executing the first programming operation, and the data of the intermediate storage state is programmed to a target storage state after executing a second programming operation; a threshold voltage distribution width of the intermediate storage state is greater than a threshold voltage distribution width of the target storage state.

9. The memory system of claim 8, wherein, The memory controller is configured to: before encoding the data to be written, obtain the data to be written from the memory device; The encoded data and the written data are obtained from the memory device before decoding the encoded data and the written data.

10. The memory system of claim 9, wherein, The memory device includes a page buffer; and the memory controller includes a buffer; The memory controller is configured to: obtain original to-be-written data from the buffer before obtaining the to-be-written data; and send the original to-be-written data to the page buffer to generate the to-be-written data corresponding to the first programming operation in the page buffer.

11. The memory system of claim 9, wherein, The memory controller is configured to: obtain a target reference voltage corresponding to a first programming operation before obtaining the written data; and control the memory device to perform a read operation on the written data using the target reference voltage.

12. The memory system of claim 11, wherein, The memory controller is configured to: obtain M flipping results of at least one code word formed by a preset number of memory cells under M reference read voltages; the flipping results include a number of bits that flip in two read results of the at least one code word under a first read voltage and a second read voltage; the first read voltage and the second read voltage differ by less than a preset voltage; M is an integer greater than or equal to 2; obtain a predicted valley voltage based on the M flipping results, the M reference read voltages, and a preset function model; the preset function model represents a relationship between the flipping results and the reference read voltages; the M flipping results are all within a preset interval; and determine the target reference voltage based on the predicted valley voltage.

13. The memory system of claim 12, wherein, The preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y = a(x + b) 2 + c wherein y represents the flipping result, x represents the reference read voltage, b represents a predicted parameter, a represents a first parameter, and c represents a second parameter.

14. An operating method of a memory system, characterized by, The method includes: in response to a power failure during a first programming operation, encoding to-be-written data corresponding to the first programming operation to obtain encoded data; writing the encoded data to a memory device of the memory system; wherein the to-be-written data is data to be written to the memory device by the first programming operation; the amount of data of the encoded data is less than the amount of data of the to-be-written data; in response to a subsequent power-on after the power failure, decoding the obtained encoded data and written data corresponding to the first programming operation to obtain at least part of error recovery data corresponding to the written data.

15. The method of operation of claim 14, wherein, The memory device includes a plurality of memory cells with N bits of storage; the N storage bits of the memory cells correspond to data of N pages; N is an integer greater than 2; the to-be-written data includes data to be written in N pages; The encoding of the to-be-written data corresponding to the first programming operation to be written to the memory device includes: performing logical operation processing on data of every two pages in the N pages to obtain the encoded data.

16. The method of operation of claim 15, wherein, The ratio of the amount of data of the data in the N pages to the amount of data of the encoded data is N:N-1.

17. The method of claim 15, wherein, performing logical operation processing on data to be written in each two pages of N pages to obtain the encoded data, including: performing or logical operation or and logical operation on data to be written in each two pages of N pages to obtain the encoded data; performing decoding processing on the encoded data obtained from the memory device and the written data corresponding to the first programming operation, including: performing or logical operation and and logical operation on the encoded data and the written data to obtain the at least partial error recovery data.

18. The method of claim 14, wherein, The method further includes: controlling to disable an error correction encoding module in a memory controller of the memory system before writing the encoded data into the memory device; controlling to disable an error correction decoding module in the memory controller after obtaining the encoded data from the memory device.

19. The method of claim 14, wherein, The memory device includes a plurality of storage units with a storage bit number of N bits, and N is an integer greater than 2; the memory device includes a first storage area and a second storage area; the storage units in the first storage area read or write one bit of data in a first mode, and the storage units in the second storage area read or write N bits of data in a second mode; The method further includes: writing the encoded data into the memory device in the first mode; The method further includes: controlling the memory device to read the encoded data in the first mode before obtaining the encoded data from the memory device.

20. The operating method according to claim 14, characterized in that, The method further includes: controlling the memory device to re-execute a programming operation using the error recovery data.

21. A method of operation according to any of claims 14 to 20, characterised by, The memory device includes a plurality of storage units, which are programmed to an intermediate storage state after performing the first programming operation, and the data of the intermediate storage state is programmed to a target storage state after performing a second programming operation; the threshold voltage distribution width of the intermediate storage state is greater than the threshold voltage distribution width of the target storage state.

22. The method of operation of claim 21, wherein, The method further includes: obtaining the to-be-written data from the memory device before encoding the to-be-written data; obtaining the encoded data and the written data from the memory device before decoding processing the encoded data and the written data.

23. The method of operation of claim 22, wherein, The method further includes: obtaining original to-be-written data from a buffer of a memory controller of the memory system before obtaining the to-be-written data; and sending the original to-be-written data to a page buffer of the memory device to generate the to-be-written data corresponding to the first programming operation in the page buffer.

24. The method of operation of claim 22, wherein, The method further includes: obtaining a target reference voltage corresponding to the first programming operation before obtaining the written data; and controlling the memory device to perform a read operation on the written data using the target reference voltage.

25. The method of operation of claim 24, wherein, The method further includes: obtaining a target reference voltage corresponding to the first programming operation before obtaining the written data; and controlling the memory device to perform a read operation on the written data using the target reference voltage. The method further includes: obtaining M flipping results corresponding to at least one code word formed by the preset number of the storage units under M reference read voltages; the flipping results include a number of bits representing flipping in two read results of at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage is less than a preset voltage; and the M is an integer greater than or equal to 2; obtaining a predicted valley bottom voltage according to the M flipping results and the M reference read voltages, and in combination with a preset function model; the preset function model represents a relationship between the flipping results and the reference read voltages; and the M flipping results are all within a preset interval; and determining the target reference voltage based on the predicted valley bottom voltage.

26. The method of operating according to claim 25, wherein, The preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y = a(x + b) 2 + c wherein the y is the flipping result, the x is the reference read voltage, the b is used to represent a predicted parameter, the a is a first parameter, and the c is a second parameter.

27. A storage medium, characterized by The storage medium has executable instructions stored thereon, and the executable instructions, when executed, implement steps of the operation method according to any one of claims 14 to 26.

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