Data recording system for mining protection device and control method

Abstract

The invention relates to the technical field of mining protection device control, in particular to a data recording system for a mining protection device and a control method, which comprises a voltage acquisition circuit, a current acquisition circuit, a digital quantity input circuit, a digital quantity output circuit, a power supply circuit, a CPU (central processing unit), an external EEPROM (electrically erasable programmable read-only memory) and an internal FLASH memory, the voltage acquisition circuit and the current acquisition circuit are used for receiving alternating-current analog quantity signals, converting the alternating-current analog quantity signals into digital signals and transmitting the digital signals to the CPU; the digital quantity input circuit is used for receiving a switching value signal outside the mining protection device and transmitting the switching value signal to the CPU; and the CPU is used for judging whether a fault and a switching-on and switching-off event occur or not according to a preset protection logic algorithm, and controlling the digital quantity output circuit to output to the relay interface. Classification management is carried out by analyzing data characteristics of the protection device, fault data with high real-time storage requirements and large data volume is stored in the FLASH memory, and it is guaranteed that key data can be stored in real time.

Description

Technical Field

[0001] This invention relates to the field of mine protection device control technology, and in particular to a data recording system and control method for mine protection devices. Background Technology

[0002] Mining protection devices are key equipment in mine power systems, integrating control, protection, detection, communication, and event recording. Data recording includes setpoint parameters, circuit breaker opening and closing records, system parameters, and fault records, which is one of the core functions of mining protection devices.

[0003] Circuit breaker opening and closing records are crucial data for mechanical life assessment and operation and maintenance management. Fault records include data such as current and voltage waveforms, fault type, and operating time during protection actions, providing essential data for equipment fault analysis, safety optimization, and intelligent operation. Therefore, mining protection devices are all designed with data storage that retains data even after power loss.

[0004] However, the following problems exist: Currently, the externally designed EEPROM configured in mining protection devices has advantages such as large storage space and long data retention time. However, EEPROM has a slow writing speed, and erasing and writing operations take about 5 milliseconds to complete. Moreover, it usually requires byte-by-byte operation, which cannot meet the requirement of completing a large amount of data storage within 1 millisecond for fault recording.

[0005] The CPU's internal Flash memory has advantages such as non-volatile data storage and high speed, which can meet the requirement of storing large amounts of fault data in a short time. However, the CPU's internal Flash memory can only be erased and written about 10,000 times. Frequent erase and write operations will shorten the lifespan of the CPU and protection devices, and affect the reliability of the protection devices.

[0006] Therefore, it is necessary to design a new data recording system and control method for mine protection devices. Summary of the Invention

[0007] The technical problem to be solved by this patent is that the data recording and storage of the mining protection device designed in this invention includes two storage media: external EEPROM memory and internal FLASH memory of the CPU.

[0008] The data recording control method provided by this invention can fully allocate external EEPROM memory and internal FLASH memory resources according to data type and storage requirements, making full use of the advantages of different memory types. It solves the problem of short FLASH lifespan caused by frequent FLASH memory erase and write operations; and it addresses the problem that the slow write speed of external EEPROM cannot meet the large volume of fault recording data and high real-time requirements.

[0009] A data recording system for a mine protection device includes a voltage acquisition circuit, a current acquisition circuit, a digital input circuit, a digital output circuit, a power supply circuit, a CPU, an external EEPROM memory, and an internal FLASH memory. The voltage acquisition circuit and the current acquisition circuit are used to receive AC analog signals and convert them into digital signals before transmitting them to the CPU. The digital input circuit is used to receive external switching signals from the mine protection device and transmit them to the CPU; The CPU is used to determine whether a fault or opening / closing event has occurred according to a pre-set protection logic algorithm, and to control the digital output circuit to output to the relay interface. The external EEPROM memory is used to store setpoint parameters, system parameters, opening and closing records, the latest write address and check value of the internal FLASH, and the number of fault data stored in the internal FLASH. The internal FLASH memory is divided into five separate circular storage blocks for storing fault data.

[0010] Based on any of the above technical solutions, further optimizations include: a memory initialization module, a data analysis and classification module, a data control and management module, a data writing module, and a data reading module; The memory initialization module is used for CPU pin initialization and verification of the integrity and correctness of stored data; The data analysis and classification module is used to divide the data to be stored into non-fault record data and fault record data, place the read data into the corresponding variables for program execution, and update the data flag bit; The data control and management module is used for external EEPROM storage address management, internal FLASH data writing page number, address, and verification data management, as well as data storage and reading correctness verification, data writing management, and data reading management. The data writing module is used to perform data writing operations, writing non-fault record data to the address corresponding to the external EEPROM memory, and storing fault record data into the internal FLASH memory. The data reading module is used to perform read operations on stored data.

[0011] The CPU integrates a memory initialization module, a data analysis and classification module, a data control and management module, a data writing module, and a data reading module.

[0012] Based on any of the above technical solutions, the following further optimizations are made: the non-fault record data includes setpoint parameters, system parameters, and opening / closing record data; the fault record data includes voltage and current values ​​at the time of the fault.

[0013] Based on any of the above technical solutions, a further optimization is made: the data flag bits include a setting parameter update flag bit, a system parameter update flag bit, a circuit breaker closing record data update flag bit, and a fault record update flag bit.

[0014] Based on any of the above technical solutions, a further optimization is made as follows: the starting addresses of the five individually cyclic storage blocks are respectively denoted as FAddress1, FAddress2, FAddress3, FAddress4, and FAddress5, and their numbers are respectively denoted as Block_Num1=1, Block_Num2=2, Block_Num3=3, Block_Num4=4, and Block_Num5=5, and the starting addresses and numbers are stored in an external EEPROM memory.

[0015] This invention also provides a control method for a data recording system for mine protection devices, characterized by comprising the following steps: S1: Initialization Operation S1.1: Initialize the FLASH memory, EEPROM memory, and variables to bring the control system into normal operation. S1.2: Determine if the system is being used for the first time. If so, divide the internal FLASH storage area into 5 circular storage blocks; Then, store the starting address (FAddress1, FAddress2, FAddress3, FAddress4, FAddress5) and number (Block_Num1=1, Block_Num2=2, Block_Num3=3, Block_Num4=4, Block_Num5=5) of each memory block into the external EEPROM memory; otherwise, proceed directly to the next step. S1.3: Verify the integrity and correctness of the stored data. If the verification passes, the data is placed in the corresponding variable for system operation. If the verification fails, the corresponding loop block data is cleared and returned to S1.3, and the previously stored data is read again for verification. S2: Data analysis and classification; S3: Data Control Management and Storage S3.1: After the data control management module detects the update flag, it determines the data type to be updated; S3.2: If the data is not a fault record, execute the storage procedure; S3.3: If it is fault record data, execute the following storage process: S3.3.1: Calculate the data storage parameters for this fault based on the latest storage block number (FLASH_Serial) and starting address (FLASH_F) of the internal FLASH stored in the external EEPROM memory; S3.3.2: The data storage block number for this fault is FLASH_Serial + 1, and the starting address of the data storage for this fault is FLASH_F + the length of the FLASH circular storage block; S3.3.3: Perform a FLASH write operation to store the fault data into the FLASH circular storage block calculated above; S3.3.4: After the write operation is completed, update the latest storage block number of the internal FLASH to the storage block number of this operation, update the latest starting address of the internal FLASH to the starting address of this operation, and record the number of data items written this time (DataN). S3.3.5: Calculate the check value CRC_Data of the current fault data. The calculation method is CRC_Data = (Flash_Data[0] + Flash_Data[1] + ... + Flash_Data[DataN-1]) & (0XFF), where Flash_Data[N] is the intermediate variable array storing the current fault data; S3.3.6: Save the updated storage block number, storage starting address, check value CRC_Data, and data count DataN to the external EEPROM memory; S3.3.7: After all data is successfully saved, clear the fault record update flag.

[0016] Based on any of the above technical solutions, the following further optimization is made: The specific steps of data analysis and classification in step S2 are as follows: S2.1: Continuously check whether the setpoint parameters, system parameters, opening and closing record data, and fault record data have been updated; S2.2: If the data is not updated, return to S2.1 to continue the detection; if the data is updated, determine whether the updated data type is non-fault record data or fault record data. S2.3: Set the corresponding update flag bit according to the data type. For non-fault record data, set the setting parameter update flag bit, system parameter update flag bit, or opening and closing record data update flag bit. For fault record data, set the fault record update flag bit. S2.4: Transmit the update flag to the data control and management module.

[0017] Based on any of the above technical solutions, a further optimization is made: If the data in step S3.2 is non-fault record data, the specific steps for executing the storage process are as follows: S3.2.1: Determine the storage variables and their corresponding storage addresses based on the flag bits and data types (setpoint parameters correspond to the setpoint parameter register address array Def_Data[N], system parameters correspond to the system parameter address array System_Data[N], and switch opening / closing record data correspond to the switch opening / closing record data address array Switch_Data[N]). S3.2.2: Execute the EEPROM data write operation instruction to write the non-fault record data to the corresponding storage address; S3.2.3: After a successful write operation, clear the flag corresponding to the updated data.

[0018] Based on any of the above technical solutions, a further optimization is made: the integrity and correctness verification of the stored data in step S1.3 includes the following sub-steps: S1.3.1: Read the latest memory block number, starting address, check value (CRC_EE), and number of fault data (DataN) stored in the external EEPROM memory. S1.3.2: Determine whether the latest storage block number and the starting address correspond (e.g., the starting address is FAddress1 when the number is 1). If they correspond, proceed to the next step; otherwise, the verification fails. S1.3.3: Read all the data of the latest storage block in the internal FLASH and put it into the intermediate variable array Flash_Data[N]; S1.3.4: Add the first DataN data in the Flash_Data[N] array and keep the lower 8 bits to obtain the check data CRC_Data; S1.3.5: Determine whether CRC_Data and CRC_EE are consistent. If they are consistent, the data is correct (verification passed); if they are inconsistent, the verification fails.

[0019] Based on any of the above technical solutions, the following further optimizations are made: the setting parameter update flag bit in step S2.3 is Defdata_Flag[N], the system parameter update flag bit is Systemdata_Flag[N], the opening and closing record data update flag bit is Switchdata_Flag[N], and the fault record update flag bit is FaultRecord_Flag.

[0020] The calculation method for the verification data in step S3.3.5 is the same as the calculation method for the verification data in step S1.3.4.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention classifies and manages data by analyzing the characteristics of protection devices, and stores fault data with high real-time storage requirements and large data volume into FLASH memory to ensure that critical data can be saved in real time.

[0022] 2. This invention divides the FLASH storage area into five independent and complete storage modules capable of storing fault data of the protection device. The data write management module controls the five storage modules to store fault data in turn, reducing the frequent writing of a single storage module and improving the service life of the FLASH memory.

[0023] 3. The data writing management module of this invention is designed with FLASH data verification function. Each time fault record data is read, the read data is compared with the verification data stored in EEPROM. The starting address, data and number of stored data bytes are consistent, which can determine whether the read data is the latest and correct data, thus ensuring the accuracy of the data.

[0024] 4. This invention employs a categorized storage strategy, storing fault data with high real-time requirements and large data volumes in a high-speed internal FLASH memory, thus solving the problem that the slow write speed of external EEPROM cannot meet the timeliness requirements of fault recording. Simultaneously, non-fault record data (setpoint parameters, system parameters, etc.) with low update frequency and requiring long-term retention is stored in a large-capacity external EEPROM memory, fully leveraging the inherent advantages of both storage media to achieve precise adaptation to different types of data storage needs.

[0025] 5. By dividing the internal FLASH memory into 5 independent circular storage blocks and adopting a circular mechanism for storing fault data in turn, the frequent erase and write operations of a single storage block are avoided, which significantly reduces the wear and tear of the FLASH memory and solves the problem of short lifespan caused by its limited number of erase and write cycles. This extends the service life of the CPU and the entire mining protection device and improves the reliability of the device operation.

[0026] 6. A dual data verification mechanism was designed. During the initialization phase, the correctness of the read data is ensured by comparing the corresponding storage block number with the starting address and the lower 8 bits of the data summation with the verification value. After the fault data is stored, the verification value is calculated in real time and stored in the EEPROM along with the storage block information. During subsequent readings, the verification value can be used to verify that the data has not been tampered with or damaged, effectively avoiding the impact of erroneous data on fault analysis, operation and maintenance management and other work, and ensuring the traceability of data.

[0027] 7. Through modular division of labor (initialization, data analysis and classification, data control and management modules, etc.) and data flag mechanism, accurate detection, classification and identification, and on-demand storage of data updates are achieved, avoiding invalid storage queries and duplicate storage operations. At the same time, fixed storage address mapping, simplified address calculation logic, and standardized communication timing configuration reduce CPU computing overhead and improve data read and write speed and overall system operating efficiency.

[0028] 8. The external EEPROM memory has the characteristic of not losing data when power is off, ensuring that set parameters, system parameters and key information stored in FLASH (start address, check value, etc.) are stably retained for a long time; after data verification fails, it can automatically clear the erroneous loop block data and read the previously stored data. The standardized hardware connection and communication protocol design enables the device to resist electromagnetic interference, power failure and other emergencies in the mining environment, improving the environmental adaptability and operational stability of the device. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or components are generally identified by similar reference numerals. In the drawings, the elements or components are not necessarily drawn to scale.

[0030] Figure 1 A schematic diagram of the core hardware components and connection structure of the mine protection device in this invention.

[0031] Figure 2 The flowchart for verifying the integrity and correctness of initialization data in this invention.

[0032] Figure 3 The data analysis and classification flowchart of this invention.

[0033] Figure 4 The data control, management, and storage flowchart of this invention.

[0034] Figure 5 Mapping diagram of data recording system module and storage area of ​​mining protection device in the method of the present invention.

[0035] Figure 6 A connection block diagram of the data recording system for a mine protection device according to the present invention. Detailed Implementation

[0036] The embodiments of the technical solution of the present invention will now be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore merely examples and should not be used to limit the scope of protection of the present invention. The specific structure of the present invention is as follows: Figures 1-6 As shown in the image.

[0037] Example 1: A data recording system for a mine protection device, comprising a voltage acquisition circuit, a current acquisition circuit, a digital input circuit, a digital output circuit, a power supply circuit, a CPU, an external EEPROM memory, and an internal FLASH memory; The voltage acquisition circuit and the current acquisition circuit are used to receive AC analog signals and convert them into digital signals before transmitting them to the CPU. The digital input circuit is used to receive external switching signals from the mine protection device and transmit them to the CPU; The CPU is used to determine whether a fault or opening / closing event has occurred according to a pre-set protection logic algorithm, and to control the digital output circuit to output to the relay interface. The external EEPROM memory is used to store setpoint parameters, system parameters, opening and closing records, the latest write address and check value of the internal FLASH, and the number of fault data stored in the internal FLASH. The internal FLASH memory is divided into five separate circular storage blocks for storing fault data.

[0038] It should be explained that: the circuits are electrically connected to the CPU through the standard signal transmission lines inside the mining protection device to ensure stable transmission of digital signals and switching signals; both the external EEPROM memory and the internal FLASH memory establish data interaction connections with the CPU through the SPI communication interface to ensure effective transmission of data read and write instructions; the storage area in the external EEPROM memory used to store the "latest write address of the internal FLASH" is a pre-divided fixed address segment (the starting address of the address segment is 0x0000-0x0003, occupying 4 bytes), the "checksum value" is stored in the address segment 0x0004-0x0005 (occupying 2 bytes), and the "number of fault data stored in the internal FLASH" is stored in the address segment 0x0006-0x0007 (occupying 2 bytes). The above address segments are non-overlapping independent areas to avoid data storage conflicts.

[0039] The voltage and current acquisition circuits convert the AC analog signals of the mine power system into digital signals that the CPU can recognize. The digital input circuit acquires external switching signals and transmits them to the CPU. The CPU analyzes the received signals through a preset protection logic algorithm to determine whether a fault or switching event has occurred. Then, according to the data type, it allocates the relevant data to the external EEPROM memory or the internal FLASH memory for storage. At the same time, the digital output circuit outputs relay control signals to realize the core control function of the protection device.

[0040] The hardware configuration with dual storage media can carry different types of data storage tasks; it can provide a hardware foundation for data classification and storage, ensuring that data with different characteristics has a suitable storage medium; and it can guarantee the stable storage and fast retrieval of various types of data during the operation of the protection device.

[0041] Based on any of the above technical solutions, further optimizations include: a memory initialization module, a data analysis and classification module, a data control and management module, a data writing module, and a data reading module; The memory initialization module is used for CPU pin initialization and verification of the integrity and correctness of stored data; The data analysis and classification module is used to divide the data to be stored into non-fault record data and fault record data, place the read data into the corresponding variables for program execution, and update the data flag bit; The data control and management module is used for external EEPROM storage address management, internal FLASH data writing page number, address, and verification data management, as well as data storage and reading correctness verification, data writing management, and data reading management. The data writing module is used to perform data writing operations, writing non-fault record data to the address corresponding to the external EEPROM memory, and storing fault record data into the internal FLASH memory. The data reading module is used to perform read operations on stored data.

[0042] It should be explained that: all modules are integrated inside the CPU, and function calls are implemented through the CPU's instruction set. The modules interact with each other through an internal data bus. The CPU pin initialization of the memory initialization module specifically configures the pins connected to the storage medium to communication mode (the SPI communication pin is configured as output / input mode, and the clock pin, data input / output pin, and chip select pin are all configured according to the SPI communication protocol). The "external EEPROM storage address management" of the data control management module includes address allocation, address mapping, and address conflict detection functions. The "internal FLASH data writing page number management" specifically manages the page number identification and switching of the five circular memory blocks.

[0043] After the system starts up, the memory initialization module first completes the CPU pin configuration and storage data verification to prepare for data storage; the data analysis and classification module monitors the update status of various types of data in real time, classifies the updated data by type and updates the flag bits; the data control and management module determines the data storage medium and storage address based on the flag bit information, and coordinates the data writing module to perform the write operation; the data reading module reads data from the corresponding storage medium and transmits it to the CPU for program execution according to the system operation requirements. All modules work together to complete the entire process management of data storage and reading.

[0044] The core function of this solution is to provide a full-process software management mechanism for data storage, thereby achieving standardized and orderly data storage. Its functions include: 1) clarifying the responsibilities of each stage of data processing through module division of labor, thereby improving data processing efficiency; 2) ensuring the accuracy and reliability of data storage and retrieval, and avoiding data loss or errors.

[0045] Based on any of the above technical solutions, the following further optimizations are made: the non-fault record data includes setpoint parameters, system parameters, and opening / closing record data; the fault record data includes voltage and current values ​​at the time of the fault.

[0046] It should be explained that: the setpoint parameters are specifically the protection threshold parameters (such as overcurrent protection threshold, overvoltage protection threshold, undervoltage protection threshold, etc.) preset by the mine protection device, and each setpoint parameter has a unique parameter identifier; the system parameters specifically include the device communication address, sampling frequency, working mode, and other configuration parameters that ensure the normal operation of the device; the opening and closing record data specifically includes the opening and closing action time (accurate to the millisecond level), action triggering conditions, action execution results, etc.; the voltage and current values ​​in the fault record data are the instantaneous values ​​of 3 cycles before and after the fault occurred (the sampling frequency is 5kHz, and 20 data points are collected per cycle), and also include the timestamp information of the time of the fault occurrence.

[0047] Based on the different uses and storage requirements of data from mining protection devices, the data is classified and defined. Setpoint parameters, system parameters, and opening / closing records have low update frequencies and low real-time storage requirements, making them suitable for the storage characteristics of external EEPROM memory. Fault record data have high update frequencies (requiring instantaneous storage when a fault occurs) and large data volumes, making them suitable for the high-speed storage characteristics of internal FLASH memory. This classification achieves a precise match between storage media and data characteristics.

[0048] The function of this solution is to clarify the data classification standards and provide a basis for subsequent targeted storage; its functions include: 1) making data storage more targeted and improving the utilization rate of storage resources; 2) facilitating subsequent data retrieval and analysis and improving data usage efficiency.

[0049] Based on any of the above technical solutions, a further optimization is made: the data flag bits include a setting parameter update flag bit, a system parameter update flag bit, a circuit breaker closing record data update flag bit, and a fault record update flag bit.

[0050] It should be explained that: each of the flag bits is a 1-bit binary variable stored in a general-purpose register inside the CPU. The flag bit state is defined as "1" (indicating that the corresponding data has been updated and a storage operation needs to be performed), and the reset state is defined as "0" (indicating that the corresponding data has not been updated and no storage is required); the "N" in the setpoint parameter update flag bit Defdata_Flag[N] is the sequence number of the setpoint parameter (N=1,2,...,n, where n is the total number of setpoint parameters, corresponding one-to-one with the setpoint parameter); the "N" in the system parameter update flag bit Systemdata_Flag[N] is the sequence number of the system parameter (N=1,2,...,m, where m is the total number of system parameters, corresponding one-to-one with the system parameter); the "N" in the switch opening and closing record data update flag bit Switchdata_Flag[N] is the sequence number of the switch opening and closing record (N=1,2,...,p, where p is the maximum number of switch opening and closing records that can be cached); and the fault record update flag bit is a single flag bit FaultRecord_Flag, corresponding to the update status of all fault record data.

[0051] When the data analysis and classification module detects an update to a certain type of data, it immediately sets the corresponding flag bit to "1" and sends a data update signal to the data control and management module. The data control and management module monitors the status of each flag bit in real time. When it detects that a flag bit is "1", it triggers the corresponding data storage process. After the storage operation is completed, the flag bit is reset to "0", completing a closed-loop control of data update-storage.

[0052] The core function of this solution is to accurately identify the data update status through flag bits, providing a clear signal for triggering the storage process; its functions include: 1) enabling on-demand triggering of data storage and avoiding invalid storage query operations; 2) clearly distinguishing the update status of different types of data, facilitating precise scheduling by the data control and management module.

[0053] Based on any of the above technical solutions, a further optimization is made as follows: the starting addresses of the five individually cyclic storage blocks are respectively denoted as FAddress1, FAddress2, FAddress3, FAddress4, and FAddress5, and their numbers are respectively denoted as Block_Num1=1, Block_Num2=2, Block_Num3=3, Block_Num4=4, and Block_Num5=5, and the starting addresses and numbers are stored in an external EEPROM memory.

[0054] It should be explained that: the five circular storage blocks have the same capacity, each with a capacity of 1024 bytes (capable of storing complete data for a single fault, including cycle data before and after the fault, timestamps, etc.); the starting address of each storage block is a fixed address of the internal FLASH memory, specifically FAddress1=0x0000, FAddress2=0x0400, FAddress3=0x0800, FAddress4=0x0C00, FAddress5=0x1000 (address in hexadecimal); the storage format of the starting address and number in the external EEPROM memory is as follows: the number (1 byte) and the starting address (4 bytes) of each storage block are arranged sequentially, the storage starting address is 0x0010, the total number of bytes occupied is 5×(1+4)=25 bytes, and the storage order is Block_Num1 and FAddress1, Block_Num2 and FAddress2...Block_Num5 and FAddress5.

[0055] When the system is used for the first time, the starting addresses and numbers of the five storage blocks are stored in a designated area of ​​the external EEPROM in a fixed format to form a storage block information lookup table. When storing fault data, the data control and management module reads the lookup table from the external EEPROM and determines the starting address of the next storage block according to the latest storage block number, so as to realize the cyclic storage of fault data in the five storage blocks. When the fifth storage block is full, it returns to the first storage block to overwrite the original data.

[0056] The function of this solution is to clarify the division criteria and information storage method of the internal FLASH storage blocks, providing a basis for cyclic storage; its functions include: 1) realizing the cyclic storage of fault data and improving the utilization rate of FLASH storage resources; 2) facilitating the data control and management module to quickly locate the storage address and improve storage efficiency.

[0057] Example 2: Compared with Example 1, this example also includes the following technical features: This invention also provides a control method for a data recording system for mine protection devices, characterized by comprising the following steps: S1: Initialization Operation S1.1: Initialize the FLASH memory, EEPROM memory, and variables to bring the control system into normal operation. S1.2: Determine if the system is being used for the first time. If so, divide the internal FLASH storage area into 5 circular storage blocks; Then, store the starting address (FAddress1, FAddress2, FAddress3, FAddress4, FAddress5) and number (Block_Num1=1, Block_Num2=2, Block_Num3=3, Block_Num4=4, Block_Num5=5) of each memory block into the external EEPROM memory; otherwise, proceed directly to the next step. S1.3: Verify the integrity and correctness of the stored data. If the verification passes, the data is placed in the corresponding variable for system operation. If the verification fails, the corresponding loop block data is cleared and returned to S1.3, and the previously stored data is read again for verification. S2: Data analysis and classification; S3: Data Control Management and Storage S3.1: After the data control management module detects the update flag, it determines the data type to be updated; S3.2: If the data is not a fault record, execute the storage procedure; S3.3: If it is fault record data, execute the following storage process: S3.3.1: Calculate the data storage parameters for this fault based on the latest storage block number (FLASH_Serial) and starting address (FLASH_F) of the internal FLASH stored in the external EEPROM memory; S3.3.2: The data storage block number for this fault is FLASH_Serial + 1, and the starting address of the data storage for this fault is FLASH_F + the length of the FLASH circular storage block; S3.3.3: Perform a FLASH write operation to store the fault data into the FLASH circular storage block calculated above; S3.3.4: After the write operation is completed, update the latest storage block number of the internal FLASH to the storage block number of this operation, update the latest starting address of the internal FLASH to the starting address of this operation, and record the number of data items written this time (DataN). S3.3.5: Calculate the check value CRC_Data of the current fault data. The calculation method is CRC_Data = (Flash_Data[0] + Flash_Data[1] + ... + Flash_Data[DataN-1]) & (0XFF), where Flash_Data[N] is the intermediate variable array storing the current fault data; S3.3.6: Save the updated storage block number, storage starting address, check value CRC_Data, and data count DataN to the external EEPROM memory; S3.3.7: After all data is successfully saved, clear the fault record update flag.

[0058] It needs to be explained that: S1.1 "Initializing the FLASH memory" includes erasing invalid data areas of the FLASH memory and configuring the FLASH read / write timings (write enable timings and erase timings are configured according to the FLASH chip datasheet); "Initializing the EEPROM memory" includes configuring the EEPROM communication timings (SPI clock frequency is set to 1MHz) and detecting the EEPROM connection status; "Initializing variables" includes setting data storage related variables (such as memory block number variables, address variables, checksum variables, etc.) to default values ​​(0 or initial defined values). The specific method for "clearing the corresponding circular block data" in S1.3 is to perform a full erase operation on the circular storage block (according to the full erase instruction of the FLASH chip). "Previous stored data" refers to the data stored in the previous storage block of the current failed verification storage block (e.g., if the current verification of Block_Num3 fails, then the data in Block_Num2 is read). The "storage parameters" in S3.3.1 only include the current storage block number and the starting address, without any other additional parameters. The length of the FLASH circular storage block is 1024 bytes (consistent with the storage block capacity in claim 5).

[0059] After the system starts up, it first completes hardware configuration and data verification through initialization operations, laying the foundation for subsequent data storage; then, it monitors the data update status in real time and classifies and labels it through data analysis and classification steps; finally, the data control and management module triggers the corresponding storage process according to the data type, non-fault data is written to EEPROM, fault data is written to FLASH according to the cyclic storage logic, and the storage information is updated and verified at the same time to ensure the accuracy, order and real-time storage of data.

[0060] The function of this solution is to realize full-process control of data storage for mine protection devices, taking into account the real-time performance, reliability, and lifespan of data storage. Its functions include: 1) standardizing the data storage operation process to ensure that all types of data storage meet technical requirements; 2) improving the reliability of data storage and the utilization rate of storage resources through cyclic storage and verification mechanisms.

[0061] Based on any of the above technical solutions, the following further optimization is made: The specific steps of data analysis and classification in step S2 are as follows: S2.1: Continuously check whether the setpoint parameters, system parameters, opening and closing record data, and fault record data have been updated; S2.2: If the data is not updated, return to S2.1 to continue the detection; if the data is updated, determine whether the updated data type is non-fault record data or fault record data. S2.3: Set the corresponding update flag bit according to the data type. For non-fault record data, set the setting parameter update flag bit, system parameter update flag bit, or opening and closing record data update flag bit. For fault record data, set the fault record update flag bit. S2.4: Transmit the update flag to the data control and management module.

[0062] It needs to be explained that: the detection cycle of "loop detection" in S2.1 is 10 milliseconds, and the detection method is to compare whether the current data is consistent with the stored historical data (both numerical changes and state changes are judged as updates); the update detection of setpoint parameters and system parameters is achieved by comparing the current value of the parameter register with the stored value; the update detection of the opening and closing record data is achieved by monitoring the rising / falling edge of the opening and closing action signal; the update detection of the fault record data is achieved by monitoring the fault trigger signal output by the CPU; the setting operation of the flag bit in S2.3 is achieved by the CPU's bit operation instruction, directly setting the corresponding register bit to "1"; the transmission of the flag bit in S2.4 is achieved by transmitting the value of the register where the flag bit is located to the input interface of the data control management module through the internal data bus.

[0063] The system continuously monitors the status of various data at fixed intervals, identifies data update events through data comparison or signal monitoring, matches and sets the corresponding update flag bit according to the data type, and finally transmits the flag bit signal to the data control and management module to provide accurate basis for triggering subsequent storage processes, ensuring that data updates can be identified and stored in a timely manner.

[0064] The function of this solution is to achieve accurate identification and classification of data updates, providing a guarantee for on-demand triggering of data storage; its functions include: 1) ensuring that no data update events are missed, and ensuring the timeliness of data storage; 2) simplifying the judgment logic of the data control and management module through classification and identification, thereby improving storage efficiency.

[0065] Based on any of the above technical solutions, a further optimization is made: If the data in step S3.2 is non-fault record data, the specific steps for executing the storage process are as follows: S3.2.1: Determine the storage variables and their corresponding storage addresses based on the flag bits and data types (setpoint parameters correspond to the setpoint parameter register address array Def_Data[N], system parameters correspond to the system parameter address array System_Data[N], and switch opening / closing record data correspond to the switch opening / closing record data address array Switch_Data[N]). S3.2.2: Execute the EEPROM data write operation instruction to write the non-fault record data to the corresponding storage address; S3.2.3: After a successful write operation, clear the flag corresponding to the updated data.

[0066] It should be explained that: the address range of the fixed parameter register address array Def_Data[N] is 0x0100-0x03FF (hexadecimal), and the array element Def_Data[N] corresponds one-to-one with the fixed parameter (e.g., Def_Data[0] corresponds to the overcurrent protection threshold, address 0x0100; Def_Data[1] corresponds to the overvoltage protection threshold, address 0x0102, etc.), and each fixed parameter occupies 2 bytes; the address range of the system parameter address array System_Data[N] is 0x0400-0x05FF, and each system parameter occupies 1-4 bytes. (Determined according to parameter type); The address range of the switch-closing record data address array Switch_Data[N] is 0x0600-0x09FF, and each switch-closing record occupies 16 bytes (including action time, trigger condition, execution result and other information); In S3.2.2, the EEPROM data write operation instructions are executed according to the SPI communication protocol, including write enable instruction, page write instruction, address instruction and data instruction. The criterion for judging the success of the write operation is to receive the write success acknowledgment signal returned by the EEPROM; In S3.2.3, the flag bit clearing operation is to set the corresponding flag bit to "0" through the CPU bit operation instruction.

[0067] The data control and management module determines the updated non-fault data type based on the received flag bit, finds the corresponding EEPROM storage address through address array mapping, and then sends a write operation instruction to the EEPROM to write the updated data to the specified address. After the write operation is successful, the flag bit is reset, completing the storage loop of non-fault data and ensuring the stable storage of non-fault data and the accurate status of the flag bit.

[0068] The function of this solution is to achieve accurate and stable storage of non-fault record data, making full use of the storage advantages of EEPROM; its functions include: 1) ensuring the orderly storage of non-fault data, facilitating subsequent query and retrieval; 2) avoiding duplicate storage and improving storage efficiency through the flag clearing mechanism.

[0069] Based on any of the above technical solutions, a further optimization is made: the integrity and correctness verification of the stored data in step S1.3 includes the following sub-steps: S1.3.1: Read the latest memory block number, starting address, check value (CRC_EE), and number of fault data (DataN) stored in the external EEPROM memory. S1.3.2: Determine whether the latest storage block number and the starting address correspond (e.g., the starting address is FAddress1 when the number is 1). If they correspond, proceed to the next step; otherwise, the verification fails. S1.3.3: Read all the data of the latest storage block in the internal FLASH and put it into the intermediate variable array Flash_Data[N]; S1.3.4: Add the first DataN data in the Flash_Data[N] array and keep the lower 8 bits to obtain the check data CRC_Data; S1.3.5: Determine whether CRC_Data and CRC_EE are consistent. If they are consistent, the data is correct (verification passed); if they are inconsistent, the verification fails.

[0070] It needs to be explained that: the external EEPROM storage address read in S1.3.1 is the fixed address range defined in claim 1 (the latest storage block number is stored in 0x0008-0x0008, the starting address is stored in 0x0009-0x000C, the check value CRC_EE is stored in 0x000D-0x000D, and the number of fault data DataN is stored in 0x000E-0x000E); the basis for judging "the number and the starting address correspond" in S1.3.2 is the fixed address range defined in claim 5. The storage block number and starting address lookup table (e.g., number 2 corresponds to starting address 0x0400, number 3 corresponds to 0x0800, etc.); in S1.3.3, "all data of the latest storage block" refers to the 1024 bytes of data of the storage block, the length of the intermediate variable array Flash_Data[N] is 1024, and the data type is 8-bit unsigned integer; in S1.3.4, the data addition operation is performed as decimal addition, and the lower 8 bits are retained, that is, the bitwise AND operation is performed on the addition result and 0xFF to ensure that the result is 8-bit data.

[0071] The integrity and correctness of stored data are verified through a two-step verification process. The first step verifies the correspondence between the storage block number and the starting address to ensure the accuracy of the storage address. The second step compares the stored verification value with the real-time calculated verification value through data summation verification to ensure that the data content has not been tampered with or damaged. This dual verification mechanism provides a guarantee for the reliability of the data.

[0072] The function of this solution is to verify the accuracy and integrity of stored data and prevent erroneous data from entering the system and affecting its operation. Its functions include: 1) ensuring that the data used by the system is true and reliable; 2) promptly detecting data storage errors and triggering the fault tolerance mechanism.

[0073] Based on any of the above technical solutions, the following further optimizations are made: the setting parameter update flag bit in step S2.3 is Defdata_Flag[N], the system parameter update flag bit is Systemdata_Flag[N], the opening and closing record data update flag bit is Switchdata_Flag[N], and the fault record update flag bit is FaultRecord_Flag.

[0074] The calculation method for the verification data in step S3.3.5 is the same as the calculation method for the verification data in step S1.3.4.

[0075] It should be explained that: Defdata_Flag[N], Systemdata_Flag[N], and Switchdata_Flag[N] are all 8-bit register variables, where Defdata_Flag[0] corresponds to the first fixed parameter, Defdata_Flag[1] corresponds to the second fixed parameter, and so on. Each bit of the register can be expanded to correspond to different data items; FaultRecord_Flag is an independent 1-bit variable, used only to indicate whether the fault data has been updated; "The calculation method of the verification data is consistent" specifically means that: both adopt the calculation logic of "adding the first DataN data of the array in decimal + keeping the lower 8 bits (bitwise AND with 0xFF)", and the order of data summation is from the 0th element of the array to the DataN-1th element. The data type is 8-bit unsigned integer, ensuring that the calculation basis of the two verifications is consistent.

[0076] Clearly define the specific identifiers of each data update flag to ensure the uniqueness and accuracy of data classification identifiers; unify the calculation method for verification data to ensure that the verification value after fault data storage is consistent with the calculation logic of the verification value during the initialization phase, thereby ensuring the comparability and accuracy of verification results and avoiding misjudgments due to differences in calculation methods.

[0077] The function of this scheme is to clarify the flag identification and unify the verification calculation logic to ensure the accuracy of data classification identification and verification; its functions include: 1) making the identification and management of flags more standardized; 2) ensuring the consistency of verification data and improving the reliability of verification results.

[0078] It should be explained that the mining protection devices mentioned in this application are commonly used standard equipment in existing mine power systems, such as: mining high-voltage vacuum switch protection devices, mining low-voltage feeder switch protection devices, mining transformer protection devices, mining motor integrated protection devices, mining line protection devices, etc.

[0079] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention. For those skilled in the art, any alternative improvements or transformations made to the implementation of the present invention fall within the protection scope of the present invention.

[0080] Any aspects of this invention not described in detail are well-known to those skilled in the art.

Claims

1. A data recording system for a mine protection device, characterized by: The voltage acquisition circuit, the current acquisition circuit, the digital input circuit, the digital output circuit, the power supply circuit, the CPU, the external EEPROM memory and the internal FLASH memory are included. The voltage acquisition circuit and the current acquisition circuit are used for receiving AC analog signals and converting the AC analog signals into digital signals and then transmitting the digital signals to the CPU. The digital input circuit is used for receiving switch signals outside the mine protection device and transmitting the switch signals to the CPU. The CPU is used for judging whether a fault and a switching event occur according to a pre-set protection logic algorithm and controlling the digital output circuit to output to a relay interface. The external EEPROM memory is used for storing fixed value parameters, system parameters, switching records, the latest writing address and check value of the internal FLASH memory and the number of fault data stored in the internal FLASH memory. The storage area of the internal FLASH memory is divided into five separate cyclic storage blocks and is used for storing fault data.

2. The system of claim 1, wherein: The memory initialization module, the data analysis and classification module, the data control and management module, the data writing module and the data reading module are further included. The memory initialization module is used for initializing CPU pins, verifying the integrity and correctness of stored data. The data analysis and classification module is used for classifying the data to be stored into non-fault record data and fault record data, placing the read data into corresponding variables for program running and updating data flag bits. The data control and management module is used for managing the external EEPROM storage address, the internal FLASH data writing page code, address and check data, verifying the correctness of data storage and reading, managing data writing and reading. The data writing module is used for performing data writing operation, writing non-fault record data into the corresponding address of the external EEPROM memory and storing fault record data into the internal FLASH memory. The data reading module is used for performing data reading operation.

3. The system of claim 2, wherein: The non-fault record data includes fixed value parameters, system parameters and switching record data, and the fault record data includes voltage value and current value parameters when a fault occurs.

4. The system of claim 3, wherein: The data flag bits include fixed value parameter update flag bit, system parameter update flag bit, switching record data update flag bit and fault record update flag bit.

5. The system of claim 4, wherein: The first addresses of the five separate cyclic storage blocks are respectively FAddress1, FAddress2, FAddress3, FAddress4 and FAddress5, and the numbers are respectively Block_Num1=1, Block_Num2=2, Block_Num3=3, Block_Num4=4 and Block_Num5=5, and the first addresses and numbers are stored in the external EEPROM memory.

6. A control method of a data recording system for a mine protection device, characterized by: The following steps are included: S1: initialization operation S1.1: initializing the FLASH memory, the EEPROM memory and variables to make the control system enter a normal running state. S1.2: Determine whether the system is used for the first time, if yes, divide the internal FLASH storage area into 5 cyclic storage blocks; And store the first address and number of each storage block to the external EEPROM memory; if not, directly enter the next step; S1.3: Verify the integrity and correctness of the stored data, and if the verification is passed, place the data into the corresponding variable for system operation, if the verification fails, clear the corresponding cyclic block data and return to S1.3 to re-read the last stored data for verification; S2: Data analysis and classification; S3: Data control management and storage S3.1: The data control management module detects the update flag bit, and judges the update data type; S3.2: If it is non-fault record data, execute the storage process; S3.3: If it is fault record data, execute the following storage process: S3.3.1: Calculate the fault data storage parameters according to the latest internal FLASH storage block number and first address stored in the external EEPROM memory; S3.3.2: This time fault data storage block number = FLASH_Serial + 1, this time fault data storage first address = FLASH_F + FLASH cyclic storage block length; S3.3.3: Perform FLASH write operation to store this time fault data into the above calculated FLASH cyclic storage block; S3.3.4: After the write operation is completed, update the latest internal FLASH storage block number to this time storage block number, update the latest internal FLASH first address to this time storage first address, and record the number of data written this time; S3.3.5: Calculate the CRC_Data of this time fault data, the calculation method is CRC_Data = (Flash_Data[0] + Flash_Data[1] + … + Flash_Data[DataN-1]) & (0XFF), where Flash_Data[N] is an intermediate variable array for storing this time fault data; S3.3.6: Save the updated storage block number, storage first address, CRC_Data, and DataN to the external EEPROM memory; S3.3.7: After all data is saved successfully, clear the fault record update flag bit.

7. The control method according to claim 6, characterized in that: The specific steps of data analysis and classification in step S2 are: S2.1: Loop to detect whether the fixed value parameter, system parameter, closing and opening record data, and fault record data have been updated; S2.2: If the data has not been updated, return to S2.1 to continue detection; if the data has been updated, judge the update data type as non-fault record data or fault record data; S2.3: According to the data type, set the corresponding update flag bit, wherein the non-fault record data corresponds to set the fixed value parameter update flag bit, system parameter update flag bit, or closing and opening record data update flag bit, and the fault record data corresponds to set the fault record update flag bit; S2.4: Transmit the update flag bit to the data control management module.

Images