Automatic identification method and system for closed-loop network topology of high-voltage distribution network

Abstract

The invention relates to the technical field of power system automation, in particular to a closed-loop network topology automatic identification method and system for a high-voltage power distribution network. The method comprises the following steps: when a fault occurs, acquiring a fault current direction of each intelligent terminal, and dividing a power flow direction region according to the fault current direction; synchronously acquiring the fault waveform arrival time recorded by each terminal; determining the distance sequence between each switch and the fault point in each region according to the waveform arrival time; a complete topology is generated based on the sequence. The system comprises distributed intelligent terminals, and each terminal is provided with a clock synchronization module, a direction detection module, a waveform monitoring module and a processing module. According to the invention, through dual criteria of the current direction and the waveform arrival time, the topology identification problem caused by multiple power supplies and bidirectional power flow of a closed-loop system is solved, full-automatic, dynamic and high-precision topology identification and updating are realized, manual configuration is not needed, and the adaptability of intelligent distributed protection is remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power system automation, in particular to a closed-loop network topology automatic identification method and system for high-voltage distribution network. BACKGROUND

[0002] With the rapid development of communication technology, intelligent distributed protection function of distribution network has become the preferred solution for fault handling isolation technology due to its high reliability, rapidity, selectivity and sensitivity. Intelligent distributed protection uses peer-to-peer communication network to share the data information, fault discrimination information and switch state information detected by each switch protection unit with adjacent switches in real time, so that protections at different locations can coordinate and cooperate within milliseconds to minimize the range and time of power failure.

[0003] Currently, in the distribution network system, the upstream and downstream relationship of the switch required by the intelligent distributed function is generally configured manually before system operation. If the network structure changes or the position relationship of adjacent switches needs to be adjusted, the staff needs to manually modify, resulting in tedious and inefficient operation and maintenance. In the open-loop system, existing solutions identify the network topology in the one-way system by judging the phase of the voltage waveform. For example, by measuring the initial phase difference of the voltage waveform between different terminals, combining the known signal propagation speed, and calculating the physical distance and relative position relationship between nodes, the automatic topology identification is realized.

[0004] However, the above method based on voltage phase is only applicable to open-loop systems with single power supply and fixed current direction. In the closed-loop system with multiple power sources and ring structure, the current direction changes dynamically during fault, which may cause the same node to receive voltage signals from different directions, resulting in phase value conflict and direction confusion, making the one-way phase sorting method invalid. In addition, when the network structure is adjusted (such as adding a switch or a power source), the existing solution cannot adapt dynamically and still needs manual intervention, which seriously limits the wide application of intelligent distributed protection in closed-loop distribution network.

[0005] Therefore, there is an urgent need in the art for a method that can automatically and dynamically identify the network topology in a closed-loop system. SUMMARY

[0006] The present application aims to overcome the shortcomings of the prior art and provide a closed-loop network topology automatic identification method and system for high-voltage distribution network, to solve the technical problem of automatic topology identification in a closed-loop system due to multiple power sources, bidirectional power flow and dynamic topology changes, significantly reducing manual intervention and improving the adaptability of intelligent distributed protection function.

[0007] To achieve the above-mentioned application purposes, the present application adopts the following technical solutions: In a first aspect, the present application provides a method for automatically identifying a closed-loop network topology of a high-voltage power distribution network, comprising the following steps: In response to a fault occurring in the power distribution network, obtaining fault current direction information detected by a plurality of intelligent terminals; Based on the fault current direction information, dividing switches corresponding to the plurality of intelligent terminals into at least two power flow direction areas; Obtaining fault waveform arrival time information recorded by the plurality of intelligent terminals based on high-precision time synchronization; For each of the power flow direction areas, determining a distance order of each switch in the area relative to a fault point based on fault waveform arrival time information recorded by each intelligent terminal in the area; Based on at least the distance order in each of the power flow direction areas, generating a topology structure of the power distribution network.

[0008] Preferably, the step of dividing power flow direction areas based on fault current direction information comprises: dividing switches with positive fault current direction into positive power flow direction areas, and dividing switches with negative fault current direction into negative power flow direction areas.

[0009] Preferably, the step of determining the distance order comprises: for switches in the same power flow direction area, determining the switch with the earliest fault waveform arrival time as the switch closest to the fault point, and sorting all switches in the area according to the order of fault waveform arrival time.

[0010] Preferably, the step of generating the topology structure comprises: determining switches judged to be closest to the fault point in different power flow direction areas as switch association relationships directly adjacent to each other.

[0011] Preferably, the high-precision time synchronization is achieved by receiving and decoding an IRIG-B code signal, and the time synchronization error between the plurality of intelligent terminals is less than 1 microsecond.

[0012] Preferably, the fault waveform comprises a voltage waveform and a current waveform; and the step of obtaining fault waveform arrival time information comprises extracting high-frequency transient characteristics of the waveforms, and taking the arrival point of the high-frequency transient characteristics as the waveform arrival time.

[0013] Preferably, the method further comprises: when a change in the grid structure of the power distribution network is detected, automatically executing the topology automatic identification method to update the topology structure.

[0014] In a second aspect, the present application provides a system for automatically identifying a closed-loop network topology of a high-voltage power distribution network, for implementing the above method, the system comprising a plurality of intelligent terminals distributed at each switch of the power distribution network; each of the intelligent terminals comprising: A high-precision clock synchronization module is configured to synchronize with an external time reference signal. A current direction detection module is configured to detect a fault current direction. A waveform monitoring module is configured to collect a fault waveform and record a time of arrival of the fault waveform. A processing module is configured to perform the following operations: exchanging the fault current direction and the time of arrival of the fault waveform with other intelligent terminals; dividing a power flow direction area based on received fault current direction information; sorting switches in a respective power flow direction area based on received fault waveform time of arrival information; and generating a topology structure according to a sorting result and a division result.

[0015] Preferably, the waveform monitoring module includes a high-speed analog-to-digital converter and a high-speed memory, which are configured to capture and store high-frequency transient characteristics of the waveform.

[0016] Preferably, the high-precision clock synchronization module is an IRIG-B code decoding module.

[0017] Compared with the prior art, the application has the following beneficial effects: Dual criteria, accurate and reliable: By combining current direction discrimination and fault waveform time of arrival detection, the application effectively solves the phase confusion problem caused by bidirectional power flow in a closed-loop system, and achieves accurate topology identification and fault location in complex scenarios.

[0018] Fully automatic and dynamically adaptive: The application does not require manual pre-configuration of topology relationships, and can automatically complete identification when a fault occurs, and automatically trigger topology reconstruction when the network structure changes (such as adding a node or switch failure), thereby achieving true full automation and dynamic adaptation, and greatly reducing the amount of operation and maintenance work.

[0019] High compatibility and practicality: By introducing high-precision time synchronization (such as IRIG-B) and capturing high-frequency transient characteristics of the fault waveform, the application ensures the identification accuracy and reliability of the method in complex closed-loop scenarios such as multi-source and ring networks, and effectively promotes the large-scale application of intelligent distributed protection in distribution networks. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description of embodiments of the present application, taken in conjunction with the accompanying drawings. The accompanying drawings are provided to aid in the understanding of the present application, and constitute a part of the specification, together with the present application, and serve to explain the present application, but do not constitute a limitation on the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0021] Figure 1 is a partial schematic diagram of a power grid provided by an embodiment of the present application; Figure 2 is a flowchart of a high-voltage power distribution network closed-loop network topology automatic identification method provided by an embodiment of the present application; Figure 3 is a principle diagram of the method provided by an embodiment of the present application; Figure 4 is a principle diagram of the method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0023] In the description of the present application, the term “power flow area” refers to a logical group dynamically divided according to the fault current direction (positive direction or reverse direction) detected by the intelligent terminal when a fault occurs. The purpose of dividing the power area is to group the switches with the same power flow direction, so as to simplify a complex closed-loop network with multiple power sources and bidirectional power flow into multiple logical sections with single internal power flow, and to create necessary conditions for subsequent accurate sequencing based on waveform arrival time. It should be noted that the “power area” is a dynamic logical concept used to assist topology analysis, which is different from the physical “fault area” determined after fault location.

[0024] Referring to Figure 1 , which shows a typical high-voltage power distribution network closed-loop system, including outgoing circuit breakers CB1 and CB2 of two substations, and multiple intelligent switches S1 to S5. In normal operation, all switches are in the closed state, forming a ring-shaped power supply network.

[0025] The high-voltage power distribution network closed-loop network topology automatic identification method of the embodiment of the present application is cooperatively executed by the intelligent terminals distributed at each switch. The flow thereof is shown in Figure 2 , and specifically includes: Step 201, in response to a fault occurring in the power distribution network, acquiring fault current direction information detected by multiple intelligent terminals; This step is the initialization triggering and preliminary information collection stage of topology identification. The purpose is to start the automatic identification process and provide core criteria for subsequent area division.

[0026] When a short circuit, grounding or other fault occurs in the power distribution network line, a fault current much larger than the normal level will be generated. The current direction detection module (for example, based on the principle of power direction relay) of each intelligent terminal (such as installed at switches S1-S5) will start immediately.

[0027] Each terminal independently detects and judges the fault current direction flowing through the switch, defined as "positive direction" or "negative direction". The direction is relative to the pre-agreed power reference direction (for example, positive from the substation bus to the line). Then, all terminals broadcast their respective fault current direction information to other terminals in the network or upload to the centralized master station within milliseconds through the communication module (such as optical Ethernet or wireless private network). At this point, each processing unit has obtained the fault current direction information set of all related terminals in the network.

[0028] Step 202, based on the fault current direction information, dividing the switches corresponding to the plurality of intelligent terminals into at least two power flow regions; This step is one of the key innovations of the application to solve the problem of closed-loop system. The purpose is to simplify the complex, bidirectional flow closed-loop network into multiple logical sections with consistent internal power flow direction, laying the foundation for subsequent accurate ordering based on unidirectional wave propagation.

[0029] The processing module (which can be distributedly deployed at each terminal or centrally at the master station) executes a classification algorithm according to the collected current direction information. All switches reporting "positive direction" fault current are divided into positive power regions; all switches reporting "negative direction" fault current are divided into negative power regions.

[0030] Combined with the embodiment: refer to Figure 1 When fault occurs at point F, switches S1, S2, S3 detect positive direction fault current and are divided into positive power regions; switches S4, S5 detect negative direction fault current and are divided into negative power regions. The two regions are logically bounded by fault point F.

[0031] Step 203, obtaining fault waveform arrival time information recorded by the plurality of intelligent terminals based on high-precision time synchronization; This step provides another dimension of high-precision measurement information for topology identification. Time synchronization is the prerequisite for ensuring the comparability of "arrival time", and fault waveform arrival time is the direct basis for calculating relative distance.

[0032] At the moment of fault occurrence, the fault point will generate a high-frequency transient electromagnetic wave (fault traveling wave), which propagates along the line at a speed close to light speed to both sides. The waveform monitoring module (including high-speed AD converter and large-capacity memory) of each intelligent terminal will capture and record the voltage and current waveforms.

[0033] The processing unit in the module extracts the high-frequency transient feature (such as the wave head) in the waveform, and records the arrival time of the feature point as the "first time". Since all terminals have achieved high-precision time synchronization of less than 1 microsecond through the IRIG-B code decoding module, the "first time" from different terminals is comparable.

[0034] Each terminal exchanges the fault waveform arrival time information recorded by each terminal through the communication network.

[0035] Step 204, for each power flow area, based on the fault waveform arrival time information recorded by each intelligent terminal in the area, determine the distance order of each switch in the area relative to the fault point; This step is to perform accurate ordering and positioning in each "subset" divided in step 202. It uses the physical principle that the arrival time is proportional to the distance when the fault wave propagates in the same propagation medium (conductor) in a single direction.

[0036] The processing module processes the switches in the forward power area and the reverse power area respectively.

[0037] For switches in the same area, directly compare the arrival time of the fault waveform. The earlier the arrival time, the closer the switch is to the fault point.

[0038] In the forward power area, compare the arrival times of S1, S2, and S3. Assuming the order is T_S3 < T_S2 < T_S1, it can be determined that in this area, the order of switches from the nearest to the farthest fault point is: S3 → S2 → S1. Similarly, in the reverse power area, if T_S4 < T_S5, the order is S4 → S5.

[0039] Step 205, based at least on the distance order in each of the power flow areas, generate the topology of the power distribution network.

[0040] This step is the final output of the process, which integrates the analysis results of the previous steps into a complete network topology graph that can be used by the protection system.

[0041] The key operation is to find the boundaries of different power areas. The switch closest to the fault point in each area (i.e. the switch with the earliest arrival time) is associated as a direct adjacent relationship.

[0042] The complete topology can be constructed by combining the order within the region and the adjacent relationship between the regions. For example, according to the order result of step 204, the order of the forward region is S1←S2←S3, and the order of the reverse region is S4→S5. Since S3 and S4 are determined to be directly adjacent, the complete path is CB1←S1←S2←S3—S4→S5→CB2.

[0043] The processing module finally generates a switch adjacent relationship table and / or a ring network topology graph, which is provided for the intelligent distributed protection function or used for graphical display of the power distribution automation system.

[0044] In some embodiments, the step of dividing the switches corresponding to the plurality of intelligent terminals into at least two power flow regions includes: dividing the switches with positive fault current directions into a forward power region; and dividing the switches with negative fault current directions into a reverse power region.

[0045] The obtained network-wide fault current direction information is used as the first key criterion for topology analysis, i.e., power flow region division. The purpose of this step is to dynamically divide the closed-loop network physically connected together into several sections with consistent internal power flow directions, so as to lay a foundation for subsequent accurate ranging and ordering relying on the unidirectional wave propagation characteristics.

[0046] The physical principle is that when a fault occurs in a closed-loop system, the fault point becomes a concave point of voltage in the system, and the fault current will flow from all connected power sources to the point. Therefore, all switches detecting the current flowing to the fault point (defined as the positive direction) are located on the same electrical side of the fault point, and all switches detecting the current flowing out of the fault point (defined as the negative direction, usually flowing to another power source or load) are located on the other electrical side of the fault point.

[0047] The complete topology can be constructed by combining the order within the region and the adjacent relationship between the regions. For example, according to the order result of step 204, the order of the forward region is S1←S2←S3, and the order of the reverse region is S4→S5. Since S3 and S4 are determined to be directly adjacent, the complete path is CB1←S1←S2←S3—S4→S5→CB2. Figure 1 The embodiments are described as follows: when the fault point F occurs, the switches S1, S2, and S3 detect the fault current direction from the CB1 power source side to the fault point F, and are divided into the forward power region; the switches S4 and S5 detect the fault current direction from the fault point F to the CB2 power source side (or the load in the CB2 direction), and are divided into the reverse power region. Through this division, the complex closed-loop network is dynamically simplified into two logical sub-networks with clear unidirectional power flow: one sub-network (the forward region) contains the path from CB1 to the fault point, and the other sub-network (the reverse region) contains the path from the fault point to CB2. This simplification is one of the core innovations of the present application for solving the bidirectional power flow interference problem of the closed-loop system, which enables the subsequent application of the wave arrival time-based ordering algorithm in each region independently and accurately, like processing an open-loop system.

[0048] In some embodiments, the step of determining the distance order of each switch in each power flow region relative to the fault point based on the fault waveform arrival time information recorded by each smart terminal in the region includes: for switches in the same power flow region, determining the switch with the earliest fault waveform arrival time as the switch closest to the fault point; and sorting all switches in the region according to the order of fault waveform arrival times.

[0049] After completing the power flow direction region division, the processing module performs the second key criterion of topology analysis—distance measurement and sorting based on high-precision time information. The purpose of this step is to accurately calculate the relative electrical distance between each switch and the fault point under the same power flow direction by utilizing the physical characteristic that fault traveling waves propagate unidirectionally at a near-constant high speed (near the speed of light) on the conductor, thereby establishing their positional order within the region.

[0050] Its technical principle is as follows Figure 2 and Figure 3 As shown.

[0051] in, L Line length; l 1 ,l 2: Distance from the fault point to the smart terminal; T M1 ,T N1 The arrival time of the waveform; the formula is as follows:

[0052] The transient voltage / current traveling wave generated when a fault occurs propagates from the fault point F along the line to both sides. Within a predefined power flow region, the waveform propagates in a single direction. According to wave theory, on the same uniform transmission line, the propagation time of the traveling wave ( t ) and propagation distance ( l Satisfying the relation : l = v * t, in v It is the speed of wave (close to the speed of light). Therefore, for waves originating from the same point (the point of failure)... F The earlier the waveform of a certain monitoring point arrives, the closer that point is to the fault point.

[0053] Specifically, after receiving the "fault waveform arrival time" reported by each smart terminal in the area, which has been strictly synchronized, the processing module executes the following logic: Locate the nearest switch: Compare the waveform arrival times of all switches in the area, and determine the switch with the smallest timestamp (i.e. the earliest arrival) as the switch closest to the fault point in the area.

[0054] Total order arrangement: Arrange the remaining switches in the order of the waveform arrival time. The switch that arrives later in time is determined to be farther from the fault point.

[0055] Generation order: Finally, output the list of switch orders from the fault point, from near to far, within the power flow area.

[0056] Take Figure 1 the previously divided forward power area (including S1, S2, S3) as an example for illustration: Assume that the processing module obtains the waveform arrival times of the three as T_S3 < T_S2 < T_S1. According to the above criterion, it can be immediately determined that S3 is the switch closest to the fault point F within the area. Furthermore, the distance order of the switches from the fault point F to the power supply CB1 direction is determined as: S3 (closest) → S2 → S1 (farthest). Similarly, within the reverse power area (including S4, S5), if T_S4 < T_S5, then the distance order of the switches from the fault point F to the power supply CB2 direction is determined as: S4 (closest) → S5.

[0057] The technical effect of this step is that: by combining with step S202 (area division), the globally complex problem of closed-loop network topology recognition is decomposed into simple "time - distance" linear sorting problems within multiple areas. It overcomes the inherent problem of the chaotic phase relationship caused by bidirectional current in the closed-loop system, and uses the natural "ranging signal" of the fault transient waveform and the time synchronization technology with nanosecond-level accuracy to achieve an objective, accurate, and automated determination of the switch position relationship, which is the core link to ensure the accuracy of the final topology generation result.

[0058] In some embodiments, the step of generating the topology structure of the distribution network at least based on the distance order within each power flow area includes: determining the switch determined to be the closest to the fault point within different power flow areas as directly adjacent switch association relationships.

[0059] The core logic of this step is to identify and establish the boundaries between areas. The fault point F electrically separates different power flow areas, and physically, it must be located on a certain section of the line, and the two ends of this section of the line are exactly the two switches that belong to two different areas and are each the closest to the fault point. Therefore, these two switches are directly electrically connected neighbors in the physical network.

[0060] During specific implementation, the processing module performs the following operations: Extract key nodes: From the "distance order" list of each power flow area, extract the switch ranked first, that is, the switch determined to be the closest to the fault point. As Figure 1 in the embodiment, the closest switch in the forward area is S3, and the closest switch in the reverse area is S4.

[0061] Establishing association: Establishing the logical association of the two "closest switches" (S3 and S4) from different areas as "directly adjacent". This means that in the generated topology relationship, S3 and S4 are marked as having a direct physical connection.

[0062] Synthesizing complete topology: In the forward power area, there is already a partial sequence from the fault point side to the power source side: S3 → S2 → S1 → CB1.

[0063] In the reverse power area, there is already a partial sequence from the fault point side to the power source side: S4 → S5 → CB2.

[0064] By establishing the S3-S4 adjacent relationship, the two partial paths are connected at the "fault point", and the complete topology path that runs through the entire ring network is obtained: CB1 ← S1 ← S2 ← S3 — S4 → S5 → CB2.

[0065] Output result: The processing module finally formats the above results into a switch adjacent relationship table and / or a visual ring network topology diagram for the power distribution automation master station system, intelligent distributed protection module, or other advanced applications to call.

[0066] The technical effect and invention point of this step is that it creatively uses the electrical quantity information (current direction, waveform arrival time) at the fault moment to deduce the physical connection relationship of the network in reverse, realizing the leap from "logical grouping sequence" to "physical topology reconstruction". In particular, by identifying and associating the "closest switches" in different power areas, the fault section is cleverly located and the structure of the entire network is determined, thereby realizing the full-automatic, dynamic, and high-precision identification of the closed-loop distribution network wiring mode without any manual preset topology, providing a crucial foundation for the correct action of intelligent distributed protection and network self-healing reconstruction.

[0067] In some embodiments, the high-precision time synchronization is achieved by receiving and decoding an IRIG-B code signal, and the time synchronization error between the plurality of intelligent terminals is less than 1 microsecond.

[0068] To achieve accurate comparison of fault waveform arrival time in step S203, one key technical basis of the present application is to establish a global unified and high-precision time reference. This step is usually performed as a background condition for system initialization or continuous operation, providing a synchronization signal for the local clock of all intelligent terminals. The specific implementation is as follows: Time source and signal distribution: A high-precision clock source (such as a Beidou / GPS dual-mode timing clock) is deployed in the substation or main station of the distribution network. The clock source generates a standard IRIG-B (Inter-Range Instrumentation Group-B) time code signal. IRIG-B code is a standardized time serial code widely used in the fields of electric power, military industry, etc. The signal can be distributed to each intelligent terminal in the network through physical media such as optical fiber, coaxial cable or Ethernet in a broadcast or point-to-point manner.

[0069] Terminal synchronization module: Each intelligent terminal has an IRIG-B code decoding module integrated inside. The module continuously receives the IRIG-B code signal from the time source, decodes the absolute time containing year, day, hour, minute, second, and even millisecond and microsecond information in real time, and uses this signal to strictly calibrate and lock the local clock (such as a high-stability crystal oscillator) inside the terminal.

[0070] Precision guarantee: Through the above mechanism, the local clocks of all intelligent terminals are synchronized to the same time reference. The synchronization error of less than 1 microsecond is a key performance indicator achieved by this embodiment. This level of precision means that even if the terminals are distributed in different geographical locations, the time stamps of any events recorded by them are controlled within 1 microsecond. For a fault traveling wave propagating at near light speed (about 300 meters per second), a time error of 1 microsecond corresponds to a distance error of only about 300 meters, which is acceptable in the scale of distribution network lines (usually kilometers), thereby ensuring the accuracy and reliability of subsequent calculations of relative distance using time difference.

[0071] Provide a reference for fault analysis: When a fault occurs, the arrival time of the high-frequency transient characteristics recorded by each terminal waveform monitoring module is given a time stamp based on this high-precision synchronization clock. These high-precision time-stamped information has direct comparability when interacting or uploading between terminals, and is a prerequisite for accurate time sorting and distance calculation in step S204.

[0072] The technical advantage of using IRIG-B code to achieve high-precision synchronization is that its signal format is standard and has strong anti-interference ability, especially suitable for use in complex electromagnetic environments such as power sites. The present invention integrates it into distributed intelligent terminals to build a monitoring system with a unified time scale of microseconds throughout the network, fundamentally solving the problem of time consistency of distributed sampling data and providing a solid technical foundation for the topology identification method based on accurate transient traveling wave distance measurement. This is one of the core technical features that distinguishes the traditional scheme and achieves the beneficial effects of the present invention.

[0073] In some embodiments, the fault waveform comprises a voltage waveform and a current waveform; and the step of obtaining the fault waveform arrival time information comprises extracting a high-frequency transient feature of the waveform, and taking the arrival point of the high-frequency transient feature as the waveform arrival time.

[0074] To perform the key operation of accurately recording the "fault waveform arrival time" in step S203, it is necessary to clearly define what is an effective "fault waveform" and how to extract an accurate time point therefrom. Embodiments of the present application provide specific and efficient technical solutions therefor. The specific implementation and technical principles are as follows: The present application simultaneously monitors voltage waveforms and current waveforms. At the moment (microsecond level) of fault occurrence, the voltage on the line will mutate, accompanied by a huge fault current. The transient processes of these two electrical quantities both contain rich fault information. Monitoring the double waveforms improves the redundancy and reliability of the information, and even in the case of interference to one kind of signal, the other kind of signal can still be used for accurate judgment.

[0075] Traditional protection mainly focuses on the amplitude and phase of power frequency quantities, but at the initial moment (usually within several microseconds to several hundred microseconds) of fault occurrence, high-frequency transient components with frequencies from hundreds of hertz to tens of kilohertz or even higher are generated. These components propagate in the form of traveling waves. The waveform monitoring module (containing a high-speed analog-to-digital converter, with a sampling rate usually reaching 1 MHz or higher) of the intelligent terminal can capture this transient process.

[0076] The module applies digital signal processing algorithms (such as wavelet transform, difference method or Hilbert-Huang transform) to the captured raw voltage and current waveform data to filter out power frequency components and noise, and extract the most dramatic and highest frequency part of the waveform, i.e. the "high-frequency transient feature". This feature point usually corresponds to the wave head generated at the fault initiation moment.

[0077] The "waveform arrival time" is not the ambiguous moment when the entire wave packet starts to distort, but is precisely defined as the moment when the first obvious mutation point (i.e. the wave head) of the above-mentioned high-frequency transient feature arrives.

[0078] Time marking: when the processing algorithm identifies the feature point, the waveform monitoring module immediately reads the local high-precision clock synchronized by the IRIG-B code, and marks the feature point with a time stamp accurate to the microsecond level. This time stamp is recorded as the "waveform arrival time".

[0079] The technical advantages and invention points of selecting the high-frequency transient feature as the arrival time criterion are as follows: Interference resistance and high precision: Power frequency signals change slowly, making it difficult to determine the precise arrival point at the nanosecond to microsecond level. High-frequency transient wavefronts are steep and change extremely rapidly, and their time position can be located very precisely (the error can be controlled at the sub-microsecond level), which directly determines the accuracy of subsequent ranging.

[0080] The key to solving the challenges of closed-loop systems lies in the fact that in closed-loop, multi-source systems, after a fault, power frequency currents from different directions may superimpose or cancel each other out, leading to confusion in amplitude and phase information. However, the initial traveling wave (high-frequency transient) propagates independently from the fault point in all directions, and its arrival time at each monitoring point depends only on the physical distance and wave velocity, unaffected by subsequent complex steady-state power flows. This makes it an ideal information source for unambiguous, high-precision time measurements in complex network environments.

[0081] This lays the foundation for accurate ranging: It is based on this high-precision and highly deterministic time mark that the calculation model of "time difference represents distance difference" in step S204 can be established, thus realizing the technological leap from the traditional "amplitude / phase comparison" to the more accurate "traveling wave head time mark and comparison".

[0082] In summary, this embodiment obtains high-quality, high-precision raw measurement data by accurately extracting and timing the high-frequency transient features in the fault voltage and current waveforms. This is the source guarantee for the high reliability and high precision of the entire topology automatic identification method.

[0083] In some embodiments, when a change in the grid structure of the distribution network is detected, the automatic topology identification method is automatically executed to update the topology.

[0084] The automatic topology identification method described in this invention not only completes topology identification in a single step when a fault occurs, but more importantly, it possesses dynamic adaptability and self-healing reconstruction capabilities. This function ensures that the system can continuously maintain the accuracy of the topology model throughout the network's operational lifecycle without any manual maintenance. Its specific implementation methods, triggering conditions, and technical effects are as follows: 1. Detection of changes in space frame structures Changes in the space frame structure can be detected through various automatic or semi-automatic methods, including but not limited to: Sudden changes in operating status: Remote control opening / closing operations of switches and tripping caused by protection actions will alter the electrical connections of the network. These events can be captured directly and in real time through remote control signals from the automation system or auxiliary contact change information of switches.

[0085] Active scanning and communication discovery: The system can periodically or after receiving maintenance instructions, actively probe through the communication links between smart terminals to discover newly connected terminal devices or identify offline (failed) terminals.

[0086] Manual input: After completing physical construction (such as adding a line or a switch), maintenance personnel can manually trigger a topology update process through the main station system.

[0087] 2. Automatic Triggering and Execution Once the system (the management unit in the main station or distributed intelligent terminals) confirms that the network structure has undergone a valid change, a complete topology identification process is automatically triggered. This process is the re-execution of the core method of this invention: Waiting for a triggering event: The system does not need to continuously inject faults or wait for actual faults to occur. Instead, it treats the next line fault as a natural, cost-free "test signal".

[0088] Process reuse: When a fault occurs, the system will fully reuse the entire process of the aforementioned steps S201 to S205: based on the new physical network, the current direction is redefined, waveform time is recorded, sorting is performed within the region and cross-regional association is performed, and the entire network topology is generated and updated.

[0089] 3. Topology Update and Activation The newly generated topology will automatically replace the existing topology configuration and take effect immediately: Data Update: The network model and graphical wiring diagram of the distribution automation master station will be updated automatically.

[0090] Protection setting / logic reconfiguration: The intelligent distributed protection function will dynamically adjust or confirm the upstream and downstream relationships, communication objects and action logic in its protection criteria based on new and accurate topology relationships, ensuring that the selectivity, speed and reliability of protection are not affected by network changes.

[0091] Seamless switching: The entire update process is completed automatically by the system, without any interruption or negative impact on the normal operation of the power grid and its fault handling capabilities.

[0092] The core inventive point and significant progress embodied in this embodiment are as follows: Achieving true "plug and play" and maintenance-free operation: Overcoming the heavy burden of manual reconfiguration and verification required for any network changes in existing technologies, greatly reducing operation and maintenance costs and improving system availability.

[0093] Ensuring long-term reliability: It ensures that the topology foundation upon which advanced applications such as intelligent distributed protection rely remains consistent with physical reality, avoiding the significant risk of protection malfunctions or failures due to outdated models.

[0094] Supporting the development of flexible distribution networks: It perfectly adapts to the development trend of frequent access of distributed power sources, dynamic load changes, and flexible network topology reconfiguration in future distribution networks, providing key basic support technologies for highly resilient distribution networks.

[0095] This dynamic self-healing function, combined with the aforementioned dual-criteria identification method, constitutes a complete, closed-loop, and intelligent distribution network topology autonomous management system. This is a key manifestation of the value of this invention extending from "method innovation" to "system-level solution".

[0096] The system embodiments of this application can be used to execute the method embodiments of this application. For details not disclosed in the system embodiments of this application, please refer to the method embodiments of this application.

[0097] A high-voltage distribution network closed-loop network topology automatic identification system, used to implement the method described above, the system comprising: Multiple smart terminals are distributed and configured at various switches in the power distribution network; Each of the aforementioned smart terminals includes: A high-precision clock synchronization module is used for synchronization with an external time reference signal; Current direction detection module, used to detect the direction of fault current; The waveform monitoring module is used to acquire fault waveforms and record their arrival time; The processing module is configured to perform the following operations: Exchange the direction of the fault current and the arrival time of the fault waveform with other intelligent terminals; Power flow direction region is divided based on the received fault current direction information; Based on the arrival time information of the received fault waveform, the switches are sorted in their respective power flow regions; A topology is generated based on the sorting and region partitioning results.

[0098] In some embodiments, the waveform monitoring module includes a high-speed analog-to-digital converter and a high-speed memory for capturing and storing high-frequency transient characteristics of the waveform.

[0099] In some embodiments, the high-precision clock synchronization module is an IRIG-B code decoding module.

[0100] In addition to the methods and systems described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the automatic identification method for closed-loop network topology of high-voltage distribution networks according to various embodiments of this application as described in the "Exemplary Methods" section of this specification.

[0101] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0102] Furthermore, embodiments of this application may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the automatic identification method for closed-loop network topology of high-voltage distribution networks according to various embodiments of this application as described in the "Exemplary Methods" section above.

[0103] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0104] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for automatically identifying a closed-loop network topology of a high-voltage distribution network, characterized in that The method comprises the following steps: obtaining fault current direction information detected by a plurality of intelligent terminals in response to a fault occurring in a power distribution network; based on the fault current direction information, dividing switches corresponding to the plurality of intelligent terminals into at least two power flow direction regions; obtaining fault waveform arrival time information recorded by the plurality of intelligent terminals based on high-precision time synchronization; for each of the power flow direction regions, determining a distance order of each switch in the region relative to a fault point based on the fault waveform arrival time information recorded by each intelligent terminal in the region; generating a topology structure of the power distribution network based on at least the distance order in each of the power flow direction regions.

2. The method of claim 1, wherein, The step of dividing the switches corresponding to the plurality of intelligent terminals into at least two power flow direction regions based on the fault current direction information comprises: dividing switches with positive fault current direction into a positive power flow direction region; dividing switches with negative fault current direction into a negative power flow direction region.

3. The method of claim 1, wherein, The step of determining a distance order of each switch in each of the power flow direction regions relative to a fault point based on the fault waveform arrival time information recorded by each intelligent terminal in the region comprises: for switches in the same power flow direction region, determining a switch with the earliest fault waveform arrival time as the switch closest to the fault point; sorting all switches in the region according to the order of fault waveform arrival time.

4. The method of claim 3, wherein, The step of generating a topology structure of the power distribution network based on at least the distance order in each of the power flow direction regions comprises: determining switches determined as closest to the fault point in different power flow direction regions as being directly adjacent to each other.

5. The method of claim 1, wherein, The high-precision time synchronization is achieved by receiving and decoding an IRIG-B code signal, and the time synchronization error between the plurality of intelligent terminals is less than 1 microsecond.

6. The method of claim 1, wherein, The fault waveform comprises a voltage waveform and a current waveform; and the step of obtaining fault waveform arrival time information comprises extracting high-frequency transient characteristics of the waveforms and taking the arrival point of the high-frequency transient characteristics as the waveform arrival time.

7. The method of claim 1, wherein, The method further comprises: when a change in the grid structure of the power distribution network is detected, automatically executing the topology automatic identification method to update the topology structure.

8. A high-voltage distribution grid closed-loop network topology automatic identification system for implementing the method according to any one of claims 1 to 7, characterized in that, The system comprises: a plurality of intelligent terminals distributed at each switch of the power distribution network; each of the intelligent terminals comprises: a high-precision clock synchronization module for synchronizing with an external time reference signal; a current direction detection module for detecting fault current direction; a waveform monitoring module for collecting fault waveforms and recording their arrival times; a processing module configured to perform the following operations: exchanging the fault current direction and the fault waveform arrival time with other intelligent terminals; performing power flow direction region division based on the received fault current direction information; performing switch sorting in each power flow direction region based on the received fault waveform arrival time information; generating a topology structure according to the sorting result and the region division result.

9. The system of claim 8, wherein, The waveform monitoring module comprises a high-speed analog-to-digital converter and a high-speed memory for capturing and storing high-frequency transient characteristics of waveforms.

10. The system of claim 8, wherein, The high-precision clock synchronization module is an IRIG-B code decoding module. The high-precision clock synchronization module is an IRIG-B code decoding module.

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