A turn-on time generating circuit and a voltage conversion system

Abstract

The application provides a conduction time generation circuit and a voltage conversion system, and relates to the technical field of power electronics. The conduction time generation circuit comprises a signal generation module, an output sampling module, a first comparator, a first output module and a second output module. When the output sampling module outputs a flip signal, the first output module outputs a start action signal to the signal generation module, so that the signal generation module starts to act, and the second output module starts to output a conduction time signal after being delayed by the first comparator. When the signal generation module outputs an end signal, the second output module stops outputting the conduction time signal, and the first output module and the second output module are synchronized to flip. The conduction time generation circuit and the voltage conversion system provided by the application can make the generated conduction time closer to the conduction time in an ideal state, reduce the influence of comparator delay on the voltage conversion circuit, and further improve the working performance of the voltage conversion circuit.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and more specifically, to a conduction time generation circuit and voltage conversion system. Background Technology

[0002] COT (Constant On-Time) is a variant of hysteretic control or boundary control. Whenever the output voltage drops to a certain threshold, the upper transistor is turned on and held for a fixed time (TON), then turned off. The system then waits for the output voltage to drop back to the threshold and repeats this process. Unlike fixed-frequency PWM control, COT control does not have a fixed turn-on clock; the turn-on time of each cycle is triggered by a "low point" in the output voltage, while the turn-off time is fixed (determined by TON).

[0003] In a COT-structured BUCK circuit, ideally, the switching frequency FSW is generated by first generating the on-time TON from the circuit module, and then generating the switching period T from the negative feedback system, where T = TON / D (D is the duty cycle, D = VOUT / VIN), and the switching frequency FSW = 1 / T. To ensure a stable switching frequency, TON is generally set to K * D, where K is a set coefficient, therefore FSW = 1 / K.

[0004] Currently, the COT structure in BUCK circuits is generally built using a switching transistor, capacitor, current source, and comparator. Therefore, in practical applications, the conduction time TON will be affected by the comparator delay. Specifically, this delay needs to be added when calculating the conduction time, i.e., TON = K*D + TD1, where TD1 represents the comparator delay.

[0005] TD1 is the delay caused by the comparator's inherent characteristics, typically a constant of 20ns to 30ns. The degree of TD1's impact on the switching frequency varies and cannot be completely avoided even with adjustments. In high-frequency and low-duty-cycle applications, the effect of TD1 becomes increasingly pronounced.

[0006] In a BUCK circuit, increasing the switching frequency can reduce the inductance and output ripple. Therefore, a BUCK circuit needs to operate at a higher frequency.

[0007] In summary, in existing COT-structured BUCK circuits, the comparator delay in the COT structure affects the operating performance of the BUCK circuit, such as affecting the accuracy of the switching frequency. Summary of the Invention

[0008] The purpose of this application is to provide a conduction time generation circuit and voltage conversion system to solve the problem that comparator delay affects the working performance of BUCK circuit in the prior art.

[0009] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0010] On one hand, this application provides a conduction time generation circuit, which includes a signal generation module, an output sampling module, a first comparator, a first output module, and a second output module. The output terminal of the signal generation module is electrically connected to the first input terminal of the first output module and the first input terminal of the second output module, respectively. The input terminal of the output sampling module is used to connect to a voltage conversion circuit. The output terminal of the output sampling module is electrically connected to the second input terminal of the first output module and the input terminal of the first comparator, respectively. The output terminal of the first comparator is electrically connected to the second input terminal of the second output module. The output terminal of the first output module is electrically connected to the driving terminal of the signal generation module. The output terminal of the second output module serves as the output port of the conduction time generation circuit.

[0011] When the output sampling module outputs a flip signal, the first output module outputs a start action signal to the signal generation module to make the signal generation module start to operate, and the second output module starts to output a conduction time signal after the delay of the first comparator.

[0012] When the signal generation module outputs an end signal, the second output module stops outputting the conduction time signal, and the first output module and the second output module flip synchronously.

[0013] Optionally, the signal generation module includes a second comparator, and the end signal generated by the signal generation module is output after being delayed by the second comparator;

[0014] The delays of the first comparator and the second comparator are equal.

[0015] Optionally, the device parameters and operating parameters of the first comparator and the second comparator are the same.

[0016] Optionally, the first comparator and the second comparator are placed close together in the same direction.

[0017] Optionally, the bias currents of the first comparator and the second comparator are the same.

[0018] Optionally, the signal generation module includes a switching transistor, a capacitor, a second comparator, and a current source. One end of the capacitor is electrically connected to the first end of the switching transistor, the current source, and the non-inverting input of the second comparator. The other end of the capacitor and the second end of the switching transistor are both grounded. A set voltage is input to the inverting input of the second comparator. The output of the second comparator is electrically connected to the first input of the first output module and the first input of the second output module. The output of the first output module is electrically connected to the driving end of the switching transistor.

[0019] When the first output module outputs a start signal, the switch is turned off.

[0020] Optionally, the output sampling module includes a third comparator, the non-inverting input of the third comparator is connected to a reference voltage source, the inverting input of the third comparator is connected to the output of a voltage conversion circuit, and the output of the third comparator is electrically connected to the non-inverting input of the first comparator and the second input of the first output module, respectively.

[0021] Optionally, the first output module includes a first inverter, a second inverter, a first NAND gate, and a second NAND gate. The input terminal of the first inverter is electrically connected to the output terminal of the signal generation module. The input terminal of the second inverter is electrically connected to the output sampling module. The two input terminals of the first NAND gate and the second NAND gate after cross-coupling are respectively electrically connected to the output terminals of the first inverter and the second inverter. The output terminal of the first NAND gate and the second NAND gate after cross-coupling is electrically connected to the driving terminal of the signal generation module.

[0022] Optionally, the second output module includes a third inverter, a fourth inverter, a third NAND gate, and a fourth NAND gate. The input terminal of the third inverter is electrically connected to the output terminal of the signal generation module. The input terminal of the fourth inverter is electrically connected to the output terminal of the first comparator. The two input terminals of the third NAND gate and the fourth NAND gate after cross-coupling are respectively electrically connected to the output terminals of the third inverter and the fourth inverter. The output terminal of the third NAND gate and the fourth NAND gate after cross-coupling serves as the output port of the conduction time generation circuit.

[0023] On the other hand, a voltage conversion system is provided, which includes a voltage conversion circuit, a driving module, and the aforementioned conduction time generation circuit. The output port of the conduction time generation circuit is electrically connected to the driving module, the driving module is electrically connected to the driving end of the voltage conversion circuit, and the output end of the voltage conversion circuit is electrically connected to the output sampling module.

[0024] Compared with the prior art, this application has the following advantages:

[0025] This application provides a conduction time generation circuit and a voltage conversion system. The conduction time generation circuit includes a signal generation module, an output sampling module, a first comparator, a first output module, and a second output module. The output terminal of the signal generation module is electrically connected to the first input terminal of the first output module and the first input terminal of the second output module, respectively. The input terminal of the output sampling module is used to connect to the voltage conversion circuit. The output terminal of the output sampling module is electrically connected to the second input terminal of the first output module and the input terminal of the first comparator, respectively. The output terminal of the first comparator is electrically connected to the second input terminal of the second output module. The output terminal of the first output module is electrically connected to the driving terminal of the signal generation module. The output terminal of the second output module serves as the output port of the conduction time generation circuit. When the output sampling module outputs a flip signal, the first output module outputs a start action signal to the signal generation module to start the signal generation module. After a delay by the first comparator, the second output module starts outputting the conduction time signal. When the signal generation module outputs an end signal, the second output module stops outputting the conduction time signal, and the first and second output modules flip synchronously.

[0026] In the conduction time generation circuit provided in this application, when the output sampling module outputs the flip signal, the second output module will start outputting the conduction time signal only after the delay of the first comparator. Therefore, the delay of the first comparator can be used to compensate for the comparator delay in the signal generation module, so that the generated conduction time TON can be closer to the ideal conduction time TON, reducing the impact of the comparator delay on the voltage conversion circuit, thereby improving the working performance of the voltage conversion circuit.

[0027] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a circuit diagram of a current-time generation circuit in the prior art.

[0030] Figure 2 This is a waveform diagram of the on-time TON in the prior art.

[0031] Figure 3A schematic diagram of the conduction time generation circuit provided in the embodiments of this application.

[0032] Figure 4 This is a waveform diagram of the conduction time TON provided in the embodiments of this application.

[0033] Figure 5 This is a schematic diagram of the voltage conversion system provided in an embodiment of this application.

[0034] Figure 6 A circuit diagram of the conduction time generation circuit provided in the embodiments of this application.

[0035] Figure 7 This is a schematic diagram of the layout of the first comparator and the second comparator provided in an embodiment of this application.

[0036] Figure 8 This is a waveform diagram of the on-time TON when the delays of the first comparator and the second comparator are equal, as provided in the embodiments of this application.

[0037] In the picture:

[0038] 110 - Signal generation module; 120 - Output sampling module; 130 - First comparator; 140 - First output module; 150 - Second output module. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0043] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0044] As described in the background section, in current COT-structured BUCK circuits, the comparator delay in the COT structure affects the operating performance of the BUCK circuit. For example... Figure 1 The diagram shows a schematic of an existing conduction time generation circuit. This circuit includes a switch M1, a capacitor C, a current source CS, and a comparator CMP1. The current output by the current source CS is I = VIN / R, where VIN represents the BUCK input voltage and R represents the resistance value in the current source. The switch M1 is an NMOS transistor. The upper end of the capacitor C is connected to the current source CS, and its voltage is VC. The lower end of the capacitor C is grounded. The drain of the switch M1 is connected to the upper end of the capacitor C, and the source of the switch M1 is connected to the lower end of the capacitor C. The non-inverting input of the comparator CMP1 is connected to VC, and the inverting input is connected to the reference voltage K1*VOUT, where VOUT represents the output voltage of the BUCK circuit, K1 represents the set coefficient, and the output of the comparator CMP1 is Y1.

[0045] exist Figure 1 In the circuit shown, during the TOFF phase, switch M1 is turned on, and the VC voltage drops to ground, equal to 0V. At this time, the voltage at the non-inverting input of comparator CMP1 (0V) is less than the voltage at the inverting input (K1*VOUT), and the output Y1 is low. When the TON timer starts, switch M1 is turned off, and current I charges capacitor C, causing the voltage VC at the upper end of capacitor C to gradually increase. When VC reaches K1*VOUT, the comparator output flips, and Y1 flips to a high level. The conduction time TON represents the time elapsed from the start of capacitor charging until it reaches K1*VOUT, causing Y1 to flip.

[0046] Therefore, the equation can be established: TON*(VIN / R) / C=K1*VOUT, where TON*(VIN / R) / C represents the VC voltage. This formula can be rearranged to: TON=K1*VOUT / ((VIN / R) / C)=(K1*R*C)*(VOUT / VIN)=K*(VOUT / VIN)=K*D, i.e., K=K1*R*C, D represents the duty cycle, i.e., D=VOUT / VIN, and K represents the coefficient used to adjust the switching frequency, where the switching frequency FSW=1 / (K1*R*C). It is evident that the TON time is a constant value and is related to the set coefficients K1, R, C, and the duty cycle.

[0047] However, the above formula for calculating the on-time TON does not actually consider the effect of the delay (TD1) of comparator CMP1. Adding this delay, TON = K*D + TD1; that is, FSW = 1 / (K + TD1 / D). The delay TD1 of comparator CMP1 is due to the device's inherent performance and refers to the delay required for comparator CMP1 to flip. TD1 is generally a constant (e.g., 20~30ns) and is independent of VOUT and VIN. For example, when TD1 is 25ns, when the non-inverting input VC of comparator CMP1 reaches K1*VOUT, comparator CMP1 cannot immediately output a high-level flip, but will output a high-level flip after 25ns.

[0048] like Figure 2 The figure shows a waveform diagram of the conduction time TON in the prior art. In an ideal state, the waveform can be flipped after K*D, that is, TON=K*D; but in practical applications, it is necessary to pass K*D+TD1 to achieve the flipping, that is, TON=K*D+TD1.

[0049] Furthermore, the delay TD1 affects the switching frequency, and the degree of impact varies depending on the VOUT and VIN values. In high-frequency and low-duty-cycle applications, the effect of TD1 becomes increasingly pronounced. In BUCK circuit applications, increasing the switching frequency reduces inductance and output ripple; therefore, BUCK circuits typically operate at higher frequencies in practice, leading to a significant impact of TD1 on their performance. For example, ideally, the operating parameters of a BUCK circuit are as follows: VIN=12V, FSW=2MHz, and TON=50ns when VOUT=1.2V; while TON=25ns when VOUT=0.6V. Taking COUT=0.6V as an example, TON=25ns, while the delay TD1 is typically 20ns~30ns. Therefore, the delay TD1 is essentially equivalent to the ideal TON, resulting in the actual TON being approximately twice the ideal TON, which severely impacts the performance of the BUCK circuit.

[0050] In view of this, to solve the above problems, this application provides a conduction time generation circuit. As one implementation, please refer to... Figure 3 The conduction time generation circuit includes a signal generation module 110, an output sampling module 120, a first comparator 130, a first output module 140, and a second output module 150. The output terminal of the signal generation module 110 is electrically connected to the first input terminal of the first output module 140 and the first input terminal of the second output module 150, respectively. The input terminal of the output sampling module 120 is used to connect to a voltage conversion circuit. The output terminal of the output sampling module 120 is electrically connected to the second input terminal of the first output module 140 and the input terminal of the first comparator 130, respectively. The output terminal of the first comparator 130 is electrically connected to the second input terminal of the second output module 150. The output terminal of the first output module 140 is electrically connected to the driving terminal of the signal generation module 110. The output terminal of the second output module 150 serves as the output port of the conduction time generation circuit.

[0051] When the output sampling module 120 outputs a toggle signal, the first output module 140 outputs a start action signal to the signal generation module 110 so that the signal generation module 110 starts to operate. The second output module 150 starts to output a conduction time signal after the delay of the first comparator 130. When the signal generation module 110 outputs an end signal, the second output module 150 stops outputting the conduction time signal, and the first output module 140 and the second output module 150 toggle synchronously.

[0052] In this application, by adding a first comparator 130, a first output module 140, and a second output module 150, when the output sampling module 120 outputs a toggle signal, the second output module 150 will only start outputting the conduction time signal after the delay of the first comparator 130. Therefore, the delay of the first comparator 130 can be used to compensate for the comparator delay in the signal generation module 110, so that the generated conduction time TON can be closer to the ideal conduction time TON, reducing the impact of the comparator delay on the voltage conversion circuit, thereby improving the working performance of the voltage conversion circuit.

[0053] Specifically, please refer to Figure 4 In the prior art, the conduction time TON is actually the low-level duration of the TON_L signal in the figure, i.e., TON=K*D+TD1. However, in this application, the low-level duration of the TON_L1 signal is used as the conduction time TON. In the figure, TD1 represents the delay of the comparator in the signal generation module 110, TD2 represents the delay of the first comparator 130, and Y2 represents the output signal of the output sampling module 120.

[0054] Combination Figure 3and Figure 4 When the output sampling module 120 outputs a toggle signal, i.e., toggles from low to high, the first output module 140 immediately outputs a start signal, i.e., a low-level signal. However, because the input of the second output module 150 is connected to the output of the output sampling module 120 by the first comparator 130, the toggle signal output by the sampling module needs to be delayed by the first comparator 130 before it is transmitted to the input of the second output module 150. That is, the second output module 150 needs to be delayed by TD2 by the first comparator 130 before it starts outputting a low-level signal. When the signal generation module 110 outputs an end signal, due to the comparator delay inside the signal generation module 110, both the first output module 140 and the second output module 150 will receive the end signal after a delay of TD1. Furthermore, since the signal generation module 110 is electrically connected to the first input of both the first output module 140 and the second output module 150, the output signals of the first output module 140 and the second output module 150 will toggle simultaneously.

[0055] It is evident that, for Figure 4 For the TON_L signal, the low-level duration in each cycle is K*D+TD1; however, for the TON_L1 signal, the low-level duration in each cycle is K*D+TD1-TD2. Since the difference between TD1 and TD2 can be set to be smaller than TD1 (i.e., TD1-TD2 < TD1), for example, if the selected TD2 value is close to TD1, then the low-level time of the TON_L1 signal can be used as the on-time TON. Therefore, TON = K*D+TD1-TD2, which is closer to the ideal TON. This significantly reduces the impact of comparator delay on the voltage conversion circuit and improves its performance.

[0056] For example, when the ideal TON is 25ns, TD1 is 25ns, and TD2 is 20ns, the actual TON in the prior art is 25ns + 25ns = 50ns, which is a large difference from the ideal TON and will significantly affect the performance of the voltage conversion circuit. However, in the solution provided in this application, the actual TON is 25ns + 25ns - 20ns = 30ns, which is closer to the ideal TON and therefore significantly improves the performance of the voltage conversion circuit.

[0057] It should be noted that the voltage conversion circuit described in this application can be a boost circuit, such as a BOOST boost circuit, or a buck circuit, such as a BUCK buck circuit. This application uses a BUCK buck circuit as an example for illustration. Please refer to [link to relevant documentation]. Figure 5The diagram below is a simplified illustration of the application scenario of the conduction time generation circuit provided in this application. In practical applications, it may include more modules, such as logic processing modules, and the BUCK circuit may also include more devices, which are not limited here.

[0058] Depend on Figure 5 As can be seen, the power stage of the BUCK circuit uses a push-pull circuit, namely, switching transistors Q1 and Q2 in the diagram. The output of the BUCK circuit is connected to the on-time generation circuit. Specifically, the output of the BUCK circuit is electrically connected to the output sampling module 120 in the on-time generation circuit. Of course, the output of the BUCK circuit can also be electrically connected to the output sampling module 120 through a voltage divider sampling circuit. The signal output by the on-time generation circuit (i.e., the on-time TON) passes through the driver module and then outputs a control signal to the power stage of the BUCK circuit. This ensures that in the power stage, when TON is active, Q1 is on and Q2 is off; while when TOFF is active, Q2 is on and Q1 is off. Furthermore, when TON is active, VOUT is low, and when TOFF is active, VOUT is high.

[0059] Based on this, please refer to Figure 6 In the conduction time generation circuit provided in this application, the signal generation module 110 includes a switch transistor M1, a capacitor C, a second comparator CMP2, and a current source CS. One end of the capacitor C is electrically connected to the first terminal of the switch transistor M1, the current source CS, and the non-inverting input terminal of the second comparator CMP2. The other end of the capacitor C and the second terminal of the switch transistor M1 are both grounded. A set voltage is input to the inverting input terminal of the second comparator CMP2, which is set to K1*VOUT, where K1 represents a coefficient and VOUT represents the output voltage of the BUCK circuit. The output terminal of the second comparator CMP2 is electrically connected to the first input terminal of the first output module 140 and the first input terminal of the second output module 150. The output terminal of the first output module 140 is electrically connected to the driving terminal of the switch transistor M1. When the first output module 140 outputs a start-action signal, the switch transistor M1 is turned off. The start-action signal mentioned in this application refers to the first output module 140 outputting a low-level signal, causing the switch transistor M1 to turn off. When the switch M1 is turned on, the VC voltage is 0, and the output of the second comparator CMP2 is Y1, which outputs a low level. When the switch M1 is turned off, the current source CS charges the capacitor C, causing the VC voltage to rise continuously. When the VC voltage rises to K*VOUT, the second comparator CMP2 flips and outputs a high level.

[0060] Therefore, when the first output module 140 outputs a start signal to the signal generation module 110, the capacitor C starts charging. Theoretically, TON can start outputting at this time. When the capacitor C is charged to VC equal to K*VOUT, the output TON ends.

[0061] In one implementation, the output sampling module 120 includes a third comparator CMP3. The non-inverting input of the third comparator CMP3 is connected to a reference voltage source VREF, and the inverting input of the third comparator CMP3 is connected to the output of a voltage conversion circuit. The output of the third comparator CMP3 is electrically connected to the non-inverting input of the first comparator 130 and the second input of the first output module 140, respectively. The inverting input of the first comparator 130 is input to K1*VOUT. The inverting input of the third comparator CMP3 is electrically connected to the output of the voltage conversion circuit through a voltage divider sampling circuit, such that the voltage input to the inverting input of the third comparator CMP3 is VFB.

[0062] In this application, the circuitry of the first output module 140 and the second output module 150 is identical. As one implementation, the first output module 140 includes a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, and a second NAND gate NAND2. The input terminal of the first inverter INV1 is electrically connected to the output terminal of the signal generation module 110, and the input terminal of the second inverter INV2 is electrically connected to the output sampling module 120. The two input terminals of the first NAND gate NAND1 and the second NAND gate NAND2, after cross-coupling, are respectively electrically connected to the output terminals of the first inverter INV1 and the second inverter INV2. The output terminal of the first NAND gate NAND1 and the second NAND gate NAND2, after cross-coupling, is electrically connected to the driving terminal of the signal generation module 110. It should be noted that the cross-coupling described in this application refers to one input terminal of the first NAND gate NAND1 being connected to the output terminal of the second NAND gate NAND2, and simultaneously, one input terminal of the second NAND gate NAND2 being connected to the output terminal of the first NAND gate NAND1. This connection method enables the first NAND gate NAND1 and the second NAND gate NAND2 to form an RS flip-flop.

[0063] The second output module 150 includes a third inverter INV3, a fourth inverter INV4, a third NAND gate NAND3, and a fourth NAND gate NAND4. The input terminal of the third inverter INV3 is electrically connected to the output terminal of the signal generation module 110. The input terminal of the fourth inverter INV4 is electrically connected to the output terminal of the first comparator 130. The two input terminals of the third NAND gate NAND3 and the fourth NAND gate NAND4 after cross-coupling are electrically connected to the output terminals of the third inverter INV3 and the fourth inverter INV4, respectively. The output terminal of the third NAND gate NAND3 and the fourth NAND gate NAND4 after cross-coupling serves as the output port of the conduction time generation circuit.

[0064] Combination Figures 4-6, using 1 to represent high level and 0 to represent low level, the working principle of the conduction time generation circuit provided by this application is described as follows:

[0065] In the TOFF stage, the VOUT of the BUCK circuit is relatively high. At this time, for the third comparator CMP3, VFB is greater than VREF, the output terminal Y2 is 0, the output of INV2 is 1, and Y1_1 is low. At the same time, TON_L = TON_L1, the output is 1, M1 is turned on, VC = 0, Y1 is low, and the outputs of INV1 and INV3 are 1. And in the TOFF stage, since VOUT is also connected to a load, VOUT will continuously decrease. At this time, VFB will also continuously decrease as VOUT decreases.

[0066] When the voltage of VFB drops to VFB < VREF, the third comparator CMP3 outputs a flip signal, and its output changes from 0 to 1. At this time, the output of INV2 is 0. Since the output of INV1 is 1 at this time, the output TON_L of the first output module 140 will become 0. Since TON_L is the driving signal of the switching tube M1, the switching tube M1 is turned off at this time, and the capacitor C starts to charge, and VC gradually increases. For the second output module 150, when the output of the third comparator CMP3 changes from 0 to 1, the voltage of the non-inverting input terminal of the first comparator 130 is equal to the power supply voltage, making the voltage of the non-inverting input terminal of the first comparator 130 greater than the voltage of the inverting input terminal, and Y1_1 will change from 0 to 1. Among them, due to the delay of the first comparator 130 itself, when the output of the third comparator CMP3 changes from 0 to 1, Y1_1 will not immediately change from 0 to 1, but needs to pass through the delay of the first comparator 130 ( Figure 4 in TD2), the signal will flip. When Y1_1 changes from 0 to 1, the output of INV4 is 0, and since the output of INV3 is also 1 at this time, when Y1_1 changes from 0 to 1, the output of the second output module 150 will change from 1 to 0.

[0067] As the capacitor C continues to charge, the voltage of VC continues to increase. When the voltage of VC increases to K1 * VOUT, the output Y1 signal of the second comparator CMP2 flips, changing from 0 to 1. This signal is the end signal, indicating the end of TON. It should be noted that when the voltage of VC increases to K1 * VOUT, due to the delay of the second comparator CMP2 itself, it will not immediately output 1, but needs to output 1 after passing through the delay TD1 of the second comparator CMP2. When Y1 flips to 1, the output of INV1 is 0, and TON_L is 1; similarly, the output of INV3 is 0, and TON_L1 is 1.

[0068] As can be seen, in the above process, the low-level time of TON_L is: TON = K*D + TD1; the low-level time of TON_L1 is: TON1 = K*D + TD1 - TD2. Taking TON1 as the conduction time makes the generated conduction time closer to the ideal conduction time K*D. That is, in the prior art, due to the delay of the second comparator CMP2, the end time of the conduction time TON is later than the ideal TON time; therefore, in this application, the delay of the first comparator 130 is used to delay the start time of the conduction time TON, thereby compensating for the delay of the second comparator CMP2 with the delay of the first comparator 130, making the generated conduction time TON closer to the ideal value, thus achieving the advantage of improving the working performance of the BUCK circuit.

[0069] Of course, the BUCK circuit performs optimally when the generated on-time TON equals the ideal value. Based on this, when the delays of the first comparator 130 and the second comparator CMP2 are equal, the delay of the first comparator 130 can completely compensate for the delay of the second comparator CMP2. The on-time formula is: TON1 = K*D + TD1 - TD1 = K*D. Therefore, when the delays of the first comparator 130 and the second comparator CMP2 are equal, the on-time TON is the ideal value K*D.

[0070] To ensure that the delays of the first comparator 130 and the second comparator CMP2 are exactly equal, their device parameters and operating parameters are completely identical. Device parameters refer to the parameters inherent to the comparator itself, such as its structure, the type of device used, and its parameters. It should be noted that device parameters also include layout parameters; the first comparator 130 and the second comparator CMP2 are placed close together in the same direction to ensure complete consistency of device parameters. Figure 7 As shown, if the second comparator CMP2 is horizontally placed on the layout (A in the figure), then the first comparator 130 should also be horizontally placed (B in the figure), and cannot be placed in any other direction (as shown in B1 in the figure, which is vertical placement). Furthermore, the first comparator 130 and the second comparator CMP2 are placed according to the principle of proximity, that is, the first comparator 130 and the second comparator CMP2 are placed with the shortest distance between them. This layout arrangement ensures that even if interference exists, the interference experienced by the first comparator 130 and the second comparator CMP2 is basically the same, thus guaranteeing the consistency of their delays. At the same time, placing them in the same direction and close together simplifies the overall structure and reduces the cost of the circuit layout.

[0071] The operating parameters mentioned in this application refer to the external parameters required by the comparator during operation, such as bias current, voltage, inverting input connection (all connected to K1*VOUT), and devices connected to the output.

[0072] Based on the fact that the delays of the first comparator 130 and the second comparator CMP2 are equal, please refer to... Figure 8 The delay TD1 of the first comparator 130 can be used to completely cancel the delay TD1 of the second comparator CMP2, so that the conduction time TON1 is equal to the value under the ideal state, that is, the conduction time TON1=K*D. In other words, the conduction time is only determined by K and Vout / Vin (i.e. D), and no longer includes the comparator delay, making Fsw more accurate. Especially in high-frequency, small duty cycle applications, the advantages are obvious. Overall, it is beneficial for the BUCK circuit to work at high frequencies and improves the working performance of the BUCK circuit.

[0073] Based on the above implementation, this application embodiment also provides a voltage conversion system, which includes a voltage conversion circuit, a driving module, and the above-mentioned conduction time generation circuit. The output port of the conduction time generation circuit is electrically connected to the driving module, the driving module is electrically connected to the driving end of the voltage conversion circuit, and the output end of the voltage conversion circuit is electrically connected to the output sampling module 120.

[0074] In summary, this application provides a conduction time generation circuit and a voltage conversion system. The conduction time generation circuit includes a signal generation module, an output sampling module, a first comparator, a first output module, and a second output module. The output terminal of the signal generation module is electrically connected to the first input terminal of the first output module and the first input terminal of the second output module, respectively. The input terminal of the output sampling module is used to connect to the voltage conversion circuit. The output terminal of the output sampling module is electrically connected to the second input terminal of the first output module and the input terminal of the first comparator, respectively. The output terminal of the first comparator is electrically connected to the second input terminal of the second output module. The output terminal of the first output module is electrically connected to the driving terminal of the signal generation module. The output terminal of the second output module serves as the output port of the conduction time generation circuit. When the output sampling module outputs a flip signal, the first output module outputs a start action signal to the signal generation module to start the signal generation module. After a delay by the first comparator, the second output module starts outputting the conduction time signal. When the signal generation module outputs an end signal, the second output module stops outputting the conduction time signal, and the first and second output modules flip synchronously. In the conduction time generation circuit provided in this application, when the output sampling module outputs the flip signal, the second output module will start outputting the conduction time signal only after the delay of the first comparator. Therefore, the delay of the first comparator can be used to compensate for the comparator delay in the signal generation module, so that the generated conduction time TON can be closer to the ideal conduction time TON, reducing the impact of the comparator delay on the voltage conversion circuit, thereby improving the working performance of the voltage conversion circuit.

[0075] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0076] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A conduction time generation circuit, characterized in that, The conduction time generation circuit includes a signal generation module, an output sampling module, a first comparator, a first output module, and a second output module. The output terminal of the signal generation module is electrically connected to the first input terminal of the first output module and the first input terminal of the second output module, respectively. The input terminal of the output sampling module is used to connect to a voltage conversion circuit. The output terminal of the output sampling module is electrically connected to the second input terminal of the first output module and the input terminal of the first comparator, respectively. The output terminal of the first comparator is electrically connected to the second input terminal of the second output module. The output terminal of the first output module is electrically connected to the driving terminal of the signal generation module. The output terminal of the second output module serves as the output port of the conduction time generation circuit. When the output sampling module outputs a flip signal, the first output module outputs a start action signal to the signal generation module to make the signal generation module start to operate, and the second output module starts to output a conduction time signal after the delay of the first comparator. When the signal generation module outputs an end signal, the second output module stops outputting the conduction time signal, and the first output module and the second output module flip synchronously.

2. The conduction time generation circuit as described in claim 1, characterized in that, The signal generation module includes a second comparator, and the end signal generated by the signal generation module is output after being delayed by the second comparator. The delays of the first comparator and the second comparator are equal.

3. The conduction time generation circuit as described in claim 2, characterized in that, The device parameters and operating parameters of the first comparator and the second comparator are the same.

4. The conduction time generation circuit as described in claim 3, characterized in that, The first comparator and the second comparator are placed close together in the same direction.

5. The conduction time generation circuit as described in claim 3, characterized in that, The bias currents of the first comparator and the second comparator are the same.

6. The conduction time generation circuit as described in claim 1, characterized in that, The signal generation module includes a switching transistor, a capacitor, a second comparator, and a current source. One end of the capacitor is electrically connected to the first end of the switching transistor, the current source, and the non-inverting input of the second comparator. The other end of the capacitor and the second end of the switching transistor are both grounded. A set voltage is input to the inverting input of the second comparator. The output of the second comparator is electrically connected to the first input of the first output module and the first input of the second output module. The output of the first output module is electrically connected to the driving end of the switching transistor. When the first output module outputs a start signal, the switch is turned off.

7. The conduction time generation circuit as described in claim 1, characterized in that, The output sampling module includes a third comparator. The non-inverting input of the third comparator is connected to a reference voltage source, and the inverting input of the third comparator is connected to the output of a voltage conversion circuit. The output of the third comparator is electrically connected to the non-inverting input of the first comparator and the second input of the first output module, respectively.

8. The conduction time generation circuit as described in claim 1, characterized in that, The first output module includes a first inverter, a second inverter, a first NAND gate, and a second NAND gate. The input terminal of the first inverter is electrically connected to the output terminal of the signal generation module. The input terminal of the second inverter is electrically connected to the output sampling module. The two input terminals of the first NAND gate and the second NAND gate after cross-coupling are respectively electrically connected to the output terminals of the first inverter and the second inverter. The output terminal of the first NAND gate and the second NAND gate after cross-coupling is electrically connected to the driving terminal of the signal generation module.

9. The conduction time generation circuit as described in claim 1, characterized in that, The second output module includes a third inverter, a fourth inverter, a third NAND gate, and a fourth NAND gate. The input terminal of the third inverter is electrically connected to the output terminal of the signal generation module. The input terminal of the fourth inverter is electrically connected to the output terminal of the first comparator. The two input terminals of the third NAND gate and the fourth NAND gate after cross-coupling are respectively electrically connected to the output terminals of the third inverter and the fourth inverter. The output terminal of the third NAND gate and the fourth NAND gate after cross-coupling serves as the output port of the conduction time generation circuit.

10. A voltage conversion system, characterized in that, The voltage conversion system includes a voltage conversion circuit, a driving module, and a conduction time generation circuit as described in any one of claims 1 to 9. The output port of the conduction time generation circuit is electrically connected to the driving module, the driving module is electrically connected to the driving terminal of the voltage conversion circuit, and the output terminal of the voltage conversion circuit is electrically connected to the output sampling module.

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