Coding and decoding method and device

Abstract

The invention provides a coding and decoding method and device. The method comprises: performing CRC coding on A information bits to be coded according to a CRC polynomial to obtain a first bit sequence, the first bit sequence comprising L CRC bits and A information bits, and performing polarization coding on the first bit sequence. Coding satisfying nesting characteristics and reduced polynomial requirements is realized according to an improved CRC polynomial.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a coding and decoding method and apparatus. Background Technology

[0002] Communication systems typically employ channel coding to improve data transmission reliability and ensure communication quality. Currently, 5G mobile communication systems encompass three major application scenarios: Enhanced Mobile Broadband (eMBB), URLLC, and Massive Machine-Type Communications (mMTC), which place new demands on data communication. Polar codes are the first channel coding method that can be rigorously proven to "achieve" channel capacity and are applicable to 5G communication and future communication systems. Summary of the Invention

[0003] This application provides a coding method and apparatus.

[0004] Firstly, this application provides an encoding method, including:

[0005] The sending end performs CRC encoding on A bits of information to be encoded using a Cyclic Redundancy Check (CRC) polynomial to obtain a first bit sequence. The first bit sequence includes L CRC bits and A information bits, where L and A are positive integers, and L = 16. The CRC polynomial is any one of the following polynomials:

[0006] D^16+D^9+D^5+D^3+D^2+D+1; or

[0007] D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or

[0008] D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or

[0009] D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or

[0010] D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or

[0011] D^16+D^14+D^11+D^6+D^4+D^3+1; or

[0012] D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or

[0013] D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or

[0014] D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or

[0015] D^16+D^15+D^9+D^6+D^4+D^2+1; or

[0016] D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or

[0017] D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or

[0018] D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0019] D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0020] D^16+D^12+D^10+D^9+D^8+D^7+D^5+D^3+1; or

[0021] D^16+D^13+D^11+D^9+D^5+D^4+D^3+D+1; or

[0022] D^16+D^12+D^10+D^7+D^5+D^3+D^2+D+1;

[0023] The first bit sequence is polar-coded.

[0024] This encoding method can satisfy the requirements of nesting characteristics and reduced polynomials, ensuring normal communication.

[0025] In one possible design, the CRC polynomial is implemented using a shift register.

[0026] In one possible design, the L CRC bits in the first bit sequence are located after the A bits of information to be encoded.

[0027] In one possible design, the transmitting end transmits the first bit sequence after polarization encoding.

[0028] In one possible design, the above encoding method can be implemented in hardware, for example, through circuits or one or more integrated circuits. The encoding method can also be implemented in software, for example, by one or more processors executing the encoding method by reading instructions stored in memory. These one or more processors can be integrated into a single chip or distributed across multiple chips. The encoding method can also be implemented partly in hardware and partly in software; for example, the processor executes the step of "CRC encoding A bits of information to be encoded according to a Cyclic Redundancy Check (CRC) polynomial" by reading instructions stored in memory, while the step of "polarizing the first bit sequence" is implemented through a logic circuit or an accelerator. Of course, those skilled in the art can also use combinations of the various methods described above in specific implementations.

[0029] In one possible design, the transmitting end is any of the following: a base station, a functional module in a base station, a chip in a base station, a terminal, a functional module in a terminal, or a chip in a terminal.

[0030] Secondly, this application provides an encoding device, comprising:

[0031] The first encoding module is used to perform CRC encoding on A bits of information to be encoded according to a Cyclic Redundancy Check (CRC) polynomial to obtain a first bit sequence. The first bit sequence includes L CRC bits and A information bits, where L and A are positive integers, and L = 16. The CRC polynomial is any one of the following polynomials:

[0032] D^16+D^9+D^5+D^3+D^2+D+1; or

[0033] D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or

[0034] D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or

[0035] D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or

[0036] D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or

[0037] D^16+D^14+D^11+D^6+D^4+D^3+1; or

[0038] D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or

[0039] D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or

[0040] D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or

[0041] D^16+D^15+D^9+D^6+D^4+D^2+1; or

[0042] D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or

[0043] D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or

[0044] D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0045] D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0046] D^16+D^12+D^10+D^9+D^8+D^7+D^5+D^3+1; or

[0047] D^16+D^13+D^11+D^9+D^5+D^4+D^3+D+1; or

[0048] D^16+D^12+D^10+D^7+D^5+D^3+D^2+D+1;

[0049] The second encoding module is used to perform polarization encoding on the first bit sequence.

[0050] In one possible design, the CRC polynomial is implemented using a shift register.

[0051] In one possible design, the L CRC bits in the first bit sequence are located after the A bits of information to be encoded.

[0052] In one possible design, the device further includes a transmitting module for transmitting the polar-coded first bit sequence.

[0053] In one possible design, the device is any one of the following: a base station, a functional module in a base station, a chip in a base station, a terminal, a functional module in a terminal, or a chip in a terminal.

[0054] Thirdly, this application provides an encoding device, including a processor, the processor being used for:

[0055] The A bits of information to be encoded are CRC encoded using a Cyclic Redundancy Check (CRC) polynomial to obtain a first bit sequence. The first bit sequence includes L CRC bits and A information bits, where L and A are positive integers, and L = 16. The CRC polynomial is any one of the following polynomials:

[0056] D^16+D^9+D^5+D^3+D^2+D+1; or

[0057] D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or

[0058] D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or

[0059] D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or

[0060] D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or

[0061] D^16+D^14+D^11+D^6+D^4+D^3+1; or

[0062] D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or

[0063] D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or

[0064] D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or

[0065] D^16+D^15+D^9+D^6+D^4+D^2+1; or

[0066] D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or

[0067] D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or

[0068] D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0069] D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0070] D^16+D^12+D^10+D^9+D^8+D^7+D^5+D^3+1; or

[0071] D^16+D^13+D^11+D^9+D^5+D^4+D^3+D+1; or

[0072] D^16+D^12+D^10+D^7+D^5+D^3+D^2+D+1;

[0073] The first bit sequence is polar-coded.

[0074] In one possible design, the encoding device further includes a memory for storing program instructions.

[0075] In one possible design, the CRC polynomial is implemented using a shift register.

[0076] In one possible design, the L CRC bits in the first bit sequence are located after the A bits of information to be encoded.

[0077] In one possible design, the device is any one of the following: a base station, a functional module in a base station, a chip in a base station, a terminal, a functional module in a terminal, or a chip in a terminal.

[0078] The aforementioned memory can be located inside or outside the processor. The aforementioned processor can be integrated into the terminal or base station.

[0079] The processor described above can be a circuit, one or more integrated circuits, or one or more dedicated chips. The processor can also be a general-purpose chip; loading the program instructions for implementing the above encoding method onto the processor will achieve the above encoding function. The processor can also be a combination of one or more of the following: circuit, integrated circuit, dedicated chip, and general-purpose chip.

[0080] Fourthly, this application provides an encoding device, comprising:

[0081] Input interface, used to acquire the bit sequence to be encoded;

[0082] A logic circuit for performing the method described in the first aspect and various possible designs of the first aspect based on the acquired bit sequence to be encoded, to obtain the encoded bits;

[0083] Output interface, used to output encoded bits.

[0084] In one possible design, the device is any one of the following: a base station, a functional module in a base station, a chip in a base station, a terminal, a functional module in a terminal, or a chip in a terminal.

[0085] Fifthly, this application provides a communication device, including the encoding device and transceiver provided in the third aspect and various possible designs of the third aspect;

[0086] The transceiver is used to transmit the bits encoded by the encoding device.

[0087] In one possible design, the communication device is any one of the following: a base station or a terminal.

[0088] Sixthly, this application provides a decoding method, including:

[0089] The receiving end receives the sequence to be decoded;

[0090] The receiving end performs polarization decoding on the sequence to be decoded according to the Cyclic Redundancy Check (CRC) polynomial to obtain the decoded sequence. The decoded sequence includes L CRC bits and A information bits, where L and A are positive integers, and L = 16. The CRC polynomial is any one of the following polynomials:

[0091] D^16+D^9+D^5+D^3+D^2+D+1; or

[0092] D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or

[0093] D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or

[0094] D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or

[0095] D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or

[0096] D^16+D^14+D^11+D^6+D^4+D^3+1; or

[0097] D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or

[0098] D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or

[0099] D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or

[0100] D^16+D^15+D^9+D^6+D^4+D^2+1; or

[0101] D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or

[0102] D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or

[0103] D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0104] D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0105] D^16+D^12+D^10+D^9+D^8+D^7+D^5+D^3+1; or

[0106] D^16+D^13+D^11+D^9+D^5+D^4+D^3+D+1; or

[0107] D^16+D^12+D^10+D^7+D^5+D^3+D^2+D+1.

[0108] This decoding method can satisfy the requirements of nesting characteristics and reduced polynomials, ensuring normal communication.

[0109] In one possible design, the CRC polynomial is implemented using a shift register.

[0110] In one possible design, the L CRC bits in the first bit sequence are located after the A bits of information to be encoded.

[0111] In one possible design, the transmitting end transmits the first bit sequence after polarization encoding.

[0112] In one possible design, the above decoding method can be implemented in hardware, for example, through circuits or one or more integrated circuits. The above encoding method can also be implemented in software, for example, by one or more processors executing the decoding method by reading instructions stored in memory. These one or more processors can be integrated into a single chip or distributed across multiple chips. The above encoding method can also be implemented partly in hardware and partly in software. Of course, those skilled in the art can also use combinations of the various methods described above in specific implementations.

[0113] In one possible design, the receiver is any of the following: a base station, a chip in a base station, a terminal, or a chip in a terminal.

[0114] In a seventh aspect, this application provides a decoding apparatus, comprising:

[0115] The acquisition module is used to acquire the bit sequence to be decoded;

[0116] The decoding module is used to perform polarization decoding on the sequence to be decoded according to the Cyclic Redundancy Check (CRC) polynomial to obtain a decoded sequence. The decoded sequence includes L CRC bits and A information bits, where L and A are positive integers, L = 16, and the CRC polynomial is any one of the following polynomials:

[0117] D^16+D^9+D^5+D^3+D^2+D+1; or

[0118] D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or

[0119] D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or

[0120] D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or

[0121] D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or

[0122] D^16+D^14+D^11+D^6+D^4+D^3+1; or

[0123] D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or

[0124] D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or

[0125] D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or

[0126] D^16+D^15+D^9+D^6+D^4+D^2+1; or

[0127] D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or

[0128] D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or

[0129] D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0130] D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0131] D^16+D^12+D^10+D^9+D^8+D^7+D^5+D^3+1; or

[0132] D^16+D^13+D^11+D^9+D^5+D^4+D^3+D+1; or

[0133] D^16+D^12+D^10+D^7+D^5+D^3+D^2+D+1.

[0134] In one possible design, the CRC polynomial is implemented using a shift register.

[0135] In one possible design, the L CRC bits in the first bit sequence are located after the A bits of information to be encoded.

[0136] In one possible design, the device further includes a receiving module for receiving a sequence of bits to be decoded.

[0137] In one possible design, the device is any of the following: a base station, a chip in a base station, a terminal, or a chip in a terminal.

[0138] Eighthly, this application provides a decoding apparatus, including a processor, the processor being used to:

[0139] Receive the sequence to be decoded;

[0140] The sequence to be decoded is polarized decoded according to the Cyclic Redundancy Check (CRC) polynomial to obtain the decoded sequence, which includes L CRC bits and A information bits, where L and A are positive integers, and L = 16. The CRC polynomial is any one of the following polynomials:

[0141] D^16+D^9+D^5+D^3+D^2+D+1; or

[0142] D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or

[0143] D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or

[0144] D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or

[0145] D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or

[0146] D^16+D^14+D^11+D^6+D^4+D^3+1; or

[0147] D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or

[0148] D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or

[0149] D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or

[0150] D^16+D^15+D^9+D^6+D^4+D^2+1; or

[0151] D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or

[0152] D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or

[0153] D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0154] D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0155] D^16+D^12+D^10+D^9+D^8+D^7+D^5+D^3+1; or

[0156] D^16+D^13+D^11+D^9+D^5+D^4+D^3+D+1; or

[0157] D^16+D^12+D^10+D^7+D^5+D^3+D^2+D+1.

[0158] In one possible design, the encoding device further includes a memory for storing program instructions.

[0159] In one possible design, the CRC polynomial is implemented using a shift register.

[0160] In one possible design, the L CRC bits in the first bit sequence are located after the A bits of information to be encoded.

[0161] In one possible design, the device is any of the following: a base station, a chip in a base station, a terminal, or a chip in a terminal.

[0162] The aforementioned memory can be located inside or outside the processor. The aforementioned processor can be integrated into the terminal or base station.

[0163] The processor described above can be a circuit, one or more integrated circuits, one or more dedicated chips, or a module. The processor can also be a general-purpose chip; loading the program instructions for implementing the above encoding method onto the processor will achieve the above encoding function. The processor can also be a combination of one or more of the following: circuit, integrated circuit, dedicated chip, and general-purpose chip.

[0164] Ninthly, this application provides a decoding apparatus, comprising:

[0165] The input interface is used to obtain the sequence to be decoded.

[0166] A logic circuit for performing the methods described in the sixth aspect and various possible designs of the sixth aspect based on the acquired sequence to be decoded, to obtain the decoded bits;

[0167] The output interface is used to output the decoded sequence.

[0168] In one possible design, the device is any one of the following: a base station, a functional module in a base station, a chip in a base station, a terminal, a functional module in a terminal, or a chip in a terminal.

[0169] In a tenth aspect, this application provides a communication device, including the encoding means and transceiver provided in the sixth aspect and various possible designs of the sixth aspect;

[0170] The transceiver is used to receive and acquire the sequence to be decoded.

[0171] In one possible design, the communication device is any one of the following: a base station or a terminal.

[0172] Eleventhly, this application provides a readable storage medium, comprising: a readable storage medium and a computer program, the computer program being used to implement the encoding method provided in the first aspect and various possible designs of the first aspect, or the decoding method provided in the sixth aspect and various possible designs of the sixth aspect.

[0173] In a twelfth aspect, this application provides a program product comprising a computer program stored in a readable storage medium, wherein at least one processor of an encoding apparatus can read the computer program from the readable storage medium, and the at least one processor executes the computer program to cause the encoding apparatus to implement the encoding method described in the first aspect and various possible designs of the first aspect, or the decoding method provided in the sixth aspect and various possible designs of the sixth aspect.

[0174] By adopting the irreducible CRC polynomial proposed in this application, the CRC nesting requirements of the system can be met, ensuring normal communication. Attached Figure Description

[0175] Figures 1(a) and 1(b) are schematic diagrams of the communication system architecture used in the embodiments of this application;

[0176] Figure 2 This is a flowchart of a communication system;

[0177] Figure 3 A flowchart illustrating an embodiment of an encoding method provided in this application;

[0178] Figure 4 This is a schematic diagram of CRC encoding.

[0179] Figure 5 This is one of the schematic diagrams of the encoding device structure in the embodiments of this application;

[0180] Figure 6 This is the second schematic diagram of the encoding device structure in the embodiments of this application;

[0181] Figure 7 This is the third schematic diagram of the encoding device structure in the embodiments of this application;

[0182] Figure 8 This is one of the schematic diagrams of the decoding device in the embodiments of this application;

[0183] Figure 9 This is the second schematic diagram of the decoding device structure in the embodiments of this application;

[0184] Figure 10 This is the third schematic diagram of the decoding device structure in the embodiments of this application;

[0185] Figure 11 This is a schematic diagram of the network device and terminal in the embodiments of this application. Detailed Implementation

[0186] Polar codes are linear block codes whose generator matrix is ​​G. N Its encoding process is as follows It is a binary row vector with a length of N (i.e., code length); and here Defined as the Kronecker product of log2 N matrices F2, x1 N These are the encoded bits (also called codewords). With the generating matrix G N Multiplying the bits yields the encoded bits; the multiplication process is the encoding process. In the encoding process of polar codes, A portion of the bits in a set are used to carry information; these are called information bits. The set of indices of the information bits is denoted as . Another portion of the bits are set to fixed values ​​pre-agreed upon by the transmitting and receiving ends; these are called frozen bits, and their index set is used... supplement This indicates that the frozen bits are usually set to 0, and the sequence of frozen bits can be arbitrarily set as long as the transmitting and receiving ends agree in advance.

[0187] To further improve the coding performance of the system, a checksum-enabled outer code, such as a cascaded Cyclic Redundancy Check (CRC) code, can be concatenated outside the polar code. When using decoding methods such as Serial Cancellation List (RCL) decoding, surviving paths are typically selected based on CRC after decoding to improve the performance of the system's channel coding.

[0188] When applying Polar codes to practical communication systems, to further improve their application flexibility, the nested nature of CRC can be considered. This involves using the same CRC polynomial to support different numbers of check bits, allowing for different optimal CRC lengths to be matched for payloads of varying sizes. For example, the various nesting methods mentioned in PCT / CN2022 / 124663 are applicable and will not be elaborated upon here. Furthermore, by evaluating the performance of error detection and correction, it was found that reduced polynomials have better error detection and correction performance than non-reduced polynomials. Therefore, it is recommended that the CRC polynomial be a reduced polynomial, meaning it cannot be factored further. Here, a reduced polynomial refers to a rational coefficient polynomial with a degree greater than zero, which cannot be factored into the product of two rational coefficient polynomials with lower degrees but both greater than zero.

[0189] This necessitates considering how to find a suitable concatenation method between CRC checksum and polar code based on nesting characteristics and the requirements of the reduced polynomial. This application focuses on determining a suitable CRC polynomial based on the value of L to meet system requirements and ensure normal communication.

[0190] The embodiments of this application can be applied to wireless communication systems. It should be noted that the wireless communication systems mentioned in the embodiments of this application include, but are not limited to: Long Term Evolution (LTE) and the three major application scenarios of 5G mobile communication systems: Enhanced Mobile Broadband (eMBB), URLLC, and Massive Machine-Type Communications (mMTC). Alternatively, the wireless communication system can also be a Device to Device (D2D) communication system, other communication systems, or future communication systems.

[0191] The communication device involved in this application can be configured in a communication device, which mainly includes network equipment or terminal equipment. If the transmitting end in this application is a network device, then the receiving end is a terminal device; if the transmitting end in this application is a terminal device, then the receiving end is a network device.

[0192] In this embodiment of the application, as shown in FIG1(a), the communication system 100 includes a network device 110 and a terminal 112. When the wireless communication network 100 includes a core network, the network device 110 can also be connected to the core network. The network device 110 can also communicate with an IP network 200, such as the Internet, a private IP network, or other data networks. The network device provides services to terminals within its coverage area. For example, referring to FIG1(a), the network device 110 provides wireless access to one or more terminals within its coverage area. In addition, the coverage areas of the network devices may overlap, such as network devices 110 and 120. The network devices can also communicate with each other; for example, network device 110 can communicate with network device 120.

[0193] Since either network device 110 or terminal 112 can use the encoding method described in this application embodiment when sending information or data, for ease of description, this application embodiment simplifies the communication system 100 to a system including a sending end and a receiving end as shown in FIG1(b). The sending end can be network device 110 and the receiving end can be terminal 112; or, the sending end can be terminal 112 and the receiving end can be network device 110. Network device 110 can be a device used to communicate with terminal devices. For example, it can be an evolved Node B (eNB or eNodeB) in an LTE system, a network-side device in a 5G network, a network-side device that communicates with a terminal in other networks, or a network-side device in a future network, etc. Alternatively, the network device can also be a relay station, access point, vehicle-mounted device, etc. In a terminal-to-device (D2D) communication system, the network device can also be a terminal that functions as a base station. Terminals may include various handheld devices, vehicle-mounted devices, wearable devices, computing devices or other processing devices connected to a wireless modem, as well as various forms of user equipment (UE), mobile station (MS), etc.

[0194] The encoding process involved in this application is roughly as follows: CRC check is performed on the information to be encoded; if necessary, the bit sequence after CRC check is interleaved, and then Polar code encoding is performed. In addition, the encoded bits after Polar code encoding can be subjected to one or more of the following according to the target code length M: rate matching, modulation, digital-to-analog conversion, frequency conversion, etc.

[0195] Figure 2 This is a flowchart of a communication system, such as... Figure 2As shown, at the transmitting end, the information source is transmitted after sequentially undergoing source coding, channel coding, rate matching (optional step), and modulation. At the receiving end, it is output to the sink after sequentially undergoing demodulation, rate matching dematching (optional step), channel decoding, and source decoding. The embodiments of this application mainly involve channel coding and channel decoding (referred to as channel coding and decoding), which will be described below with specific examples. The channel coding and decoding in the embodiments of this application can use Polar codes with concatenated CRC checks.

[0196] This application provides an encoding method and apparatus to satisfy nesting characteristics and reduced polynomial requirements. The method and apparatus involved in this application are applicable to both control channels and data channels, and to both uplink and downlink. The encoding method and apparatus provided in this application are described in detail below with reference to the accompanying drawings.

[0197] Figure 3 A flowchart of an embodiment of an encoding method provided in this application is shown below. Figure 3 As shown, the execution entity in this embodiment is the sending end, and the method in this embodiment may include:

[0198] S101. The sending end performs CRC encoding on the A bits of information to be encoded according to the CRC polynomial to obtain the first bit sequence. The first bit sequence includes L CRC bits and A information bits, where L and A are positive integers. L is also often referred to as the CRC length.

[0199] Considering the nesting characteristics and the requirements of the irreducible polynomial, when L=16, the CRC polynomial is any one of the following polynomials:

[0200] D^16+D^9+D^5+D^3+D^2+D+1; or

[0201] D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or

[0202] D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or

[0203] D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or

[0204] D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or

[0205] D^16+D^14+D^11+D^6+D^4+D^3+1; or

[0206] D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or

[0207] D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or

[0208] D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or

[0209] D^16+D^15+D^9+D^6+D^4+D^2+1; or

[0210] D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or

[0211] D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or

[0212] D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0213] D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0214] D^16+D^12+D^10+D^9+D^8+D^7+D^5+D^3+1; or

[0215] D^16+D^13+D^11+D^9+D^5+D^4+D^3+D+1; or

[0216] D^16+D^12+D^10+D^7+D^5+D^3+D^2+D+1.

[0217] It should be noted that the polynomials here can also be represented in hexadecimal notation, and the symmetric forms of these polynomials also apply. For example, the polynomial D^16+D^9+D^5+D^3+D^2+D+1 can be represented as 1E881, and its symmetric form is D^16+D^15+D^14+D^13+D^11+D^7+1. The other polynomials can be deduced in the same way, and will not be elaborated further below.

[0218] The specific process of CRC encoding based on the selected polynomial is no different from the currently used CRC encoding.

[0219] Specifically, after receiving A bits of information to be encoded, the sending end adds L CRC bits according to the CRC polynomial to obtain the first bit sequence.

[0220] The aforementioned A bits of information to be encoded can be arranged in sequence or in reverse order, or they may be obtained after other processing of the information bits; no limitation is made here.

[0221] One implementation of CRC encoding is as a shift register. For example, Figure 4 This is a common method for implementing CRC encoding using a shift register (or simply register). The feedback tap of the register is determined by the CRC polynomial D^4 + D^2 + 1, and the register content is initialized to a preset value. During encoding, the bits to be encoded are shifted into the register bit by bit from one side. A bit XOR operation is performed between the feedback tap and the corresponding state of the register, thus changing the register state. After all the bits to be encoded have been shifted into the register, bits of 0 equal to the CRC length are shifted in. Then, the register state is read and used as the CRC bits, which are then used as the CRC codeword. The L CRC bits in the first bit sequence can be located after the A bits to be encoded, before the A bits to be encoded, or at any position agreed upon by the sending and receiving ends.

[0222] S102. The transmitting end interleaves the first bit sequence to obtain the second bit sequence.

[0223] The interleaving step described above can be performed on a portion of the bits in the first bit sequence, or on all bits in the first bit sequence. It should be noted that this step is optional: it is only necessary when the positions of information bits and / or CRC check bits need to be adjusted; otherwise, this step can be omitted in the actual encoding process. In this case, the second bit sequence in step S103 is the same as the first bit sequence. Specific interleaving schemes are not the focus of this application and will not be elaborated further.

[0224] S103. The transmitting end performs polar coding on the second bit sequence to obtain the third bit sequence. When step S102 is omitted, this step is for the transmitting end to perform polar coding on the first bit sequence to obtain the third bit sequence.

[0225] The polar coding method used by the sending end for the second bit sequence can be an existing polar coding method, which will not be elaborated here.

[0226] S104 (not shown in the figure): The transmitting end performs some or all of the steps, including but not limited to rate matching, modulation, analog-to-digital conversion, and frequency conversion, on the third bit sequence before transmitting it.

[0227] It should be noted that the rate matching step in step S104 is optional. If the code length of the encoded code is the same as the code length of the target code, rate matching is not required. Since the focus of this embodiment of the invention is not on step S104, it will not be described in detail here. For example, in one possible implementation, those skilled in the art can refer to the practices in the prior art.

[0228] The encoding method provided in this embodiment involves the sending end performing CRC encoding on A bits of information to be encoded according to the CRC polynomial proposed in this application to obtain a first bit sequence. Then, the first bit sequence is interleaved (if necessary) and polar encoded. This ensures that the polar encoding method used after cascading CRC can meet the requirements of nesting characteristics and the reduced polynomial.

[0229] It should be noted that after the receiving end (decoding side) receives the bits of information to be decoded, it also needs to perform CRC verification according to the same CRC polynomial, which will not be elaborated here.

[0230] The decoding method at the receiving end in this embodiment of the application generally includes the following operations: receiving the sequence to be decoded, and performing Polar code decoding on the obtained sequence to be decoded according to the CRC polynomial. The receiving end can be any of the following: a base station, a functional module in the base station, a chip in the base station, a terminal, a functional module in the terminal, or a chip in the terminal.

[0231] based on Figure 3 The same inventive concept as the encoding method shown, such as Figure 5 As shown, this application embodiment also provides a device 700, which is used to perform... Figure 3 The encoding method shown. Figure 3 The encoding method shown may be partially or entirely implemented in hardware or software. When implemented in hardware, the encoding device 700 includes: an input interface 701 for acquiring the bit sequence to be encoded; and a logic circuit 702 for executing the above-described encoding method. Figure 3 The encoding method shown is described in detail in the previous method embodiments and will not be repeated here; the output interface 703 is used to output the encoded bit sequence.

[0232] Optionally, the encoding device 700 can be a chip or an integrated circuit in its specific implementation.

[0233] Optionally, when some or all of the encoding methods in the above embodiments are implemented by software, such as Figure 6 As shown, the encoding device 800 includes: a memory 801 for storing a program; and a processor 802 for executing the program stored in the memory 801. When the program is executed, the encoding device 800 can perform the above-described functions. Figure 3The encoding method provided in the embodiment.

[0234] Optionally, the memory 801 described above can be a physically independent unit or it can be integrated with the processor 802.

[0235] Optionally, when the above Figure 3 When part or all of the encoding method in the embodiment is implemented by software, the encoding device 800 may also include only the processor 802. The memory 801 for storing the program is located outside the encoding device 800, and the processor 802 is connected to the memory 801 via circuits / wires to read and execute the program stored in the memory 801.

[0236] The processor 802 can be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.

[0237] The processor 802 may further include hardware chips. These hardware chips may be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The PLDs may be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof.

[0238] The memory 801 may include volatile memory, such as random-access memory (RAM); the memory 801 may also include non-volatile memory, such as flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory 801 may also include a combination of the above types of memory.

[0239] based on Figure 3 The same inventive concept as the encoding method shown, such as Figure 7As shown in the diagram, this application also provides a schematic diagram of an encoding device embodiment. The device may include: a first encoding module 901, an interleaving module 902, and a second encoding module 903. The first encoding module 901 is used to perform cyclic redundancy check (CRC) encoding on A bits of information to be encoded according to a CRC polynomial to obtain a first bit sequence. The first bit sequence includes L CRC bits and A information bits, where L and A are positive integers. Where L = 16, and the CRC polynomial is any one of the following polynomials:

[0240] D^16+D^9+D^5+D^3+D^2+D+1; or

[0241] D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or

[0242] D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or

[0243] D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or

[0244] D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or

[0245] D^16+D^14+D^11+D^6+D^4+D^3+1; or

[0246] D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or

[0247] D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or

[0248] D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or

[0249] D^16+D^15+D^9+D^6+D^4+D^2+1; or

[0250] D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or

[0251] D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or

[0252] D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0253] D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; or

[0254] D^16+D^12+D^10+D^9+D^8+D^7+D^5+D^3+1; or

[0255] D^16+D^13+D^11+D^9+D^5+D^4+D^3+D+1; or

[0256] D^16+D^12+D^10+D^7+D^5+D^3+D^2+D+1.

[0257] Generally, CRC encoding uses a CRC polynomial implemented through a shift register. The L CRC bits in the first bit sequence can be located after the A bits to be encoded, before the A bits to be encoded, or at any position agreed upon by the sending and receiving ends. The interleaving module 902 is optional and is used to perform an interleaving operation on the first bit sequence to obtain the second bit sequence. This module is only necessary when adjustments to the positions of information bits and / or CRC check bits are required for methods such as distributed CRC. If there is no such need, this module can be omitted in the actual encoding process; in this case, the second bit sequence is the same as the first bit sequence. The second encoding module 903 is used to perform polar encoding on the second bit sequence. When the interleaving module 902 is not present, the second encoding module 903 is used to perform polar encoding on the first bit sequence.

[0258] It is important to note that Figure 7 The diagram does not show modules such as rate matching, modulation, and transmission. The transmission module is used to send the encoded sequence. Of course, before transmission, rate matching (if necessary) and modulation operations are required.

[0259] Based on the same inventive concept as the decoding method provided in the above embodiments, such as Figure 8 As shown, this application embodiment also provides a decoding apparatus 1000, which can be used to execute the decoding method provided in this application embodiment. The decoding apparatus 1000 includes:

[0260] The acquisition module 1001 is used to acquire the bit sequence to be decoded;

[0261] The decoding module 1002 is used to perform decoding operations on the bit sequence to be decoded according to a decoding method determined based on CRC polynomial and polar coding method.

[0262] Based on the same inventive concept of the decoding method provided in the above embodiments, such as Figure 9 As shown in the embodiments of this application, a decoding device 1100 is also provided, which is used to execute the above-described decoding method. Part or all of the above-described decoding method can be implemented in hardware or software. When implemented in hardware, the decoding device 1100 includes: an input interface 1101 for acquiring the bit sequence to be decoded; a logic circuit 1102 for executing the above-described decoding method; and an output interface 1103 for outputting the decoded sequence.

[0263] Optionally, the decoding device 1100 may be a chip or an integrated circuit in its specific implementation.

[0264] Optionally, when some or all of the decoding methods in the above embodiments are implemented by software, such as... Figure 10 As shown, the decoding device 1200 includes: a memory 1201 for storing a program; and a processor 1202 for executing the program stored in the memory 1201. When the program is executed, the decoding device 1200 can implement the decoding method provided in the above embodiments.

[0265] Optionally, the memory 1201 described above can be a physically independent unit or it can be integrated with the processor 1202.

[0266] Optionally, when some or all of the decoding methods in the above embodiments are implemented by software, the decoding device 1200 may also include only the processor 1202. The memory 1201 for storing programs is located outside the decoding device 1200, and the processor 1202 is connected to the memory 1201 via circuits / wires to read and execute the programs stored in the memory 1201.

[0267] The processor 1202 can be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.

[0268] The processor 1202 may further include a hardware chip. This hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0269] Memory 1201 may include volatile memory, such as random-access memory (RAM); memory 1201 may also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory 1201 may also include combinations of the above types of memory.

[0270] This application also provides a network device, see [link to relevant documentation] Figure 11 As shown, the aforementioned encoding and / or decoding devices can be installed in network device 110. In addition to the encoding and decoding devices, network device 110 may also include a transceiver 1302. The bit sequence encoded by the encoding device is subsequently transformed or processed and then transmitted to terminal 112 via transceiver 1302. Alternatively, transceiver 1302 may also be used to receive information / data from terminal 112. This information / data is processed through a series of steps to be converted into a sequence to be decoded, and after processing by the decoding device, a decoded sequence is obtained. Network device 110 may also include a network interface 1304 for communication with other network devices.

[0271] Similarly, the aforementioned encoding and / or decoding devices can be configured in terminal 112. In addition to the aforementioned encoding and / or decoding devices, terminal 112 may also include a transceiver 1312. The bit sequence encoded by the encoding device, after subsequent transformations or processing (including but not limited to rate matching, modulation, digital-to-analog conversion, frequency conversion, etc., some or all), is transmitted to network device 110 through transceiver 1312. Alternatively, transceiver 1312 may also be used to receive information / data from network device 110. This information / data undergoes a series of processing steps to be converted into a sequence to be decoded (including but not limited to frequency conversion, analog-to-digital conversion, demodulation, de-rate matching, etc., some or all), and after processing by the decoding device, a decoded sequence is obtained. Terminal 112 may also include an input / output interface 1314 for receiving user input information. Information that needs to be sent to network device 110 needs to be processed by the encoder before being sent to network device 110 through transceiver 1312. Data decoded by the decoder, after subsequent processing, can also be presented to the user through input / output interface 1314.

[0272] This application embodiment also provides a computer storage medium storing a computer program, the computer program including functions for executing... Figure 3 The encoding method shown in the above embodiments and the decoding method provided in the above embodiments.

[0273] This application also provides a Polar code encoding device, including the above-mentioned... Figures 5-7 Any encoding device and Figures 8-10 Any type of decoding device.

[0274] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform... Figure 3 The encoding method shown and the decoding method provided in the above embodiments.

[0275] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0276] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0277] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0278] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0279] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0280] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. An encoding method characterized by comprising: The method comprises the following steps: The sending end performs CRC encoding on A to-be-encoded information bits according to a CRC polynomial to obtain a first bit sequence, the first bit sequence comprises L CRC bits and A information bits, L and A are positive integers, wherein L=16, and the CRC polynomial is any one of the following polynomials: D^16+D^9+D^5+D^3+D^2+D+1; or D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or D^16+D^14+D^11+D^6+D^4+D^3+1; or D^16+D^15+D^14+D^13+D^9+D^8+D^6+D^2+1; or D^16+D^15+D^14+D^12+D^11+D^10+D^9+D^6+D^5+D^2+1; or D^16+D^13+D^11+D^10+D^8+D^6+D^5+D^2+1; or D^16+D^15+D^9+D^6+D^4+D^2+1; or D^16+D^15+D^12+D^10+D^8+D^7+D^3+D^2+1; or D^16+D^14+D^12+D^11+D^5+D^4+D^3+D^2+1; or D^16+D^12+D^10+D^9+D^5+D^4+D^3+D^2+1; or D^16+D^15+D^13+D^11+D^10+D^9+D^5+D^4+D^3+D^2+1; The first bit sequence is polar encoded.

2. A decoding method, comprising: The method comprises the following steps: A receiving end receives a to-be-decoded sequence; The receiving end performs polar decoding on the to-be-decoded sequence according to a CRC polynomial to obtain a decoded sequence, the decoded sequence comprises L CRC bits and A information bits, L and A are positive integers, wherein L=16, and the CRC polynomial is any one of the following polynomials: D^16+D^9+D^5+D^3+D^2+D+1; or D^16+D^14+D^13+D^10+D^8+D^3+D^2+D+1; or D^16+D^13+D^12+D^11+D^10+D^9+D^6+D+1; or D^16+D^12+D^10+D^9+D^7+D^5+D^3+D+1; or D^16+D^15+D^14+D^13+D^12+D^11+D^8+D^7+D^6+D^4+1; or D^16+D^14+D^11+D^6+D^4+D^3+1; or D16+D15+D14+D13+D9+D8+D6+D2+1; or D16+D15+D14+D12+D11+D10+D9+D6+D5+D2+1; or D16+D13+D11+D10+D8+D6+D5+D2+1; or D16+D15+D9+D6+D4+D2+1; or D16+D15+D12+D10+D8+D7+D3+D2+1; or D16+D14+D12+D11+D5+D4+D3+D2+1; or D16+D12+D10+D9+D5+D4+D3+D2+1; or D16+D15+D13+D11+D10+D9+D5+D4+D3+D2+1.

3. The method according to claim 1 or 2, characterized in that, The CRC polynomial is implemented by a shift register.

4. The method according to any one of claims 1 to 3, characterized in that, The L CRC bits are located after the A information bits to be encoded.

5. The method of claim 1, wherein, The sending end sends the first bit sequence after the polar encoding.

6. The method of any one of claims 1 or 3-5, wherein, The sending end is any one of a base station, a chip in a base station, a terminal, or a chip in a terminal.

7. The method according to any one of claims 2-4, characterized in that, The receiving end is any one of a base station, a functional module in a base station, a chip in a base station, a terminal, a functional module in a terminal, or a chip in a terminal.

8. An encoding apparatus, comprising: Comprising: A first encoding module configured to perform CRC encoding on A information bits to be encoded according to a CRC polynomial to obtain a first bit sequence, the first bit sequence comprising L CRC bits and A information bits, L and A being positive integers, wherein L=16, and the CRC polynomial is any one of the following polynomials: D16+D9+D5+D3+D2+D+1; or D16+D14+D13+D10+D8+D3+D2+D+1; or D16+D13+D12+D11+D10+D9+D6+D+1; or D16+D12+D10+D9+D7+D5+D3+D+1; or D16+D15+D14+D13+D12+D11+D8+D7+D6+D4+1; or D16+D14+D11+D6+D4+D3+1; or D16+D15+D14+D13+D9+D8+D6+D2+1; or D16+D15+D14+D12+D11+D10+D9+D6+D5+D2+1; or D16+D13+D11+D10+D8+D6+D5+D2+1; or D16+D15+D9+D6+D4+D2+1; or D16+D15+D12+D10+D8+D7+D3+D2+1; or D16+D14+D12+D11+D5+D4+D3+D2+1; or D16+D12+D10+D9+D5+D4+D3+D2+1; or D 16 +D 14 +D 12 +D 11 +D 5 +D 4 +D 3 +D 2 +1; or D 16 +D 12 +D 10 +D 9 +D 5 +D 4 +D 3 +D 2 +1; or D 16 +D 15 +D 13 +D 11 +D 10 +D 9 +D 5 +D 4 +D 3 +D 2 +1; The second encoding module is used for polar encoding the first bit sequence.

9. A decoding device, comprising: Comprise: The acquisition module is used for acquiring a bit sequence to be decoded. The decoding module is used for performing polar decoding on the bit sequence to be decoded according to a cyclic redundancy check (CRC) polynomial to obtain a decoded sequence, the decoded sequence comprising L CRC bits and A information bits, L and A being positive integers, wherein L=16, and the CRC polynomial is any one of the following polynomials: D 16 +D 9 +D 5 +D 3 +D 2 +D+1; or D 16 +D 14 +D 13 +D 10 +D 8 +D 3 +D 2 +D+1; or D 16 +D 13 +D 12 +D 11 +D 10 +D 9 +D 6 +D+1; or D 16 +D 12 +D 10 +D 9 +D 7 +D 5 +D 3 +D+1; or D 16 +D 15 +D 14 +D 13 +D 12 +D 11 +D 8 +D 7 +D 6 +D 4 +1; or D 16 +D 14 +D 11 +D 6 +D 4 +D 3 +1; or D 16 +D 15 +D 14 +D 13 +D 9 +D 8 +D 6 +D 2 +1; or D 16 +D 15 +D 14 +D 12 +D 11 +D 10 +D 9 +D 6 +D 5 +D 2 +1; or D 16 +D 13 +D 11 +D 10 +D 8 +D 6 +D 5 +D 2 +1; or D 16 +D 15 +D 9 +D 6 +D 4 +D 2 +1; or D 16 +D 15 +D 12 +D 10 +D 8 +D 7 +D 3 +D 2 +1; or D 16 +D 14 +D 12 +D 11 +D 5 +D 4 +D 3 +D 2 +1; or D 16 +D 12 +D 10 +D 9 +D 5 +D 4 +D 3 +D 2 +1; or D 16 +D 15 +D 13 +D 11 +D 10 +D 9 +D 5 +D 4 +D 3 +D 2 +1.

10. The apparatus of claim 8 or 9, wherein, The CRC polynomial is implemented by a shift register.

11. The apparatus of any one of claims 8-10, wherein, The L CRC bits are located after the A information bits to be encoded.

12. The apparatus of claim 8, wherein, The device further comprises a sending module used for sending the polar encoded first bit sequence.

13. The apparatus of any of claims 8 or 10-12, wherein, The device is any one of the following: a base station, a chip in a base station, a terminal, or a chip in a terminal.

14. The apparatus of any of claims 9-11, wherein, The device is any one of the following: a base station, a functional module in a base station, a chip in a base station, a terminal, a functional module in a terminal, or a chip in a terminal.

15. An encoding apparatus, comprising: The processor is used for: CRC encoding is performed on A information bits to be encoded according to a cyclic redundancy check (CRC) polynomial to obtain a first bit sequence, the first bit sequence comprising L CRC bits and A information bits, L and A being positive integers, wherein L = 16, and the CRC polynomial being any one of the following polynomials: D 16 +D 9 +D 5 +D 3 +D 2 +D+1; or D 16 +D 14 +D 13 +D 10 +D 8 +D 3 +D 2 +D+1; or D 16 +D 13 +D 12 +D 11 +D 10 +D 9 +D 6 +D+1; or D 16 +D 12 +D 10 +D 9 +D 7 +D 5 +D 3 +D+1; or D 16 +D 15 +D 14 +D 13 +D 12 +D 11 +D 8 +D 7 +D 6 +D 4 +1; or D 16 +D 14 +D 11 +D 6 +D 4 +D 3 +1; or D 16 +D 15 +D 14 +D 13 +D 9 +D 8 +D 6 +D 2 +1; or D 16 +D 15 +D 14 +D 12 +D 11 +D 10 +D 9 +D 6 +D 5 +D 2 +1; or D 16 +D 13 +D 11 +D 10 +D 8 +D 6 +D 5 +D 2 +1; or D 16 +D 15 +D 9 +D 6 +D 4 +D 2 +1; or D 16 +D 15 +D 12 +D 10 +D 8 +D 7 +D 3 +D 2 +1; or D 16 +D 14 +D 12 +D 11 +D 5 +D 4 +D 3 +D 2 +1; or D 16 +D 12 +D 10 +D 9 +D 5 +D 4 +D 3 +D 2 +1; or D 16 +D 15 +D 13 +D 11 +D 10 +D 9 +D 5 +D 4 +D 3 +D 2 +1; polar encoding is performed on the first bit sequence.

16. A decoding device, comprising: A processor is included, and the processor is configured to: receive a sequence to be decoded; perform polar decoding on the sequence to be decoded according to a cyclic redundancy check (CRC) polynomial to obtain a decoded sequence, the decoded sequence comprising L CRC bits and A information bits, L and A being positive integers, wherein L = 16, and the CRC polynomial being any one of the following polynomials: D 16 +D 9 +D 5 +D 3 +D 2 +D+1; or D 16 +D 14 +D 13 +D 10 +D 8 +D 3 +D 2 +D+1; or D 16 +D 13 +D 12 +D 11 +D 10 +D 9 +D 6 +D+1; or D 16 +D 12 +D 10 +D 9 +D 7 +D 5 +D 3 +D+1; or D 16 +D 15 +D 14 +D 13 +D 12 +D 11 +D 8 +D 7 +D 6 +D 4 +1; or D 16 +D 14 +D 11 +D 6 +D 4 +D 3 +1; or D 16 +D 15 +D 14 +D 13 +D 9 +D 8 +D 6 +D 2 +1; or D 16 +D 15 +D 14 +D 12 +D 11 +D 10 +D 9 +D 6 +D 5 +D 2 +1; or D 16 +D 13 +D 11 +D 10 +D 8 +D 6 +D 5 +D 2 +1; or D 16 +D 15 +D 9 +D 6 +D 4 +D 2 +1; or D 16 +D 15 +D 12 +D 10 +D 8 +D 7 +D 3 +D 2 +1; or D 16 +D 14 +D 12 +D 11 +D 5 +D 4 +D 3 +D 2 +1; or D 16 +D 12 +D 10 +D 9 +D 5 +D 4 +D 3 +D 2 +1; or D 16 +D 15 +D 13 +D 11 +D 10 +D 9 +D 5 +D 4 +D 3 +D 2 +1. D16+D15+D14+D13+D9+D8+D6+D2+1; or D16+D15+D14+D12+D11+D10+D9+D6+D5+D2+1; or D16+D13+D11+D10+D8+D6+D5+D2+1; or D16+D15+D9+D6+D4+D2+1; or D16+D15+D12+D10+D8+D7+D3+D2+1; or D16+D14+D12+D11+D5+D4+D3+D2+1; or D16+D12+D10+D9+D5+D4+D3+D2+1; or D16+D15+D13+D11+D10+D9+D5+D4+D3+D2+1.

17. The apparatus of claim 15 or 16, wherein, The encoding apparatus further comprises a memory for storing program instructions.

18. The apparatus of any one of claims 15-17, wherein, The CRC polynomial is implemented by a shift register.

19. The apparatus of any one of claims 15-18, wherein, The L CRC bits are located after the A information bits to be encoded.

20. The apparatus of any one of claims 15 or 17-19, wherein, The apparatus is any one of the following: a base station, a chip in a base station, a terminal, or a chip in a terminal.

21. The apparatus of any one of claims 16-19, wherein, The apparatus is any one of the following: a base station, a functional module in a base station, a chip in a base station, a terminal, a functional module in a terminal, or a chip in a terminal.

22. An encoding apparatus, comprising: Comprising: an input interface configured to obtain a bit sequence to be encoded; a logic circuit configured to perform the method of any one of claims 1 or 2-5 based on the obtained bit sequence to be encoded, to obtain encoded bits; an output interface configured to output the encoded bits.

23. A communications device, characterized by The communication device comprises the encoding apparatus of any one of claims 15 or 17-19 and a transceiver; The transceiver is configured to transmit the encoded bits of the encoding apparatus.

24. A decoding device, comprising: Comprising: an input interface configured to obtain a bit sequence to be decoded; a logic circuit configured to perform the method of any one of claims 2-4 based on the obtained bit sequence to be decoded, to obtain decoded bits; an output interface configured to output the decoded bits.

25. A communications device, characterized by The communication device comprises the decoding apparatus of any one of claims 16-19 and a transceiver; The transceiver is configured to receive the bit sequence to be decoded.

26. A readable storage medium characterized by, Comprising: a readable storage medium and a computer program, the computer program being configured to implement the method of any one of claims 1-4.

27. A program product, characterized by The program product comprises a computer program stored in a readable storage medium, at least one processor of a communication device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to enable the communication device to implement the method of any one of claims 1-4.

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