Method and system for testing communication between board cards

Abstract

The embodiment of the invention provides a method and system for testing communication between board cards. The test system comprises a to-be-tested control board and a jig board, wherein the to-be-tested control board comprises a controller and a plurality of communication ports connected with the controller; the FPGA comprises a plurality of test modules, and the test modules are connected with the communication ports in a one-to-one correspondence manner; comprising the steps of receiving a request signal sent by a controller based on a communication port; the request signal is used for representing a target IP address of the target test module; based on the test module, determining a target MAC address of the target test module according to a target IP address of the target test module carried in the request signal; based on the test module, according to the target MAC address, generating and sending a response signal to the controller; wherein the controller is used for generating a test result based on the target MAC address in the response signal and the pre-stored IP address and MAC address of the test module. The method is used for achieving the effect of reducing the test cost of the communication test between the board cards.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and particularly relates to a communication test method and a test system between boards. BACKGROUND

[0002] In the production test phase of a server, a serial gigabit media independent interface (SGMII) signal is widely used in data transmission between a graphics processing unit (GPU) and a baseboard management controller (BMC) as a core interface for high-speed communication between boards. The reliability of the SGMII signal directly affects the overall communication performance and stability of the server, and therefore, the SGMII signal of each control board needs to be verified.

[0003] In the related art, a complete local network environment needs to be built, for example, the SGMII signal needs to be converted into a gigabit media independent interface (GMII) signal through a physical layer transceiver (PHY) chip, and a network is formed through an RJ45 interface and a switch, so as to realize communication test of the SGMII of the control board. However, this test method needs complex hardware devices and network topology, resulting in high test cost. SUMMARY

[0004] The communication test method and the test system between boards provided by the embodiments of the present application can reduce the test cost of communication test between boards.

[0005] In a first aspect, the embodiments of the present application provide a communication test method between boards, which is applied to an FPGA of a fixture board in a test system, the test system comprising a control board under test and the fixture board, the control board under test comprising a controller and a plurality of communication ports connected with the controller; the FPGA comprising a plurality of test modules, the test modules being connected with the communication ports one by one; the controller pre-storing IP addresses and MAC addresses of the test modules; and the method comprising:

[0006] receiving a request signal sent by the controller based on the communication port; wherein the request signal is used to represent a target IP address of a target test module;

[0007] determining a target MAC address of the target test module according to the target IP address of the target test module carried in the request signal based on the test module.

[0008] generating and sending a response signal to the controller according to the target MAC address based on the test module; wherein the controller is configured to generate a test result based on the target MAC address in the response signal and the pre-stored IP address and MAC address of the test module; and the test result is used to represent the communication state of the communication port of the control board under test.

[0009] In a possible implementation, the determining the target MAC address of the target test module according to the target IP address of the target test module carried in the request signal based on the test module comprises:

[0010] For each test module, when the target IP address of the target test module in the request signal matches the IP address of the test module successfully, the MAC address of the test module is determined as the target MAC address of the target test module.

[0011] In a possible implementation, the FPGA further comprises a conversion module, the conversion module is connected with the test module, and the conversion module is connected with the communication port one by one.

[0012] the receiving the request signal sent by the controller based on the communication port comprises:

[0013] receiving the request signal sent by the controller based on the communication port based on the conversion module;

[0014] transmitting the request signal to the test module after converting the request signal into a parallel request signal based on the conversion module.

[0015] In a possible implementation, the generating and sending a response signal to the controller according to the target MAC address based on the test module comprises:

[0016] generating an initial response signal according to the target MAC address based on the test module;

[0017] sending the initial response signal to the controller after converting the initial response signal into a response signal based on the conversion module.

[0018] In a second aspect, the embodiments of the present application provide a communication test method between boards, which is applied to a controller of a control board under test in a test system, the test system comprising the control board under test and a fixture board, the control board under test comprising a plurality of communication ports connected with the controller; the fixture board comprising an FPGA, the FPGA comprising a plurality of test modules, the test modules being connected with the communication ports one by one; and the controller pre-storing IP addresses and MAC addresses of the test modules; and the method comprising:

[0019] In response to the test request, a request signal is sent to the FPGA of the fixture board based on the communication port; wherein the request signal is used to represent a target IP address of a target test module;

[0020] A response signal returned by the FPGA is received based on the communication port; wherein the response signal carries a target MAC address of the target test module;

[0021] A test result is generated based on the target MAC address in the received response signal and the pre-stored IP address and MAC address of the test module; wherein the test result is used to represent the communication state of the communication port of the control board under test.

[0022] In a possible implementation, the test result is generated based on the target MAC address in the received response signal and the pre-stored IP address and MAC address of the test module, including:

[0023] For each communication port, the target MAC address in the received response signal and the pre-stored IP address and MAC address of the test module are matched to obtain a matching result;

[0024] The test result is generated based on the matching result.

[0025] In a possible implementation, the communication port is a serial gigabit media independent interface (SGMII).

[0026] In a third aspect, an embodiment of the present application provides a communication test device between boards, which is applied to the FPGA of a fixture board in a test system, the test system including a control board under test and a fixture board, the control board under test including a controller and a plurality of communication ports connected to the controller; the FPGA including a plurality of test modules, the test modules being connected to the communication ports one by one; the controller pre-storing IP addresses and MAC addresses of the test modules; the device including:

[0027] A receiving module is configured to receive a request signal sent by the controller based on the communication port; wherein the request signal is used to represent a target IP address of a target test module;

[0028] A determining module is configured to determine a target MAC address of a target test module according to the target IP address of the target test module carried in the request signal based on the test module;

[0029] a sending module configured to generate and send a response signal to the controller according to the target MAC address based on the test module; wherein the controller is configured to generate a test result based on the target MAC address in the response signal and the pre-stored IP address and MAC address of the test module; and the test result is used to represent the communication state of the communication port of the control board under test.

[0030] In a fourth aspect, an embodiment of the present application provides a communication test device between boards, which is applied to a controller of a control board under test in a test system, the test system comprising the control board under test and a fixture board, the control board under test comprising a plurality of communication ports connected to the controller; the fixture board comprising an FPGA, the FPGA comprising a plurality of test modules, the test modules being connected to the communication ports one by one; and the controller pre-storing IP addresses and MAC addresses of the test modules; and the device comprising:

[0031] a sending module configured to send a request signal to the FPGA of the fixture board based on the communication port in response to a test request; wherein the request signal is used to represent a target IP address of a target test module;

[0032] a receiving module configured to receive a response signal returned by the FPGA based on the communication port; wherein the response signal carries a target MAC address of a target test module;

[0033] a generating module configured to generate a test result based on the target MAC address in the received response signal and the pre-stored IP address and MAC address of the test module; and the test result is used to represent the communication state of the communication port of the control board under test.

[0034] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising: a memory and a processing unit.

[0035] The memory stores computer-executable instructions.

[0036] The processing unit executes the computer-executable instructions stored in the memory, so that the processing unit performs various possible implementations of the first aspect or the second aspect.

[0037] In a sixth aspect, an embodiment of the present application provides a test system, the test system comprising a control board under test and a fixture board, the control board under test comprising a controller and a plurality of communication ports connected to the controller; the fixture board comprising an FPGA, the FPGA comprising a plurality of test modules, the test modules being connected to the communication ports one by one; and the controller pre-storing IP addresses and MAC addresses of the test modules.

[0038] The FPGA is configured to perform the various possible implementation manners of the first aspect.

[0039] The controller is configured to perform the various possible implementation manners of the second aspect.

[0040] In a seventh aspect, an embodiment of the present application provides a computer readable storage medium, wherein computer execution instructions are stored in the computer readable storage medium, and the computer execution instructions are configured to implement the various possible implementation manners of the first aspect or the second aspect when executed by a processing unit.

[0041] In an eighth aspect, an embodiment of the present application provides a computer program product, comprising a computer program configured to implement the various possible implementation manners of the first aspect or the second aspect when executed by a processing unit.

[0042] The communication test method and test system between the boards provided by the embodiments of the present application, the controller sends a request signal carrying a target IP address to the FPGA of the fixture board through the communication port in response to a test request, the FPGA matches the target IP address through the test module and determines the corresponding target MAC address, generates a response signal carrying the target MAC address and returns to the controller, and the controller compares the received target MAC address with the pre-stored IP address and MAC address of the test module to generate a test result representing the state of the communication port. In this way, the FPGA integrated test module is used to replace the traditional complete local area network architecture including a PHY chip and a switch, and the multi-channel parallel test can be realized without additional hardware configuration, which simplifies the test environment construction process, reduces the test cost, ensures the accuracy of fault positioning through the accurate matching of the IP-MAC address, and at the same time, the multi-channel synchronous test mode greatly shortens the single board test period, improves the test efficiency in the batch production scene, and the whole process does not need manual intervention, which reduces the operation threshold and avoids human errors. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate one embodiment consistent with the present application and, together with the description, serve to explain the principles of the application.

[0044] Figure 1 It is a schematic diagram of an application scenario of a prior art;

[0045] Figure 2 It is a structural schematic diagram of a test system provided by the present application;

[0046] Figure 3 It is a structural schematic diagram of a test system provided by the present application;

[0047] Figure 4 It is a flowchart of a communication test method between boards provided by the present applicationFigure 1 ;

[0048] Figure 5 A flowchart of a communication test method between boards provided by the present application Figure 2 ;

[0049] Figure 6 A schematic diagram of an application scenario provided by an embodiment of the present application

[0050] Figure 7 A schematic diagram of a matching result provided by an embodiment of the present application

[0051] Figure 8 A structural schematic of a communication test device between boards provided by the present application Figure 1 ;

[0052] Figure 9 A structural schematic of a communication test device between boards provided by the present application Figure 2 ;

[0053] Figure 10 A structural schematic of an electronic device provided by the present application.

[0054] The specific embodiments of the present application have been shown and described in the above drawings, and will be described in more detail hereinafter. These drawings and the written description are not intended to restrict the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0055] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The same or similar components are denoted by the same reference numerals throughout the drawings and the following description, unless otherwise specified. The embodiments described in the following exemplary embodiments are not representative of all embodiments consistent with the present application. Rather, they are merely examples of devices and methods consistent with some aspects of the present application, as detailed in the appended claims.

[0056] Figure 1 A schematic diagram of an application scenario of a prior art, as shown in Figure 1 The conventional test needs to build a complete network environment, which usually includes a jig board, a control board under test, and a switch, wherein the jig board includes a microcontroller and a plurality of PHY chips connected one-to-one with RJ45 interfaces, the control board under test includes a BMC and a plurality of communication ports, the communication ports are connected one-to-one with the PHY chips, the RJ45 interfaces are connected one-to-one with the ports of the switch, and based on this, the control board under test is connected to a local area network.

[0057] PHY chip, used to convert the serial high-speed signal of SGMII into parallel GMII signal, to realize physical layer communication.

[0058] Microcontroller, used to initialize and dynamically configure the PHY chip, such as setting the rate, duplex mode, etc.

[0059] RJ45 interface and switch networking: connect the GMII signal to the switch through the RJ45 interface, and build a complete network environment to simulate the actual communication scenario.

[0060] The BMC first reads the link state register of the PHY chip through its own debugging tool combined with the microcontroller of the fixture board, confirms that the communication port of the BMC and the control board, the SGMII link physical layer between the communication port and the PHY chip of the fixture board have been normally established (i.e. the link state is UP), and then the BMC sends a data packet (such as a ping packet or an iperf traffic data) to the switch connected to the fixture board, and at the same time, the received data packet is captured on the switch side through a network tool (such as Wireshark), and the number and content of the data packet are verified synchronously whether they are consistent with the BMC sent, if there is no packet loss and no content damage in the sending process, it can be determined that the communication between the BMC and the fixture board is normal, that is, the communication of the communication port of the BMC is normal.

[0061] It can be seen that in the traditional test scheme, a complete LAN environment needs to be built, and this test method not only needs complex hardware equipment and network topology, but also requires the test personnel to have high network configuration ability, resulting in high test cost. The inventors of the present application consider that the core requirement of SGMII signal test is to verify the signal on-off state, rather than complete network communication, and the traditional scheme excessively relies on network networking, resulting in increased cost and complexity. Therefore, the present application provides a communication test method between boards, which uses FPGA to replace the combination of traditional PHY chip and microcontroller to convert the serial data of SGMII signal into parallel GMII data, and directly responds to the BMC test instruction through the preset ARP test module, without the need to build a complete network environment. This scheme can solve the problems of high hardware cost and complex process in traditional testing through hardware function integration and protocol layer simplification.

[0062] Figure 2 A structural schematic diagram of a test system provided by the present application is provided. As shown in Figure 2As shown, the test system 100 includes a control board under test 101 and a fixture board 102, the control board under test 101 includes a controller 103 and a plurality of communication ports 104 connected with the controller, and the fixture board 102 includes a Field Programmable Gate Array (FPGA) 105, the FPGA includes a plurality of test modules 106, and the test modules 106 are connected with the communication ports 104 one by one. Figure 2 The two communication ports are taken as an example for illustration.

[0063] The control board under test 101 is an electronic board card to be tested, for example, can be a server mainboard, a network device single board, etc., and is a test object of the test system, and the embodiment of the application does not limit the type of the control board under test. The control board under test is used to initiate a test instruction through a self-controller, and receives a response signal returned by the fixture board to complete fault judgment of the communication port.

[0064] The controller 103, as an initiator and a result judging party of a test process, pre-stores unique Internet Protocol Address (IP) addresses and Media Access Control (MAC) addresses of all test modules in the fixture board, sends a test request signal to each communication port through an internal link of the board card, receives a response signal returned through the communication port, analyzes the received response signal, matches the MAC address carried in the response signal with the pre-stored address information, generates a test result representing a communication state of each communication port, and supports positioning and recording of a fault channel. The controller can be a control unit with processing capability inherent to the control board under test, for example, can be a BMC or other microcontroller, etc., and the embodiment of the application does not limit this.

[0065] The communication port 104 refers to a communication interface used by the control board under test to communicate with other board cards, for example, can be an SGMII interface. Optionally, the control board under test can include a LAN SWITCH, and the LAN SWITCH is used to provide the communication port. It should be noted that the embodiment of the application does not limit the number of communication ports included in the control board under test, and the number can be set based on actual needs.

[0066] The fixture board 102 is a special test tool, used to receive a request signal of the control board under test, simulate a response signal returned by a network node, and provide a basis for fault judgment of the communication port.

[0067] The FPGA 105, as the core control unit of the jig board, is integrated with an SGMII-to-GMII function module, realizes bidirectional conversion between serial SGMII signals and parallel GMII signals, instantiates multiple independent test modules through logical programming, ensures that the signal processing of each test module does not interfere with each other, and supports multi-channel parallel response. It can be understood that the FPGA can be integrated with a high-speed serializer / deserializer (SERDES) module, a parallel data processing unit, a logical resource block, and a GPIO interface, supports user-defined logical programming, and can realize SGMII signal conversion, test module instantiation and other functions through a hardware description language; and the SERDES module of the FPGA directly supports the SGMII protocol, without the need for an external independent PHY chip, which can simplify the hardware architecture and reduce the cost of building a test environment.

[0068] The test module 106 refers to a lightweight address resolution protocol (ARP) test module realized through logical programming inside the FPGA. Each test module occupies independent FPGA logical resources, including an address storage unit, an ARP protocol processing unit, and a data interface unit, without an entity hardware chip. Each test module is preconfigured with a unique IP address and MAC address, and the address information is fixed in the FPGA logic, without the need for external instruction configuration; further, the test module can receive a test request signal, analyze the target IP address therein, trigger ARP response logic if the target IP address is consistent with the preconfigured IP address of the test module, generate a response signal carrying the IP address and MAC address of the test module, and return the response signal to the control board under test to complete closed-loop interaction. It should be noted that the communication ports of the test module and the control board under test are set one-to-one, support synchronous reception and response to multi-channel test requests, and test multiple ports in parallel.

[0069] Optionally, the SGMII-to-GMII function module can be integrated in the test module or separately arranged, for example, Figure 3 A structural schematic diagram of a test system provided by the present application is shown in FIG. 1. Figure 3 As shown in FIG. 1, the FPGA further includes a conversion module 107 integrated with a high-speed serializer / deserializer (SERDES) for realizing reception and transmission of SGMII signals and conversion between SGMII signals and GMII signals. The conversion module is connected one-to-one with the test module, and the conversion module is connected one-to-one with the communication port.

[0070] Test System 100 is a dedicated test system for verifying the communication status of communication ports between boards. For example, it can be used for the single-board testing phase of a server to detect the continuity of high-speed serial communication ports on which inter-board communication depends. Through a lightweight architecture that coordinates the control board under test and the fixture board, it replaces the traditional complex networking test environment and achieves low-cost and high-efficiency batch testing.

[0071] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0072] Figure 4 Flowchart of the inter-board communication testing method provided in this application Figure 1 ,like Figure 4 As shown, the method includes:

[0073] S201. In response to the test request, the controller sends a request signal to the FPGA on the fixture board via the communication port.

[0074] For example, a test request refers to a command signal that triggers a test, which can be issued by a host computer or triggered by the self-test of the control board under test, and is used to initiate connectivity verification of the communication port. Optionally, the test request may carry the target IP address of the target test module, which is used to test the specific communication port connected to the target test module.

[0075] A request signal is a data packet carrying test instructions, such as an ARP request signal. This request signal can be used to identify the target IP address of the target test module, thus locating the target test module. The target test module is the test module corresponding to the communication port to be tested. The target IP address is a unique Internet Protocol address pre-stored by the target test module, used for accurate identification of the test module.

[0076] In one example, the user sends a test request to the controller of the control board under test via a host computer. The controller immediately responds and calls its internal communication driver. Based on the test request, it determines the target IP address of the target test module from the pre-stored IP addresses of test modules. Based on the target IP address of the target test module and the preset request signal format, it generates a request signal and distributes it to the communication ports through the board's internal LAN interaction chip. Each communication port converts the parallel request signal into a serial request signal (SGMII signal) and transmits it to the FPGA on the fixture board via a test cable. It should be noted that the format of the request signal is not limited in this embodiment.

[0077] It should be noted that the test request can be used to represent that all communication ports of the control board under test are tested in batches, at this time, the test request can be represented as "arp -a", and the target IP address of the target test module indicated by the test request is the IP address of all pre-stored test modules; it can also be used to represent that part of the communication ports of the control board under test are tested, at this time, the test request can be represented as "arp -target IP address".

[0078] Correspondingly, the FPGA receiving controller receives the request signal sent by the communication port.

[0079] For example, the SERDES interface of the FPGA directly receives the request signal and transmits it into the internal processing link.

[0080] S202, the FPGA determines the target MAC address of the target test module according to the target IP address of the target test module carried in the request signal based on the test module.

[0081] Exemplarily, the target MAC address is a unique media access control address pre-stored by the target test module, which is used for the controller to verify the link connectivity.

[0082] In one example, after the FPGA receives the request signal, the FPGA converts the serial request signal into a parallel request signal based on the test module, and then distributes it to each test module according to the channel. Each test module extracts the target IP address in the request signal and compares it with the pre-stored IP address of itself. If the test module detects that the target IP address in the request signal is consistent with the pre-stored IP address of itself, it calls the internal address storage unit to extract the MAC address of itself as the target MAC address of the target test module.

[0083] S203, the FPGA generates and sends a response signal to the controller according to the target MAC address based on the test module.

[0084] Exemplarily, the response signal is a feedback data packet of the test module to the request signal, which can be an ARP response signal, for example. The response signal can carry the target IP address and the target MAC address of the target test module.

[0085] In one example, the test module that matches successfully can generate a response signal according to the target MAC address and a pre-set response signal format, convert the serial response signal into a parallel response signal, and then send it to the controller of the control board under test.

[0086] Correspondingly, the controller receives the response signal returned by the FPGA based on the communication port.

[0087] For example, after the communication port of the control board under test receives a serial signal, the serial signal is converted into parallel data and forwarded to the controller via the LAN interaction chip. The communication interface of the controller receives the response signal in real time.

[0088] S204, the controller generates a test result based on the target MAC address in the received response signal and the pre-stored IP address and MAC address of the test module.

[0089] For example, the pre-stored IP address and MAC address of the test module are reference data solidified in the storage unit of the controller before testing, which are completely consistent with the address information of the test module of the FPGA and are the reference for verifying the effectiveness of the response signal.

[0090] The test result is used to represent the communication state of the communication port of the control board under test, which can be normal communication and abnormal communication, for example. The communication state is a representation of the hardware link integrity of the communication port, which directly reflects the hardware quality of the port and the transmission link.

[0091] In one example, the controller can extract the target MAC address and the target IP address in each channel response signal and match them one by one with the pre-stored IP address and MAC address of the test module. If the target MAC address of the target IP address in the response signal is completely consistent with the MAC address corresponding to the pre-stored target IP address, it is determined that the communication port corresponding to the channel is in normal communication. If no response signal is received or the target MAC address of the target IP address in the response signal does not match the MAC address corresponding to the pre-stored target IP address, it is determined that the communication port is abnormal.

[0092] Optionally, the controller can integrate the determination results of all channels to generate a test report containing the channel number, state and abnormal reason.

[0093] The communication testing method between boards provided in this application involves the controller responding to a test request and sending a request signal carrying the target IP address to the FPGA on the fixture board via the communication port. The FPGA matches the target IP address and determines the corresponding target MAC address through the test module, generating a response signal carrying the target MAC address and sending it back to the controller. The controller compares the received target MAC address with the pre-stored IP address and MAC address of the test module to generate a test result characterizing the status of the communication port. This method replaces the traditional complex local area network architecture, including PHY chips and switches, with an integrated test module based on the FPGA. Multi-channel parallel testing can be achieved without additional hardware configuration, simplifying the test environment setup process, reducing test costs, and ensuring accurate fault location through precise IP-MAC address matching. Simultaneously, the multi-channel synchronous test mode significantly shortens the single-board test cycle, improves test efficiency in mass production scenarios, and the entire process requires no manual intervention, lowering the operational threshold and avoiding human error.

[0094] Figure 5 Flowchart of the inter-board communication testing method provided in this application Figure 2 ,like Figure 5 As shown, in this embodiment... Figure 4 Based on the embodiments, the communication testing method between boards is described in detail, and the method includes:

[0095] S301. In response to a test request, the controller sends a request signal to the FPGA on the fixture board via the communication port.

[0096] For example, taking a control board under test that includes 8 communication ports as an example, the pre-stored IP address and MAC address of the test module can be represented as:

[0097] ARP_0 MAC address 00:11:22:33:44:55, IP address 192.168.1.10;

[0098] ARP_1 MAC address 00:11:22:33:44:56, IP address 192.168.1.11;

[0099] ARP_2 MAC address 00:11:22:33:44:57, IP address 192.168.1.12;

[0100] ARP_3 MAC address 00:11:22:33:44:58, IP address 192.168.1.13;

[0101] ARP_4 MAC address 00:11:22:33:44:59, IP address 192.168.1.14;

[0102] ARP_5 MAC address 00:11:22:33:44:60, IP address 192.168.1.15;

[0103] ARP_6 MAC address 00:11:22:33:44:61, IP address 192.168.1.16;

[0104] ARP_7 MAC address 00:11:22:33:44:62, IP address 192.168.1.17.

[0105] The test request can be arp –a, and the controller generates a request signal based on the pre-stored IP addresses of all the test modules described above in response to the test request, distributes the request signal to the 8 SGMII communication ports through the board internal LAN interaction chip, and converts the parallel request number signal to a serial request signal by each communication port, which is transmitted to the FPGA of the fixture board through the test cable.

[0106] Figure 6 A schematic diagram of an application scenario provided by an embodiment of the present application is shown in FIG. 1. Figure 6 As shown in FIG. 1, the measured control board (IP address: 192.168.1.102) can broadcast an ARP request signal to the test module of the FPGA of the fixture board: Who is 192.168.1.10? Please tell me 192.168.1.102.

[0107] Correspondingly, the FPGA receives the request signal sent by the controller based on the conversion module based on the communication port.

[0108] For example, the FPGA receives the serial request signal through the SERDES interface based on the conversion module, and completes the cross-device transmission of the request signal.

[0109] S302, the FPGA transmits the request signal to the test module after converting it into a parallel request signal based on the conversion module.

[0110] Exemplarily, the parallel request signal refers to the converted GMII format signal, and the data is transmitted in a parallel manner and can be directly parsed by the test module.

[0111] In one example, after the FPGA receives 8-channel serial request signals based on the conversion module, the signal clock is extracted through the built-in clock recovery circuit, the serial data is split by bytes and converted into parallel GMII data, and after the conversion is completed, the parallel request signal of each channel is distributed to the corresponding 8 test modules based on the conversion module through the parallel data bus inside the FPGA, so as to ensure that each test module only receives the request data of its own channel and avoid interference between channels.

[0112] S303, the FPGA determines the MAC address of the test module as the target MAC address of the target test module when the target IP address of the target test module in the request signal matches the IP address of the test module.

[0113] Exemplarily, each test module pre-stores a unique IP address and MAC address, and the address information is fixed in the storage unit inside the module through hardware programming. The target IP address of the target test module in the request signal is the unique identifier of the target test module specified by the controller in the request, which is used to accurately locate the test module to be responded. The IP address of the test module is the unique identifier pre-stored by the test module itself. The MAC address is the physical address of the test module, which is used for link layer data interaction. The target MAC address is the physical address of the target test module determined after matching.

[0114] In one example, the FPGA can extract the target IP address from the received parallel request signal for each test module, and compare it with the pre-stored IP address bit by bit; when the test module detects that the target IP address in the request signal is consistent with the pre-stored IP address, it extracts the corresponding MAC address from the internal storage unit as the target MAC address; the test module that does not match successfully discards the current request signal and does not perform subsequent operations.

[0115] S304, the FPGA generates an initial response signal based on the test module and the target MAC address.

[0116] Exemplarily, the initial response signal refers to the response data in parallel format generated by the test module, which can be, for example, an ARP response data packet in GMII format, containing target IP address, target MAC address and other associated information. Specifically, based on the matched test module, the internal ARP response construction logic is called, and the target MAC address and the IP address of the test module are used as core data to encapsulate the data packet according to the ARP protocol frame format, add frame header, check bit and other fields, and form a complete initial response signal in GMII format.

[0117] S305, the FPGA converts the initial response signal into a response signal based on the conversion module and sends it to the controller.

[0118] Exemplarily, the response signal is a serial response data converted for cross-device transmission, which is consistent with the core information of the initial response signal but different in format. For example, the FPGA converts the initial response signal in GMII format into a serial signal in SGMII format based on the conversion module, encodes the serial signal into a response signal through a parallel-to-serial circuit, transmits the response signal to the SGMII communication port of the control board under test through a test cable, and decodes the serial signal into parallel data through the communication port and transmits the parallel data to the controller through a LAN interaction chip.

[0119] Correspondingly, the controller receives the response signal returned by the FPGA based on the communication port.

[0120] S306, for each communication port, matching the target MAC address in the received response signal with the pre-stored IP address and MAC address of the test module to obtain a matching result.

[0121] Exemplarily, the matching result is an independent determination conclusion of normal / abnormal communication of each communication port, which contains information such as port number and determination state. The normal communication indicates that the sending and receiving links and related hardware of the communication port are fault-free, and data can be transmitted normally; the abnormal communication indicates that there are problems such as open circuit and module failure in the link, resulting in data transmission failure or distortion.

[0122] In one example, the controller can call the pre-stored IP address and MAC address of the test module, compare the target MAC address in the received response signal with the pre-stored MAC address corresponding to the target IP address, and if they are consistent, it means that the matching is successful, and it is determined that the communication of the communication port is normal; if they are not consistent, it means that the matching fails, and if the matching fails or the target MAC address of the target test module is not received, it is determined that the communication of the communication port is abnormal.

[0123] For example, Figure 7 A schematic diagram of a matching result provided by an embodiment of the present application is shown in Figure 7 (a), the communication port (192.168.1.102) does not receive the target MAC address of the test module corresponding to 192.168.1.10, so it is determined that the communication of the communication port (192.168.1.102) is abnormal; and Figure 7 (b) shows that the communication port (192.168.1.102) receives the target MAC address of the test module corresponding to 192.168.1.10, and the target MAC address is consistent with the pre-stored MAC address corresponding to 192.168.1.10, indicating that the communication of the communication port (192.168.1.102) is normal.

[0124] S307, generating a test result based on the matching result.

[0125] Exemplarily, the test result is a summary report of matching results of all communication ports, and the state of each communication port is presented in a clear format, so as to facilitate the user to quickly locate the fault. For example, the controller can collect the matching results of 8 communication ports, arrange them in order according to the port number, and clearly show the on-off state of each communication port. Further, a structured test report can be generated, which can include test time, total number of ports, number of normal ports, list of abnormal ports and abnormal reasons, and is displayed through the upper computer interface or stored locally. Table 1 is a schematic of a test result provided by an embodiment of the present application.

[0126] Table 1 Test result

[0127]

[0128] The communication test method between boards provided by the embodiment of the present application, the controller sends a request signal to the FPGA of the fixture board through the communication port in response to a test request, the FPGA receives the request signal based on the conversion module and converts it into a parallel format and transmits it to the test module, the target MAC address is determined based on each test module through matching the target IP address in the request and an initial response signal is generated, the initial response signal is converted into a serial response signal by the conversion module and is returned to the controller, the controller compares the received target MAC address with the pre-stored address to determine the state of each communication port, and finally generates a test result based on the determination results of all ports. In this way, based on the FPGA integrated conversion module and test module, the configuration link of the traditional test independent PHY chip and microcontroller is omitted, the test environment building process is simplified and the hardware cost is reduced; at the same time, each test module is processed in parallel to realize multi-channel synchronous test, combined with the address accurate matching logic, which not only improves the efficiency of batch testing, but also accurately locates the fault port; and the whole process does not need manual intervention, the stability of the test is ensured through hardware level signal processing, and human operation errors are effectively avoided, providing an efficient and reliable solution for single board production test.

[0129] Figure 8 Structure diagram of the communication test device between boards provided by the present application Figure 1 As shown in Figure 8 The communication test device between boards provided by the embodiment can be applied to the FPGA, which includes:

[0130] The receiving module 401 is configured to receive the request signal sent by the controller based on the communication port; wherein the request signal is used to represent the target IP address of the target test module;

[0131] The determination module 402 is configured to determine the target MAC address of the target test module according to the target IP address of the target test module carried in the request signal based on the test module;

[0132] The sending module 403 is configured to generate and send a response signal to the controller according to the target MAC address based on the test module; and the controller is configured to generate a test result based on the target MAC address in the response signal and the pre-stored IP address and MAC address of the test module; and the test result is used to represent the communication state of the communication port of the control board under test.

[0133] In a possible implementation, the determining module 402 is configured to:

[0134] For each test module, when the target IP address of the target test module in the request signal matches the IP address of the test module successfully, the MAC address of the test module is determined as the target MAC address of the target test module.

[0135] In a possible implementation, the FPGA further includes a conversion module, which is connected with the test module and connected with the communication ports one by one.

[0136] The receiving module 401 is configured to:

[0137] The request signal sent by the controller based on the communication port is received based on the conversion module.

[0138] The request signal is converted into a parallel request signal and then transmitted to the test module based on the conversion module.

[0139] In a possible implementation, the sending module 403 is configured to:

[0140] The initial response signal is generated according to the target MAC address based on the test module.

[0141] The initial response signal is converted into a response signal and then sent to the controller based on the conversion module.

[0142] The communication test device between the boards provided in this embodiment can execute the method provided in the method embodiment, and has similar implementation principles and technical effects, which will not be described here in detail.

[0143] Figure 9 The structure of the communication test device between the boards provided in this embodiment Figure 2 As shown in Figure 9 The communication test device between the boards 500 provided in this embodiment can be applied to a controller and includes:

[0144] The sending module 501 is configured to send a request signal to the FPGA of the fixture board based on the communication port in response to a test request; and the request signal is used to represent the target IP address of the target test module.

[0145] The receiving module 502 is configured to receive a response signal returned by the FPGA based on the communication port; wherein the response signal carries a target MAC address of the target test module;

[0146] The generating module 503 is configured to generate a test result based on the target MAC address in the received response signal and the pre-stored IP address and MAC address of the test module; wherein the test result is used to represent the communication state of the communication port of the measured control board.

[0147] In a possible implementation, the generating module 503 is configured to:

[0148] For each communication port, the target MAC address in the received response signal and the pre-stored IP address and MAC address of the test module are matched to obtain a matching result.

[0149] The test result is generated based on the matching result.

[0150] In a possible implementation, the communication port is a serial gigabit media independent interface (SGMII).

[0151] The communication test device between the boards provided by the embodiment can execute the method provided by the method embodiment, and has similar implementation principles and technical effects, which will not be described here.

[0152] Figure 10 The structure of the electronic device provided in the present application is shown in the figure. Figure 10 As shown in the figure, the electronic device 600 provided by the embodiment includes at least one processing unit 601 and a memory 602. Optionally, the electronic device 600 further includes a communication component 603. The processing unit 601, the memory 602 and the communication component 603 are communicatively connected. The electronic device can be the controller or the FPGA described above.

[0153] In the specific implementation process, the at least one processing unit 601 executes the computer execution instructions stored in the memory 602, so that the at least one processing unit 601 executes the method described above.

[0154] The specific implementation process of the processing unit 601 can refer to the method embodiment described above, and has similar implementation principles and technical effects, which will not be described here.

[0155] In the above embodiments, it should be understood that the processing unit can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or can also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly embodied as hardware processor execution, or executed by a combination of hardware and software modules in the processor. The processing unit can also be a programmable logic unit.

[0156] The memory can include a random access memory (RAM), and can also include a non-volatile memory (NVM), such as at least one disk memory.

[0157] The communication connection can be a bus connection, where the bus can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus, an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus. The communication connection can also be based on programmable interconnection resources.

[0158] The present application also provides a computer program product, comprising a computer program, which, when executed by the processing unit, implements the above method.

[0159] The present application also provides a computer readable storage medium, which stores computer execution instructions, and when the processing unit executes the computer execution instructions, the above method is implemented.

[0160] The above-mentioned readable storage medium can be realized by any type of volatile or nonvolatile storage devices or their combinations, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0161] An exemplary readable storage medium is coupled to the processing unit, so that the processing unit can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processing unit. The processing unit and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processing unit and the readable storage medium can also exist as discrete components in the device.

[0162] The division of units is only a logical functional division, and in actual implementation, there can be another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection between the units through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0163] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0164] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0165] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the method of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0166] It can be understood by those skilled in the art that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware. The aforementioned program can be stored in a computer readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, and various media that can store program codes.

[0167] Finally, it should be noted that: those skilled in the art will easily think of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application that follow the general principles of the present application and include common knowledge or conventional technical means in the art that are not disclosed in the present application, and is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present application is only limited by the appended claims.

Claims

1. A method of testing board-to-board communication, the method comprising: The method is applied to an FPGA of a fixture board in a test system, the test system comprising a control board under test and the fixture board, the control board under test comprising a controller and a plurality of communication ports connected with the controller; the FPGA comprising a plurality of test modules, the test modules being connected with the communication ports one by one; the controller pre-storing IP addresses and MAC addresses of the test modules; the method comprising: receiving a request signal sent by the controller based on the communication ports; wherein the request signal is used to represent a target IP address of a target test module; determining a target MAC address of the target test module based on the target IP address of the target test module carried in the request signal based on the test module; generating and sending a response signal to the controller based on the target MAC address based on the test module; wherein the controller is used to generate a test result based on the target MAC address in the response signal and the pre-stored IP addresses and MAC addresses of the test modules; the test result is used to represent a communication state of the communication ports of the control board under test.

2. The method of claim 1, wherein, The method further comprises: for each test module, when the target IP address of the target test module in the request signal matches the IP address of the test module successfully, determining the MAC address of the test module as the target MAC address of the target test module.

3. The method according to claim 1 or 2, characterized in that, The FPGA further comprises a conversion module connected with the test modules, the conversion module being connected with the communication ports one by one; The method further comprises: receiving the request signal sent by the controller based on the communication ports based on the conversion module; converting the request signal into a parallel request signal and then transmitting the parallel request signal to the test modules based on the conversion module.

4. The method of claim 3, wherein, The method further comprises: generating an initial response signal based on the target MAC address based on the test module; converting the initial response signal into a response signal and then sending the response signal to the controller based on the conversion module.

5. A method of testing inter-board communication, characterized by, The method is applied to a controller of a control board under test in a test system, the test system comprising the control board under test and a fixture board, the control board under test comprising a plurality of communication ports connected with the controller; the fixture board comprising an FPGA, the FPGA comprising a plurality of test modules, the test modules being connected with the communication ports one by one; the controller pre-storing IP addresses and MAC addresses of the test modules; the method comprising: in response to a test request, sending a request signal to the FPGA of the fixture board based on the communication ports; wherein the request signal is used to represent a target IP address of a target test module; receive a response signal returned by the FPGA based on the communication port; wherein the response signal carries a target MAC address of a target test module; generate a test result based on the target MAC address in the received response signal and pre-stored IP address and MAC address of the test module; wherein the test result is used to represent the communication state of the communication port of the control board under test.

6. The method of claim 5, wherein, The method further includes: For each communication port, match the target MAC address in the received response signal and the pre-stored IP address and MAC address of the test module to obtain a matching result; generate the test result based on the matching result.

7. The method of claim 5, wherein, The communication port is a serial gigabit media independent interface (SGMII).

8. A test system, characterized by The test system includes a control board under test and a fixture board, the control board under test includes a controller and a plurality of communication ports connected to the controller; the fixture board includes an FPGA, the FPGA includes a plurality of test modules, the test modules are connected to the communication ports one by one; the controller pre-stores IP address and MAC address of the test module; The FPGA is configured to execute the method according to any one of claims 1-4; The controller is configured to execute the method according to any one of claims 5-7.

9. An electronic device, comprising: The method further includes: a memory, a processing unit; The memory stores computer execution instructions; The processing unit executes the computer execution instructions stored in the memory, so that the processing unit executes the method according to any one of claims 1-7.

10. A computer readable storage medium characterized by, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processing unit to implement the method according to any one of claims 1-7.

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