Network test transmission optimization method and test system

Abstract

The invention provides a network test transmission optimization method and a test system, and belongs to the technical field of network test.According to the network test transmission optimization method, by only transmitting header and load description information of less than four layers, compared with transmission of a complete data packet, the data transmission amount of a PCIe bus is greatly reduced, and bandwidth occupation of the PCIe bus is remarkably reduced; the FPGA intelligent network card locally completes load generation, assembly and detection without relying on mainboard CPU processing, data interaction time delay is reduced, and the concurrent test capability of a test instrument is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of network testing, and in particular to a network testing transmission optimization method and a testing system. BACKGROUND

[0002] With the rapid development of cloud computing, big data and 5G communication technology, the network bandwidth of data centers is undergoing a rapid evolution process from 10Gbps to 25Gbps, 100Gbps, 200Gbps and even 400Gbps. In order to verify the performance and stability of these high-speed network devices such as switches, routers, firewalls, load balancers, etc., network testing instruments play a crucial role.

[0003] In actual 4-7 layer network testing, there are two typical scenarios: the first type is that there is no requirement for the specific content of the 4-layer or above (i.e. above the transport layer, including the application layer, presentation layer, etc.) load, and only the data packet format compliance and transmission performance testing requirements need to be met; the second type is that the content of the 4-layer or above load is limited, i.e. the load set is fixed and can be enumerated in advance, and there is no need to transmit the complete load data each time.

[0004] In the prior art, whether the 4-layer or above load content is required or not, the complete data packet (including the 4-layer or below header and the 4-layer or above load) is transmitted through the PCIe (peripheral component interconnect express) bus. When the port rate reaches the 400G level, the transmission of the 4-layer or above load will occupy a large amount of PCIe bandwidth, causing the PCIe bus to be saturated, limiting the port rate improvement and concurrent testing capability of the testing instrument, and unable to meet the testing requirements in the high-bandwidth scenario. Therefore, there is an urgent need for a PCIe transmission optimization scheme for the above two types of scenarios to reduce the amount of transmission data on the PCIe bus without affecting the testing accuracy, and to break through the performance bottleneck. SUMMARY

[0005] The present application provides a network testing transmission optimization method and a testing system to solve the defect of large amount of bus data during testing in the prior art, and to achieve the effect of reducing the data transmission amount of the PCIe bus.

[0006] The present application provides a network testing transmission optimization method, which is applied to a testing system including an instrument mainboard and a field programmable gate array (FPGA) intelligent network card, the instrument mainboard and the FPGA intelligent network card are connected through a peripheral component interconnect express (PCIe) bus; the method includes a sending process and a receiving process. The sending process comprises: the instrument mainboard generates a 4-layer or below header and load description information corresponding to a 4-layer or above load according to test requirements; the instrument mainboard sends the 4-layer or below header and the load description information to the FPGA intelligent network card through the PCIe bus; the FPGA intelligent network card receives the 4-layer or below header and the load description information, and obtains corresponding 4-layer or above load content according to the load description information; the FPGA intelligent network card assembles the 4-layer or below header and the obtained 4-layer or above load content into a complete data packet, and sends the complete data packet to the network under test through a physical port. The receiving process comprises: the FPGA intelligent network card receives a data packet from the network under test through a physical port, and parses a 4-layer or below header and a 4-layer or above load; the FPGA intelligent network card performs feature detection on the 4-layer or above load, and obtains corresponding load description information; the FPGA intelligent network card sends the 4-layer or below header and the obtained load description information to the instrument mainboard through the PCIe bus; and the instrument mainboard completes test data statistics according to the received 4-layer or below header and load description information.

[0007] According to the network test transmission optimization method provided in the application, when the test scenario is that there is no requirement for 4-layer or above load content, the load description information is load length information. The obtaining of the 4-layer or above load content according to the load description information specifically comprises: The FPGA intelligent network card locally generates random data meeting length requirements as load data according to the load length information, and inserts a target pseudo-random binary sequence as an identifier at a preset position of the load data.

[0008] According to the network test transmission optimization method provided in the application, the FPGA intelligent network card performs feature detection on the 4-layer or above load, and the feature detection specifically comprises: The FPGA intelligent network card detects whether the target pseudo-random binary sequence exists in the 4-layer or above load of the received data packet; If the target pseudo-random binary sequence is detected, it is determined that the data packet does not need to transmit load content, load length is extracted as the load description information, and the load description information is sent to the instrument mainboard through the PCIe bus.

[0009] According to the network test transmission optimization method provided in the application, when the test scenario is that 4-layer or above load content is limited, the load description information is a load ID. Before the sending process is performed, the method further comprises a pre-configuration process, and the pre-configuration process comprises: The instrument mainboard generates a mapping table of all preset 4-layer or more load contents, corresponding load IDs and check values; The mapping table is loaded into the local memory of the FPGA smart network card through the PCIe bus.

[0010] According to the network test transmission optimization method, the corresponding 4-layer or more load content is obtained according to the load description information, and specifically includes the following steps. The FPGA smart network card queries the mapping table in the local memory according to the received load ID, and reads the corresponding 4-layer or more load content.

[0011] According to the network test transmission optimization method, in the receiving process, the FPGA smart network card performs feature detection on the 4-layer or more load, and specifically includes the following steps. The FPGA smart network card calculates the check value of the received 4-layer or more load, and queries the mapping table in the local memory according to the calculated check value; If the query matching is successful, the corresponding load ID is obtained as the load description information, and is sent to the instrument mainboard through the PCIe bus; if the query matching fails, the complete data packet is written into the memory of the instrument mainboard through the PCIe bus.

[0012] According to the network test transmission optimization method, the check value is calculated by using the MD5 algorithm, and the mapping table contains the corresponding relationship of the load ID, the load content and the MD5 value.

[0013] According to the network test transmission optimization method, the target pseudo-random binary sequence is a pseudo-random sequence PRBS-31 sequence, and the preset position is the 16th byte to the 48th byte after the starting position of the 4-layer or more load.

[0014] The application also provides a test system, which includes: The instrument mainboard is configured with upper-layer driving software, and is used for generating or processing the 4-layer or more load description information and the load description information of the data packet, and performing data interaction through the PCIe bus; The FPGA smart network card is connected with the instrument mainboard through the PCIe bus, and is configured with a local memory and a logic processing unit. The test system is configured to execute any one of the network test transmission optimization methods.

[0015] The application also provides an electronic device, which includes a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements any one of the network test transmission optimization methods when executing the program.

[0016] The application further provides a non-transitory computer-readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement any one of the network test transmission optimization methods.

[0017] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement any one of the network test transmission optimization methods.

[0018] The network test transmission optimization method and the test system provided by the application can greatly reduce the data transmission amount of the PCIe bus and significantly reduce the bandwidth occupation of the PCIe bus by transmitting only the 4-layer header and the load description information compared with transmitting complete data packets, the FPGA smart network card can locally complete load generation, assembly and detection without relying on the CPU of the motherboard for processing, the data interaction delay is reduced, and the concurrent test capability of the test instrument is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0020] Figure 1 Fig. 1 is a structural schematic diagram of the test system provided by the application; Figure 2 Fig. 2 is a flow schematic diagram of the network test transmission optimization method provided by the application; Figure 3 Fig. 3 is a structural schematic diagram of the electronic device provided by the application. DETAILED DESCRIPTION

[0021] In order to make the objects, technical solutions and advantages of the application clearer, the technical solutions in the application will be described clearly and completely below with reference to the drawings in the application. Obviously, the described embodiments are some embodiments of the application, but not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0022] The following will be described with reference to the drawings Figure 1 Fig. 3 describes the network test transmission optimization method and the test system of the application.

[0023] As shown in FIG. 1, the embodiment of the present application provides a test system, which is physically mainly composed of an instrument mainboard and an FPGA (Field Programmable Gate Array) smart network card, and the two communicate through a PCIe bus.

[0024] The instrument mainboard refers to a computing platform loaded with a high-performance general-purpose processor, which can be, for example, loaded with an x86 architecture CPU, supports a PCIE4.0 / 5.0 bus (x16 channel), and runs upper-layer driving software. The instrument mainboard can run an operating system (such as Linux) and upper-layer driving software. In the present application, the instrument mainboard is no longer responsible for the transportation of full-quantity data, but is transformed into a control core. The instrument mainboard is used to realize the maintenance of a protocol stack state machine, the generation of a 4-layer below header (L2-L4 Header), and the generation and management of load description information.

[0025] The software stack of the instrument mainboard: contains user-mode test application programs, kernel-mode or DPDK (Data Plane Development Kit) driving programs. The upper-layer driving software is responsible for managing a PCIe descriptor ring and realizing efficient interaction with the FPGA.

[0026] The FPGA smart network card refers to a network interface card integrated with a high-performance FPGA chip, which uses, for example, an Xilinx FPGA chip, integrates a 16GB DDR4 local RAM, and a hardware MD5 verification module.

[0027] The core logic processing unit of the FPGA chip is internally programmed with firmware that realizes the logic of the present application. The local memory is usually on-board DDR4 SDRAM or HBM. The physical port supports a QSFP-DD or OSFP package interface, and provides 100G / 400G physical connection. The FPGA can realize, internally, a PCIe Endpoint controller, a DMA engine, a data packet parser, a data packet assembler, a PRBS generation / verification module, a MD5 hardware acceleration module, etc.

[0028] The PCIe bus is used as a physical channel connecting the mainboard and the network card. In the present embodiment, a PCIe4.0x16 or PCIe5.0x16 interface can be used to provide as high a basic bandwidth as possible.

[0029] The 4-layer below header (L2-L4 Header) refers to the control information part in a network data packet, which usually contains an Ethernet frame header (MAC address, VLAN), an IP header (source / destination IP, TTL, protocol number), and a TCP / UDP header (source / destination port, sequence number, ACK number, flag bit). The length of this part is usually fixed and short, about 54-100 bytes.

[0030] 4-layer payload (L4+Payload) refers to the data part after the TCP / UDP header, that is, the application layer data such as HTTP message, FTP data block. In the 400G test, this part often accounts for more than 90% of the bandwidth.

[0031] The payload description information is not real payload data, but a short index or instruction for indicating how the FPGA network card generates or restores the payload. The payload description information can be a length value or a unique ID index.

[0032] As shown in Figure 2 The network test transmission optimization method of the embodiment of the application can be applied to the test system of the foregoing embodiment, that is, the test system can execute the network test transmission optimization method in the following embodiment. The method mainly includes a sending process and a receiving process.

[0033] The sending process includes: the instrument mainboard generates the 4-layer below header and the corresponding payload description information of the 4-layer above payload according to the test requirement; the instrument mainboard sends the 4-layer below header and the payload description information to the FPGA smart network card through the PCIe bus; the FPGA smart network card receives the 4-layer below header and the payload description information, and acquires the corresponding 4-layer above payload content according to the payload description information; the FPGA smart network card assembles the 4-layer below header and the acquired 4-layer above payload content into a complete data packet, and sends the complete data packet to the network under test through a physical port; The receiving process includes: the FPGA smart network card receives the data packet from the network under test through the physical port, and parses the 4-layer below header and the 4-layer above payload; the FPGA smart network card performs feature detection on the 4-layer above payload, and acquires the corresponding payload description information; the FPGA smart network card sends the 4-layer below header and the acquired payload description information to the instrument mainboard through the PCIe bus; and the instrument mainboard completes test data statistics according to the received 4-layer below header and the payload description information.

[0034] In some embodiments, the sending process is as follows.

[0035] The upper layer driving software of the instrument mainboard configures the header of the data packet according to the current test flow configuration. Meanwhile, a short payload description information is generated according to the test scene.

[0036] The instrument mainboard writes only the header Header and the payload description information into the descriptor ring accessible by the FPGA smart network card through the PCIe bus.

[0037] Compared with transmitting a complete packet, only a small number of bytes need to be transmitted at this time, and the PCIe bandwidth occupation is greatly reduced. For example, the PCIe bandwidth that can only run at 20Gbps can now theoretically drive physical traffic at 400Gbps.

[0038] The sending engine inside the FPGA smart NIC reads the descriptor and extracts the header. At the same time, the payload description information is parsed. If the description information is the length, the FPGA NIC starts the internal random number generator to generate data of the specified length.

[0039] If the description information is the payload ID, the FPGA smart NIC can start the DDR4 read controller to grab the pre-stored data block from the on-board memory according to the payload ID.

[0040] The packet assembly logic inside the FPGA smart NIC splices the header and the payload generated locally by the FPGA smart NIC, recalculates the IP checksum and the TCP / UDP checksum, and finally adds the frame check sequence, and sends it to the optical port through the physical MAC layer.

[0041] In some embodiments, the receiving process is as follows.

[0042] The FPGA smart NIC receives 400G line-speed traffic from the physical port. The parsing logic quickly separates the header and the payload. Instead of uploading the data directly, the FPGA smart NIC performs feature detection on the payload.

[0043] The FPGA smart NIC internally checks in parallel whether the payload contains a specific PRBS (Pseudo Random Binary Sequence) signature or calculates the MD5 hash value of the payload.

[0044] If the feature matching is successful, it means that it is a test packet, and the FPGA smart NIC can discard the heavy payload data and only extract the payload description information such as the payload length or the payload ID representing the payload.

[0045] The FPGA smart NIC only writes the "header + payload description information" into the motherboard memory through the PCIe DMA (Direct Memory Access). After receiving the simplified packet, the upper-layer software can count the packet loss, out-of-order, and delay according to the header, confirm the correctness of the data content according to the payload description information, and complete the test closed loop.

[0046] According to the network test transmission optimization method provided by the embodiment of the application, by transmitting only the 4-layer header and the payload description information, compared with transmitting the complete data packet, the data transmission amount of the PCIe bus is greatly reduced, and the bandwidth occupation of the PCIe bus is significantly reduced; the FPGA smart NIC locally completes the payload generation, assembly, and detection, without relying on the motherboard CPU processing, reduces the data interaction delay, and improves the concurrent test capability of the test instrument.

[0047] In the scenario of random load test without content requirement, such as RFC2544 benchmark test, TCP throughput test, etc., which does not focus on specific application layer content, the load description information can be load length information.

[0048] In some embodiments, the corresponding 4-layer or above load content is obtained according to the load description information, specifically including: the FPGA intelligent network card generates random data locally according to the load length information to meet the length requirement as load data, and inserts a target pseudo-random binary sequence as an identifier at a preset position of the load data.

[0049] The FPGA intelligent network card can integrate a linear feedback shift register module. When receiving the length instruction, the linear feedback shift register module operates at full speed, and 64 bytes or 128 bytes of pseudo-random numbers can be generated every clock cycle until the specified length is filled.

[0050] In some embodiments, the target pseudo-random binary sequence is a PRBS-31 sequence, and the preset position is the 16th byte to the 48th byte after the start position of the 4-layer or above load.

[0051] In order for the receiving end to identify that this is a test packet rather than background traffic or abnormal packets, a mark can be added.

[0052] For example, the mark can be a PRBS-31 sequence, which has a very long period and is extremely difficult to conflict with natural data. The insertion position can be selected as the 16th-48th byte after the start position. The first 16 bytes are avoided to prevent position offset caused by the expansion of the header of some protocols; and the length of 32 bytes is selected to ensure the robustness of detection.

[0053] Specifically, in the multiplexer logic of the FPGA intelligent network card when packetizing, when the counter reaches 16, the data source can be forcibly switched to the fixed PRBS generator output, lasting for 32 bytes, and then switched back to the random number generator.

[0054] In some embodiments, the FPGA intelligent network card performs feature detection on the 4-layer or above load, specifically including: the FPGA intelligent network card detects whether the target pseudo-random binary sequence exists in the 4-layer or above load of the received data packet; if the target pseudo-random binary sequence is detected, it is determined that the data packet does not need to transmit the load content, the load length is extracted as the load description information, and the load description information is sent to the instrument mainboard through the PCIe bus.

[0055] The receiving engine of the FPGA intelligent network card can include a sliding window detector or a fixed position comparator. When the 16th byte of the data packet is parsed, the comparator starts to compare the received bit stream with the locally pre-stored PRBS-31 sequence bit by bit.

[0056] If 32 bytes are matched, the FPGA smart NIC can perform a truncation operation, discard the payload content, retain only the header, and fill in the actual length value parsed into the PCIe descriptor and return it. If there is no match, it may be a protocol control packet or non-test data, and the FPGA smart NIC can perform a pass-through operation to upload the complete packet.

[0057] In this embodiment, through the PRBS identification mechanism, 100% data compression is achieved, and the legality of the data at the receiving end is guaranteed, i.e., it is not random code, but a marked test stream, solving the contradiction between bandwidth and accuracy.

[0058] In some embodiments, in the fixed payload test scenario with limited content, such as HTTP / HTTPS new connection test, web page playback, virus attack feature library playback, etc., the load content of these scenarios must be specific and cannot be random numbers, but the content set is limited.

[0059] When the test scenario is a 4-layer or more load content, the load description information can be a load ID.

[0060] Before executing the sending process, the method further includes a pre-configuration process, which includes: the instrument mainboard generates a mapping table of all preset 4-layer or more load content and its corresponding load ID and check value; and loads the mapping table into the local memory of the FPGA smart NIC through the PCIe bus.

[0061] In the initialization stage before the test starts, a cache warm-up can be performed. The upper-layer software scans all test messages to be sent, such as 100 different HTTP GET request message bodies, and assigns an ID (0~99) to each content. The MD5 value (128 bits) of each content is calculated, and a mapping table structure is constructed. The real content data and the mapping table can be transported to the FPGA on-board DDR4 memory through PCIe. Through one-time transportation, it can be used multiple times, and there is no need to repeatedly transmit static data during the test process.

[0062] According to the load description information, the corresponding 4-layer or more load content is obtained, specifically including: the FPGA smart NIC queries the mapping table in the local memory according to the received load ID, and reads the corresponding 4-layer or more load content.

[0063] When the FPGA smart NIC receives the "send ID=5" instruction, the internal memory controller calculates the physical address offset in the DDR4 according to ID=5. The FPGA smart NIC initiates local DMA reading, reads out the corresponding HTTP message body from the DDR4, and sends the read data after splicing to the IP / TCP header.

[0064] In some embodiments, in the receiving process, the FPGA smart NIC performs feature detection on the 4-layer or above load, specifically including: the FPGA smart NIC calculates the check value of the received 4-layer or above load, and queries the mapping table in the local memory according to the calculated check value; if the query matching is successful, the corresponding load ID is obtained as the load description information, and is sent to the instrument mainboard through the PCIe bus; if the query matching fails, the complete data packet is written into the memory of the instrument mainboard through the PCIe bus.

[0065] The check value is calculated by using the MD5 algorithm, and the mapping table contains the corresponding relationship of the load ID, the load content and the MD5 value.

[0066] The FPGA smart NIC cannot sequentially calculate MD5 as the CPU does. In this embodiment, the FPGA smart NIC can use the MD5 calculation engine of the pipeline architecture. When the data packet flows in at a rate of 400Gbps, the data can be divided into 512-bit blocks, and each clock cycle is sent to the MD5 pipeline. Regardless of the length of the packet, the 128-bit MD5 digest value can be calculated within several clock cycles after the data stream ends.

[0067] The FPGA smart NIC not only stores the "ID-content", but also stores the hash lookup table or content addressable memory logic of "MD5-ID". After calculating the MD5 value of the received packet, a fast matching is performed in the local storage of the FPGA smart NIC.

[0068] If the matching is successful, it means that the received packet content is correct and belongs to the preset set. At this time, the FPGA smart NIC does not need to upload the data, nor does it need to upload the MD5, but only needs to upload the ID. After receiving the ID, the instrument mainboard can confirm that a correct HTTP request has been received.

[0069] If the matching fails, it means that it may be an out-of-order packet, a tampered packet or a non-test packet. At this time, in order to facilitate the investigation of the problem, the FPGA smart NIC uploads the complete data packet to the instrument mainboard for analysis through the PCIe.

[0070] In this embodiment, the test rigor and the content integrity can be ensured through the check matching. At the same time, the ID feedback mechanism maintains a very low PCIe bandwidth occupation.

[0071] It can be understood that the 4-layer or above load content has no requirement in the scene, which ensures the load format compliance through a specific PRBS sequence, and the 4-layer or above load content is limited in the scene, which ensures the correctness of the load transmission through the MD5 check, and does not affect the core indicators such as throughput, delay and packet loss rate in the 4-7 layer network test.

[0072] In addition, the scheme of the embodiment of the present application has strong compatibility, can be based on the existing FPGA intelligent network card and PCIe bus architecture, does not need to modify the hardware interface, only needs to upgrade the FPGA firmware and the upper layer driving software, can adapt to mainstream 4-7 layer network test instruments, and has low upgrade cost.

[0073] Fig. 3 shows a schematic diagram of an entity structure of an electronic device, as shown in Fig. 3, the electronic device can include a processor 310, a communication interface 320, a memory 330 and a communication bus 340, wherein the processor 310, the communication interface 320, the memory 330 complete the communication among each other through the communication bus 340. The processor 310 can call the logical instructions in the memory 330 to execute the network test transmission optimization method, which includes a sending process and a receiving process; the sending process includes that the instrument mainboard generates the 4-layer below header and the corresponding load description information of the 4-layer above load of the data packet according to the test demand; the instrument mainboard sends the 4-layer below header and the load description information to the FPGA intelligent network card through the PCIe bus; the FPGA intelligent network card receives the 4-layer below header and the load description information, and obtains the corresponding 4-layer above load content according to the load description information; the FPGA intelligent network card assembles the 4-layer below header and the obtained 4-layer above load content into a complete data packet, and sends it to the network under test through a physical port; the receiving process includes that the FPGA intelligent network card receives the data packet from the network under test through the physical port, and parses to obtain the 4-layer below header and the 4-layer above load; the FPGA intelligent network card performs feature detection on the 4-layer above load, and obtains the corresponding load description information; the FPGA intelligent network card sends the 4-layer below header and the obtained load description information to the instrument mainboard through the PCIe bus; and the instrument mainboard completes the test data statistics according to the received 4-layer below header and the load description information.

[0074] In addition, the logical instructions in the memory 330 described above can be realized in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product stored in a storage medium includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0075] In another aspect, the present application also provides a computer program product, which comprises a computer program, the computer program being stored in a non-transitory computer readable storage medium, and the computer program being executable by a processor to enable the computer to perform the network test transmission optimization method provided by the above method, which comprises a sending process and a receiving process; the sending process comprises: generating, by an instrument mainboard, a 4-layer or lower header of a data packet and load description information corresponding to a 4-layer or higher load according to a test requirement; sending, by the instrument mainboard, the 4-layer or lower header and the load description information to an FPGA smart network card through a PCIe bus; receiving, by the FPGA smart network card, the 4-layer or lower header and the load description information, and obtaining the corresponding 4-layer or higher load content according to the load description information; and assembling, by the FPGA smart network card, the 4-layer or lower header and the obtained 4-layer or higher load content into a complete data packet, and sending the complete data packet to a network under test through a physical port; the receiving process comprises: receiving, by the FPGA smart network card, the data packet from the network under test through the physical port, and parsing the 4-layer or lower header and the 4-layer or higher load; performing feature detection on the 4-layer or higher load by the FPGA smart network card, and obtaining the corresponding load description information; sending, by the FPGA smart network card, the 4-layer or lower header and the obtained load description information to the instrument mainboard through the PCIe bus; and completing, by the instrument mainboard, test data statistics according to the received 4-layer or lower header and the load description information.

[0076] In yet another aspect, the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executable by a processor to implement the network test transmission optimization method provided by the above method, which comprises a sending process and a receiving process; the sending process comprises: generating, by an instrument mainboard, a 4-layer or lower header of a data packet and load description information corresponding to a 4-layer or higher load according to a test requirement; sending, by the instrument mainboard, the 4-layer or lower header and the load description information to an FPGA smart network card through a PCIe bus; receiving, by the FPGA smart network card, the 4-layer or lower header and the load description information, and obtaining the corresponding 4-layer or higher load content according to the load description information; and assembling, by the FPGA smart network card, the 4-layer or lower header and the obtained 4-layer or higher load content into a complete data packet, and sending the complete data packet to a network under test through a physical port; the receiving process comprises: receiving, by the FPGA smart network card, the data packet from the network under test through the physical port, and parsing the 4-layer or lower header and the 4-layer or higher load; performing feature detection on the 4-layer or higher load by the FPGA smart network card, and obtaining the corresponding load description information; sending, by the FPGA smart network card, the 4-layer or lower header and the obtained load description information to the instrument mainboard through the PCIe bus; and completing, by the instrument mainboard, test data statistics according to the received 4-layer or lower header and the load description information.

[0077] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purposes of the embodiments according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0078] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software and the necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0079] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for network test transmission optimization, the method comprising: The method is applied to a test system comprising an instrument mainboard and a field programmable gate array (FPGA) intelligent network card, and the instrument mainboard is connected with the FPGA intelligent network card through a peripheral component interconnect express (PCIe) bus; The method comprises a sending process and a receiving process; The sending process comprises: the instrument mainboard generates a 4-layer or lower header and load description information corresponding to a 4-layer or higher load of a data packet according to a test requirement; the instrument mainboard sends the 4-layer or lower header and the load description information to the FPGA intelligent network card through the PCIe bus; the FPGA intelligent network card receives the 4-layer or lower header and the load description information, and acquires corresponding 4-layer or higher load content according to the load description information; and the FPGA intelligent network card assembles the 4-layer or lower header and the acquired 4-layer or higher load content into a complete data packet, and sends the complete data packet to a network under test through a physical port. The receiving process comprises: the FPGA intelligent network card receives a data packet from the network under test through the physical port, and analyzes the 4-layer or lower header and the 4-layer or higher load; the FPGA intelligent network card performs feature detection on the 4-layer or higher load, and acquires corresponding load description information; the FPGA intelligent network card sends the 4-layer or lower header and the acquired load description information to the instrument mainboard through the PCIe bus; and the instrument mainboard completes test data statistics according to the received 4-layer or lower header and load description information.

2. The network test transmission optimization method of claim 1, wherein, When the test scenario is that the 4-layer or higher load content has no requirement, the load description information is load length information. The FPGA intelligent network card acquires corresponding 4-layer or higher load content according to the load length information, and generates random data of a length required by the load length information as load data, and inserts a target pseudo-random binary sequence as an identifier at a preset position of the load data. The FPGA intelligent network card performs feature detection on the 4-layer or higher load, and specifically comprises the following steps:

3. The network test transmission optimization method of claim 2, wherein, The FPGA intelligent network card detects whether the target pseudo-random binary sequence exists in the 4-layer or higher load of the received data packet. If the target pseudo-random binary sequence is detected, it is determined that the data packet does not need to transmit load content, the load length is extracted as the load description information, and the load description information is sent to the instrument mainboard through the PCIe bus. When the test scenario is that the 4-layer or higher load content is limited, the load description information is a load ID.

4. The network test transmission optimization method of claim 1, wherein, Before the sending process is performed, the method further comprises a pre-configuration process, and the pre-configuration process comprises the following steps: The instrument mainboard generates a mapping table of all preset 4-layer or higher load content, corresponding load IDs and check values; The mapping table is loaded into a local memory of the FPGA intelligent network card through the PCIe bus. The FPGA intelligent network card acquires corresponding 4-layer or higher load content according to the received load ID, and queries the mapping table in the local memory to read corresponding 4-layer or higher load content.

5. The network test transmission optimization method of claim 4, wherein, ​ ​ 6. The network test transmission optimization method of claim 4, wherein, In the receiving process, the FPGA intelligent network card performs feature detection on the 4-layer or more load, specifically including: The FPGA intelligent network card calculates a check value of the received 4-layer or more load, and queries the mapping table in the local memory according to the calculated check value; If the query is matched successfully, the corresponding load ID is obtained as the load description information, and is sent to the instrument mainboard through the PCIe bus; if the query is not matched, the complete data packet is written into the memory of the instrument mainboard through the PCIe bus.

7. The network test transmission optimization method of claim 6, wherein, The check value is calculated by using an MD5 algorithm, and the mapping table contains the corresponding relationship among the load ID, load content and MD5 value.

8. The network test transmission optimization method of claim 2, wherein, The target pseudo-random binary sequence is a pseudo-random sequence PRBS-31 sequence, and the preset position is the 16th byte to the 48th byte after the starting position of the 4-layer or more load.

9. A test system, characterized by Comprise: An instrument mainboard configured with upper-layer driving software, used for generating or processing the 4-layer or less header and load description information of a data packet, and performing data interaction through a PCIe bus; An FPGA intelligent network card connected with the instrument mainboard through the PCIe bus, configured with a local memory and a logic processing unit; The test system is configured to perform the network test transmission optimization method according to any one of claims 1 to 8.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by a processor to implement the network test transmission optimization method according to any one of claims 1 to 8.

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