Multi-input multi-output routing scheduling device

Abstract

The invention discloses a multi-input multi-output routing scheduling device, which comprises an input port module used for acquiring transaction data in real time, analyzing the transaction data to obtain a destination address, and caching the transaction data to a corresponding virtual output queue according to the destination address of the transaction data, when the transaction data volume cached in any virtual output queue reaches a preset data sending threshold value, a transmission request is sent to an output port module matched with the virtual output queue; the output port module is used for arbitrating at least one transmission request sent by each input port module in a set time interval to obtain a target virtual output queue located on a target input port module, and continuously reading a set number of complete data sequences from the target virtual output queue on the target input port module and sending the complete data sequences. According to the device disclosed by the invention, the utilization rate of cache resources is improved, and the condition of data congestion is effectively relieved.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a multi-input multi-output routing scheduling device. Background Technology

[0002] With the explosive growth of data traffic in scenarios such as data center networks, high-performance computing, and 5G core networks, network equipment switching architectures are facing unprecedented challenges in throughput and latency. Especially with many-to-one communication becoming the mainstream, the "Hall blockage" phenomenon caused by output port congestion has become a core bottleneck restricting the improvement of switching performance.

[0003] In existing technologies, shared cache architectures improve utilization to some extent by centralizing cache resources, but their scheduling algorithms have significant drawbacks in extreme congestion scenarios: on the one hand, the lack of a resource guarantee mechanism for input ports may lead to some ports being completely blocked due to resource preemption; on the other hand, the cache block release strategy is rigid, and frequent allocation-release operations bring significant scheduling overhead. This imbalance between fairness, efficiency, and stability makes it difficult for existing solutions to simultaneously achieve high throughput, low latency, and reliable service quality guarantees in high-speed switching scenarios. Summary of the Invention

[0004] This invention provides a multiple-input multiple-output (MIMO) routing scheduling device to address the problems of reduced throughput and difficulty in ensuring port fairness caused by resource contention in a centralized caching architecture.

[0005] According to one aspect of the present invention, a data transmission apparatus is provided, comprising: a plurality of input port modules and a plurality of output port modules, wherein:

[0006] The input port module is used to acquire transaction data in real time, obtain the destination address by parsing the transaction data, and cache the transaction data in the corresponding virtual output queue according to the destination address. When the amount of cached transaction data in any virtual output queue reaches the preset data transmission threshold, a transmission request is sent to the output port module that matches the virtual output queue.

[0007] The output port module is used to arbitrate at least one transmission request sent by each input port module within a set time interval, obtain a target virtual output queue located on the target input port module, and continuously read a set number of complete data sequences from the target virtual output queue on the target input port module for transmission.

[0008] According to another aspect of the present invention, a data exchange device is provided, including: a network-on-a-chip, a high-speed switch, or a router.

[0009] The multi-input multi-output (MIMO) routing scheduling device of this invention includes: an input port module, used to acquire transaction data in real time, parse the transaction data to obtain the destination address, cache the transaction data in the corresponding virtual output queue according to the destination address, and send a transmission request to the output port module matching the virtual output queue when the amount of cached transaction data in any virtual output queue reaches a preset data transmission threshold; and an output port module, used to arbitrate at least one transmission request sent by each input port module within a set time interval to obtain a target virtual output queue located on the target input port module, and continuously read a set number of complete data sequences from the target virtual output queue on the target input port module for transmission. Through the collaborative management mechanism of the centralized cache pool and virtual output queues, efficient sharing and dynamic allocation of cache resources are achieved, effectively improving system throughput and resource utilization.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a multi-input multi-output routing scheduling device according to Embodiment 1 of the present invention;

[0013] Figure 2 This is a schematic diagram of the structure of a multi-input multi-output routing scheduling device according to Embodiment 2 of the present invention;

[0014] Figure 3 This is a schematic diagram of the structure of a data exchange device according to Embodiment 2 of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Example 1

[0018] Figure 1 This is a schematic diagram of a multi-input multi-output routing scheduling device provided in Embodiment 1 of the present invention. This embodiment can be applied to situations where there is many-to-one communication contention in a multi-port data exchange system.

[0019] Correspondingly, such as Figure 1 As shown, the device includes:

[0020] The input port module 110 and the output port module 120 are provided, wherein each input port module contains multiple parallel virtual output queues, one virtual output queue corresponds to one output port module, and the input port module 110 is connected to the output port module 120.

[0021] The input port module 110 is used to acquire transaction data in real time, obtain the destination address by parsing the transaction data, and cache the transaction data in the corresponding virtual output queue according to the destination address. When the amount of cached transaction data in any virtual output queue reaches the preset data transmission threshold, a transmission request is sent to the output port module that matches the virtual output queue.

[0022] The destination address can be understood as the identification information included in the header of the transaction data packet, used to uniquely determine the target location to which the transaction data needs to be delivered. The virtual output queue can be understood as a logical queue maintained independently within each input port for each possible output port. It is not a physically independent storage hardware, but a logical range dedicated to storing specific stream data (i.e., data sent from this inlet to a specific outlet) through queue management logic and pointers.

[0023] In this embodiment, the input port module is the starting point of the data processing flow, responsible for real-time processing of received high-speed data. Its core function is to classify data and trigger transmission. Specifically, the module first performs deep analysis on the incoming transaction data to accurately identify the destination address information contained in the data packets. Subsequently, based on this destination address, the module precisely guides each data packet to its corresponding virtual output queue for temporary storage. Each virtual output queue is dedicated to storing data destined for a specific output port, thereby logically isolating data flows from different directions and laying the foundation for eliminating head-of-line congestion. When the module detects that the amount of transaction data accumulated in a virtual output queue has reached a preset start threshold, it will proactively send a request signal to the corresponding target output port module, indicating that the queue is ready to send and requesting the output end to schedule it.

[0024] Optionally, based on the above embodiments, the input port module includes an input port, a queue management unit, and a data writing unit, wherein:

[0025] The input port is used to receive transaction data in real time.

[0026] The queue management unit is used to maintain each virtual output queue within the input port module, receive and parse the destination address of the received transaction data, determine the virtual output queue for caching the transaction data based on the destination address, and send a data write request for the transaction data to the data writing unit.

[0027] The data writing unit is used to determine the virtual output queue to which the received transaction data needs to be written based on the received data write request, and to continuously write each data bit in the transaction data into the cache resource block allocated to the virtual output queue.

[0028] In this context, a cache resource block can be understood as the basic physical unit that constitutes the cache resource library, implemented by a static random access memory (SRAM) with independent read and write ports. Its storage capacity is specifically designed to be no less than the basic unit length of a single data transfer, ensuring that each resource block can completely accommodate a basic data unit.

[0029] Generally, the input port, as the physical interface for data inflow, is responsible for continuously receiving high-speed data streams from the outside. Its core function is to ensure a stable connection of the data bit stream, providing a reliable data source for subsequent processing stages.

[0030] Generally, the queue management unit is the control core of the input port, responsible for implementing fine-grained data stream classification and scheduling. Internally, the queue management unit maintains an independent virtual output queue for each possible output destination, forming a complete virtual output queue matrix. When transaction data arrives, the queue management unit performs deep parsing of the data packet header, accurately extracts the target address information, and then directs the data to the corresponding virtual output queue according to a preset routing table. Simultaneously, the queue management unit continuously monitors the depth status of each virtual output queue, records the amount of data buffered in each queue, and triggers a transmission request when the transaction data volume reaches a preset threshold. The queue management unit is also responsible for maintaining the queue's metadata information, including status parameters such as the current queue head pointer and data packet count.

[0031] Generally, the data writing unit is responsible for safely and reliably storing the classified data entities into the physical cache. After receiving the write instruction from the queue management unit, the data writing unit continuously writes each bit of the transaction data into the cache block allocated to the queue.

[0032] Optionally, based on the above embodiments, the input port module may further include a resource prediction and allocation unit, wherein:

[0033] The resource prediction and application unit is used to monitor the available data cache space of the virtual output queue before the data writing unit writes the transaction data into the virtual output queue; when the available data cache space is insufficient, it initiates a cache resource block allocation request to the cache resource management module to instruct the cache resource management module to allocate an additional free cache resource block to the virtual output queue in the input / output port.

[0034] Generally, the resource prediction and allocation unit plays a crucial role in ensuring resource availability before data writing operations begin. This unit continuously tracks and calculates the current occupied storage space and remaining available space of each virtual output queue, monitoring the cache balance of each queue in real time. When new transaction data needs to be stored in a virtual output queue, this unit pre-determines whether the queue's existing free space is sufficient to accommodate the amount of data to be written.

[0035] If the available space in the target virtual output queue is insufficient to store newly arrived transaction data, the resource prediction and allocation unit will immediately initiate a resource allocation process. This involves sending a formal allocation request to the cache resource management module, which is responsible for global resource management, explicitly specifying the virtual output queue identifier that requires the resources. This process occurs before actual data is written, demonstrating the predictability and proactivity of resource allocation.

[0036] Through this pre-judgment and advance request mechanism, the resource prediction and request unit ensures that the target virtual output queue has acquired sufficient storage resources when the data writing unit actually begins executing the write operation. This design avoids waiting or interruption due to insufficient resources during the write process, thus guaranteeing the continuity and efficiency of data processing. This working method of the unit achieves efficient coordination between resource allocation and data writing, enabling the entire data processing flow to proceed smoothly.

[0037] Optionally, based on the above embodiments, the input port module may further include a resource return unit, wherein:

[0038] The resource rollback unit is specifically used for: monitoring the data readout status of each cache resource block occupied by each virtual output queue within the input / output port; when it is detected that the data in the target cache resource block allocated to the target virtual output queue has been completely readout, checking whether there is any subsequent data to be sent in the target virtual output queue, and simultaneously detecting whether any new transaction data that needs to be cached to the target virtual output queue has arrived in the input port module; when it is confirmed that there is no subsequent data to be sent in the target virtual output queue and no new transaction data has arrived, sending a cache resource release command to the cache resource management module.

[0039] The cache resource management module can also be used to: respond to a cache resource release instruction; determine the target cache resource block to be released specified by the instruction; mark the status of the target cache resource block as free, and add it to the free resource list.

[0040] Generally, the resource rollback unit continuously monitors the data reading progress of each storage block occupied by the virtual output queue. By tracking the position changes of the read pointer, this unit can accurately determine whether the data in each storage block has been completely retrieved. When it is detected that all data in a storage block has been read, the unit immediately initiates the resource release assessment process. When initiating the release assessment, the resource rollback unit performs two checks simultaneously: first, confirming whether there are any subsequent data packets waiting to be sent in the virtual output queue corresponding to the storage block; and second, monitoring whether new transaction data that needs to be stored in the queue has arrived at the input end. This judgment process needs to comprehensively consider the real-time status of the queue and the latest situation of the data flow to ensure that resources still in use are not mistakenly reclaimed. When the resource rollback unit confirms that there is no data to be sent in the queue and no new data has arrived, it generates a release command containing the target storage block identifier and sends it to the cache resource management module.

[0041] Correspondingly, upon receiving a release command, the cache resource management module immediately parses the command content, determines the specific storage block number that needs to be reclaimed, marks the status of that storage block as free, and updates the global resource list so that it can be reused for subsequent allocation operations. This collaborative mechanism enables the dynamic reclamation and reuse of storage resources.

[0042] The output port module 120 is used to arbitrate at least one transmission request sent by each input port module within a set time interval, obtain a target virtual output queue located on the target input port module, and continuously read a set number of complete data sequences from the target virtual output queue on the target input port module for transmission.

[0043] In this embodiment, the output port module undertakes the critical tasks of scheduling and transmission. Its core task is to efficiently and fairly handle the competing requests from multiple input ports for the same output resource. This module continuously listens for transmission requests from all input port modules. When multiple requests to this port are received within a set decision period, the arbitration mechanism within the output port module is activated, selecting a winner from these requests according to a predetermined fair strategy. After successful arbitration, the module grants an exclusive transmission license to the input port module corresponding to the winning request. Under this license, the data read unit continuously reads a complete data block (i.e., a complete data burst sequence) from the winning virtual output queue and sends it to the output link, thereby maximizing the efficiency of each transmission and avoiding the overhead caused by fragmented transmissions.

[0044] Furthermore, based on the above embodiments, a multiple-input multiple-output (MIMO) routing scheduling device may further include: a cache resource management module and a centralized cache pool, wherein the centralized cache pool includes multiple cache resource blocks, wherein:

[0045] The cache resource management module is used to maintain the resource idle status of each cache resource block in all centralized cache pools, generate and update the idle resource list, and respond to the cache resource block allocation request sent by each input port module, allocate idle cache resource blocks in the resource cache pool to the corresponding virtual output queue in the input / output port according to the idle resource list.

[0046] Generally, the cache resource management module acts as the global manager of all cache resources in the entire device. Its core responsibility is to accurately grasp the real-time status of the centralized cache pool, which consists of a large number of independent cache resource blocks, and continuously track whether each cache resource block is currently idle and available or has been allocated and used. This module dynamically generates and maintains a complete list of idle resources, which clearly records the identifiers of all storage blocks that can be allocated immediately.

[0047] When a virtual output queue at an input port needs cache space to store newly arrived transaction data, but its currently allocated storage space is insufficient, the corresponding queue management unit will submit a resource allocation request to the cache resource management module. At this time, the cache resource management module will respond to the request, select a suitable free storage block from its maintained list of free resources, and formally allocate it to the specific virtual output queue that made the request. Simultaneously, it will update relevant status information to ensure the accuracy and global consistency of resource allocation.

[0048] Optionally, based on the above embodiments, the number of free cache resource blocks in the resource cache pool module is at least twice the number of input port modules, to ensure that each input port module can be allocated at least two cache resource blocks.

[0049] Generally, the resource caching pool module is designed to ensure that the total number of available free storage units is far greater than the number of input ports. This design principle is primarily to address potential extreme congestion scenarios. When a large amount of data floods into the device simultaneously, each input port may need to cache multiple data blocks. If the total resources are insufficient, some ports may experience data loss or transmission halts due to their inability to allocate storage space in time. By reserving sufficient resource margins, this design ensures that even under the most unfavorable operating conditions, each input port can at least obtain the minimum resource guarantee necessary to maintain basic data transmission. This reserved resource is equivalent to providing an independent buffer zone for each port, preventing overall performance degradation due to global resource exhaustion. This resource allocation strategy fundamentally avoids transmission deadlock problems that may be caused by resource contention, ensuring the stability and reliability of the device operation.

[0050] Optionally, based on the above embodiments, the output port module may include an output arbitrator unit, a data readout unit, and an output port, wherein:

[0051] The output arbitrator unit is used to receive at least one transmission request sent by each input port module within a set time interval, perform centralized arbitration on all received transmission requests, obtain the target virtual output queue located on the target input port module, and send an authorization signal to the target input port module to grant the target input port module exclusive transmission rights.

[0052] The data readout unit is used to continuously read a set number of complete data sequences from the cache resource block occupied by the target virtual output queue on the winning target input port module after receiving the authorization signal from the output arbitrator unit, control the data path to send each complete data sequence out through the output port without interruption, and monitor the progress status of data reading in real time.

[0053] Generally, the output arbitrator unit is responsible for coordinating access contention among multiple input ports for the same output channel. Within a set decision cycle, this unit collects transmission requests from all input ports, all directed to the current output port. The arbitrator uses an internally preset scheduling strategy to uniformly evaluate and select the winning virtual output queue. Once selected, the arbitrator sends a special permission signal to the input port containing the winning queue. This signal grants that input port exclusive access to the output channel, during which time it will not respond to requests from other ports.

[0054] Generally, the data read unit initiates operation immediately upon receiving the authorization signal from the arbitrator. This unit locates the physical storage area currently occupied by the winning virtual output queue and initiates a continuous read process. During the read operation, the data read unit ensures that each read operation completely retrieves the data of a minimum transmission unit and maintains uninterrupted data transmission. Throughout the transmission, the unit tracks the data read progress in real time, including monitoring the current read position and remaining data volume, ensuring that the entire data block is sent out completely and orderly through the output port.

[0055] Optionally, based on the above embodiments, the output arbitrator unit is specifically used for:

[0056] Maintain a polling pointer that iterates through all ports that have submitted transmission requests in a preset order;

[0057] In each arbitration cycle, the transmission request sent by the port currently pointed to by the polling pointer is selected as the winning request;

[0058] After arbitration is completed, the polling pointer is immediately moved to the next port in the sequence to make a transmission request, to ensure that the winning chance is evenly distributed among all requesting ports in consecutive arbitration cycles.

[0059] Generally, the arbitration mechanism maintains a dynamic indicator flag that cycles through all ports that have submitted transmission requests in a pre-defined circular order. This flag records the starting position of the current polling, ensuring that each arbitration cycle begins its check from the correct position.

[0060] Generally, at the start of each decision slot, the arbitration mechanism first checks whether the port pointed to by the current marker has made a transmission request. If there is an pending transmission request on that port, the request on that port is directly determined as the winner of this arbitration, and transmission permission is granted to it. This design ensures the immediacy of arbitration decisions and avoids unnecessary delays.

[0061] Generally, after the arbitration process for the current port is completed, the dynamic tag will immediately move to the next port to be checked in a predetermined order, regardless of whether the port makes a request. This design ensures that the arbitration mechanism can continuously scan all active ports, avoiding the situation where a port cannot obtain service for a long time due to tag stagnation, and also preventing active ports from excessively consuming resources, thus maintaining the principle of fairness in scheduling overall.

[0062] The multi-input multi-output (MIMO) routing scheduling device of this invention includes: an input port module, used to acquire transaction data in real time, parse the transaction data to obtain the destination address, cache the transaction data in the corresponding virtual output queue according to the destination address, and send a transmission request to the output port module matching the virtual output queue when the amount of cached transaction data in any virtual output queue reaches a preset data transmission threshold; and an output port module, used to arbitrate at least one transmission request sent by each input port module within a set time interval to obtain a target virtual output queue located on the target input port module, and continuously read a set number of complete data sequences from the target virtual output queue on the target input port module for transmission. Through the collaborative management mechanism of the centralized cache pool and virtual output queues, efficient sharing and dynamic allocation of cache resources are achieved, effectively improving system throughput and resource utilization.

[0063] Example 2

[0064] Figure 2 This is a schematic diagram of a multi-input multi-output routing scheduling device provided in Embodiment 2 of the present invention.

[0065] like Figure 2As shown, the multiple-input multiple-output (MIMO) routing and scheduling device includes a memory resource pool, multiple identical input port processing modules (including input port 1, input port 2...input port N), and multiple output port processing modules (including output port 1, output port 2...output port M). The memory resource pool consists of multiple independent dual-port SRAMs (Static Random-Access Memory blocks) serving as a globally shared centralized cache pool, providing physical storage space for the virtual output queues of all input ports. Each input port processing module further includes: a queue control module: used to receive input transaction data, parse its destination address, and direct the data to the corresponding VOQ (Virtual Output Queue) according to the address. Each input port internally maintains K VOQs (VOQ 0 to VOQ K-1), corresponding to K possible output destinations. A resource arbitration and request module: used to monitor the available cache space of the target VOQ before writing data. If the space is insufficient, it requests a new free SRAM block from the global resource manager and allocates it to the VOQ. Data writing module: Responsible for continuously writing transaction data into the SRAM block allocated to the corresponding VOQ. Resource return indication: Indicates that this module has a resource reclamation function, used to initiate the release process of the SRAM block when it detects that the data in a certain SRAM block has been completely read out and its associated VOQ has no subsequent data. Each output port processing module further includes: Scheduler: Acting as the arbitrator of this output port, it receives transmission requests from all input ports (from the corresponding sequence number of the VOQ). It uses a fair scheduling algorithm such as round-robin to select a winner from these requests. Data reading module: After receiving authorization from the scheduler, it continuously and uninterruptedly reads complete data units from the SRAM block occupied by the winning VOQ. Output interface: Sends the read data to the external link.

[0066] After transaction data arrives at the input port, its internal queue control module parses the destination address, determines the target output port Y, and logically assigns it to the virtual output queue (VOQ-Y) corresponding to this port. Subsequently, the resource arbitration and allocation module checks the available cache space of this VOQ-Y. If the space is insufficient, it requests new static random-access memory (SRAM) from the global resource manager. The data writing module then continuously writes transaction data into the allocated SRAM block. When the amount of data cached in VOQ-Y reaches the transmission threshold, the input port module sends a transmission request to the scheduler of the target output port Y. The scheduler collects all requests sent to port Y, selects the winning request through fair arbitration, and authorizes it. The data reading module of the winning port then continuously reads the complete data burst sequence from the SRAM block occupied by the corresponding VOQ-Y and sends it. At the same time, the resource return mechanism monitors the read status of the SRAM block. When a block of data is completely read and its corresponding VOQ has no subsequent data waiting or new data arriving, the release process is triggered, the SRAM block is marked as free, and it is reclaimed into the global memory resource pool.

[0067] In a specific example, when transaction data arrives at the input port, the internal queue control module parses its destination address, determines the target output port Y, and logically assigns it to the virtual output queue (VOQ-Y) corresponding to this port. Next, resource allocation and writing occur: the resource arbitration and allocation module checks the available buffer space of VOQ-Y; if space is insufficient, it allocates a new SRAM block. Subsequently, the data writing module continuously writes the transaction data into the allocated SRAM block. When the amount of data buffered in VOQ-Y reaches a preset transmission threshold, the input port module sends a transmission request to the scheduler of the target output port Y. Then, the arbitration and authorization phase begins: the scheduler of output port Y collects all requests sent to this port and selects the winning request through a fair arbitration mechanism (such as round-robin). After winning, the data reading and sending phase begins: the scheduler sends authorization to the winning input port, and the output port's data reading module then continuously reads a complete data burst sequence from the SRAM block occupied by the corresponding VOQ-Y and sends it. Meanwhile, the resource reclamation mechanism continues to operate: during the data reading process, the system monitors the reading status of SRAM blocks. When a block of data is completely read out and there is no subsequent data waiting in its corresponding VOQ and no new data arrives, the release process is triggered, marking the SRAM block as free and reclaiming it into the global memory resource pool for subsequent allocation, thus forming an efficient data scheduling and resource management process.

[0068] Example 3

[0069] Figure 3 This is a schematic diagram of a data exchange device provided in Embodiment 3 of the present invention, including the multi-input multi-output routing scheduling device described in any one of the embodiments of the present invention. The data exchange device includes: a network on-chip, a high-speed switch, or a router.

[0070] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0071] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A routing and scheduling apparatus for multiple-input multiple-output, characterized by, The device comprises a plurality of input port modules and a plurality of output port modules, and the input port modules are connected with the output port modules, wherein: each input port module comprises a plurality of parallel virtual output queues, and one virtual output queue corresponds to one output port module; The input port module is used for acquiring transaction data in real time, obtaining a destination address by analyzing the transaction data, and caching the transaction data into a corresponding virtual output queue according to the destination address of the transaction data; when the amount of cached transaction data in any virtual output queue reaches a preset data sending threshold, a transmission request is sent to the output port module matched with the virtual output queue. The output port module is used for arbitrating at least one transmission request sent by each input port module within a set time interval, obtaining a target virtual output queue located on a target input port module, and continuously reading a set number of complete data sequences from the target virtual output queue on the target input port module for sending.

2. The MIMO routing scheduler apparatus of claim 1, wherein, The device further comprises a cache resource management module and a centralized cache pool, and the centralized cache pool comprises a plurality of cache resource blocks; The cache resource management module is used for maintaining the resource idle state of each cache resource block in all centralized cache pools, generating and updating an idle resource list, and responding to a cache resource block allocation request sent by each input port module, allocating an idle cache resource block in the resource cache pool to the corresponding virtual output queue in the input-output port according to the idle resource list.

3. The MIMO routing scheduler apparatus of claim 2, wherein, The number of idle cache resource blocks in the resource cache pool module is at least twice the number of input port modules, so as to ensure that each input port module can be allocated at least two cache resource blocks.

4. The MIMO routing scheduler apparatus of claim 2, wherein, The input port module comprises an input port, a queue management unit and a data writing unit, wherein: The input port is used for receiving transaction data in real time; The queue management unit is used for maintaining each virtual output queue in the input port module, receiving and analyzing the destination address of the received transaction data, determining the virtual output queue for caching the transaction data according to the destination address, and sending a data writing request for the transaction data to the data writing unit; The data writing unit is used for determining the virtual output queue to which the received transaction data needs to be written according to the received data writing request, and continuously writing each data bit in the transaction data into the cache resource block allocated for the virtual output queue.

5. The MIMO routing scheduler apparatus of claim 4, wherein, The input port module further comprises a resource pre-judgment and application unit, wherein: The resource pre-judgment and application unit is used for monitoring the available data cache space of the virtual output queue before the data writing unit writes the transaction data into the virtual output queue; when the available data cache space is insufficient, a cache resource block allocation request is initiated to the cache resource management module to indicate the cache resource management module to additionally allocate an idle cache resource block for the virtual output queue in the input-output port.

6. The MIMO routing scheduler apparatus of claim 1, wherein, The input port module further comprises a resource return unit, wherein: The resource rollback unit is specifically configured to: monitor data readout states of each cache resource block occupied by each virtual output queue in the input / output port; when detecting that data in a target cache resource block allocated for a target virtual output queue is completely read out, check whether there is subsequent data to be sent in the target virtual output queue, and synchronously detect whether new transaction data that needs to be cached to the target virtual output queue arrives in the input port module; when confirming that there is no subsequent data to be sent in the target virtual output queue and no new transaction data arrives, send a cache resource release instruction to the cache resource management module; The cache resource management module is further configured to: respond to the cache resource release instruction; determine a target cache resource block to be released specified by the instruction; mark a state of the target cache resource block as idle, and add the target cache resource block to the idle resource list.

7. The MIMO routing scheduler apparatus of claim 1, wherein, The output port module includes an output arbiter unit, a data readout unit and an output port, wherein: The output arbiter unit is configured to receive at least one transmission request sent by each input port module in a set time interval, centrally arbitrate all received transmission requests, obtain a target virtual output queue located on a target input port module, and send an authorization permission signal to the target input port module to grant the target input port module exclusive transmission permission; The data readout unit is configured to, after receiving the authorization permission signal of the output arbiter unit, continuously read a set number of complete data sequences from a cache resource block occupied by the target virtual output queue on the winning target input port module, control the data channel to uninterruptedly pass each complete data sequence through the output port to the outside, and monitor a progress state of data reading in real time.

8. The MIMO routing scheduler apparatus of claim 6, wherein, The output arbiter unit is specifically configured to: maintain a polling pointer, which circulates through all ports that propose transmission requests in a preset order; in each arbitration cycle, select a transmission request sent by a port pointed to by the current polling pointer as a winning request; after completing arbitration, immediately move the polling pointer to the next port that proposes a transmission request in the order, to ensure that the winning opportunity is evenly distributed to all ports that propose requests in continuous arbitration cycles.

9. A data exchange device, characterized by The routing and scheduling device includes a multiple-input multiple-output as claimed in any one of claims 1-8.

10. The data exchange device of claim 9, wherein, The data switching device includes a network on chip, a high-speed switch or a router.

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