Data transmission method and device, electronic equipment and storage medium

Abstract

The invention provides a data transmission method and device, electronic equipment and a storage medium, and belongs to the technical field of chips. The method is applied to a first chip, and comprises the following steps: training a data transmission link between the first chip and a second chip based on a link training frame to obtain link state information; if the link state information indicates that the data transmission link is in an abnormal state, interacting with the second chip based on at least one of the retransmission synchronization frame and the credit synchronization frame to recover the data transmission link; if the link state information indicates that the data transmission link is in a normal state, interaction with the second chip is carried out based on the data transmission link to obtain a link negotiation result, and the link negotiation result is used for indicating a data transmission mode between the first chip and the second chip; and performing data transmission with the second chip based on the data transmission link and the link negotiation result. This improves the link negotiation efficiency, thereby improving the overall efficiency of data transmission.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a data transmission method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the increasing demand for big data and information processing, electronic devices often integrate more chips. In this context, the need for high-speed data transmission between multiple chips is growing, placing higher demands on the performance, reliability, and negotiation efficiency of the data transmission links. Therefore, improving data transmission efficiency to adapt to various complex communication scenarios and meet the needs of efficient communication between chips is a problem that needs to be solved. Summary of the Invention

[0003] This application provides a data transmission method, apparatus, electronic device, and storage medium, which can reveal cross-module performance coupling problems and improve the accuracy of data transmission. The technical solution is as follows: On the one hand, a data transmission method is provided, the method comprising: Based on the link training frame, the data transmission link between the first chip and the second chip is trained to obtain link status information. The link training frame carries link configuration data, and the link status information is used to characterize the connectivity status of the data transmission link. If the link status information indicates that the data transmission link is in an abnormal state, the second chip is interacted with based on at least one of the retransmission synchronization frame and the credit synchronization frame to restore the data transmission link. The retransmission synchronization frame is used to synchronize the retransmission buffer state with the receiving window state, and the credit synchronization frame is used to synchronize the flow control credit state. If the link status information indicates that the data transmission link is in a normal state, the link negotiation result is obtained by interacting with the second chip based on the data transmission link. The link negotiation result is used to indicate the data transmission method between the first chip and the second chip. Based on the data transmission link and the link negotiation result, data is transmitted with the second chip.

[0004] On the other hand, a data transmission device is provided, configured in a first chip, the device comprising: The training module is used to train the data transmission link between the first chip and the second chip based on the link training frame to obtain link status information. The link training frame carries link configuration data, and the link status information is used to characterize the connectivity status of the data transmission link. The recovery module is used to interact with the second chip based on at least one of a retransmission synchronization frame and a credit synchronization frame to restore the data transmission link if the link status information indicates that the data transmission link is in an abnormal state. The retransmission synchronization frame is used to synchronize the retransmission buffer state with the receiving window state, and the credit synchronization frame is used to synchronize the flow control credit state. The negotiation module is used to interact with the second chip based on the data transmission link if the link status information indicates that the data transmission link is in a normal state, and obtain the link negotiation result. The link negotiation result is used to indicate the data transmission mode between the first chip and the second chip. The transmission module is used to transmit data with the second chip based on the data transmission link and the link negotiation result.

[0005] In some embodiments, the training module is configured to: send a first link training frame to the second chip, the first link training frame carrying link configuration data supported by the first chip; receive a second link training frame sent by the second chip, the second link training frame carrying link configuration data supported by the second chip; determine the data intersection between the link configuration data supported by the first chip and the second chip based on the data carried by the first link training frame and the second link training frame; and perform sub-channel calibration and physical connectivity detection on the data transmission link based on the data intersection to obtain the link status information.

[0006] In some embodiments, the link training frame includes a channel-level training frame and a link-level training frame; the channel-level training frame carries the number of sub-channels, polarity data, and codeword alignment data; the link-level training frame carries sub-channel synchronization rules, transmission rate range, and transmission bit width range, wherein the sub-channel synchronization rules are used to achieve data transmission synchronization of multiple sub-channels in the data transmission link.

[0007] In some embodiments, the abnormal state indicated by the link status information includes a retransmission mismatch state; The recovery module is configured to, when in the retransmission mismatch state, send a first retransmission synchronization frame to the second chip, the first retransmission synchronization frame carrying the retransmission buffer occupancy status and the start position of the receiving window corresponding to the first chip; receive a second retransmission synchronization frame sent by the second chip, the second retransmission synchronization frame carrying the retransmission buffer occupancy status and the start position of the receiving window corresponding to the second chip; and perform calibration based on the data carried by the second retransmission synchronization frame to achieve synchronization of the retransmission buffer status and the receiving window status of the first chip and the second chip.

[0008] In some embodiments, the abnormal state indicated by the link status information includes a credit mismatch state; The recovery module is configured to, when in the credit mismatch state, send a first credit synchronization frame to the second chip, the first credit synchronization frame carrying the current credit limit and buffer reservation status of the first chip; receive a second credit synchronization frame sent by the second chip, the second credit synchronization frame carrying the current credit limit and buffer reservation status of the second chip; and perform calibration based on the data carried by the second credit synchronization frame to achieve synchronization of the flow control credit status of the first chip and the second chip.

[0009] In some embodiments, the abnormal state indicated by the link status information includes a link connectivity interruption state; The recovery module is used to, in the case of the link connection interruption state, re-establish the physical connection and parameter synchronization of the data transmission link based on the link training frame; and to perform the steps in the retransmission mismatch state and the credit mismatch state based on the retransmission synchronization frame and the credit synchronization frame.

[0010] In some embodiments, the recovery module is further configured to, during the recovery process of the data transmission link, notify the second chip to enter the synchronization state based on a synchronization initiation frame, the synchronization initiation frame carrying a synchronization start instruction; notify the second chip to perform parameter and state alignment based on a synchronization interaction frame, the synchronization interaction frame carrying parameter data, state identifier, and alignment reference information; and notify the second chip that synchronization has been completed based on a synchronization completion frame, the synchronization completion frame carrying a synchronization result identifier, the synchronization result identifier being used to characterize whether the alignment was successful.

[0011] On the other hand, a chip is provided, wherein if the chip is a first chip, the first chip includes a link training state machine, a link recovery state machine, and a link transmission state machine; The link training state machine is used to train the data transmission link between the first chip and the second chip based on the link training frame to obtain link state information. The link training frame carries link configuration data, and the link state information is used to characterize the connectivity state of the data transmission link. The link recovery state machine is used to interact with the second chip based on at least one of the retransmission synchronization frame and the credit synchronization frame to restore the data transmission link if the link state information indicates that the data transmission link is in an abnormal state. The retransmission synchronization frame is used to synchronize the retransmission buffer state and the receiving window state, and the credit synchronization frame is used to synchronize the flow control credit state. The link transmission state machine is used to interact with the second chip based on the data transmission link if the link status information indicates that the data transmission link is in a normal state, to obtain a link negotiation result, the link negotiation result being used to indicate the data transmission method between the first chip and the second chip; and to transmit data with the second chip based on the data transmission link and the link negotiation result.

[0012] In some embodiments, the link training state machine is configured to send a first link training frame to the second chip, the first link training frame carrying link configuration data supported by the first chip; receive a second link training frame sent by the second chip, the second link training frame carrying link configuration data supported by the second chip; determine the data intersection between the link configuration data supported by the first chip and the second chip based on the data carried by the first link training frame and the second link training frame; and perform sub-channel calibration and physical connectivity detection on the data transmission link based on the data intersection to obtain the link state information.

[0013] In some embodiments, the link training frame includes a channel-level training frame and a link-level training frame; the channel-level training frame carries the number of sub-channels, polarity data, and codeword alignment data; the link-level training frame carries sub-channel synchronization rules, transmission rate range, and transmission bit width range, wherein the sub-channel synchronization rules are used to achieve data transmission synchronization of multiple sub-channels in the data transmission link.

[0014] In some embodiments, the abnormal state indicated by the link status information includes a retransmission mismatch state; The link recovery state machine includes a retransmission synchronization state machine. When in the retransmission mismatch state, the retransmission synchronization state machine sends a first retransmission synchronization frame to the second chip, the first retransmission synchronization frame carrying the retransmission buffer occupancy status and the start position of the receive window corresponding to the first chip; receives a second retransmission synchronization frame sent by the second chip, the second retransmission synchronization frame carrying the retransmission buffer occupancy status and the start position of the receive window corresponding to the second chip; and performs calibration based on the data carried in the second retransmission synchronization frame to synchronize the retransmission buffer state and receive window state of the first chip and the second chip.

[0015] In some embodiments, the abnormal state indicated by the link status information includes a credit mismatch state; The link recovery state machine includes a credit synchronization state machine. When in the credit mismatch state, the credit synchronization state machine sends a first credit synchronization frame to the second chip, the first credit synchronization frame carrying the current credit limit and buffer reservation status of the first chip; receives a second credit synchronization frame sent by the second chip, the second credit synchronization frame carrying the current credit limit and buffer reservation status of the second chip; and performs calibration based on the data carried in the second credit synchronization frame to synchronize the flow control credit status of the first chip and the second chip.

[0016] In some embodiments, the abnormal state indicated by the link status information includes a link connectivity interruption state; The link recovery state machine includes a retransmission synchronization state machine, a credit synchronization state machine, and a retraining state machine, and the retransmission synchronization state machine and the credit synchronization state machine are both connected to the retraining state machine. The retraining state machine is used to re-establish the physical connectivity and parameter synchronization of the data transmission link based on the link training frame when the link connectivity is interrupted; the retransmission synchronization state machine is used to execute the steps when the retransmission is mismatched based on the retransmission synchronization frame; the credit synchronization state machine is used to execute the steps when the credit is mismatched based on the credit synchronization frame.

[0017] In some embodiments, the link recovery state machine is further configured to, during the recovery of the data transmission link, notify the second chip to enter the synchronization state based on a synchronization initiation frame, the synchronization initiation frame carrying a synchronization start instruction; notify the second chip to perform parameter and state alignment based on a synchronization interaction frame, the synchronization interaction frame carrying parameter data, state identifier, and alignment reference information; and notify the second chip that synchronization has been completed based on a synchronization completion frame, the synchronization completion frame carrying a synchronization result identifier, the synchronization result identifier being used to characterize whether the alignment was successful.

[0018] On the other hand, an electronic device is provided, which includes a first chip and a second chip for implementing the data transmission method in the embodiments of this application.

[0019] On the other hand, a computer-readable storage medium is provided, wherein at least one computer program is stored in the computer-readable storage medium, and the at least one computer program is loaded and executed by a processor to implement the data transmission method in the embodiments of this application.

[0020] On the other hand, a computer program product is provided, including a computer program that is executed by a processor to implement the data transmission method in the embodiments of this application.

[0021] This application provides a data transmission method that subdivides the link negotiation process into three stages: basic link training, abnormal state recovery, and transmission parameter interaction. Dedicated function frames are configured for each stage. Using this method, the first and second chips on both sides of the link can achieve precise communication of status and parameters. Particularly in the abnormal recovery stage, retransmission synchronization frames and credit synchronization frames can be flexibly selected to synchronize retransmission status and flow control credit status, facilitating efficient adjustment of the data transmission link to a normal state and thus completing the transmission agreement. This not only improves the efficiency of link negotiation, thereby improving the overall efficiency of data transmission, but also enhances the link's recovery capability and transmission stability under abnormal scenarios, thus meeting the high-speed communication requirements between multiple chips. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the implementation environment of a data transmission method provided in an embodiment of this application; Figure 2 This is a flowchart of a data transmission method provided according to an embodiment of this application; Figure 3 This is a schematic diagram of a hierarchical negotiation according to an embodiment of this application; Figure 4 This is a schematic diagram of an overall state unit according to an embodiment of this application; Figure 5 This is a flowchart of another data transmission method provided according to an embodiment of this application; Figure 6 This is a schematic diagram of a functional frame provided according to an embodiment of this application; Figure 7 This is a schematic diagram of a link-layer state machine group according to an embodiment of this application; Figure 8 This is a block diagram of a data transmission device provided according to an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0025] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with essentially the same function. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on the quantity or execution order.

[0026] In this application, the term "at least one" means one or more, and "multiple" means two or more.

[0027] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0028] To facilitate understanding, the key terms and concepts involved in this application will be explained below.

[0029] Link: refers to the supporting communication control protocol that enables communication and interconnection between two chips, that is, the data transmission link between chips.

[0030] Link-retraining (Link Retraining) refers to the process of transforming a disordered data transmission link into a controllable and effective working state through specific procedures, actions, and methods, thereby supporting effective data interaction between higher-level communication entities.

[0031] Layered architecture is a modular system design methodology used to decompose the functions of a complex communication system into multiple independent, ordered, and functionally singular layers. The layers interact through standardized interfaces, with upper-layer functions built upon lower-layer functions, and lower layers providing services to upper layers. Examples of commonly used layered architectures include the OSI seven-layer reference model (Open Systems Interconnection Reference Model) and the TCP / IP four-layer model (Transmission Control Protocol / Internet Protocol model).

[0032] This application uses the OSI architecture adapted to Network-on-Chip (NOC) as an example for illustration, but it does not constitute a limitation. NOC is an interconnect architecture that enables efficient communication between multiple processors, memory units, and peripherals on a single chip. The following describes the hierarchical division and core functions of the OSI architecture it adapts to.

[0033] In the OSI seven-layer reference model, from bottom to top, the layers are Physical Layer (PHY), Data Link Layer (DLL), Network Layer, Transport Layer, Session Layer, Presentation Layer, and Application Layer. This application focuses on the Physical Layer, Data Link Layer, and Network Layer.

[0034] The physical layer, as the bottom layer of the layered architecture, defines the physical medium characteristics (such as metal traces, serial and parallel transmission modes), electrical characteristics (such as operating voltage and transmission frequency), and timing rules for interconnections between chips, enabling the physical transmission of bit streams and providing a basic transmission channel for upper-layer links. For example, the physical layer can be further divided into a Physical Coding Sublayer (PCS), which is used for digital processing functions such as data encoding and decoding, clock recovery, frame synchronization, scrambling and descrambling.

[0035] The link layer, situated above the physical layer, ensures the reliability of data transmitted at the physical layer. For example, the link layer can be further subdivided into a Media Access Control (MAC) sublayer. The MAC sublayer controls access permissions to the physical layer media. Based on this architecture, the link layer specifically performs packet structure conversion between the network layer and the MAC sublayer, adds link reliability control mechanisms, and provides trusted transmission services to the communication entities at both ends of the link. In some high-speed communication scenarios, the DLL can be integrated with the MAC and PCS designs.

[0036] RETRY (Retransmission) is a reliability assurance function implemented at the link layer. It retransmits data packets that are detected as erroneous during transmission, based on the actual packet length controlled by the link layer, thereby compensating for errors in a single transmission and reducing the risk of data loss.

[0037] Error-recovery (link recovery): This is a link-level fault recovery mechanism. When a data transmission link experiences a transmission error and cannot be recovered through real-time error correction, retransmission, or other technical means, but the entire data transmission link has not yet entered a completely uncontrollable fault state, a specific link recovery process and algorithm are used to attempt to restore the link to a stable data transmission state. If recovery still fails after multiple attempts, it is determined that the link cannot achieve effective data transmission, providing a basis for subsequent fault handling.

[0038] Credit (Credit Counting Unit): This refers to the counting unit used by communication entities at both ends of a data transmission link when communicating based on reserved buffer technology. The buffer provider notifies the buffer user in real time of the initial buffer size and the dynamic changes in buffer usage during transmission. The basic counting unit used in this notification process is called a credit counting unit. Its core function is to achieve traffic coordination between the two ends of the link, avoid buffer overflow or idleness, and ensure the orderliness of data transmission.

[0039] XPU is a general term for accelerated processors, encompassing various computing units such as GPUs (Graphics Processing Units), NPUs (Neural Processing Units), FPGAs (Field-Programmable Gate Arrays), and various domain-specific accelerators (such as AI accelerators and storage accelerators) within DSAs (Domain-Specific Architectures). GPUs include GPGPUs (General-Purpose Graphics Processing Units). These computing units undertake core computing acceleration tasks in scenarios such as Artificial Intelligence (AI) and high-performance computing. Different types of XPUs, based on their respective hardware architectures and computing characteristics, are adapted to different application scenarios.

[0040] Figure 1 This is a schematic diagram illustrating the implementation environment of a data transmission method according to an embodiment of this application. See also... Figure 1 The implementation environment includes a first chip 101 and a second chip 102. The first chip 101 and the second chip 102 can be directly or indirectly connected via wired or wireless communication, which is not limited herein.

[0041] For example, either the first chip or the second chip can be a CPU, GPU, Application-Specific Integrated Circuit (ASIC), FPGA, memory controller chip, network interface chip, or artificial intelligence acceleration chip, etc. This application embodiment does not limit the chip type of the first chip and the second chip. Furthermore, the first chip and the second chip can be in the same electronic device or configured in different electronic devices; this application embodiment does not limit this. For example, in an AI server scenario, the first chip can be a GPU, and the second chip can be a CPU. The two are directly connected via a wired high-speed interconnect link to achieve computational power collaboration and high-speed data transmission during AI model training.

[0042] It should be noted that the above implementation environment is only an example, and only the first chip and the second chip are used as examples for illustration. More chips or other components may exist in this implementation environment. The method provided in this application embodiment can also be implemented in other implementation environments, and this application embodiment does not limit this.

[0043] With the increasing demand for big data and information processing, electronic devices often integrate more chips. In this context, the need for high-speed data transmission between multiple chips is growing, placing higher demands on the performance and reliability of these data transmission links. For example, interface protocols for heterogeneous interconnection between CPUs (Central Processing Units) and XPUs provide a unified standard interface for direct connection between CPUs and XPUs, resolving compatibility issues between different types of XPUs and CPUs. These protocols are a general term for standards defining data interaction and instruction control between the central processing unit and various accelerator processors. They possess a comprehensive functional system, such as supporting standard operations like memory access, interrupts, control, and atomic operations between the CPU and XPU, ensuring collaborative operation between heterogeneous computing units. They also support functions customized for artificial intelligence computing systems, such as address translation, unified memory, and virtualization, providing core technical support for corresponding scenarios. For instance, this protocol can interconnect multiple large-scale CPUs and GPUs through specific direct connection interfaces, realizing direct inter-chip transmission links based on printed lines, cables, and optical fibers. Based on this transmission link, combined with an integrated inter-chip cache coherence protocol and a unified memory access architecture, a conceptually single processor can be formed at the user level. Multiple actual processors can then ensure data consistency across inter-chip memory access based on the cache coherence protocol, sharing memory capacity and bandwidth. This scenario places higher demands on the link auto-negotiation mechanism.

[0044] Based on this, this application proposes a data transmission method that constructs a full-link, full-protocol-layer, and multi-stage self-negotiation mechanism. Based on hierarchical, staged, and modular concepts, it builds a comprehensive automatic link negotiation mechanism supporting multi-level and multi-process processes such as basic link training, link recovery training, and high-level credit interaction mechanisms. It provides link connectivity negotiation mechanisms when the link self-starts or encounters errors, or provides corresponding negotiation mechanisms for higher application-layer interaction needs, thereby improving link negotiation efficiency and overall data transmission efficiency.

[0045] Figure 2 This is a flowchart of a data transmission method according to an embodiment of this application. The method is illustrated using an application to a first chip as an example. (See also...) Figure 2 The method includes the following steps: 201. Based on the link training frame, the data transmission link between the first chip and the second chip is trained to obtain the link status information. The link training frame carries the link configuration data, and the link status information is used to characterize the connectivity status of the data transmission link.

[0046] In this embodiment, the data transmission link is the physical channel and supporting communication control protocol connecting the first chip and the second chip for inter-chip data interaction, serving as the fundamental carrier for inter-chip data transmission. The link training frame undertakes the training tasks at each stage of the entire link basic training or link recovery training process. Exemplarily, the link training frame includes function frames sent from the first chip to the second chip, and also function frames sent from the second chip to the first chip. The first chip and the second chip interact by sending and receiving link training frames to exchange their respective supported link configuration parameters, thereby reaching a consensus to complete basic link negotiation. Link status information consists of the link-related configuration parameters supported by the chip, such as the number of sub-channels, transmission rate, and transmission bit width. Exemplarily, the link configuration parameters are divided into channel-level configuration parameters and link-level configuration parameters, to negotiate hierarchically for each sub-channel and the entire data transmission link. Based on this, the connectivity status of the data transmission link is detected in real time to obtain link status information. Link status information characterizes the connectivity status of the data transmission link, including normal status and abnormal statuses such as retransmission mismatch, credit mismatch, and connectivity interruption, providing a basis for subsequent link processing decisions.

[0047] 202. If the link status information indicates that the data transmission link is in an abnormal state, the first chip interacts with the second chip based on at least one of the retransmission synchronization frame and the credit synchronization frame to restore the data transmission link. The retransmission synchronization frame is used to synchronize the retransmission buffer state with the receiving window state, and the credit synchronization frame is used to synchronize the flow control credit state.

[0048] In this embodiment, an abnormal state is a state where the link cannot transmit data normally, such as retransmission mismatch, credit mismatch, and link connectivity interruption, which needs to be recovered through a specific interactive process. The retransmission synchronization frame is a functional frame used to implement retransmission synchronization training, carrying data such as the chip's retransmission buffer occupancy status and the starting position of the receive window, thereby achieving synchronization and alignment of the retransmission buffer state and the receive window state. The retransmission buffer state characterizes the chip's retransmission buffer occupancy status and can affect the storage and transmission efficiency of retransmitted data. The receive window state is the effective range state of the chip's received data; its synchronization determines whether the retransmitted data can be correctly received. The credit synchronization frame is a functional frame used to implement credit synchronization training, carrying information such as the current credit limit and buffer reservation status, thereby achieving synchronization of the flow control credit state. The flow control credit state is a flow control (i.e., flow control) mechanism state based on credit counting; the credit limit reflects the available space of the buffer, and synchronizing this state can prevent buffer overflow or idleness.

[0049] 203. If the link status information indicates that the data transmission link is in a normal state, the first chip interacts with the second chip based on the data transmission link to obtain the link negotiation result. The link negotiation result is used to indicate the data transmission method between the first chip and the second chip.

[0050] In this embodiment, the normal state refers to a state where the link is physically connected, parameters are adapted, and the basic requirements for data transmission are met. The link negotiation result refers to the data transmission method agreement determined through interaction between chips, including key parameters such as transmission rate, transmission bit width, encoding method, and flow control strategy, providing a unified standard for subsequent data transmission. The data transmission method includes detailed rules and forms for data transmission between chips, which will not be elaborated upon in this embodiment.

[0051] 204. Based on the data transmission link and the link negotiation result, the first chip and the second chip transmit data.

[0052] In this embodiment, based on the established data transmission link and the negotiated data transmission method, data can be transmitted efficiently and stably between chips according to unified rules. The training, recovery and negotiation in the above steps provide a guarantee for the implementation of this step.

[0053] This application provides a data transmission method that subdivides the link negotiation process into three stages: basic link training, abnormal state recovery, and transmission parameter interaction. Dedicated function frames are configured for each stage. Using this method, the first and second chips on both sides of the link can achieve precise communication of states and parameters. Especially in the abnormal recovery stage, retransmission synchronization frames and credit synchronization frames can be flexibly selected to synchronize retransmission states and flow control credit states, facilitating efficient adjustment of the data transmission link to a normal state and thus completing the transmission agreement. This not only improves the efficiency of link negotiation, thereby improving the overall efficiency of data transmission, but also enhances the link's recovery capability and transmission stability in abnormal scenarios, thus meeting the high-speed communication requirements between multiple chips.

[0054] Having briefly introduced the data transmission method proposed in this application above, the multi-dimensional hierarchical design in this application will now be explained. This multi-level design is divided into multi-level coordination processes and multi-level negotiation control management.

[0055] First, the negotiation process is multi-layered. A multi-layered negotiation process means that the negotiation process of the data transmission link covers the entire process from the physical layer, the link layer to the transport layer, and each layer has a clear division of labor and cooperates with each other to ensure the integrity of the link from physical connectivity to protocol adaptation.

[0056] The physical layer is the foundational layer for link transmission, further divided into the PHY sublayer and the PCS sublayer. The PHY sublayer adapts to the physical characteristics of the basic link, including link channel quantity awareness, basic clock locking, and the configuration and selection of basic rate parameters, ensuring the physical layer link has basic transmission conditions and transmitting information such as the physical link connectivity status from the PHY sublayer to the PCS sublayer. The PCS sublayer handles synchronization and parameter negotiation for the basic link, such as exchanging information on encoding methods, scrambling algorithms, rate ranges, and speed levels. It also performs functions such as individual usability confirmation for each channel, codeword alignment for a single channel, and alignment negotiation for multiple channels, thus providing a stable physical transmission channel for the link layer.

[0057] The link layer, serving as an intermediate layer between the physical layer and the user layer, ensures reliable transmission. It achieves data transmission stability through protocol negotiation and state detection, essentially completing the link's protocol negotiation handshake. For example, the link layer confirms the usage of reliability mechanisms such as FEC (Forward Error Correction), CRC (Cyclic Redundancy Check), and retransmission algorithms. It also verifies retransmission status in real time, detects link operation status, and initiates recovery procedures upon detecting transmission errors or anomalies. Furthermore, the link layer controls link state confirmation and regenerative training, including link retraining and retransmission correctness negotiation, ensuring the link can quickly recover to a stable transmission state after an anomaly.

[0058] The link user layer is the interface layer between the link and upper-layer applications. It is used to adapt the link to the kernel communication system and perform protocol conversion, ensuring that data transmission meets the requirements of upper-layer applications. For example, the link user layer is used to perform upper-layer protocol version handshakes, clarifying the compatible protocol standards between the two parties; agreeing on core communication parameters, including frame structure, packet structure, parsing strategies, etc., to provide a unified format specification for data transmission; implementing a bilateral credit transfer and synchronization mechanism, ensuring the effective operation of the flow control mechanism through credit limit management; and supporting a bilateral low-power state transfer and synchronization mechanism to achieve energy-saving management when the link is idle, improving the flexibility and energy efficiency of link use.

[0059] For ease of description, see Figure 3 As shown, Figure 3 This is a schematic diagram of a hierarchical negotiation according to an embodiment of this application. The negotiation process proceeds sequentially through PHY sublayer training, PCS sublayer training, MAC layer training, and protocol layer training.

[0060] Accordingly, during the PHY sublayer training phase, the system first waits for the power supply to reach a stable state to confirm PHY readiness; it then loads basic parameters, completes PLL (Phase-Locked Loop) initialization, and ensures clock signal stability; both ends conduct analog signal handshakes at the default base rate to establish a preliminary physical connection; once the basic physical link conditions are met, a PHY ready signal is sent to the PCS sublayer, and the number of physical subchannels actually used in the link is confirmed. During the PCS layer training phase, the focus is on basic link state synchronization. First, both sides interactively confirm that the physical layers are both in the ready state; then, based on the default base rate and bit width, core training information such as maximum bit width, maximum rate, and optional feature support is synchronized; Max performance training is performed, determining the transmission rate and bandwidth according to a logic from high to low (or from wide to narrow), verifying link stability through sending and receiving handshake frames, and dynamically adjusting the physical layer signal quality to optimize transmission performance; finally, the link status is confirmed. If the status is normal, the MAC layer is notified that it is ready; if it does not meet the requirements, training is restarted until the transmission requirements are met. This is similar to the training logic of protocols such as PCIe, and will not be elaborated further here.

[0061] During the MAC layer training phase, the core focus is on the mechanism handshake. First, a protocol version handshake is completed to clarify the compatible protocol generations for both sides. Then, a verification mechanism handshake is performed to confirm whether FEC (Functional Emission Control) is enabled and the corresponding FEC encoding version (usually consistent with the protocol version). Following this, a retransmission mechanism handshake is conducted, agreeing on key information such as whether to enable retransmission, CRC encoding type, and MAC layer frame type. Retransmission-related data, such as sequence number range and current receive window position, are exchanged as needed to ensure the orderly operation of the retransmission mechanism. During the protocol layer training phase, the focus is on negotiating upper-layer adaptation parameters, including protocol version handshakes to unify communication standards, bilateral credit information handshakes to synchronize flow control credit status, and bilateral low-power state handshakes to achieve energy-saving coordination. It should be noted that the functions of MAC layer training and protocol layer training can be uniformly handled by the MAC layer, reducing layer-level interaction overhead and improving the overall efficiency of link negotiation through integrated negotiation.

[0062] Secondly, the multi-layered negotiation control management refers to adopting a multi-level, functionally specialized design concept to construct an overall negotiation control state machine group. Each level of state machine collaborates and links together, comprehensively covering the entire process requirements of link negotiation. Accordingly, the first level is the basic training state machine, used to implement the basic link training process, including link physical connectivity detection, basic parameter interaction, sub-channel calibration, etc., completing the basic adaptation of the link from disorder to order. The second level is the recovery training state machine, which executes corresponding recovery processes for abnormal link states (such as retransmission mismatch, credit mismatch, connectivity interruption, etc.), restoring the link to a normal transmission state through operations such as retransmission synchronization, credit synchronization, and link retraining. The third level is the user protocol handshake state machine, responsible for the protocol interface and parameter negotiation of the link user layer, including upper-layer protocol version confirmation, communication parameter agreement, credit synchronization, etc., ensuring that link transmission accurately matches the requirements of upper-layer applications. Through the cooperation of each level of state machines, not only is the professional processing of each stage of link negotiation guaranteed, but also efficient collaboration throughout the entire process is achieved, providing support for the stability and efficiency of data transmission.

[0063] For ease of description, see Figure 4 As shown, Figure 4 This is a schematic diagram of an overall state machine group provided according to an embodiment of this application. The state machine group adopts a hierarchical architecture combining central control and decentralized control. It has a central control state machine for the link state as its core, which manages three sub-state machines: the basic training control state machine for the link (i.e., the link training state machine in the aforementioned chip), the transmission control state machine for the link (i.e., the link transmission state machine in the chip), and the recovery control state machine for the link (i.e., the link recovery state machine in the chip). Each sub-state machine is further subdivided into functionally specific lower-level state machines, achieving refined control over the entire link lifecycle. A detailed description follows.

[0064] The link state control state machine is the core scheduling unit of the entire state machine group, responsible for coordinating the state switching of the link at different stages, such as transitioning from the basic training stage to the transmission stage, and from the transmission stage to the recovery stage. During the basic training stage, the link basic training control state machine is responsible, which is further subdivided into three functional state machines: the link detection control state machine, used to detect basic conditions such as link physical connectivity and sub-channel availability; the link confirmation control state machine, used to complete the interaction and compatibility confirmation of basic link parameters; and the link configuration control state machine, used to negotiate and configure core parameters such as link transmission rate and transmission bit width. During the normal transmission stage, the link transmission control state machine is responsible, which is further subdivided into two functional state machines: the normal transmission control state machine, used to manage the data sending and receiving logic during stable link transmission; and the retransmission control state machine, used to handle the retransmission process after data errors during transmission, ensuring data transmission reliability. During the link anomaly recovery phase, the link recovery control state machine is responsible, which is further divided into three functional state machines: the retransmission synchronization control state machine (i.e., the retransmission synchronization state machine in the chip) is used to complete the state synchronization of the retransmission buffer and the receiving window in response to the retransmission mismatch state; the retraining control state machine (i.e., the retraining state machine in the chip) is used to restart the basic link training process to rebuild physical connectivity; and the credit synchronization control state machine (i.e., the credit synchronization state machine in the chip) is used to calibrate and align the flow control credit state in response to the credit mismatch state.

[0065] This hierarchical state machine architecture not only ensures the coordination of the entire link process through the central control state machine, but also realizes fine-grained control of each stage through functionally dedicated lower-level state machines, effectively improving the efficiency and reliability of link state switching and adapting to the complex requirements of high-speed communication between multiple chips for link state control.

[0066] Building upon the above description of the multi-dimensional hierarchical design in this application, the following section explains the multi-dimensional phased design. This multi-dimensional phased design includes functional flow phased design, execution flow phased design, and link layer functional frame phased design.

[0067] The functional flow phased design is divided into the basic link training phase, the link recovery training phase, and the information system handshake mechanism. The execution flow phased design is divided into the training flow phased design and the general interactive control phased design. The link layer functional frame phased design includes link training frames, retransmission synchronization frames, and credit synchronization frames, etc. These will be described in detail in the embodiments given below.

[0068] Figure 5 This is a flowchart of another data transmission method provided according to an embodiment of this application. The method is illustrated using an application to a first chip as an example. See [link to flowchart]. Figure 5 The method includes the following steps: 501. Based on the link training frame, the data transmission link between the first chip and the second chip is trained to obtain link status information. The link training frame carries link configuration data, and the link status information is used to characterize the connectivity status of the data transmission link.

[0069] In this embodiment of the application, the principle of link training in this step is the same as that in step 201 above, and will not be repeated here.

[0070] Correspondingly, this step corresponds to the basic link training stage. The basic adaptation of the data transmission link between the first chip and the second chip is achieved through the link training frame, physical connectivity detection and parameter negotiation are completed, and link status information representing the link connectivity status is obtained.

[0071] In the basic link training phase, the process proceeds step-by-step according to the logic of link detection, link information exchange, and link working state negotiation, ensuring the link achieves both physical connectivity and parameter adaptation. Specifically, in the link detection phase, basic link conditions are checked, including whether the link is powered on and connected, and whether each sub-channel is in place and available, thus clarifying the basic physical conditions of the link. In the link information exchange phase, channel-level parameter exchange takes place, including bidirectional transmission of key information such as symbol alignment, polarity detection, and maximum rate range for each sub-channel. Simultaneously, multi-round handshake frame exchanges verify the continuous stability of link transmission. In the link working state negotiation phase, core link working parameters are determined, such as the order of available sub-channels (forward or reverse order), multi-channel data transmission synchronization rules, transmission rate, and transmission bit width. After parameter negotiation, accelerated training is performed through the link retraining process in the subsequent link recovery training phase to achieve optimal link transmission performance.

[0072] In some embodiments, basic link training is implemented between chips based on the interaction of link training frames. Accordingly, the first chip sends a first link training frame to the second chip, the first link training frame carrying link configuration data supported by the first chip, the link configuration data including at least one of channel-level and link-level related parameters; the second chip receives a second link training frame sent by the second chip, the second link training frame carrying link configuration data supported by the second chip; based on the data carried by the first and second link training frames, the data intersection between the link configuration data supported by the first and second chips is determined; based on the data intersection, sub-channel calibration is performed on the data transmission link, and physical connectivity detection is performed to obtain link status information.

[0073] By bidirectionally sending link training frames carrying configuration data of their respective supported links, the intersection of configuration data between chips is accurately determined, and sub-channel calibration and physical connectivity detection are performed based on this intersection. This method ensures that link training is based on mutually compatible configurations, avoids invalid training, improves the targeting and accuracy of training, and can quickly and accurately obtain link status information reflecting the true connectivity status of the link, providing a reliable data foundation for subsequent link anomaly recovery or normal negotiation.

[0074] In some embodiments, link training frames are used to undertake training tasks at each stage of the entire link training and recovery training process. Link training frames include channel-level training frames and link-level training frames. Channel-level training frames are used for basic adaptation of a single channel, such as carrying the number of sub-channels, polarity data, and codeword alignment data. Through specific codeword encoding, they complete the single-channel's fluency verification, codeword alignment, and other basic parameter confirmation and bidirectional handshake, ensuring that a single sub-channel has the conditions for data transmission. Polarity data refers to parameters characterizing the positive and negative logic of sub-channel data transmission, used to calibrate the logical consistency of data transmission and avoid data parsing errors caused by polarity reversal; codeword alignment data refers to reference data used to achieve data symbol synchronization within a single channel. Link-level training frames are used for collaborative adaptation of multiple channels, such as carrying sub-channel synchronization rules, transmission rate range, and transmission bit width range. Sub-channel synchronization rules are used to achieve data transmission synchronization of multiple sub-channels in the data transmission link. Through specific encoded frames, they carry information during link-level negotiation, ensuring the consistency of multi-channel collaborative work. Based on this, the first and second link training frames mentioned above can both be channel-level training frames or link-level training frames, which will not be elaborated further.

[0075] For ease of description, see Figure 6 As shown, Figure 6 This is a schematic diagram of a functional frame provided according to an embodiment of this application. Wherein, Figure 6 Figure (a) shows a channel-level function frame. When this function frame is a channel-level training frame, the information codewords of the data modules at different stages will be assigned different information values. Accordingly, taking Lane 0, Lane 1 to Lane 15 (i.e., multiple sub-channels) as examples, each sub-channel's function frame adopts a three-segment structure of special codeword, information codeword, and special codeword. The special codeword is the identifier and control carrier of the channel-level function frame, and it will be assigned different control meanings at different training stages. The information code field is located between two special codewords and is the parameter carrying area. Different training stages (such as Lane in-situ detection, polarity calibration) will assign different parameter values ​​(such as the number of sub-channels, polarity data, codeword alignment data, etc.) to these information codewords. Figure 6Figure (b) shows a link-level functional frame. When this functional frame is a link-level training frame, special codewords and information codewords of data modules at different stages will be assigned different information values. Accordingly, the verification information group is used to carry the verification parameters of the link-level data and to verify the integrity of the functional frame data; the retransmission interaction information group is used to store retransmission-related status parameters (such as retransmission buffer occupancy and the start position of the receive window) to adapt to retransmission synchronization training scenarios; the user layer information synchronization information group is used to transmit user layer coordination parameters (such as credit limit and low power status) to support upper layer protocol adaptation; the frame identification and control information group contains control information such as the type identifier and stage identifier of the functional frame, which is used by both parties in the link to identify the purpose and processing logic of the frame.

[0076] By subdividing link training frames into channel-level and link-level frames, each carrying its own configuration data, the implementation of each negotiation stage is supported. Channel-level training frames ensure the adaptation of basic parameters and codeword alignment for sub-channels, while link-level training frames realize the synchronization of multiple sub-channels and the negotiation of key parameters such as transmission rate and bit width. Layered training makes the link training logic clearer and the division of labor more explicit, ensuring both the connectivity of individual sub-channels and the consistency of multi-channel collaboration, thereby improving the comprehensiveness and efficiency of link training.

[0077] After completing the basic link training, if an anomaly occurs in the data transmission link, the link recovery training phase begins to adjust the data transmission link back to a normal state. For possible link anomalies such as retransmission mismatch, credit mismatch, and connectivity interruption, corresponding recovery procedures are executed, as described in steps 502 to 504 below. Through operations such as retransmission synchronization, credit synchronization, and link retraining, the link is restored to a normal transmission state. These procedures are detailed below.

[0078] 502. If the link status information indicates that the data transmission link is in a retransmission mismatch state, the first chip interacts with the second chip based on the retransmission synchronization frame to restore the data transmission link. The retransmission synchronization frame is used to synchronize the retransmission buffer state with the receiving window state.

[0079] In this embodiment, the retransmission mismatch state refers to an abnormal state in which the retransmission buffer state and the receiving window state between the first chip and the second chip are inconsistent due to factors such as data transmission errors, link interference, and temporary hardware failures, which in turn causes the retransmission data to be unable to be correctly identified and received, the transmission order to be disordered, and the link to be unable to complete the retransmission process normally.

[0080] Correspondingly, this step corresponds to the retransmission synchronization training phase in the link recovery training phase. If data transmission errors cause retransmission state confusion, dedicated function frame interactions are used to resynchronize both parties and restore normal transmission. During the retransmission synchronization training phase, when the link is in extreme error scenarios such as retransmission mismatch, or when there are specific synchronization requirements, the link suspends normal data transmission and initiates the retransmission synchronization training process. Through dedicated link-layer function frames (such as retransmission synchronization frames), the synchronization handshake of the link-layer retransmission state is completed. With the bidirectional interaction of a series of link-layer function frames, the synchronization and alignment of the retransmission buffer state and receive window state of both parties are accurately achieved, enabling the link to regain normal transmission capability. This process can additionally support state communication and alignment under higher-level specific flow control scenarios, depending on actual needs. For example, when the user layer uses non-Credit flow control, if the link cannot work due to buffer congestion, this process can be used to complete the handshake communication of the states of both parties, avoiding data loss and ensuring that the link can quickly adapt when the user layer resumes operation.

[0081] In some embodiments, retransmission synchronization training is achieved between chips based on the interaction of retransmission synchronization frames. Accordingly, in the case of retransmission mismatch, the first chip sends a first retransmission synchronization frame to the second chip, the first retransmission synchronization frame carrying the retransmission buffer occupancy status and the start position of the receiving window corresponding to the first chip; the second chip receives a second retransmission synchronization frame sent by the second chip, the second retransmission synchronization frame carrying the retransmission buffer occupancy status and the start position of the receiving window corresponding to the second chip; calibration is performed based on the data carried by the second retransmission synchronization frame to achieve synchronization of the retransmission buffer status and receiving window status of the first chip and the second chip.

[0082] The retransmission buffer occupancy status refers to the usage status of the retransmission buffer in the chip used to store data to be retransmitted. This includes core information such as the size of the occupied storage space, the remaining available space, the number of data to be retransmitted, and its unique identifier. This reflects the load on the retransmission buffer. The receive window start position refers to the effective address or identifier starting point when the chip receives data. The chip only receives data transmitted within this starting position and subsequent ranges, making it a key parameter for defining the effective data reception range. The retransmission buffer status refers to the comprehensive state characterizing the overall operation of the retransmission buffer, such as the retransmission buffer occupancy status, the transmission priority of data to be retransmitted, the buffer's read / write status, and whether there is a risk of data overflow. This can affect the storage efficiency and transmission order of retransmitted data. The receive window status refers to the comprehensive state characterizing the effective range of data received by the chip, including the receive window start position, receive window size, the identifier range of currently receivable data, and whether there is a receive overflow. Its synchronization consistency with the sender determines whether retransmitted data can be correctly identified and received.

[0083] To address retransmission mismatch issues, a retransmission synchronization frame carrying the retransmission buffer occupancy status and the start position of the receive window is used for bidirectional interaction, enabling precise calibration and synchronization of retransmission-related states between chips. This method can pinpoint the core problem of retransmission mismatch, quickly resolve transmission faults, shorten link recovery time, and avoid data loss or transmission disorder caused by retransmission mismatch.

[0084] 503. If the link status information indicates that the data transmission link is in a credit mismatch state, the first chip interacts with the second chip based on the credit synchronization frame to restore the data transmission link. The credit synchronization frame is used to realize the synchronization of the flow control credit status.

[0085] In this embodiment, credit mismatch refers to an abnormal state in which the flow control credit status between the first chip and the second chip is inconsistent due to factors such as link transmission errors, hardware abnormalities, and flow control parameter configuration deviations, which in turn causes problems such as buffer overflow, data congestion, and waste of transmission resources, and the link cannot complete the orderly data transmission as expected.

[0086] Correspondingly, this step corresponds to the credit synchronization training phase within the link recovery training phase. If the flow control mechanism for buffered credit limits (Credit) becomes disordered, synchronization is renegotiated through the interaction of dedicated function frames to avoid data congestion and resource waste. During the credit synchronization training phase, if a link error or other unforeseen event causes credit mismatch at the user layer on both ends (especially applicable to scenarios using Credit flow control), this process can be initiated under the instruction of the link user layer. Through a re-handshake communication between the two Credits, the credit status is updated and calibrated to ensure the flow control mechanism returns to normal.

[0087] In some embodiments, credit synchronization training is achieved between chips based on the interaction of credit synchronization frames. Accordingly, in the event of a credit mismatch, the first chip sends a first credit synchronization frame to the second chip, the first credit synchronization frame carrying the current credit limit and buffer reservation status of the first chip; it receives a second credit synchronization frame sent by the second chip, the second credit synchronization frame carrying the current credit limit and buffer reservation status of the second chip; and calibration is performed based on the data carried in the second credit synchronization frame to achieve synchronization of the flow control credit status of the first chip and the second chip.

[0088] The current credit limit refers to the remaining buffer usage rights allocated by the chip to the other party based on the flow control mechanism. It is a core parameter representing the available space of the buffer, and the other party can only send data within this limit to avoid buffer overflow. The buffer reservation status refers to the occupation and allocation status of the buffer resources reserved in the chip for data transmission, such as the total capacity of the reserved buffer, the size of the buffer already allocated to the current link, and the remaining reservable space, which is used to ensure the stability of the buffer resource supply for data transmission. The flow control credit status represents the overall operating status of the flow control based on the Credit mechanism, including key information such as the current credit limit, buffer reservation status, credit consumption rate, and credit replenishment cycle, which determines the operating efficiency of the flow control mechanism and the orderliness of data transmission.

[0089] To address the abnormal state of credit mismatch, a credit synchronization frame carrying the current credit limit and buffer reservation status is transmitted bidirectionally. This accurately calibrates the flow control credit status between chips, effectively solving problems such as flow control disorder, buffer overflow or idleness caused by credit mismatch. It improves the efficiency of abnormal recovery, ensures the normal operation of the flow control mechanism, guarantees the orderly transmission of data, and is suitable for high-concurrency data transmission scenarios of multiple chips.

[0090] 504. If the link status information indicates that the data transmission link is in a link connectivity interruption state, the first chip interacts with the second chip based on the retransmission synchronization frame and the credit synchronization frame to restore the data transmission link. The retransmission synchronization frame is used to synchronize the retransmission buffer state and the receiving window state, and the credit synchronization frame is used to synchronize the flow control credit state.

[0091] In this embodiment of the application, the link connectivity interruption state refers to an abnormal state in which the physical transmission channel between the first chip and the second chip fails and parameter synchronization is lost due to factors such as physical link disconnection, hardware failure, or extreme interference, and the link cannot transmit data or interact.

[0092] Correspondingly, this step corresponds to the link retraining process in the link recovery training phase. When a physical connectivity interruption occurs, the basic physical link must be rebuilt first, and then the core transmission status synchronized to ensure a full link recovery. In the link retraining process, the basic link training must first be restarted through the link training frame to complete the physical layer re-adaptation. Then, for derivative problems such as retransmission mismatch and credit mismatch that may be caused by the interruption, the state calibration is completed through the corresponding synchronization frame to achieve a complete recovery of the link from physical to logical. In addition, even if the current data transmission link is still in a connected state, after completing the relevant differences (such as transmission frequency, transmission bit width, etc.) configuration, link retraining is still performed. At this time, the link restart operation is restarted by re-directing to the basic link training.

[0093] In some embodiments, link recovery is achieved through collaborative interaction between chips based on link training frames, retransmission synchronization frames, and credit synchronization frames. Correspondingly, in the case of a link connectivity interruption, the physical connectivity and parameter synchronization of the data transmission link are re-established based on the link training frames; and the steps taken in the retransmission mismatch and credit mismatch states are executed based on the retransmission synchronization frames and credit synchronization frames. Here, physical connectivity and parameter synchronization refer to the negotiation and adaptation of basic parameters such as sub-channel presence detection, clock locking, codeword alignment, transmission rate, or transmission bit width in the link through interaction with the link training frames, restoring the link's physical transmission capability and providing a foundation for subsequent state synchronization.

[0094] In response to the abnormal state of link connectivity interruption, physical connectivity and parameter synchronization are first reconstructed through link training frames. Then, retransmission synchronization frames and credit synchronization frames are combined to solve potential retransmission mismatch and credit mismatch problems. This comprehensively covers the multi-level problems that may exist after the interruption, ensuring stable and efficient data transmission after the link is restored. It avoids subsequent transmission failures due to incomplete interruption recovery, and improves the success rate and reliability of link recovery.

[0095] Having described the various sub-stages of the link recovery training phase above, the following section explains the phased design of the execution process. In this process, an information system handshake mechanism is used to achieve interaction.

[0096] The training process is further subdivided into stages, including sub-channel level state detection, link level information interaction, and link level state negotiation. For details, please refer to the basic link training stage in step 501 above, which will not be repeated here.

[0097] The general interactive control process is divided into three phases: the interaction initiation phase, the interaction synchronization phase, and the interaction completion phase. Accordingly, in the interaction initiation phase, a specific frame for the current process is sent to notify the other party to initiate the current interaction. In the interaction synchronization phase, once both parties have fulfilled the corresponding specific frame sending conditions and received quantities, the process transitions to the interaction synchronization phase, where specific frames are used to initiate formal information exchange and status synchronization operations. In the interaction completion phase, once the corresponding revenue quantity conditions are met in the formal information exchange phase, the process returns to this phase, where specific frames are used to communicate and complete the entire general interactive control phase.

[0098] For each of the above stages, synchronization initiation frames, synchronization interaction frames, and synchronization completion frames are provided. These frames are all sub-types of retransmission synchronization frames or credit synchronization frames. Retransmission synchronization frames / credit synchronization frames refer to link layer function frames used during retransmission recovery and credit recovery processes after the link physical layer is ready. For easier description, see [link to documentation]. Figure 6 In Figure (b), data content is organized and allocated in units of frames, and relevant information is retrieved at different stages.

[0099] In the synchronization initiation phase, a synchronization initiation frame is used to notify both parties in the link to begin the synchronization process, in conjunction with the state transitions of the relevant state machines. Once the relevant control state machine enters the synchronization state, it sends and receives synchronization interaction frames to complete the information exchange of the current state. After completing the first two phases, the entire process is synchronized again based on the synchronization completion frame, and then the synchronization phase ends.

[0100] In some embodiments, the link recovery process is described in conjunction with each synchronization frame. Accordingly, during the recovery process of the data transmission link, the first chip notifies the second chip to enter the synchronization state based on the synchronization initiation frame, which carries a synchronization start instruction; the second chip is notified to perform parameter and state alignment based on the synchronization interaction frame, which carries parameter data, state identifier, and alignment reference information; and the second chip is notified that synchronization has been completed based on the synchronization completion frame, which carries a synchronization result identifier, which is used to indicate whether the alignment was successful.

[0101] Among them, the synchronization start command refers to the control command that triggers the other party to enter the synchronization state. Parameter data refers to the core configuration parameters that need to be synchronized, such as retransmission buffer occupancy and credit limit; status identifier refers to the unique identifier that represents the current link status of the sender, such as indicating retransmission buffer status and flow control credit status; alignment reference information refers to the reference standard used for parameter calibration between the two parties, such as reference timestamp and reference status value.

[0102] During link recovery, the orderly interaction of synchronous initiation frames, synchronous interaction frames, and synchronous completion frames clarifies the instructions and data transmission at each stage of link recovery. Synchronous initiation frames ensure both parties enter a synchronized state, synchronous interaction frames guarantee precise alignment of parameters and states, and synchronous completion frames provide timely feedback on the alignment results. This mechanism standardizes and makes the link recovery process transparent, avoiding recovery failures or inefficiencies caused by asynchronous operations between the two parties, improving the orderliness and success rate of link recovery, shortening recovery time, and ensuring rapid and stable data transmission.

[0103] For ease of description, see Figure 7 As shown, Figure 7 This is a schematic diagram of a link layer state machine group according to an embodiment of this application. The state machine group includes four functionally dedicated sub-state machines: a synchronization state machine, a transmission state machine, a link layer operating state control state machine, and a retransmission state machine. Ellipses correspond to the current state, and the associations between states correspond to switching conditions.

[0104] In detail, the synchronization state machine (left side) is responsible for the synchronization alignment of both ends during link startup or recovery. Its process starts from the START state, sequentially entering the S_SYNC state to initiate the synchronization process, the DONE state to complete synchronization preparation, the SYNC_SND state to send the synchronization signal, and finally entering the SYNC_RCV state to receive the other party's synchronization signal. If an error occurs during the synchronization process, it switches to the SETNACK state to mark the synchronization failure, then enters the S_INIT state to reinitialize, and then returns to the START state to restart the synchronization process. The sending state machine (upper right side) is responsible for managing the order of data transmission, ensuring that data is packaged and transmitted according to specifications. Its process starts from the CTAIL state to prepare the tail data, then enters the HEAD state to send the header identifier, and finally enters the DTAIL state to send the data content. Through orderly state switching, it ensures that data is transmitted according to correct logic. The link layer working state control state machine (middle side) is responsible for switching the link's standby, working, and fault states. Its core working state is ACTIVE. When the link starts, it first enters the INIT state to complete initialization, then enters the SYNC state to cooperate with the synchronization process, and finally enters the ACTIVE state to maintain normal operation. During operation, if data congestion occurs, it switches to the OVERRUN state; if an unacknowledged signal is received, it switches to the NACK state; if a serious fault occurs, it switches to the FAULT state. After the fault is recovered, it switches back to the ACTIVE state to continue working. The retransmission state machine (lower right) is used to handle the retransmission process after data transmission errors. It first enters the P_UNIT state to prepare the retransmission unit, then enters the P_HEAD state to send the retransmission header identifier, and finally enters the P_TAIL state to send the retransmission data content.

[0105] Based on this, during the link startup phase, the synchronization state machine first completes the synchronization between the two ends; after successful synchronization, the link layer working state control state machine switches to the ACTIVE state; thereafter, the sending state machine performs normal data transmission; if an error occurs during data transmission, the retransmission state machine is triggered to initiate the retransmission process. Through the cooperation of each state machine, the stable and efficient operation of the link layer is ensured.

[0106] 505. If the link status information indicates that the data transmission link is in a normal state, the first chip interacts with the second chip based on the data transmission link to obtain the link negotiation result. The link negotiation result is used to indicate the data transmission method between the first chip and the second chip.

[0107] In this embodiment of the application, the principle of link negotiation in this step is the same as that in step 203, and will not be repeated here.

[0108] 506. Based on the data transmission link and the link negotiation result, the first chip and the second chip transmit data.

[0109] In this embodiment of the application, the principle of data transmission in this step is the same as that in step 204, and will not be repeated here.

[0110] This application provides a data transmission method that subdivides the link negotiation process into three stages: basic link training, abnormal state recovery, and transmission parameter interaction. Dedicated function frames are configured for each stage. Using this method, the first and second chips on both sides of the link can achieve precise communication of states and parameters. Especially in the abnormal recovery stage, retransmission synchronization frames and credit synchronization frames can be flexibly selected to synchronize retransmission states and flow control credit states, facilitating efficient adjustment of the data transmission link to a normal state and thus completing the transmission agreement. This not only improves the efficiency of link negotiation, thereby improving the overall efficiency of data transmission, but also enhances the link's recovery capability and transmission stability in abnormal scenarios, thus meeting the high-speed communication requirements between multiple chips.

[0111] More specifically, this link self-negotiation system, as a fundamental supporting technology, enables training on basic link connectivity and efficient negotiation of link width, speed, etc. It provides recoverable negotiation after link errors; when a link experiences numerous uncorrectable errors or frequent retransmissions, self-recovery can be achieved through the link recovery training system. Furthermore, when the retransmission mechanisms at both ends of the link experience communication anomalies due to link errors, a new docking and negotiation process can be completed through the corresponding link retransmission recovery mechanism, thereby restoring normal use. Using this method, a comprehensive multi-layered, multi-stage, and multi-dimensional training, recovery, and synchronization mechanism can be constructed for high-speed interconnect links, efficiently ensuring the overall applicability of the link. In other words, this method effectively couples the resolution of multi-layered protocol and multi-angle link problems and abnormal state repair, further coupling the link from its original layered mechanism to form a complete link basic training, recovery training, and high-level state synchronization process and control mechanism. Moreover, this method is applicable to the construction and design of multi-layered training and recovery mechanisms for any link interconnected based on high-speed SerDes, demonstrating high applicability.

[0112] Figure 8 This is a block diagram of a data transmission apparatus according to an embodiment of this application. The apparatus is used to perform the steps of the data transmission method described above, see below. Figure 8 The data transmission device includes: a training module 801, a recovery module 802, a negotiation module 803, and a transmission module 804.

[0113] The training module 801 is used to train the data transmission link between the first chip and the second chip based on the link training frame to obtain link status information. The link training frame carries link configuration data, and the link status information is used to characterize the connectivity status of the data transmission link. The recovery module 802 is used to interact with the second chip based on at least one of the retransmission synchronization frame and the credit synchronization frame to restore the data transmission link if the link status information indicates that the data transmission link is in an abnormal state. The retransmission synchronization frame is used to synchronize the retransmission buffer state with the receiving window state, and the credit synchronization frame is used to synchronize the flow control credit state. The negotiation module 803 is used to interact with the second chip based on the data transmission link if the link status information indicates that the data transmission link is in a normal state, and obtain the link negotiation result. The link negotiation result is used to indicate the data transmission method between the first chip and the second chip. The transmission module 804 is used to transmit data with the second chip based on the data transmission link and the link negotiation result.

[0114] In some embodiments, the training module 801 is configured to send a first link training frame to the second chip, the first link training frame carrying link configuration data supported by the first chip; receive a second link training frame sent by the second chip, the second link training frame carrying link configuration data supported by the second chip; determine the data intersection between the link configuration data supported by the first chip and the second chip based on the data carried by the first link training frame and the second link training frame; and perform sub-channel calibration and physical connectivity detection on the data transmission link based on the data intersection to obtain link status information.

[0115] In some embodiments, the link training frame includes a channel-level training frame and a link-level training frame; the channel-level training frame carries the number of sub-channels, polarity data, and codeword alignment data; the link-level training frame carries the sub-channel synchronization rules, transmission rate range, and transmission bit width range, and the sub-channel synchronization rules are used to realize the data transmission synchronization of multiple sub-channels in the data transmission link.

[0116] In some embodiments, the abnormal states indicated by the link status information include retransmission mismatch states; The recovery module 802 is used to send a first retransmission synchronization frame to the second chip when the retransmission mismatch is in a state of retransmission; the first retransmission synchronization frame carries the retransmission buffer occupancy status and the start position of the receiving window corresponding to the first chip; receive a second retransmission synchronization frame sent by the second chip; the second retransmission synchronization frame carries the retransmission buffer occupancy status and the start position of the receiving window corresponding to the second chip; and perform calibration based on the data carried by the second retransmission synchronization frame to achieve synchronization of the retransmission buffer status and the receiving window status of the first chip and the second chip.

[0117] In some embodiments, the abnormal states indicated by the link state information include credit mismatch states; The recovery module 802 is used to send a first credit synchronization frame to the second chip when the credit mismatch is in a state, the first credit synchronization frame carrying the current credit limit and buffer reservation status of the first chip; receive a second credit synchronization frame sent by the second chip, the second credit synchronization frame carrying the current credit limit and buffer reservation status of the second chip; and perform calibration based on the data carried by the second credit synchronization frame to achieve synchronization of the flow control credit status of the first chip and the second chip.

[0118] In some embodiments, the abnormal state indicated by the link status information includes a link connectivity interruption state; The recovery module 802 is used to re-establish the physical connectivity and parameter synchronization of the data transmission link based on the link training frame when the link connectivity is interrupted; and to perform the steps when the link is in the retransmission mismatch state and the credit mismatch state based on the retransmission synchronization frame and the credit synchronization frame.

[0119] In some embodiments, the recovery module 802 is further configured to, during the recovery process of the data transmission link, notify the second chip to enter the synchronization state based on a synchronization initiation frame, the synchronization initiation frame carrying a synchronization start instruction; notify the second chip to perform parameter and state alignment based on a synchronization interaction frame, the synchronization interaction frame carrying parameter data, state identifier and alignment reference information; and notify the second chip that synchronization has been completed based on a synchronization completion frame, the synchronization completion frame carrying a synchronization result identifier, the synchronization result identifier being used to characterize whether the alignment was successful.

[0120] This application provides a data transmission device that comprehensively collects time-series data of multi-dimensional performance indicators during chip simulation operation, integrates and aligns the data in the time domain, accurately captures the dynamic changes of each indicator under different time windows, and performs comprehensive analysis of multi-indicator collaborative data in conjunction with a performance evaluation model. This can cover key collaborative scenarios such as instruction execution, data interaction, and resource scheduling of multiple chip modules, thus comprehensively reflecting the collaborative state of each module. It overcomes the limitations of single-indicator analysis, avoids missing hidden performance bottlenecks in cross-module coupling, and can reveal cross-module performance coupling problems. The performance evaluation results can more realistically reflect the actual operating state of the chip, reduce evaluation bias, and improve the accuracy and reliability of data transmission in the pre-silicon stage, thereby providing accurate and effective data support for chip iterative upgrades.

[0121] It should be noted that the data transmission device provided in the above embodiments is only illustrated by the division of the above functional modules when running the application. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the chip can be divided into different functional modules to complete all or part of the functions described above. In addition, the data transmission device and data transmission method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0122] This application also provides a chip that includes the state machine described in the above embodiments, used to implement the data transmission method described in the above embodiments. See [link to relevant documentation]. Figure 4 This will not be elaborated upon further here.

[0123] This application also provides an electronic device, which includes a first chip and a second chip, for implementing the data transmission method described in the above embodiments. See [link to relevant documentation]. Figure 1 This will not be elaborated upon further here.

[0124] This application also provides a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor to implement the data transmission method described in the above embodiments. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0125] This application also provides a computer program product, including a computer program that is executed by a processor to implement the data transmission method in this application embodiment.

[0126] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0127] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data transmission method, characterized by, The method applied to a first chip comprises: training a data transmission link between the first chip and a second chip based on a link training frame to obtain link state information, the link training frame carrying link configuration data, and the link state information being used to represent a connectivity state of the data transmission link; if the link state information indicates that the data transmission link is in an abnormal state, interacting with the second chip based on at least one of a retransmission synchronization frame and a credit synchronization frame to recover the data transmission link, the retransmission synchronization frame being used to realize synchronization of retransmission buffer state and receiving window state, and the credit synchronization frame being used to realize synchronization of flow control credit state; if the link state information indicates that the data transmission link is in a normal state, interacting with the second chip based on the data transmission link to obtain link negotiation results, the link negotiation results being used to indicate a data transmission mode between the first chip and the second chip; performing data transmission with the second chip based on the data transmission link and the link negotiation results.

2. The method of claim 1, wherein, The method comprises: sending a first link training frame to the second chip, the first link training frame carrying link configuration data supported by the first chip; receiving a second link training frame sent by the second chip, the second link training frame carrying link configuration data supported by the second chip; determining a data intersection between link configuration data supported by the first chip and the second chip based on data carried by the first link training frame and the second link training frame; performing sub-channel calibration and physical connectivity detection on the data transmission link based on the data intersection to obtain the link state information.

3. The method according to claim 1 or 2, characterized in that, The link training frame comprises a channel-level training frame and a link-level training frame; the channel-level training frame carries sub-channel quantity, polarity data and code word alignment data; the link-level training frame carries sub-channel synchronization rules, transmission rate range and transmission bit width range, and the sub-channel synchronization rules are used to realize data transmission synchronization of multiple sub-channels in the data transmission link.

4. The method of claim 1, wherein, The abnormal state indicated by the link state information comprises a retransmission mismatch state; The method comprises: in the case of the retransmission mismatch state, sending a first retransmission synchronization frame to the second chip, the first retransmission synchronization frame carrying retransmission buffer occupancy and receiving window starting position corresponding to the first chip; receiving a second retransmission synchronization frame sent by the second chip, the second retransmission synchronization frame carrying retransmission buffer occupancy and receiving window starting position corresponding to the second chip; performing calibration based on data carried by the second retransmission synchronization frame to realize synchronization of retransmission buffer state and receiving window state of the first chip and the second chip.

5. The method of claim 1, wherein, The abnormal state indicated by the link state information comprises a credit mismatch state; The first chip is configured to interact with the second chip based on at least one of a retransmission synchronization frame and a credit synchronization frame to recover the data transmission link, including: In a case where the first chip is in the credit mismatch state, the first chip sends a first credit synchronization frame to the second chip, the first credit synchronization frame carrying a current credit limit and a buffer reservation state of the first chip; The first chip receives a second credit synchronization frame sent by the second chip, the second credit synchronization frame carrying a current credit limit and a buffer reservation state of the second chip; The first chip performs calibration based on data carried in the second credit synchronization frame to synchronize flow control credit states of the first chip and the second chip.

6. The method according to claim 4 or 5, characterized in that, The abnormal state indicated by the link state information includes a link connectivity interruption state; The first chip is configured to interact with the second chip based on at least one of a retransmission synchronization frame and a credit synchronization frame to recover the data transmission link, including: In a case where the first chip is in the link connectivity interruption state, the first chip re-establishes physical connectivity and parameter synchronization of the data transmission link based on the link training frame; The first chip performs steps in a case where the first chip is in the retransmission mismatch state and the credit mismatch state based on the retransmission synchronization frame and the credit synchronization frame.

7. The method of claim 1, wherein, The method further includes: In a recovery process of the data transmission link, the first chip notifies the second chip to enter a synchronization state based on a synchronization initiation frame, the synchronization initiation frame carrying a synchronization start instruction; The first chip notifies the second chip to align parameters and states based on a synchronization interaction frame, the synchronization interaction frame carrying parameter data, state identification, and alignment reference information; The first chip notifies the second chip that the synchronization has been completed based on a synchronization completion frame, the synchronization completion frame carrying a synchronization result identification, the synchronization result identification being used to represent whether alignment is successful.

8. A data transmission apparatus, characterized by comprising: The apparatus is configured in the first chip, and the apparatus includes: A training module configured to train a data transmission link between the first chip and a second chip based on a link training frame to obtain link state information, the link training frame carrying link configuration data, and the link state information being used to represent a connectivity state of the data transmission link; A recovery module configured to, if the link state information indicates that the data transmission link is in an abnormal state, interact with the second chip based on at least one of a retransmission synchronization frame and a credit synchronization frame to recover the data transmission link, the retransmission synchronization frame being used to synchronize a retransmission buffer state and a receiving window state, and the credit synchronization frame being used to synchronize a flow control credit state; A negotiation module configured to, if the link state information indicates that the data transmission link is in a normal state, interact with the second chip based on the data transmission link to obtain a link negotiation result, the link negotiation result being used to indicate a data transmission mode between the first chip and the second chip; A transmission module configured to perform data transmission with the second chip based on the data transmission link and the link negotiation result.

9. A chip, characterized by If the chip is a first chip, the first chip includes a link training state machine, a link recovery state machine, and a link transmission state machine; The link training state machine is configured to train a data transmission link between the first chip and the second chip based on a link training frame to obtain link state information, the link training frame carrying link configuration data, and the link state information being used to represent a connectivity state of the data transmission link. The link recovery state machine is configured to, if the link state information indicates that the data transmission link is in an abnormal state, interact with the second chip based on at least one of a retransmission synchronization frame and a credit synchronization frame to recover the data transmission link, the retransmission synchronization frame being used to synchronize a retransmission buffer state and a receiving window state, and the credit synchronization frame being used to synchronize a flow control credit state. The link transmission state machine is configured to, if the link state information indicates that the data transmission link is in a normal state, interact with the second chip based on the data transmission link to obtain a link negotiation result, the link negotiation result being used to indicate a data transmission mode between the first chip and the second chip. Data is transmitted between the first chip and the second chip based on the data transmission link and the link negotiation result.

10. An electronic device, the electronic device comprising a first chip and a second chip, and being configured to implement the data transmission method according to any one of claims 1 to 7.

11. A computer readable storage medium, characterized in that, The computer readable storage medium is configured to store at least one piece of computer program, the at least one piece of computer program being used to execute the data transmission method according to any one of claims 1 to 7.

12. A computer program product comprising a computer program, characterized in that, The computer program is configured to, when executed by a processor, implement the data transmission method according to any one of claims 1 to 7.

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