Semiconductor structure and preparation method thereof, memory device and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a memory device and electronic equipment. The semiconductor structure comprises a first transistor arranged on one side of a substrate; the first transistor comprises at least two grid electrodes which are sequentially distributed at intervals in the direction perpendicular to the substrate; the semiconductor layer is provided with channel regions which extend along the direction vertical to the substrate and respectively correspond to the at least two grids; and a gate insulating layer disposed between the at least two gates and the semiconductor layer. According to the invention, the electric field of the drain terminal is reduced, the gate-induced drain leakage current is reduced, the retention time is prolonged, and the refresh frequency is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and its fabrication method, a memory device, and an electronic device. Background Technology

[0002] With the development and progress of semiconductor technology, semiconductor structures are constantly evolving towards miniaturization, high storage density, high integration, and low power consumption. At the same time, they are also facing problems and challenges from performance and process aspects. Summary of the Invention

[0003] This application proposes a semiconductor structure and its fabrication method, a memory device, and an electronic device, which can reduce the drain electric field, decrease the gate-induced drain leakage current, increase the hold time, and reduce the refresh frequency.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure including a first transistor disposed on one side of a substrate; the first transistor includes: At least two gates are distributed sequentially at intervals along a direction perpendicular to the substrate; A semiconductor layer having a channel region extending in a direction perpendicular to the substrate and corresponding to at least two gates respectively; A gate insulating layer is disposed between at least two gates and semiconductor layers.

[0005] In some optional embodiments of this application, at least one of the following is included: The materials for the semiconductor layer include crystalline semiconductor materials; The semiconductor layer also includes a first polar region and a second polar region. The first polar region is connected to the end of the channel region near the substrate and extends in a direction parallel to the substrate. The second polar region is connected to the end of the channel region away from the substrate and extends in a direction parallel to the substrate. The second polar region is located on the side of the gate away from the substrate. The doping concentration of the first polar region and the second polar region is greater than the doping concentration of the channel region. The channel region at least partially surrounds the outer periphery of the gate.

[0006] In some optional embodiments of this application, the semiconductor structure further includes a component disposed on the side of the first transistor away from the substrate: In a capacitor, the second electrode region of the semiconductor layer is electrically connected to the first electrode plate of the capacitor, serving as a storage unit. or, The second transistor includes at least one gate, and a second polar region of the semiconductor layer is electrically connected to one of the gates of the second transistor, serving as a memory cell.

[0007] In some optional embodiments of this application, when the semiconductor structure includes a capacitor, the capacitor includes a first electrode plate, a capacitor dielectric layer, and a second electrode plate disposed sequentially. The first electrode plate is a cylindrical shape with one end open, and the opening faces away from the substrate. The capacitor dielectric layer conformally covers the inner wall of the first electrode plate, and the second electrode plate conformally covers the capacitor dielectric layer and fills the inner cavity of the first electrode plate.

[0008] Secondly, embodiments of this application provide a storage device, including: As described above, the semiconductor structure includes a plurality of memory cells arranged in an array, and each memory cell includes a first transistor. Multiple bit lines, where the first transistors of several memory cells located in the same row share a single bit line; Multiple word lines: The first transistors of several memory cells located in the same column share a single word line.

[0009] Thirdly, embodiments of this application provide an electronic device, including: Such as the semiconductor structure described above; or, Such as the storage devices mentioned above.

[0010] Fourthly, embodiments of this application provide a method for fabricating a semiconductor structure, including: A stacked structure is fabricated on one side of a substrate, the stacked structure having at least two gates spaced apart sequentially along a direction perpendicular to the substrate; Fabricate a gate insulating layer covering the stacked structure and the substrate; A semiconductor layer is fabricated such that it covers at least a portion of the gate insulating layer and has a channel region extending in a direction perpendicular to the substrate and corresponding to at least two gates respectively; the at least two gates, the semiconductor layer, and the gate insulating layer form a first transistor.

[0011] In some optional embodiments of this application, the semiconductor layer is fabricated, including: An initial semiconductor layer is formed on the side of the gate insulating layer away from the substrate. The material of the initial semiconductor layer is an amorphous semiconductor material. At least a portion of the initial semiconductor layer is doped. The initial semiconductor layer has an initial channel region extending in a direction perpendicular to the substrate and corresponding to at least two gates respectively. The metal-induced crystallization process is used to crystallize the amorphous semiconductor material of the initial semiconductor layer into a crystalline state to form a semiconductor layer, the initial channel region is formed into a channel region, and the doped impurities are activated.

[0012] In some optional embodiments of this application, an initial semiconductor layer is formed on the side of the gate insulating layer away from the substrate, including: Deposit amorphous silicon material to form a conformal amorphous silicon thin film covering the gate insulating layer; An amorphous silicon thin film is patterned to form an amorphous silicon film layer, and the amorphous silicon film layer has an initial channel region that at least partially surrounds the outer periphery of the gate, a first initial electrode region that is connected to the end of the initial channel region near the substrate and extends in a direction parallel to the substrate, and a second initial electrode region that is connected to the end of the initial channel region away from the substrate and extends in a direction parallel to the substrate, wherein the second initial electrode region is located on the side of the gate away from the substrate. Ion implantation was performed on the first and second initial polar regions using a self-aligned process, and the amorphous silicon film after ion implantation was used as the initial semiconductor layer.

[0013] In some optional embodiments of this application, a metal-induced crystallization process is employed to crystallize the amorphous semiconductor material of the initial semiconductor layer into a crystalline state to form a semiconductor layer, thereby forming a channel region from the initial channel region and activating the doped impurities, including: A capping layer is fabricated and conformally covers the gate insulating layer and the initial semiconductor layer. The capping layer has a first via, the bottom of which exposes at least a portion of the first initial electrode region of the initial semiconductor layer. An induction layer is fabricated, and the induction layer covers at least a portion of the first initial polar region exposed by the first via, wherein the material of the induction layer includes metal; A first heat treatment is performed to form metal silicides from the amorphous silicon material in at least a portion of the first initial polar region covered by the induced layer; A second heat treatment is performed to crystallize the remaining amorphous silicon of the initial semiconductor layer into monocrystalline or polycrystalline silicon using metal silicide as a template, thereby forming a semiconductor layer and activating the doped impurities; the first initial electrode region, the initial channel region, and the second initial electrode region of the initial semiconductor layer form the first electrode region, the channel region, and the second electrode region of the semiconductor layer, respectively.

[0014] In some optional embodiments of this application, at least one of the following is included: The first heat treatment includes annealing at 350°C to 450°C for 10 min to 60 min, so that the metal of the inducing layer reacts with the amorphous silicon of at least a portion of the first initial polar region covered by the inducing layer to form metal silicide. The second heat treatment includes: metal-induced crystallization annealing at 500℃-575℃ for 12h-24h, which causes the unreacted amorphous silicon of the initial semiconductor layer to crystallize into single-crystal silicon using metal silicide as a template, and activates the doped impurities to form a semiconductor layer.

[0015] In some optional embodiments of this application, a stacked structure is fabricated on one side of the substrate, including: A first initial insulating layer and an initial gate are sequentially and alternately fabricated on one side of the substrate to form an initial stacked structure; The initial stacked structure is patterned to form a first insulating layer and a gate that alternate sequentially, as the stacked structure.

[0016] In some optional embodiments of this application, after fabricating the semiconductor layer, the following steps are also included: A second insulating layer is fabricated and made to cover the first transistor; A second via is formed by patterning, penetrating the second insulating layer, with the bottom of the second via exposing the end of the semiconductor layer away from the substrate; A first electrode plate, a capacitor dielectric layer, and a second electrode plate are sequentially fabricated within the second through hole to form a capacitor. The first electrode plate conformally covers the inner wall and bottom of the second through hole, exposing the semiconductor layer. The capacitor dielectric layer conformally covers the first electrode plate, and the second electrode plate conformally covers the capacitor dielectric layer and fills the second through hole.

[0017] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, a substrate is used to support a first transistor. The channel region of the first transistor extends along a direction perpendicular to the substrate, which reduces the area occupied by the channel region in a horizontal plane parallel to the substrate. This allows for the fabrication of more channel regions within a limited area of ​​the horizontal plane, thereby improving integration density and storage density, and facilitating miniaturization. The channel region corresponds to at least two gates of the first transistor, respectively, so that each gate can be used to control the first transistor to turn on or off, improving gate control capability and efficiency. A gate insulating layer is disposed between all the gates of the first transistor and the semiconductor layer, electrically isolating the gates from the semiconductor layer. All the gates of the first transistor are sequentially spaced along a direction perpendicular to the substrate, forming a segmented gate structure. Using a segmented gate structure can reduce the drain electric field, reduce the gate-induced drain leakage current, increase the hold time, and reduce the refresh frequency.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application; Figures 2 to 12 This is a schematic diagram of the structure of a semiconductor structure fabrication method provided in this application at different processes; Figure 13 This is a schematic diagram of a circuit structure for a semiconductor structure provided in an embodiment of this application; Figure 14This is a schematic diagram of the structure of a storage device provided in an embodiment of this application; Figure 15 This is a schematic diagram of the circuit structure of a storage device provided in an embodiment of this application.

[0020] Figure label: 1000 - Memory device; 100 - Semiconductor structure; 10 - Substrate; 20 - First transistor; 21 - Gate; 211 - Initial gate; 22 - Semiconductor layer; 221 - Channel region; 222 - First electrode region; 223 - Second electrode region; 23 - Gate insulating layer; 24 - Initial semiconductor layer; 241 - Initial channel region; 246 - First initial electrode region of the initial semiconductor layer; 247 - Second initial electrode region of the initial semiconductor layer; 242 - Amorphous silicon thin film; 243 - Amorphous silicon film layer; 244 - First initial electrode region of the amorphous silicon film layer; 245 - Second initial electrode region of the amorphous silicon film layer; 2 5-Cover layer; 251-First via; 26-Inducing layer; 261-Metal silicide; 27-Second insulating layer; 271-Second via; 30-Capacitor; 31-First electrode; 311-Opening; 312-Inner cavity; 32-Capacitor dielectric layer; 33-Second electrode; 40-Insulating structure; 41-Isolation layer; 42-First insulating layer; 421-First initial insulating layer; 50-Layered structure; 51-Initial layered structure; 200-Bit line; 201-First interconnect structure; 300-Word line; 301-Second interconnect structure; 400-Peripheral logic circuit; 500-Electronic plate line. Detailed Implementation

[0021] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0022] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0024] Traditional 1T1C (1 Transistor 1 Capacitor) DRAM (Dynamic Random Access Memory) technology nodes are currently facing miniaturization bottlenecks, and stackable 3D (3 Dimension) DRAM is the research hotspot for future DRAM technology.

[0025] Monolithic 3D integration technology is an advanced semiconductor manufacturing technology. Traditional semiconductor processes, mainly based on silicon, are represented by 3D V-cache (3D vertical cache), which are usually based on advanced bonding technology, but suffer from limited integration density and high cost.

[0026] The related technology discloses a 1T1C DRAM structure and fabrication method, in which the access transistor uses an IGZO (Indium Gallium Zinc Oxide) transistor. However, IGZO transistors suffer from poor reliability and low on-state current.

[0027] The semiconductor structure, its fabrication method, storage device, and electronic device provided in this application are intended to solve at least one of the above-mentioned technical problems in the related art.

[0028] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0029] This application provides a semiconductor structure 100, the schematic diagram of which is shown below. Figure 12 As shown, the circuit structure diagram is as follows: Figure 13 As shown, the semiconductor structure 100 includes a first transistor 20 disposed on one side of the substrate 10; the first transistor 20 includes at least two gates 21, a semiconductor layer 22 and a gate insulating layer 23, the at least two gates 21 are sequentially spaced apart along a direction perpendicular to the substrate 10; the semiconductor layer 22 has a channel region 221 extending along a direction perpendicular to the substrate 10 and corresponding to the at least two gates 21 respectively; the gate insulating layer 23 is disposed between the at least two gates 21 and the semiconductor layer 22.

[0030] In this embodiment, the substrate 10 is used to support the first transistor 20. The channel region 221 of the first transistor 20 extends along a direction perpendicular to the substrate 10, which reduces the area occupied by the channel region 221 in a horizontal plane parallel to the substrate 10. This allows for the fabrication of more channel regions 221 within a limited area of ​​the horizontal plane, thereby improving integration density and storage density, and facilitating miniaturization. The channel region 221 corresponds to at least two gates 21 of the first transistor 20 (i.e., all gates 21 of the first transistor 20), so that each gate 21 can be used to control the opening or closing of the first transistor 20, improving gate control capability and efficiency. A gate insulating layer 23 is disposed between all gates 21 of the first transistor 20 and the semiconductor layer 22, electrically isolating the gates 21 from the semiconductor layer 22. All gates 21 of the first transistor 20 are sequentially spaced along a direction perpendicular to the substrate 10, forming a segmented gate structure. This segmented gate structure can reduce the drain electric field, reduce gate-induced drain leakage current (GIDL), increase hold time, and reduce refresh frequency.

[0031] Optionally, such as Figure 12 As shown in the embodiment of this application, the first transistor 20 includes two gates 21, which are arranged sequentially at intervals along a direction perpendicular to the substrate 10 to form a discrete dual-gate structure.

[0032] It should be noted that, in the embodiments of this application, the channel region 221 corresponds to at least two gates 21 respectively, meaning that on a vertical plane perpendicular to the substrate 10, the orthographic projection of the channel region 221 intersects with the orthographic projection of at least two gates 21 respectively.

[0033] In some optional embodiments of this application, the material of semiconductor layer 22 includes a crystalline semiconductor material. The material of channel region 221 includes a crystalline semiconductor material, which makes channel region 221 have high carrier mobility and velocity, low impedance, and can improve the read / write efficiency of semiconductor structure, reduce gate resistance, improve transistor operating performance, and reduce power consumption.

[0034] Optionally, in this embodiment, the semiconductor layer 22 is made of polycrystalline silicon, monocrystalline silicon, or quasi-monocrystalline silicon crystallized using a metal-induced crystallization process. The channel region 221 is made of polycrystalline silicon, monocrystalline silicon, or quasi-monocrystalline silicon crystallized using a metal-induced crystallization process. The first transistor 20 is a crystalline silicon transistor.

[0035] In some optional embodiments of this application, such as Figure 12As shown, the semiconductor layer 22 also includes a first polar region 222 and a second polar region 223. The first polar region 222 is connected to the end of the channel region 221 near the substrate 10 and extends in a direction parallel to the substrate 10. The second polar region 223 is connected to the end of the channel region 221 away from the substrate 10 and extends in a direction parallel to the substrate 10. The second polar region 223 is located on the side of the gate 21 away from the substrate 10. The doping concentration of the first polar region 222 and the second polar region 223 is greater than the doping concentration of the channel region 221.

[0036] Optionally, in this embodiment, the first electrode region 222 serves as one of the source and drain of the first transistor 20, and the second electrode region 223 serves as the other of the source and drain of the first transistor 20.

[0037] In this embodiment, the doping concentration of the first electrode region 222 and the second electrode region 223 is greater than the doping concentration of the channel region 221. That is, the doping concentration of the channel region 221 is less than the doping concentration of the source and drain. This can reduce the source and drain resistance, increase the carrier velocity, improve the read and write efficiency of the semiconductor structure, improve the working performance of the transistor, and reduce energy consumption.

[0038] Optionally, in this embodiment, the materials of the first electrode region 222 and the second electrode region 223 respectively include crystalline semiconductor materials. Optionally, the materials of the first electrode region 222 and the second electrode region 223 respectively include polycrystalline silicon, monocrystalline silicon, or quasi-monocrystalline silicon crystallized using a metal-induced crystallization process.

[0039] In some optional embodiments of this application, such as Figure 12 As shown, the channel region 221 at least partially surrounds the outer periphery of the gate 21.

[0040] In this embodiment, in the circumferential direction of each gate 21, the channel region 221 surrounds part of the outer periphery of each gate 21 or surrounds the entire outer periphery of each gate 21, so as to increase the area of ​​the gate 21 corresponding to the channel region 221 and improve the gate control capability.

[0041] In some optional embodiments of this application, such as Figure 12 As shown, the semiconductor structure 100 also includes a capacitor 30 disposed on the side of the first transistor 20 away from the substrate 10, and the second electrode region 223 of the semiconductor layer 22 is electrically connected to the first electrode plate 31 of the capacitor 30, serving as a storage cell.

[0042] In this embodiment, the first transistor 20 and the capacitor 30 are electrically connected to form a 1T1C memory cell.

[0043] In some optional embodiments of this application, such as Figure 12As shown, capacitor 30 includes a first electrode 31, a capacitor dielectric layer 32, and a second electrode 33 arranged sequentially. The capacitor dielectric layer 32 is disposed between the first electrode 31 and the second electrode 33, thereby electrically isolating the first electrode 31 and the second electrode 33.

[0044] In some optional embodiments of this application, such as Figure 12 As shown, the first electrode 31 is electrically connected to the second electrode region 223 of the semiconductor layer 22. Optionally, the first electrode region 222 is the drain electrode, and the second electrode region 223 is the source electrode.

[0045] Optionally, such as Figure 12 As shown, this application embodiment provides a 1T1C memory cell, which includes a first transistor 20 and a capacitor 30. The channel region 221 is made of polycrystalline silicon, single-crystal silicon, or quasi-single-crystal silicon formed by metal-induced crystallization. The first transistor 20 is a crystalline silicon transistor with a discrete dual-gate structure and a vertical channel region. The source of the crystalline silicon transistor is electrically connected to one of the plates (specifically the first plate 31) of the capacitor 30.

[0046] In some optional embodiments of this application, such as Figure 11 and Figure 12 As shown, the first electrode plate 31 is cylindrical with one end open 311, and the opening 311 faces away from the substrate 10. The capacitor dielectric layer 32 is shaped to cover the inner wall of the first electrode plate 31. The second electrode plate 33 is shaped to cover the capacitor dielectric layer 32 and fill the inner cavity 312 of the first electrode plate 31.

[0047] This arrangement increases the area of ​​the first electrode plate 31 and the second electrode plate 33, thereby increasing the capacitance and improving the charge carrying capacity of the capacitor 30.

[0048] Of course, in some other optional embodiments of this application, the semiconductor structure 100 may also include a second transistor disposed on the side of the first transistor 20 away from the substrate 10, the second transistor including at least one gate, and the second polar region 223 of the semiconductor layer 22 electrically connected to one of the gates of the second transistor, as a memory cell.

[0049] In this embodiment of the application, the first transistor 20 and the second transistor are electrically connected to form a 2T0C (2 Transistor 0 Capacitor, two transistors without capacitors) memory cell.

[0050] Optionally, in this embodiment, the second transistor may have the same or similar structure as the first transistor 20. In this case, the second transistor has at least two gates, and one of the at least two gates of the second transistor is electrically connected to the second electrode region 223 of the first transistor 20. Alternatively, the second transistor may also have the same or similar structure as conventional transistors in the art. In this case, the second transistor has one gate, and this gate of the second transistor is electrically connected to the second electrode region 223 of the first transistor 20. The specific structure of the second transistor will not be described in detail here.

[0051] The semiconductor structure of this application embodiment can be applied to DRAM, such as forming 1T1C DRAM, 2T0C DRAM, etc., and further, it can be applied to wafer-level three-dimensional integration solutions.

[0052] Based on the same inventive concept, this application provides a storage device 1000, the structural schematic diagram of which is shown below. Figure 14 As shown, the circuit structure diagram is as follows: Figure 15 As shown, the memory device 1000 includes: a semiconductor structure 100 as described above, a plurality of bit lines 200, and a plurality of word lines 300.

[0053] Bit line 200 is electrically connected to one end of semiconductor layer 22 of semiconductor structure 100 near substrate 10; word line 300 is electrically connected to gate 21 of first transistor 20 of semiconductor structure 100; peripheral logic circuit 400 is disposed on substrate 10.

[0054] In this embodiment, the word line 300 is electrically connected to the gate 21 of the first transistor 20, and the voltage signal on the word line 300 can control the first transistor 20 to turn on or off; the bit line 200 is electrically connected to one end of the semiconductor layer 22 of the first transistor 20, and data information can be written through the semiconductor layer 22 via the bit line 200 for storage, or data information can be read through the semiconductor layer 22 via the bit line 200.

[0055] In this embodiment, the word line 300 is electrically connected to all the gates 21 of the first transistor 20, and the first transistor 20 can be turned on or off simultaneously by all the gates 21 of the first transistor 20, which can improve gate control capability and efficiency.

[0056] Optionally, such as Figure 14 As shown in the embodiment of this application, bit line 200 is electrically connected to the first pole region 222.

[0057] In some optional embodiments of this application, such as Figure 14 and Figure 15As shown, the memory device 1000 includes multiple bit lines (BL) 200, multiple word lines (WL) 300, and multiple memory cells arranged in an array, each memory cell including a first transistor 20.

[0058] In some optional embodiments of this application, such as Figure 14 As shown, the storage cell also includes a capacitor 30. The second electrode region 223 of the first transistor 20 is electrically connected to the first electrode plate 31 of the capacitor 30, so that the first transistor 20 and the capacitor 30 form a 1T1C storage cell.

[0059] Of course, in some alternative embodiments of this application, the memory cell may include a second transistor, and the second pole region 223 of the first transistor 20 may be electrically connected to a gate of the second transistor, so that the first transistor 20 and the second transistor form a 2TOC memory cell.

[0060] Optionally, such as Figure 15 As shown in the embodiment of this application, multiple memory cells are arrayed in a horizontal plane parallel to the substrate 10.

[0061] In some optional embodiments of this application, such as Figure 15 As shown, the first transistors 20 of several memory cells located in the same row share a bit line (BL) 200.

[0062] This configuration reduces the number of bit lines (BL) 200, which is beneficial for layout design, reduces the area occupied by bit lines (BL) 200, facilitates miniaturization, and improves device density and integration.

[0063] In some optional embodiments of this application, such as Figure 15 As shown, the first transistors 20 of several memory cells located in the same column share a word line (WL) 300.

[0064] This configuration reduces the number of word lines (WL) 300, which is beneficial for layout design, reduces the area occupied by word lines (WL) 300, facilitates miniaturization, and improves device density and integration. A single word line 300 can simultaneously control the first transistors 20 of several memory cells located in the same column, improving operational efficiency.

[0065] In some optional embodiments of this application, the storage device 1000 may further include a peripheral logic circuit 400 disposed on the substrate 10, and a first transistor 20 disposed on one side of the substrate 10. The peripheral logic circuit 400 and the first transistor 20 are stacked on the substrate 10 to achieve a three-dimensional integration effect of the storage device 1000.

[0066] In some optional embodiments of this application, such as Figure 14 As shown, the storage device 1000 also includes a plate line 500, which is electrically connected to the second plate 33 of the capacitor 30.

[0067] Optionally, such as Figure 15 As shown in the embodiment of this application, the memory device 1000 includes multiple plate lines (PLs) 500, and the first transistors 20 of several memory cells located in the same row share a single plate line (PL) 500. This reduces the number of plate lines (PLs) 500, which is beneficial for layout design, reduces the area occupied by the plate lines (PLs) 500, and facilitates miniaturization, thereby increasing device density and integration.

[0068] Optionally, such as Figure 12 and Figure 14 As shown in the embodiment of this application, the isolation layer 41, the first insulating layer 42, the cover layer 25, and the second insulating layer 27 form an insulating structure 40. The insulating structure 40 fills between each effective component of the memory device 1000 (effective components include, for example, the gate 21 of the first transistor 20, the semiconductor layer 22, the capacitor 30, and various interconnect structures, etc.) to electrically isolate each effective component.

[0069] The storage devices in this application embodiment can be applied to wafer-level three-dimensional integration solutions such as 1T1C DRAM or 2T0C DRAM.

[0070] It should be noted that the storage device in the embodiments of this application includes the semiconductor structure of the embodiments of this application. Therefore, the storage device in the embodiments of this application also has the above-mentioned beneficial effects of the semiconductor structure of the embodiments of this application, which will not be repeated here.

[0071] In some optional embodiments of this application, the storage device can be random access memory, specifically static random access memory or dynamic random access memory, and of course, it can also be flash memory, etc.

[0072] Based on the same inventive concept, this application provides a method for fabricating a semiconductor structure, the process flow diagram of which is shown below. Figure 1 As shown, schematic diagrams of the semiconductor structure fabrication method at different stages are illustrated below. Figures 2 to 12 As shown, the method for fabricating this semiconductor structure includes: S101. A stacked structure 50 is formed on one side of the substrate 10. The stacked structure 50 has at least two gates 21 that are spaced apart sequentially along a direction perpendicular to the substrate 10.

[0073] S102, Fabricate a gate insulating layer 23 covering at least two gates 21 and the substrate 10.

[0074] S103. Fabricate a semiconductor layer 22 such that the semiconductor layer 22 covers at least a portion of the gate insulating layer 23 and has a channel region 221 extending in a direction perpendicular to the substrate 10 and corresponding to at least two gates 21 respectively; the at least two gates 21, the semiconductor layer 22 and the gate insulating layer 23 form a first transistor 20.

[0075] In this embodiment, at least two gates 21 are formed on one side of the substrate 10, followed by the formation of a gate insulating layer 23 and a semiconductor layer 22 to form a first transistor 20. The substrate 10 serves as a support for the first transistor 20.

[0076] At least two gates 21 are sequentially spaced along a direction perpendicular to the substrate 10 to form a gate-splitting structure. The gate-splitting structure can reduce the drain electric field, reduce the gate-induced drain leakage current (GIDL), increase the hold time, and reduce the refresh frequency.

[0077] The fabricated gate insulating layer 23 covers at least two gates 21, and the fabricated semiconductor layer 22 covers at least part of the gate insulating layer 23. The gate 21 and the semiconductor layer 22 can be electrically isolated through the gate insulating layer 23.

[0078] The fabricated semiconductor layer 22 has a channel region 221 extending in a direction perpendicular to the substrate 10. This reduces the area occupied by the channel region 221 in a horizontal plane parallel to the substrate 10, allowing more channel regions 221 to be fabricated within a limited area of ​​the horizontal plane. This improves integration density and storage density, facilitating miniaturization. Furthermore, the fabricated channel region 221 corresponds to at least two fabricated gates 21, enabling each gate 21 to control the opening or closing of the first transistor 20, thus improving gate control capability and efficiency.

[0079] In some optional embodiments of this application, such as Figure 2 and Figure 3 As shown, a stacked structure 50 is fabricated on one side of the substrate 10, including: like Figure 2 As shown, a first initial insulating layer 421 and an initial gate 211 are sequentially and alternately fabricated on one side of the substrate 10 to form an initial stacked structure 51.

[0080] Optionally, the first initial insulating layer 421 and the initial gate 211 can be sequentially and alternately fabricated using a deposition process. Optionally, the material of the first initial insulating layer 421 includes, but is not limited to, SiO2. The material of the initial gate 211 includes, but is not limited to, TiN, Poly (polycrystalline silicon), etc.

[0081] Optionally, such as Figure 2As shown in the embodiment of this application, before fabricating the initial stacked structure 51 on one side of the substrate 10, the method for fabricating the semiconductor structure further includes: fabricating an isolation layer 41 on one side of the substrate 10, the isolation layer 41 covering the substrate 10. The initial stacked structure 51 is fabricated on the side of the isolation layer 41 away from the substrate. The isolation layer 41 can be used to electrically isolate the substrate 10 and the gate 21, avoiding electrical connection between the substrate 10 and the gate 21 and causing interference.

[0082] Optionally, in this embodiment, the material of the isolation layer 41 includes, but is not limited to, SiO2.

[0083] Next, as Figure 3 As shown, the initial stacked structure 51 is patterned to form a first insulating layer 42 and a gate 21 that alternate sequentially, as the stacked structure 50.

[0084] Optionally, the initial stacked structure 51 can be patterned by etching process to remove the initial stacked structure 51 located outside the region corresponding to the gate to be formed, and the remaining initial stacked structure 51 (i.e. the initial stacked structure 51 located within the region to be formed) forms the stacked structure 50, wherein the remaining first initial insulating layer 421 forms the first insulating layer 42, and the remaining initial gate 211 forms the gate 21.

[0085] Optionally, such as Figure 3 As shown in the embodiment of this application, two gates 21 are formed by the above process. These two gates 21 are distributed sequentially at intervals along a direction perpendicular to the substrate 10 to form a discrete dual-gate structure, which is used as the two back gates of the first transistor 20.

[0086] In some optional embodiments of this application, such as Figure 4 As shown, the gate insulating layer 23 is fabricated, including: An insulating material is deposited and conformally covers the stacked structure 50 and the substrate 10 to form a gate insulating layer 23.

[0087] Optionally, such as Figure 4 As shown in the embodiment of this application, the formed gate insulating layer 23 conformally covers the stacked structure 50 and the isolation layer 41.

[0088] Optionally, in this embodiment, the material of the gate insulating layer 23 includes, but is not limited to, SiO2.

[0089] In some optional embodiments of this application, such as Figures 4 to 9 As shown, the semiconductor layer 22 is fabricated, including: like Figures 4 to 6As shown, an initial semiconductor layer 24 is formed on the side of the gate insulating layer 23 away from the substrate 10. The material of the initial semiconductor layer 24 is an amorphous semiconductor material. At least a portion of the initial semiconductor layer 24 is doped. The initial semiconductor layer 24 has an initial channel region 241 extending in a direction perpendicular to the substrate 10 and corresponding to at least two gates 21 respectively.

[0090] Optionally, the material of the initial semiconductor layer 24 includes, but is not limited to, amorphous silicon.

[0091] Next, as Figures 7 to 9 As shown, a metal-induced crystallization process is used to crystallize the amorphous semiconductor material of the initial semiconductor layer 24 into a crystalline state to form the semiconductor layer 22, the initial channel region 241 forms the channel region 221, and the doped impurities are activated.

[0092] In this embodiment, a metal-induced crystallization process is employed, which can improve the uniformity and stability of large-area crystalline (single-crystal or polycrystalline) materials while obtaining an appropriate crystallization rate. Metal-induced crystallization technology has advantages such as simple process, enabling amorphous silicon thin films to crystallize in a short time, high efficiency, and producing single-crystal or polycrystalline silicon thin films with high mobility and low impedance.

[0093] In some optional embodiments of this application, such as Figures 4 to 6 As shown, an initial semiconductor layer 24 is formed on the side of the gate insulating layer 23 away from the substrate 10, including: like Figure 4 As shown, amorphous silicon material is deposited to form an amorphous silicon thin film 242 that conformally covers the gate insulating layer 23.

[0094] Next, as Figure 5 As shown, the amorphous silicon thin film 242 is patterned to form an amorphous silicon film layer 243, and the amorphous silicon film layer 243 has an initial channel region 241 that at least partially surrounds the outer periphery of the gate 21, a first initial electrode region 244 that is connected to the end of the initial channel region 241 near the substrate 10 and extends in a direction parallel to the substrate 10, and a second initial electrode region 245 that is connected to the end of the initial channel region 241 away from the substrate 10 and extends in a direction parallel to the substrate 10. The second initial electrode region 245 is located on the side of the gate 21 away from the substrate 10.

[0095] Optionally, the amorphous silicon thin film 242 can be patterned by etching to remove the amorphous silicon thin film 242 located outside the active region to be formed (including the regions corresponding to the channel region, source, and drain). The remaining amorphous silicon thin film 242 (i.e., the amorphous silicon thin film 242 located within the active region) forms an amorphous silicon film layer 243. The amorphous silicon film layer 243 located in the region corresponding to the channel region forms an initial channel region 241, the amorphous silicon film layer 243 located in the region corresponding to the drain region forms a first initial electrode region 244, and the amorphous silicon film layer 243 located in the region corresponding to the source region forms a second initial electrode region 245.

[0096] Next, as Figure 6 As shown, a self-aligned process is used to implant ions into the first initial polar region 244 and the second initial polar region 245, and the amorphous silicon film layer 243 after ion implantation serves as the initial semiconductor layer 24.

[0097] The first initial electrode region 244 and the second initial electrode region 245 are doped by ion implantation, that is, the source and drain to be formed are doped.

[0098] Optionally, in this embodiment, a self-aligned process is used to implant phosphorus ions into the first initial electrode region 244 and the second initial electrode region 245. Optionally, the phosphorus ion implantation energy is 5 keV to 10 keV, and the phosphorus ion implantation dose is 3 × 10⁻⁶. 15 cm -2 .

[0099] It should be noted that, as Figure 5 and Figure 6 As shown in the embodiments of this application, the first initial polar region 244 of the amorphous silicon film layer 243 is the first initial polar region before ion implantation (e.g., Figure 5 As shown), the second initial polar region 245 of the amorphous silicon film 243 is the second initial polar region before ion implantation (as shown). Figure 5 (As shown). After ion implantation, the first initial polar region 244 of the amorphous silicon film 243 forms the first initial polar region 246 of the initial semiconductor layer 24, and the second initial polar region 245 of the amorphous silicon film 243 forms the second initial polar region 247 of the initial semiconductor layer 24. That is, the first initial polar region 246 is the first initial polar region after ion implantation (as shown). Figure 6 As shown), the second initial polar region 247 is the second initial polar region after ion implantation (as shown). Figure 6 (As shown).

[0100] In some optional embodiments of this application, such as Figures 7 to 9 As shown, a metal-induced crystallization process is used to crystallize the amorphous semiconductor material of the initial semiconductor layer 24 into a crystalline state to form the semiconductor layer 22, the initial channel region 241 forms the channel region 221, and the doped impurities are activated, including: like Figure 7 As shown in the embodiment of this application, a cover layer 25 is fabricated and conformally covers the gate insulating layer 23 and the initial semiconductor layer 24. The cover layer 25 has a first via 251, and the bottom of the first via 251 exposes at least a portion of the first initial electrode region 246 of the initial semiconductor layer 24.

[0101] Optionally, in this embodiment, the material of the capping layer 25 includes, but is not limited to, SiO2. SiO2 can be deposited and etched to form the capping layer 25 and the first via 251, which defines a metal-induced contact window.

[0102] Next, as Figure 7 As shown, an induction layer 26 is fabricated and at least partially covers the first initial polar region 246 exposed by the first via 251. The material of the induction layer 26 includes metal.

[0103] Optionally, the metal includes nickel (Ni). Ni can be deposited to form the induced layer 26. In other embodiments, the metal may also be other metallic materials such as aluminum (Al), copper (Cu), and cobalt (Co), and this application is not limited thereto.

[0104] Next, as Figure 8 As shown, a first heat treatment is performed to form a metal silicide 261 on at least a portion of the amorphous silicon material covered by the induced layer 26 in the first initial polar region 246.

[0105] Optionally, the first heat treatment includes annealing at 350°C to 450°C for 10 min to 60 min, so that the metallic nickel of the inducing layer 26 reacts with the amorphous silicon of the first initial electrode region 246 to form nickel silicide.

[0106] In this embodiment of the application, annealing within the specified temperature and time range enables amorphous silicon to react with nickel to form NiSi2. The lattice mismatch between NiSi2 and single-crystal silicon is minimal, resulting in the highest induced crystal quality.

[0107] Next, as Figure 9 As shown, a second heat treatment is performed to crystallize the remaining amorphous silicon of the initial semiconductor layer 24 into monocrystalline silicon or polycrystalline silicon using metal silicide 261 as a template, so as to form semiconductor layer 22 and activate the doped impurities; the first initial electrode region 246, the initial channel region 241 and the second initial electrode region 247 of the initial semiconductor layer 24 respectively form the first electrode region 222, the channel region 221 and the second electrode region 223 of semiconductor layer 22.

[0108] Optionally, in this embodiment of the application, after the first heat treatment and before the second heat treatment, the process further includes: removing the inducing layer 26 that has not reacted with the amorphous silicon material of the first initial electrode region 246. After the metallic nickel of the inducing layer 26 reacts with the amorphous silicon of the first initial electrode region 246 to form nickel silicide, the unreacted inducing layer 26 is removed, that is, the unreacted metallic nickel is removed.

[0109] In some optional embodiments of this application, a second heat treatment is performed, including: metal-induced crystallization annealing at 500°C-575°C for 12-24 hours, so that the remaining amorphous silicon of the initial semiconductor layer 24 crystallizes into single-crystal silicon and activates the doped impurities to form the semiconductor layer 22.

[0110] In this embodiment, during the annealing process, the amorphous silicon of the initial semiconductor layer 24 crystallizes into monocrystalline silicon or near-monocrystalline silicon using the NiSi2 crystal phase as a template, and the previously implanted phosphorus impurities are also electrically activated. Crystallization and impurity activation can be achieved simultaneously through a single annealing process, reducing preparation time and manufacturing costs.

[0111] After metal-induced crystallization annealing, the first initial electrode region 246, the initial channel region 241, and the second initial electrode region 247 of the initial semiconductor layer 24 form the first electrode region 222, the channel region 221, and the second electrode region 223 of the semiconductor layer 22, respectively. Since NiSi2 has a face-centered cubic (FCC) structure, which is extremely close to the lattice structure of single-crystal silicon with a lattice mismatch of only 0.4%, it can be considered that amorphous silicon crystallizes into a near-single-crystal silicon. Figure 9 As shown, metal silicide 261 (i.e. NiSi2) is part of the first pole region 222.

[0112] In some optional embodiments of this application, such as Figures 10 to 12 As shown, after fabricating semiconductor layer 22, the process also includes: like Figure 10 As shown, a second insulating layer 27 is fabricated and covers the first transistor 20. The second insulating layer 27 fills the first via 251 and covers the cover layer 25.

[0113] Optionally, the material of the second insulating layer 27 includes, but is not limited to, SiO2.

[0114] Next, as Figure 10 As shown, a second via 271 is formed by patterning through the second insulating layer 27, and the bottom of the second via 271 exposes the end of the semiconductor layer 22 away from the substrate 10.

[0115] Optionally, such as Figure 10As shown in the embodiment of this application, the bottom of the second through hole 271 exposes the second electrode region 223 of the semiconductor layer 22 so that the first electrode plate 31 of the subsequently formed capacitor 30 is electrically connected to the second electrode region 223.

[0116] Next, as Figure 11 and Figure 12 As shown, a first electrode 31, a capacitor dielectric layer 32, and a second electrode 33 are sequentially fabricated within the second through hole 271 to form a capacitor 30. The first electrode 31 conformally covers the inner wall of the second through hole 271 and the semiconductor layer 22 exposed at the bottom. The capacitor dielectric layer 32 conformally covers the first electrode 31. The second electrode 33 conformally covers the capacitor dielectric layer 32 and fills the second through hole 271.

[0117] In this embodiment, the first electrode 31 conformally covers the inner wall of the second through hole 271 and the exposed semiconductor layer 22 at the bottom, so that the first electrode 31 is formed into a cylindrical shape with one end open. The capacitor dielectric layer 32 and the second electrode 33 sequentially conformally cover the first electrode 31, and the second electrode 33 fills the second through hole 271, which can increase the area of ​​the first electrode 31 and the second electrode 33, thereby increasing the capacitance and improving the charge carrying capacity of the capacitor 30.

[0118] Optionally, the materials of the first electrode 31 and the second electrode 33 are, but not limited to, metals, and the material of the capacitor dielectric layer 32 is, but not limited to, dielectric materials.

[0119] In this embodiment, capacitor 30 and first transistor 20 form a 1T1C memory cell. This embodiment proposes a method for fabricating a 1T1C memory cell structure of a crystalline silicon transistor based on a low-cost metal-induced process, which can be applied to DRAM.

[0120] It should be noted that the semiconductor structure preparation method provided in the embodiments of this application can be used to prepare the semiconductor structure of the embodiments of this application. Therefore, the semiconductor structure of the embodiments of this application also has the above-mentioned beneficial effects of the semiconductor structure preparation method provided in the embodiments of this application, which will not be repeated here.

[0121] Based on the same inventive concept, embodiments of this application provide a method for fabricating a memory device, which includes: the method for fabricating a semiconductor structure as described above.

[0122] In some optional embodiments of this application, such as Figure 2 As shown, before fabricating the stacked structure 50 on one side of the substrate 10, the method for fabricating the memory device further includes: providing an initial substrate and fabricating a peripheral logic circuit 400 on the initial substrate to obtain the substrate 10.

[0123] In this embodiment, after the peripheral logic circuit 400 is fabricated using conventional CMOS (Complementary Metal Oxide Semiconductor) technology, the semiconductor structure fabrication method provided in this embodiment is then executed (i.e., the fabrication of the stacked structure 50 and subsequent steps are performed, as described above, and will not be repeated here).

[0124] In some optional embodiments of this application, such as Figure 14 As shown, after fabricating the semiconductor layer 22, the method for fabricating the memory device further includes: fabricating a first interconnect structure 201 that is electrically connected to one end of the semiconductor layer 22 near the substrate 10, the first interconnect structure 201 being used for electrical connection with the bit line 200.

[0125] Optionally, such as Figure 12 and Figure 14 As shown in the embodiment of this application, after the capacitor 30 is fabricated, the first interconnect structure 201 is fabricated, and the first polar region 222 of the semiconductor layer 22 is electrically connected to the bit line 200 through the first interconnect structure 201.

[0126] In some optional embodiments of this application, such as Figure 14 As shown, after fabricating the semiconductor layer 22, the method for fabricating the memory device further includes: fabricating a second interconnect structure 301 that is electrically connected to the gate 21 of the first transistor 20, the second interconnect structure 301 being used to be electrically connected to the word line 300.

[0127] Optionally, such as Figure 12 and Figure 14 As shown in the embodiment of this application, after the capacitor 30 is fabricated, the second interconnect structure 301 is fabricated, and the two gates 21 of the first transistor 20 are electrically connected to the word line 300 through the second interconnect structure 301.

[0128] In some optional embodiments of this application, such as Figure 14 As shown, after fabricating capacitor 30, the method for fabricating the memory device further includes: fabricating a third interconnect structure electrically connected to the second plate 33 of capacitor 30, the third interconnect structure being used to electrically connect to plate line 500, so that the second plate 33 is electrically connected to plate line 500 through the third interconnect structure.

[0129] Optionally, after completing the semiconductor structure fabrication method provided in the embodiments of this application, the interconnect structure can be fabricated according to conventional back-end processes in the art to realize the electrical connection between the various memory cell structures.

[0130] This application proposes a method for fabricating a 1T1C memory device based on a low-cost metal-induced process of crystalline silicon transistors, which is compatible with conventional CMOS back-end processes in the art and can be applied to DRAM.

[0131] It should be noted that the method for fabricating the memory device provided in the embodiments of this application includes the method for fabricating the semiconductor structure provided in the embodiments of this application. Therefore, the method for fabricating the memory device provided in the embodiments of this application also has the above-mentioned beneficial effects of the method for fabricating the semiconductor structure provided in the embodiments of this application, which will not be repeated here.

[0132] The method for preparing the storage device provided in this application can be used to prepare the storage device of this application. Therefore, the storage device of this application also has the above-mentioned beneficial effects of the method for preparing the storage device provided in this application, which will not be repeated here.

[0133] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: a semiconductor structure 100 as described above; or a semiconductor structure prepared by the semiconductor structure preparation method described above; or a memory device 1000 as described above; or a memory device prepared by the memory device preparation method described above.

[0134] It should be noted that, since the electronic devices of the embodiments of this application include the semiconductor structures of the embodiments of this application, or semiconductor structures prepared using the methods for preparing semiconductor structures of the embodiments of this application, or memory devices of the embodiments of this application, or memory devices prepared using the methods for preparing memory devices of the embodiments of this application, the electronic devices of the embodiments of this application also possess the aforementioned beneficial effects of the semiconductor structures of the embodiments of this application, or semiconductor structures prepared using the methods for preparing semiconductor structures of the embodiments of this application, or memory devices of the embodiments of this application, or memory devices prepared using the methods for preparing memory devices of the embodiments of this application. These advantages will not be elaborated upon here.

[0135] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include, for example, memory in a computer, and is not limited thereto.

[0136] By applying the embodiments of this application, at least the following beneficial effects can be achieved: In this embodiment, a substrate is used to support a first transistor. The channel region of the first transistor extends along a direction perpendicular to the substrate, which reduces the area occupied by the channel region in a horizontal plane parallel to the substrate. This allows for the fabrication of more channel regions within a limited area of ​​the horizontal plane, thereby improving integration density and storage density, and facilitating miniaturization. The channel region corresponds to at least two gates of the first transistor, respectively, so that each gate can be used to control the first transistor to turn on or off, improving gate control capability and efficiency. A gate insulating layer is disposed between all the gates of the first transistor and the semiconductor layer, electrically isolating the gates from the semiconductor layer. All the gates of the first transistor are sequentially spaced along a direction perpendicular to the substrate, forming a segmented gate structure. Using a segmented gate structure can reduce the drain electric field, reduce the gate-induced drain leakage current, increase the hold time, and reduce the refresh frequency.

[0137] In this embodiment, the material of the channel region includes polycrystalline silicon, monocrystalline silicon, or quasi-monocrystalline silicon crystallized by a metal-induced crystallization process, which makes the channel region have high carrier mobility and speed, low impedance, and can improve the read and write efficiency of the semiconductor structure, reduce the gate resistance, improve the working performance of the transistor, and reduce energy consumption.

[0138] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0139] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0140] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0141] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0142] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0143] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises a first transistor disposed on one side of a substrate, wherein the first transistor comprises: at least two gates, which are sequentially and spacedly arranged along a direction perpendicular to the substrate; a semiconductor layer, which has channel regions extending along a direction perpendicular to the substrate and corresponding to the at least two gates respectively; a gate insulating layer disposed between the at least two gates and the semiconductor layer.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure comprises at least one of the following: the material of the semiconductor layer comprises a crystalline semiconductor material; the semiconductor layer further comprises a first extreme region and a second extreme region, the first extreme region is connected to one end of the channel region close to the substrate and extends along a direction parallel to the substrate, the second extreme region is connected to one end of the channel region away from the substrate and extends along a direction parallel to the substrate, the second extreme region is located on the side of the gate away from the substrate, and the doping concentration of the first extreme region and the second extreme region is greater than that of the channel region; the channel region at least partially surrounds the outer periphery of the gate.

3. The semiconductor structure of claim 2, wherein, The semiconductor structure further comprises, on the side of the first transistor away from the substrate: a capacitor, the second extreme region of the semiconductor layer is electrically connected to a first plate of the capacitor, serving as a storage unit; or a second transistor comprising at least one gate, the second extreme region of the semiconductor layer is electrically connected to one gate of the second transistor, serving as a storage unit. When the semiconductor structure comprises a capacitor, the capacitor comprises a first plate, a capacitor dielectric layer and a second plate which are sequentially arranged; 4. The semiconductor structure of claim 3, wherein, the first plate is in the shape of a cylinder with one end open, the opening faces away from the substrate, the capacitor dielectric layer covers the inner wall of the first plate in a conformal manner, and the second plate covers the capacitor dielectric layer in a conformal manner and fills the inner cavity of the first plate. The semiconductor structure comprises:

5. A memory device, comprising: the semiconductor structure according to any one of claims 1 to 4, wherein the semiconductor structure comprises a plurality of storage units arranged in an array, and the storage units comprise first transistors; a plurality of bit lines, wherein the first transistors of a plurality of storage units in the same row share one bit line; a plurality of word lines, wherein the first transistors of a plurality of storage units in the same column share one word line. The semiconductor structure comprises:

6. An electronic device, comprising: the semiconductor structure according to any one of claims 1 to 4; or the memory device according to claim 5. The semiconductor structure comprises: forming a stack structure on one side of a substrate, wherein the stack structure has at least two gates sequentially and spacedly arranged along a direction perpendicular to the substrate; 7. A method of fabricating a semiconductor structure, characterized by, forming a gate insulating layer covering the stack structure and the substrate; forming a semiconductor layer, wherein the semiconductor layer covers at least part of the gate insulating layer and has channel regions extending along a direction perpendicular to the substrate and corresponding to the at least two gates respectively; the at least two gates, the semiconductor layer and the gate insulating layer form a first transistor. The semiconductor layer is formed by: forming an initial semiconductor layer on the side of the gate insulating layer away from the substrate, wherein the material of the initial semiconductor layer is amorphous semiconductor material, at least part of the initial semiconductor layer is doped, and the initial semiconductor layer has initial channel regions extending along a direction perpendicular to the substrate and corresponding to the at least two gates respectively; 8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: ​ ​ crystallizing amorphous semiconductor material of the initial semiconductor layer into a crystalline state to form the semiconductor layer, the initial channel region forms the channel region, and activates the doped impurities.

9. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: An initial semiconductor layer is formed on a side of the gate insulating layer away from the substrate, comprising: Depositing amorphous silicon material to form an amorphous silicon film conformally covering the gate insulating layer; Patterning the amorphous silicon film to form an amorphous silicon film layer, and making the amorphous silicon film layer have the initial channel region at least partially surrounding the outer periphery of the gate, a first initial electrode region connected to one end of the initial channel region close to the substrate and extending in a direction parallel to the substrate, and a second initial electrode region connected to one end of the initial channel region away from the substrate and extending in a direction parallel to the substrate, the second initial electrode region being on a side of the gate away from the substrate; Ion implantation is performed on the first initial electrode region and the second initial electrode region using a self-alignment process, and the amorphous silicon film layer after ion implantation serves as the initial semiconductor layer.

10. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: crystallizing amorphous semiconductor material of the initial semiconductor layer into a crystalline state to form the semiconductor layer, the initial channel region forms the channel region, and activates the doped impurities, comprising: forming a cover layer, and making the cover layer conformally cover the gate insulating layer and the initial semiconductor layer, the cover layer having a first through hole, the bottom of the first through hole exposing at least part of the first initial electrode region of the initial semiconductor layer; forming an induction layer, and making the induction layer cover at least part of the first initial electrode region exposed by the first through hole, the material of the induction layer comprising metal; performing a first heat treatment to form a metal silicide from amorphous silicon material of at least part of the first initial electrode region covered by the induction layer; performing a second heat treatment to crystallize remaining amorphous silicon of the initial semiconductor layer into single crystal silicon or polycrystalline silicon using the metal silicide as a template to form the semiconductor layer and activate the doped impurities; the first initial electrode region, the initial channel region, and the second initial electrode region of the initial semiconductor layer form the first electrode region, the channel region, and the second electrode region of the semiconductor layer, respectively.

11. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: comprising at least one of the following: performing a first heat treatment, comprising: performing an annealing treatment at 350-450°C for 10-60min to make the metal of the induction layer react with the amorphous silicon of at least part of the first initial electrode region covered by the induction layer to form a metal silicide; performing a second heat treatment, comprising: performing a metal-induced crystallization annealing treatment at 500-575°C for 12-24h to crystallize unreacted amorphous silicon of the initial semiconductor layer into single crystal silicon using the metal silicide as a template, and activate the doped impurities to form a semiconductor layer.

12. The method of claim 7 to 11, wherein forming a stack structure on a side of a substrate, comprising: forming a first initial insulating layer and an initial gate alternately on a side of the substrate to form an initial stack structure; The initial stack structure is patterned to form first insulating layers and the gate electrodes alternately, as the stack structure.

13. The method of producing a semiconductor structure according to any one of claims 7 to 11, wherein After the semiconductor layer is made, further comprising: a second insulating layer is made, covering the first transistor; a second via is formed by patterning, penetrating the second insulating layer, and exposing one end of the semiconductor layer away from the substrate at the bottom of the second via; a capacitor is formed by sequentially making a first plate, a capacitor dielectric layer, and a second plate in the second via, the first plate conformally covering the inner wall and the bottom of the second via and exposing the semiconductor layer, the capacitor dielectric layer conformally covering the first plate, and the second plate conformally covering the capacitor dielectric layer and filling the second via.

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