Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method forms a first anti-reflection layer to protect a first gate structure in a first area. After etching a second area to form grooves on both sides of a second gate structure, all the first anti-reflection layer is removed, first etching is performed to remove part of a hard mask layer on the top of the first gate structure, second etching is performed to remove a first insulating layer on a substrate of the first area, and part of the hard mask layer of the first gate structure is removed. The hard mask layer of the first gate structure is etched twice, so that the thickness of the hard mask layer of the first gate structure removed is close to the thickness of the hard mask layer of the second gate structure removed in the process of etching the second area to form the grooves, thereby reducing the height difference between the first gate structure and the second gate structure, and improving the gate height load effect caused by the process asymmetry of the second area etching to form the grooves.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In the manufacturing process of semiconductor devices, stress can change the bandgap and carrier mobility of silicon material. Therefore, by controlling stress, the carrier mobility can be increased, thereby increasing the drive current and improving the performance of transistors.

[0003] As semiconductor manufacturing process nodes continue to advance to 28 nanometers and more advanced levels, it is usually necessary to form an embedded silicon-germanium (Embedded SiGe) structure in the source / drain regions of PMOS transistors. The embedded SiGe structure can effectively improve hole mobility by introducing compressive strain into the channel region, thereby increasing the drive current of PMOS transistors. NMOS transistors, on the other hand, do not require the formation of an embedded SiGe structure.

[0004] The fabrication of PMOS transistors requires additional steps to form an embedded silicon-germanium structure, and these additional process steps may result in different heights between PMOS and NMOS transistors. Summary of the Invention

[0005] Therefore, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure to address the problems in the prior art.

[0006] In a first aspect, this application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0007] A substrate is provided, the substrate including a first region and a second region, the first region having a first gate structure formed thereon, and the second region having a second gate structure formed thereon, wherein the gate structure includes a hard mask layer disposed on top.

[0008] A first insulating layer is formed to cover the first gate structure, the second gate structure, and the exposed area of ​​the substrate;

[0009] A first anti-reflective layer is formed in the first region and filled between the first gate structures, wherein the top surface of the first anti-reflective layer is higher than the top surface of the first insulating layer;

[0010] The second region is etched to form grooves in the substrate on both sides of the second gate structure, while the first insulating layer on the top surface of the second gate structure and part of the hard mask layer of the second gate structure are removed.

[0011] Remove the first anti-reflective layer;

[0012] Perform a first etching to remove the first insulating layer exposed at the top of the first gate structure, and remove a portion of the hard mask layer at the top of the first gate structure;

[0013] A second etching is performed to remove the first insulating layer on the substrate in the first region, while also removing a portion of the hard mask layer of the first gate structure.

[0014] In one embodiment, after the second etching is performed, the thickness of the remaining hard mask layer of the first gate structure is substantially the same as the thickness of the remaining hard mask layer of the second gate structure.

[0015] In one embodiment, the hard mask layer includes a first sublayer and a second sublayer stacked sequentially in a direction away from the substrate, wherein the etching resistance of the first sublayer is greater than that of the second sublayer.

[0016] In one embodiment, prior to performing the first etching, the method further includes:

[0017] A second anti-reflective layer is formed in the first region and the second region, and a second photoresist layer is formed on the second anti-reflective layer, wherein the top surface of the second anti-reflective layer is higher than the top surface of the second gate structure;

[0018] The second anti-reflective layer of the first region is etched back, exposing a portion of the first insulating layer at the top of the first gate structure;

[0019] After the first etching is performed, the remaining second anti-reflective layer in the first region is removed, exposing the first insulating layer on the substrate in the first region.

[0020] In one embodiment, the step of etching back the second anti-reflective layer of the first region includes: etching back the second anti-reflective layer of the first region to a top surface that is lower than the top surface of the second sub-layer.

[0021] In one embodiment, the re-etching of the second anti-reflective layer in the first region includes: re-etching the second anti-reflective layer in the first region to a height where the top surface is lower than the bottom surface of the second sub-layer and higher than or equal to the bottom surface of the first sub-layer.

[0022] In one embodiment, the first etching removes at least a portion of the second sublayer from the first gate structure.

[0023] In one embodiment, after forming grooves in the substrates on both sides of the second gate structure, the method further includes: epitaxially growing a silicon-germanium layer in the grooves.

[0024] In one embodiment, the first region is an NMOS region and the second region is a PMOS region.

[0025] Secondly, this application provides a semiconductor structure prepared by the semiconductor structure preparation method described in the first aspect.

[0026] The semiconductor structure fabrication method and semiconductor structure of this application involve forming a first anti-reflection layer in a first region to protect a first gate structure, etching a second region to form grooves on both sides of the second gate structure, removing all of the first anti-reflection layer, performing a first etching to remove a portion of the hard mask layer at the top of the first gate structure, and performing a second etching to remove the first insulating layer on the substrate of the first region, while simultaneously removing a portion of the hard mask layer of the first gate structure. The hard mask layer of the first gate structure is etched twice so that the thickness of the hard mask layer removed from the first gate structure is close to the thickness of the hard mask layer removed from the second gate structure during the etching process of forming grooves in the second region. This reduces the height difference between the first and second gate structures, improves the gate height load effect caused by process asymmetry due to the etching process of forming grooves in the second region, and provides a more uniform starting surface for subsequent process steps that require planarization or are sensitive to morphology, which is beneficial to improving the uniformity and yield of device performance. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor structure provided in one embodiment;

[0029] Figure 2 This is a schematic diagram of the structure after the first insulating layer covers the first gate structure and the second gate structure, as provided in one embodiment.

[0030] Figure 3 This is a schematic diagram of the structure after the first anti-reflection layer is formed in the first region, as provided in one embodiment.

[0031] Figure 4 This is a schematic diagram of the structure after forming grooves in the substrates on both sides of the second gate structure and removing the first anti-reflection layer in one embodiment.

[0032] Figure 5 This is a schematic diagram of the structure after epitaxial growth of a silicon-germanium layer in a groove, as provided in one embodiment;

[0033] Figure 6 This is a schematic diagram of the structure after the second anti-reflection layer and the second photoresist layer are formed in the second region, as provided in one embodiment.

[0034] Figure 7 This is a schematic diagram of the structure after the second anti-reflection layer of the first region is etched back and the portion of the first insulating layer exposing the top of the first gate structure, provided in one embodiment.

[0035] Figure 8 This is a schematic diagram of the structure after removing the first insulating layer exposed at the top of the first gate structure in one embodiment;

[0036] Figure 9 This is a schematic diagram of the structure after removing a portion of the hard mask layer at the top of the first gate structure, as provided in one embodiment.

[0037] Figure 10 This is a schematic diagram of the structure after removing the remaining first anti-reflective layer of the first region in one embodiment;

[0038] Figure 11 This is a schematic diagram of the structure after performing the second etching in one embodiment;

[0039] Figure 12 This is a schematic diagram of the structure after removing the second anti-reflection layer and the second photoresist layer in the second region, as provided in one embodiment.

[0040] Explanation of reference numerals in the attached figures:

[0041] 11. Substrate; A1. First region; A2. Second region; 120. First gate structure; 220. Second gate structure; 21. Gate conductive layer; 22. Hard mask layer; 221. First sub-layer; 222. Second sub-layer; 23. Insulating sidewall; 31. First insulating layer; 32. First anti-reflection layer; 33. Second anti-reflection layer; 34. Second photoresist layer; 24. Trench; 25. Silicon-germanium layer. Detailed Implementation

[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0044] In semiconductor device fabrication, the gates of the PMOS and NMOS regions are fabricated together in the same process. However, after the gate is formed, photolithography and etching steps are required for the PMOS region to form grooves embedded in the substrate on both sides of the PMOS transistor gate, and to form an embedded germanium-silicon structure within the grooves. During the formation of the embedded germanium-silicon structure, the NMOS region is protected by photoresist or other masking materials. After the embedded germanium-silicon structure is formed in the PMOS region, photoresist or other masking materials are used to protect the PMOS region, and the isolation sidewalls of the NMOS region are etched to expose the substrate of the NMOS region.

[0045] However, the etching depth of the PMOS region's recesses is much greater than the etching depth of the isolation sidewalls in the NMOS region. This results in uneven consumption of the hard mask layer on top of the gates of both PMOS and NMOS transistors during the process. Consequently, the hard mask layer on top of the PMOS transistor gate is significantly thinned, while the hard mask layer on top of the NMOS transistor gate is relatively intact. This leads to a significant height difference between the gates of the PMOS and NMOS transistors, known as the gate height loading effect. This height difference continuously affects subsequent processes, such as the uniformity of chemical mechanical polishing (CMP), potentially causing uncontrollable variations in device dimensions and ultimately impacting the uniformity and yield of device performance.

[0046] Therefore, how to eliminate or mitigate the high gate load effect caused by the process differences between PMOS and NMOS transistors has become an urgent problem to be overcome for 28-nanometer and more advanced technology nodes.

[0047] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method for fabricating a semiconductor structure includes the following steps:

[0048] Step S101: Provide a substrate 11, which includes a first region A1 and a second region A2. A first gate structure 120 is formed on the first region A1, and a second gate structure 220 is formed on the second region A2. The gate structure includes a hard mask layer 22 disposed on the top.

[0049] Step S102: Form a first insulating layer 31 to cover the first gate structure 120, the second gate structure 220, and the exposed area of ​​the substrate 11.

[0050] Step S103: A first anti-reflection layer 32 is formed in the first region A1 and filled between the first gate structures 120. The top surface of the first anti-reflection layer 32 is higher than the top surface of the first insulating layer 31.

[0051] Step S104: Etch the second region A2 to form a groove 24 in the substrate 11 on both sides of the second gate structure 220, and at the same time remove the first insulating layer 31 on the top surface of the second gate structure 220 and part of the hard mask layer 22 of the second gate structure 220.

[0052] Step S105: Remove the first anti-reflective layer 32.

[0053] Step S106: Perform the first etching to remove the first insulating layer 31 exposed at the top of the first gate structure 120, and remove part of the hard mask layer 22 at the top of the first gate structure 120.

[0054] Step S107: Perform a second etching to remove the first insulating layer 31 on the substrate 11 of the first region A1, and at the same time remove part of the hard mask layer 22 of the first gate structure 120.

[0055] The semiconductor structure fabrication method of this embodiment involves forming a first anti-reflection layer 32 in the first region A1 to protect the first gate structure 120, etching the second region A2 to form grooves 24 on both sides of the second gate structure 220, removing all of the first anti-reflection layer 32, performing a first etching to remove a portion of the hard mask layer 22 at the top of the first gate structure 120, performing a second etching to remove the first insulating layer 31 on the substrate 11 of the first region A1, and simultaneously removing a portion of the hard mask layer 22 of the first gate structure 120; and performing a second etching on the hard mask layer 22 of the first gate structure 120. The etching process involves two etching operations to ensure that the thickness of the hard mask layer 22 of the first gate structure 120 removed is close to the thickness of the hard mask layer 22 of the second gate structure 220 removed during the etching of the second region A2 to form the groove 24. This reduces the height difference between the first gate structure 120 and the second gate structure 220, improves the gate height load effect caused by process asymmetry due to the etching of the second region A2 to form the groove 24, and provides a more uniform starting surface for subsequent process steps that require planarization or are sensitive to morphology. This is beneficial for improving the uniformity and yield of device performance.

[0056] Appendix Figures 2-12 This embodiment illustrates a schematic diagram of the semiconductor structure fabrication method. The following is a description of the process described in the appendix. Figures 2-12 The method for fabricating the semiconductor structure in this embodiment will be described.

[0057] In step S101, refer to Figure 2The substrate 11 can be a semiconductor substrate, and the material of the substrate 11 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. Dopant ions can also be implanted into the substrate 11 to change the electrical parameters according to design requirements. The substrate 11 can be a single-layer substrate or a multi-layer substrate.

[0058] The substrate 11 has isolation trenches (not shown in the figure) that divide the substrate 11 into multiple spaced active regions (not shown in the figure). Shallow trench isolation structures (not shown in the figure) are formed within the isolation trenches and are made of an insulating material for electrical insulation between different active regions. The material of the shallow trench isolation structure may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon percarbonoxide. For example, the shallow trench isolation structure may include a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer sequentially covering the trench walls.

[0059] Reference Figure 2 The substrate 11 includes a first region A1 and a second region A2. A first gate structure 120 on the first region A1 and a second gate structure 220 on the second region A2 are formed in the same process. The first gate structure 120 and the second gate structure 220 have the same film structure and the same initial height. The first gate structure 120 includes a gate conductive layer 21 and a hard mask layer 22 sequentially stacked on the first region A1. The second gate structure 220 includes a gate conductive layer 21 and a hard mask layer 22 sequentially stacked on the second region A2. The hard mask layer 22 of the first gate structure 120 and the hard mask layer 22 of the second gate structure 220 have the same initial thickness. The top surface of the hard mask layer 22 of the first gate structure 120 and the top surface of the hard mask layer 22 of the second gate structure 220 are located on the same horizontal plane.

[0060] In this embodiment, the first gate structure 120 and the second gate structure 220 can be formed as follows: a conductive material layer (not shown in the figure) and a hard mask material layer (not shown in the figure) are sequentially deposited on a substrate 11. The conductive material layer can be a single layer or multiple layers, and the hard mask material layer can be a single layer or multiple layers. A patterned mask is formed on the hard mask material layer, and the hard mask material layer is etched according to the patterned mask to form the hard mask layer 22 of the first gate structure 120 and the hard mask layer 22 of the second gate structure 220. Then, the patterned mask is removed, and the conductive material layer is etched according to the hard mask layer 22 to form the gate conductive layer 21 of the first gate structure 120 and the gate conductive layer 21 of the second gate structure 220.

[0061] The material of the gate conductive layer 21 may include semiconductor materials such as polysilicon, or may include metal materials with good conductivity such as tungsten or copper; the material of the hard mask layer 22 may include insulating media such as silicon oxide or silicon nitride, but is not limited thereto.

[0062] In this embodiment, refer to Figure 2 The first gate structure 120 and the second gate structure 220 also include insulating sidewalls 23, which cover the sidewalls of the first gate structure 120 and the second gate structure 220. In this embodiment, the insulating sidewalls 23 can be formed in the following manner: an insulating material layer can be deposited to cover the first gate structure 120, the second gate structure 220, and the top surface of the substrate 11, and then the insulating material layer on the substrate 11 is removed by etching back. During the etching back process, the insulating material layer on the top surface of the first gate structure 120 and the insulating material layer on the top surface of the second gate structure 220 (not shown in the figure) are removed, and the insulating sidewalls 23 are formed on the sidewalls of the first gate structure 120 and the sidewalls of the second gate structure 220.

[0063] The insulating sidewall 23 is used to prevent the gate conductive layer 21 from being exposed in the process space, and to prevent the gate conductive layer 21 from being contaminated by the process environment, which would lead to a decrease in conductivity. At the same time, the insulating sidewall 23 can prevent the first gate structure 120 and the second gate structure 220 from being damaged or deformed in subsequent processes.

[0064] For example, the material of the insulating sidewall 23 may include silicon oxide, silicon nitride, or other insulating dielectric materials.

[0065] In step S102, refer to Figure 2 The insulating material can be deposited using chemical vapor deposition (CVD) or other deposition processes to form a first insulating layer 31. The first insulating layer 31 covers the sidewalls and top surface of the first gate structure 120, the sidewalls and top surface of the second gate structure 220, the top surface of the substrate 11 located between adjacent first gate structures 120, the top surface of the substrate 11 located between adjacent second gate structures 220, and the top surface of the substrate 11 located between the first gate structure 120 and the second gate structure 220.

[0066] The first insulating layer 31 may include a nitride layer, an oxide layer, or a stacked nitride layer and an oxide layer. In this embodiment, the material of the first insulating layer 31 includes silicon nitride.

[0067] In step S103, refer to Figure 3An organic material can be spin-coated onto the substrate 11 to form a first anti-reflective layer 32. The first anti-reflective layer 32 fills the spaces between the first gate structures 120, the second gate structures 220, and between the first gate structure 120 and the second gate structure 220. The top surface of the first anti-reflective layer 32 is planar and higher than the highest point of the first insulating layer 31. In this embodiment, by controlling the spin-coating process parameters, it is ensured that the thickness of the first anti-reflective layer 32 after spin-coating is sufficient to make its top surface higher than the top surface of the first insulating layer 31.

[0068] Then, refer to Figure 3 Photoresist material is spin-coated onto the first anti-reflection layer 32 in the first region A1 to form a first photoresist layer (not shown in the figure). The first anti-reflection layer 32 in the second region A2 is removed by etching according to the first photoresist layer, exposing the first insulating layer 31 on the second gate structure 220 of the second region A2, while retaining the first anti-reflection layer 32 located in the first region A1.

[0069] For example, the initial thickness of the first anti-reflective layer 32 can be 500 Å to 1500 Å; the thickness of the first photoresist layer is 1500 Å to 2500 Å.

[0070] In step 104, refer to Figure 4 The first gate structure 120 of the first region A1 is protected by the first anti-reflective layer 32, and the second region A2 is etched. Since the top surface of the substrate 11 of the second region A2 is covered by the first insulating layer 31, the first insulating layer 31 on the top surface of the substrate 11 and the top surface of the second gate structure 220 of the second region A2 needs to be etched away first until the top surface of the substrate 11 of the second region A2 is exposed. Then, using the second gate structure 220 of the second region A2 and the shallow trench isolation structure in the substrate 11 as a mask, the substrate 11 on both sides of the second gate structure 220 is etched to form grooves 24 on both sides of the second gate structure 220. The grooves 24 extend from the top surface of the substrate 11 to the bottom surface. During the etching process to form the grooves 24, part of the hard mask layer 22 of the second gate structure 220 is etched away. In this embodiment, the thickness of the hard mask layer 22 removed from the top of the second gate structure 220 is the third thickness.

[0071] In this embodiment, an anisotropic plasma etching process is used to etch the first insulating layer 31. Furthermore, the etching gas used in the anisotropic plasma etching process is a gas containing carbon and fluorine, such as one or more of CF4, C4F8, C5F8, and C4F6.

[0072] In some embodiments, refer to Figure 4The groove 24 is a sigma trench. Along the depth direction of the groove 24, the middle region of the groove 24 protrudes to both sides relative to the top and bottom of the groove 24; that is, the width of the middle region of the groove 24 is greater than the width of the top and the width of the bottom of the groove 24. After forming the silicon-germanium layer 25 in the groove 24 of this shape, it is beneficial to further improve the compressive stress of the channel region of the PMOS transistor.

[0073] For example, the formation process of the groove 24 includes: first, etching the substrate 11 of the PMOS region on both sides of the second gate structure 220 using an anisotropic plasma etching process to form an initial groove 24 in the substrate 11 of the PMOS region; the etching gas used in the anisotropic plasma etching process includes CF4 and HBr; and then etching the initial groove 24 using a wet etching process to form the groove 24. The wet etching process uses an etching solution with different etching rates for different crystal orientations, such as tetramethylammonium hydroxide (MAH) solution or ammonia water (NH3.H2O) solution.

[0074] In step S105, refer to Figure 4 After the high-etching depth of the groove 24 process is completed in the second region A2, the first anti-reflection layer 32 is dissolved and removed by a wet process to expose the first region A1, so as to adjust the height of the first gate structure 120 in the first region A1.

[0075] In this embodiment, after step S105 and before step S106, step S110 is also performed: an epitaxial growth of a silicon-germanium layer 25 in the groove 24.

[0076] Reference Figure 5 The silicon-germanium layer 25 can be formed by selective epitaxy, meaning that the epitaxial rate of the silicon-germanium layer 25 on semiconductor materials is much greater than the epitaxial rate on other materials (such as silicon oxide and silicon nitride).

[0077] In some embodiments, when forming the silicon-germanium layer 25, P-type impurity ions can be in-situ doped into the silicon-germanium layer 25. The P-type impurity ions are one or more of boron ions, gallium ions, or indium ions.

[0078] In other embodiments, the first antireflective layer 32 may be removed after the silicon-germanium layer 25 is formed linearly.

[0079] Furthermore, in this embodiment, referring to Figure 6 Before performing the first etch, the following steps were also performed:

[0080] Step S100-1: A second anti-reflective layer 33 is formed in the first region A1 and the second region A2, and a second photoresist layer 34 is formed on the second anti-reflective layer 33. The top surface of the second anti-reflective layer 33 is higher than the top surface of the second gate structure 220. The second anti-reflective layer 33 fills the spaces between the first gate structure 120 and the second gate structure 220, and the top surface of the second anti-reflective layer 33 is higher than the top surface of the second gate structure 220. After coating the surface of the second anti-reflective layer 33 with photoresist to form the second photoresist layer 34, the second photoresist layer 34 is exposed and developed to expose the surface of the second anti-reflective layer in the first region A1.

[0081] Step S100-2: Irradiate the second anti-reflection layer 33 of the first region A1 back to expose a portion of the first insulating layer 31 at the top of the first gate structure 120.

[0082] Reference Figure 7 The second anti-reflective layer 33 of the first region A1 is etched back, and by controlling the thickness of the second anti-reflective layer 33 removed by the etch-back, a portion of the first insulating layer 31 on the top of the first gate structure 120 is exposed.

[0083] For example, a dry etching process can be used, such as plasma etching of the first antireflective layer 32 based on oxygen (O2) and fluorine (F2) gas.

[0084] In this embodiment, the etch-back process has a high etching rate for the second anti-reflection layer 33 and high selectivity for the first insulating layer 31, so as to avoid over-etching and damaging the first insulating layer 31, which is beneficial to improving the control accuracy of the process.

[0085] In step S106, refer to Figure 8 After etching the second anti-reflection layer 33 to the target height, the first insulating layer 31 on top of the first gate structure 120 exposed by the second anti-reflection layer 33 is etched away, and the first insulating layer 31 exposed on top of the first gate structure 120 is completely etched away. The insulating sidewall 23 originally covered by the first insulating layer 31 is also removed to expose part of the hard mask layer 22 on top of the first gate structure 120.

[0086] Subsequently, the etching conditions were seamlessly switched or continuous etching was performed, as per [reference]. Figure 9 The first etching removes a portion of the hard mask layer 22 at the top of the first gate structure 120, reducing the thickness of the hard mask layer 22 at the top of the first gate structure 120. In this embodiment, the first etching removes a first thickness of the hard mask layer 22 at the top of the first gate structure 120.

[0087] In this embodiment, a plasma etching process is used to etch and remove the first insulating layer 31 on top of the first gate structure 120 exposed by the second anti-reflective layer 33. The etching process has a high etching rate for the first insulating layer 31, and the etching gas can be a gas containing carbon and fluorine, such as one or more of CF4, C4F8, C5F8, and C4F6.

[0088] After the first etching is performed and before the second etching is performed, step S100-3 is also performed: the remaining second anti-reflective layer 33 of the first region A1 is removed to expose the first insulating layer 31 on the substrate 11 of the first region A1.

[0089] Reference Figure 10 The second anti-reflection layer 33 of the first region A1 is completely removed, exposing the first insulating layer 31 on the top surface of the substrate 11 of the first region A1 and the first insulating layer 31 covering the sidewall of the first gate structure 120.

[0090] In this embodiment, a dry ashing process (e.g., oxygen plasma treatment) or a wet chemical solution can be used to remove the second anti-reflective layer 33 in the first region A1. The process for removing the second anti-reflective layer 33 in the first region A1 has high selectivity for the first insulating layer 31, ensuring that the second anti-reflective layer 33 in the first region A1 is completely removed without damaging any existing device structure. It is understood that the second anti-reflective layer 33 in the second region A2 is protected by the second photoresist layer 34 and is thus retained.

[0091] In step S107, refer to Figure 11 The first insulating layer 31 on the substrate 11 of the first region A1 is removed, and the hard mask layer 22 exposed on top of the first gate structure 120 is further thinned using an etchant. In this embodiment, the second etching removes the second thickness of the hard mask layer 22 on top of the first gate structure 120.

[0092] In this embodiment, a dry etching process (e.g., a fluorine-based chemical gas containing a high proportion of isotropic etching components) or a wet etching process can be used to etch and remove the first insulating layer 31 on the substrate 11 of the first region A1, as well as the hard mask layer 22 on top of the first gate structure 120. The etching process is etchable on both the removed first insulating layer 31 and the hard mask layer 22 that needs to be thinned simultaneously, but has high selectivity for the underlying substrate 11 and gate conductive layer 21 to prevent damage to the active region of the device.

[0093] The etching duration of the second etching is determined by the thickness of the first insulating layer 31 on the substrate 11 and the second thickness of the hard mask layer 22, so as to completely remove the first insulating layer 31 on the substrate 11 of the first region A1, and at the same time remove the second thickness of the hard mask layer 22 on the top of the first gate structure 120.

[0094] Then, refer to Figure 12 The second photoresist layer 34 is removed by ashing, and the second anti-reflection layer 33 of the second region A2 is removed by etching, exposing the structure of the second region A2.

[0095] In some embodiments, refer to Figure 11 After the second etching is performed, the thickness of the remaining hard mask layer 22 of the first gate structure 120 is basically the same as the thickness of the remaining hard mask layer 22 of the second gate structure 220.

[0096] In this embodiment, a first-thickness hard mask layer 22 of the first gate structure 120 is removed by a first etching, and a second-thickness hard mask layer 22 of the first gate structure 120 is removed again by a second etching. The total thickness of the hard mask layer 22 that is consumed and removed from the first gate structure 120 is increased by the two etchings, thereby reducing the height difference between the first gate structure 120 and the second gate structure 220. This improves the problem of inconsistent heights of the first gate structure 120 and the second gate structure 220 caused by the asymmetry of the fabrication process of the first region A1 and the second region A2, thereby improving the gate height load effect and providing uniform surface conditions for subsequent global planarization processes such as chemical mechanical polishing.

[0097] In some embodiments, refer to Figure 4 , Figure 9 , Figure 11 The process involves etching the first region A2 to form a groove 24 in the substrate 11 on both sides of the second gate structure 220, and etching the third region A2 to form a groove 24, thereby removing the hard mask layer 22 of the second gate structure 220.

[0098] The sum of the first thickness and the second thickness is equal to the third thickness; after removing the first insulating layer 31 on the substrate 11 of the first region A1, the top surface of the first gate structure 120 and the top surface of the second gate structure 220 are at the same horizontal height.

[0099] In step 104, refer to Figure 4 The third thickness at which the hard mask layer 22 of the second gate structure 220 is removed is related to factors such as the depth of the etched groove 24. In this embodiment, the process parameters of the first and second etching can be adjusted according to the third thickness so that the sum of the first and second thicknesses is as close as possible to the third thickness, thereby reducing the height difference between the top surface of the first gate structure 120 and the top surface of the second gate structure 220.

[0100] In some embodiments, refer to Figure 2The hard mask layer 22 includes a first sublayer 221 and a second sublayer 222 sequentially stacked along a direction away from the substrate 11, wherein the etching resistance of the first sublayer 221 is greater than that of the second sublayer 222. For example, the material of the first sublayer 221 may include silicon nitride, and the material of the second sublayer 222 may include silicon oxide, such as a silicon oxide layer formed by tetraethyl orthosilicate (TEOS) chemical vapor deposition.

[0101] In step 104, refer to Figure 4 The second sublayer 222 of the second gate structure 220 is completely etched away, and the first sublayer 221 of the second gate structure 220 is partially removed. That is, the third thickness is greater than the thickness of the second sublayer 222, but less than the sum of the thicknesses of the first sublayer 221 and the second sublayer 222.

[0102] In some embodiments, refer to Figure 7 Step S100-2: Re-etching the second anti-reflection layer 33 of the first region A1 includes: re-etching the second anti-reflection layer 33 of the first region A1 back to the top surface that is lower than the top surface of the second sub-layer 222.

[0103] The etching time can be controlled by the etching duration to etch the second anti-reflection layer 33 of the first region A1 back to the target height. The target height is set so that the remaining top surface of the second anti-reflection layer 33 of the first region A1 is lowered below the top surface of the second sub-layer 222 (silicon oxide layer) in the hard mask layer 22. In this embodiment, the first anti-reflection layer 32 is etched back until its top surface is lower than the top surface of the second sub-layer 222 to ensure that after exposing the insulating sidewalls of the first anti-reflection layer 32, at least a portion of the second sub-layer 222 of the first gate structure 120 can be exposed. This allows at least a portion of the second sub-layer 222 of the first gate structure 120 to be etched away, thereby reducing the thickness of the hard mask layer 22 of the first gate structure 120.

[0104] In this embodiment, the removal thickness of the second anti-reflection layer 33 in the first region A1 is set according to the thickness of the first sub-layer 221 and the second sub-layer 222. For example, the second anti-reflection layer 33 in the first region A1 can be etched back to remove 200 to 800 angstroms. In this way, sufficient material margin is left for the subsequent etching of the first sub-layer 221 of the first gate structure 120, avoiding premature etching through to the lower first sub-layer 221 (silicon nitride layer) or the gate conductive layer 21.

[0105] In some embodiments, refer to Figure 7 Step S100-2: Re-etching the second anti-reflection layer 33 of the first region A1 includes: re-etching the second anti-reflection layer 33 of the first region A1 to a height where the top surface is lower than the bottom surface of the second sub-layer 222 and higher than or equal to the bottom surface of the first sub-layer 221.

[0106] In this embodiment, the second anti-reflection layer 33 of the first region A1 is etched to a height where the top surface is lower than the bottom surface of the second sub-layer 222 and higher than or equal to the bottom surface of the first sub-layer 221. This allows the etching to remove part of the second anti-reflection layer 33 of the first region A1, thus exposing the entire second sub-layer 222 of the first gate structure 120. This provides a larger process window for the first etching to thin the thickness of the second sub-layer 222, reducing the etching difficulty.

[0107] In some embodiments, refer to Figure 8 , Figure 9 In step S106, the first etching removes at least a portion of the second sublayer 222 of the first gate structure 120.

[0108] In this embodiment, the thickness of the second sub-layer 222 removed by the first etching can be controlled by controlling the etching parameters. The thickness of the second sub-layer 222 removed by the first etching can be set according to the third thickness and the thickness of the lower first sub-layer 221.

[0109] In some implementations, refer to Figure 8 , Figure 9 In step S106, the second sublayer 222 on top of the first gate structure 120 can be completely removed to expose the underlying first sublayer 221. In other embodiments, to ensure that the second sublayer 222 on top of the first gate structure 120 is completely removed, etching may slightly remove a portion of the underlying first sublayer 221 (a few angstroms to tens of angstroms).

[0110] Further, the first etching removes a hard mask layer 22 of a first thickness, which can range from 50 angstroms to 600 angstroms. In step S108, the process parameters of the second etching are adjusted according to the third thickness and the first thickness so that the sum of the first thickness and the second thickness is as close as possible to the third thickness.

[0111] In some embodiments, the first region A1 is an NMOS region, and the second region A2 is a PMOS region. The NMOS region is used to form NMOS transistors, and the PMOS region is used to form PMOS transistors. The NMOS and PMOS regions may be adjacent or non-adjacent, and there may be one or more NMOS regions and one or more PMOS regions. It should be noted that... Figures 2-12 The example only uses one NMOS region and one PMOS region of substrate 11, with the PMOS region located on one side of the NMOS region, as an example for illustration, and should not limit the scope of protection of this application.

[0112] The semiconductor structure fabrication method of this application does not require the introduction of additional equipment and photomasks. By adding two highly controllable etching operations in the first region A1, the thickness of the hard mask layer 22 of the first gate structure 120 removed is close to the thickness of the hard mask layer 22 of the second gate structure 220 removed during the etching of the second region A2 to form the groove 24. This improves the gate high load effect caused by process asymmetry due to the etching of the second region A2 to form the groove 24. It has good process compatibility and feasibility, and hardly increases the additional manufacturing cost.

[0113] According to an exemplary embodiment, this embodiment provides a semiconductor structure fabricated using the semiconductor structure fabrication method of the above embodiment. For example, the semiconductor structure of this embodiment can be a semiconductor device such as Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Flash EPROM, Ferroelectric Random Access Memory (FRAM), Magnetic Random-Access Memory (MRAM), Phase Change Random-Access Memory (PRAM), etc.

[0114] According to an exemplary embodiment, this embodiment provides an electronic device, including the semiconductor structure described in the above embodiments. The electronic device may be a storage device, mobile phone, computer, tablet computer, television, artificial intelligence device, etc.

[0115] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a first region and a second region, the first region having a first gate structure formed thereon, and the second region having a second gate structure formed thereon, wherein the gate structure includes a hard mask layer disposed on top. A first insulating layer is formed to cover the first gate structure, the second gate structure, and the exposed area of ​​the substrate; A first anti-reflective layer is formed in the first region and filled between the first gate structures, wherein the top surface of the first anti-reflective layer is higher than the top surface of the first insulating layer; The second region is etched to form grooves in the substrate on both sides of the second gate structure, while the first insulating layer on the top surface of the second gate structure and part of the hard mask layer of the second gate structure are removed. Remove the first anti-reflective layer; Perform a first etching to remove the first insulating layer exposed at the top of the first gate structure, and remove a portion of the hard mask layer at the top of the first gate structure; A second etching is performed to remove the first insulating layer on the substrate in the first region, while also removing a portion of the hard mask layer of the first gate structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the second etching is performed, the thickness of the remaining hard mask layer of the first gate structure is substantially the same as the thickness of the remaining hard mask layer of the second gate structure.

3. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that, The hard mask layer includes a first sublayer and a second sublayer stacked sequentially along a direction away from the substrate, wherein the etching resistance of the first sublayer is greater than that of the second sublayer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, Before performing the first etching, the process also includes: A second anti-reflective layer is formed in the first region and the second region, and a second photoresist layer is formed on the second anti-reflective layer, wherein the top surface of the second anti-reflective layer is higher than the top surface of the second gate structure; The second anti-reflective layer of the first region is etched back, exposing a portion of the first insulating layer at the top of the first gate structure; After the first etching is performed, the remaining second anti-reflective layer in the first region is removed, exposing the first insulating layer on the substrate in the first region.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The process of etching back the second anti-reflective layer of the first region includes: etching the second anti-reflective layer of the first region back to a top surface that is lower than the top surface of the second sub-layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The process of etching back the second anti-reflective layer of the first region includes: etching the second anti-reflective layer of the first region back to a height where the top surface is lower than the bottom surface of the second sub-layer and higher than or equal to the bottom surface of the first sub-layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The first etching removes at least a portion of the second sublayer from the first gate structure.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming grooves in the substrates on both sides of the second gate structure, the method further includes: epitaxially growing a silicon-germanium layer in the grooves.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first region is an NMOS region, and the second region is a PMOS region.

10. A semiconductor structure, characterized in that, It is prepared by the method of preparing the semiconductor structure as described in any one of claims 1-9.

Images