Formation method of semiconductor structure
By forming a metal layer on the second substrate and transferring it to the first substrate using a stripping technique, the problem of roughness at the metal layer contact surface is solved, thereby improving the performance of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2024-11-06
- Publication Date
- 2026-05-08
AI Technical Summary
Existing methods for forming metal layers result in high surface roughness at the contact surfaces of adjacent metal layers, increasing contact resistance and reducing semiconductor structural performance.
A metal layer is formed on the second substrate and then transferred to the first substrate by mechanical or thermal peeling. This ensures that the formation processes of the metal layer and the first substrate are independent of each other and do not affect each other, thereby improving the surface smoothness and contact effect of the metal layer.
By using an independent metal layer formation process, the contact effect between the metal layer and the underlying film layer is improved, the contact resistance is reduced, and the performance of the semiconductor structure is enhanced.
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Figure CN122003097A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] In semiconductor manufacturing, multiple different processes are typically performed, including the process of forming metal layers.
[0003] Currently, the method for forming metal layers uses a "high-energy" manufacturing process based on the vaporization of metal precursors. This usually involves hot metal atoms or clusters bombarding the contact area. This process, through kinetic energy transfer or chemical reactions between metal atoms and daughter atoms, will damage the contact surface of adjacent metal layers.
[0004] Therefore, the performance of the currently developed semiconductor structures needs to be improved. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a method for forming a semiconductor structure, which can improve the performance of the semiconductor structure.
[0006] This invention provides a method for forming a semiconductor structure, comprising:
[0007] Provide a first substrate; perform one or more metal stacking operations on the first substrate, the metal stacking operations including: providing a second substrate; forming a metal layer on the second substrate; performing a separation operation on the second substrate and the metal layer, and transferring the metal layer to the first substrate.
[0008] Optionally, in the case of performing multiple metal stacking operations, the metal layer that has been transferred to the first substrate is the previous metal layer, and the metal layer to be transferred to the first substrate is the current metal layer.
[0009] In the step of transferring the metal layer onto the first substrate during the metal stacking operation, the current metal layer is attached to the previous metal layer.
[0010] Optionally, the method of performing the separation operation on the second substrate and the metal layer, and transferring the metal layer onto the first substrate, includes at least one of the following:
[0011] Mechanical peeling;
[0012] Thermal peeling.
[0013] Optionally, the metal layer includes either a first type of metal layer or a second type of metal layer, and the adhesion between the first type of metal layer and the second substrate is less than the adhesion between the second type of metal layer and the second substrate;
[0014] When the metal layer is a first type of metal layer, a mechanical peeling method is used to separate the second substrate and the metal layer, and transfer the metal layer onto the first substrate;
[0015] When the metal layer is a second type of metal layer, a thermal peeling method is used to separate the second substrate and the metal layer, and transfer the metal layer to the first substrate.
[0016] Optionally, the material of the first type of metal layer includes one or more of Al, W, N, Co, Mo, Ti, Ta, TaN, and MgO;
[0017] The materials for the second type of metal layer include one or more of Ag, Au, Pt, Pd, CoFeB, and CoFe.
[0018] Optionally, the step of separating the second substrate and the metal layer using a mechanical peeling method and transferring the metal layer onto the first substrate includes:
[0019] The metal layer is peeled off from the second substrate using a suction cup;
[0020] After the metal layer is peeled off from the second substrate, it is transferred to the first substrate using the suction cup.
[0021] Optionally, in the step of providing the second substrate, the second substrate further has a buffer layer, and the metal layer is located on the buffer layer;
[0022] The steps of performing a separation operation between the second substrate and the metal layer using a thermal peeling method, and transferring the metal layer onto the first substrate, include:
[0023] The second substrate is inverted on the first substrate, such that the metal layer is located on the first substrate;
[0024] After the second substrate is inverted on the first substrate, a heating operation is performed on the second substrate to decompose the buffer layer, thereby separating the second substrate from the metal layer.
[0025] Optionally, the melting point of the metal layer is higher than the decomposition temperature of the buffer layer.
[0026] Optionally, the material of the buffer layer includes one or more of polypropylene carbonate, polyethylene carbonate, and highly branched polymers.
[0027] Optionally, the thickness of the buffer layer is 100 nm to 1000 nm along the normal direction of the second substrate surface.
[0028] Optionally, a spin coating process is used to form the buffer layer on the second substrate.
[0029] Optionally, in the step of providing the second substrate, the second substrate further has an adhesive layer located between the second substrate and the buffer layer.
[0030] Optionally, the material of the adhesive layer includes one or more of Ge, GaAs, IGZO, WSe2, WS2 and MoS2.
[0031] Optionally, the thickness of the adhesive layer along the normal direction of the second substrate surface is 10 nm to 500 nm.
[0032] Optionally, after forming the metal layer on the second substrate and before performing a separation operation on the second substrate and the metal layer, the forming method further includes annealing the metal layer.
[0033] Optionally, multiple metal stacking operations are performed on the first substrate to form an initial magnetic tunnel junction stack structure composed of multiple metal layers. The initial magnetic tunnel junction stack structure includes: a magnetic orientation reference film, a tunneling oxide film, and a magnetic orientation free film stacked sequentially.
[0034] The initial magnetic tunneling stack structure is graphically represented to form a magnetic tunneling stack structure.
[0035] Optionally, in the step of providing the first substrate, a dielectric layer is formed on the first substrate, a conductive plug is formed within the dielectric layer, and the top of the conductive plug is exposed by the dielectric layer.
[0036] The metal layer closest to the first substrate is electrically connected to the conductive plug.
[0037] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0038] In the semiconductor structure formation method provided in this embodiment of the invention, in the step of performing one or more metal stacking operations on the first substrate, a metal layer is formed on the second substrate, so that the formation processes of the metal layer and the first substrate are independent of each other and do not affect each other. Alternatively, when performing multiple metal stacking operations, the formation processes of each metal layer are independent of each other and do not affect each other, which helps to improve the surface smoothness of the metal layer. After the metal layer is transferred to the first substrate, the contact effect between the metal layer and the underlying film layer is improved (for example, when performing multiple metal stacking operations, improving the contact effect of adjacent metal layers can reduce contact resistance), thereby improving the performance of the semiconductor structure. Attached Figure Description
[0039] Figures 1 to 6This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention;
[0040] Figures 7 to 11 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0041] As described in the background section, the performance of currently formed semiconductor structures needs to be improved.
[0042] Research has found that in a semiconductor structure formation method, one or more metal layers are usually deposited on a substrate. When multiple metal layers are deposited on the substrate, the contact surface between adjacent metal layers will have a large roughness, which will increase the contact resistance between these adjacent metal layers and thus reduce the performance of the semiconductor structure.
[0043] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a first substrate; performing one or more metal stacking operations on the first substrate, wherein the metal stacking operations include: providing a second substrate; forming a metal layer on the second substrate; performing a separation operation on the second substrate and the metal layer, and transferring the metal layer to the first substrate.
[0044] The semiconductor structure formation method provided in this invention forms a metal layer on a second substrate, ensuring that the formation processes of the metal layer and the first substrate are independent and do not affect each other. Alternatively, when performing multiple metal stacking operations, the formation processes of each metal layer are independent and do not affect each other. This improves the surface smoothness of the metal layer, and after transferring the metal layer to the first substrate, it enhances the contact effect between the metal layer and the underlying film layer (e.g., when performing multiple metal stacking operations, improving the contact effect between adjacent metal layers can reduce contact resistance). Therefore, it can improve the performance of the semiconductor structure.
[0045] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described exemplarily below with reference to the accompanying drawings.
[0046] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.
[0047] See Figure 1 Provides a first substrate 100.
[0048] The first substrate 100 is used to provide a process platform for subsequent process manufacturing.
[0049] In this embodiment, the first substrate 100 is used to provide a process platform for forming a magnetic random access memory (MRAM). Specifically, the MRAM device is a spin transfer torque magnetoresistive random access memory (STT-MRAM).
[0050] In other embodiments, the substrate may also provide a process platform for forming other types of devices, such as metal-insulator-metal capacitors, which are not limited herein.
[0051] In this embodiment, the first substrate 100 includes a substrate made of silicon. In other embodiments, the substrate material may also include other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be a material suitable for process requirements or easy to integrate.
[0052] In this embodiment, a transistor may be formed in the substrate. The transistor may include one or both of NMOS and PMOS transistors.
[0053] Specifically, the transistor includes a gate structure and source / drain doped regions located in the substrate on both sides of the gate structure.
[0054] In this embodiment, an interlayer dielectric layer and contact hole plugs that penetrate the interlayer dielectric layer and contact the source / drain doped regions are also formed in the substrate. The interlayer dielectric layer covers the surface of the source / drain doped regions and the sidewalls of the gate structure. Other types of semiconductor devices can also be formed in the substrate, and functional structures such as resistive structures and conductive structures can also be formed in the substrate.
[0055] In this embodiment, a metal interconnect layer 102 is formed on the first substrate 100, and the metal interconnect layer 102 is used to realize the connection between the first substrate 100 and the subsequently formed semiconductor device.
[0056] In this embodiment, during the step of providing the first substrate 100, a dielectric layer 104 is formed on the first substrate 100, a conductive plug 106 is formed within the dielectric layer 104, and the top of the conductive plug 106 is exposed by the dielectric layer 104.
[0057] The dielectric layer 104 is used to achieve isolation between the subsequent metal layer and the metal interconnect layer 102.
[0058] In this embodiment, the dielectric layer 104 is made of dielectric materials such as low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride.
[0059] Specifically, the dielectric layer 104 is made of a low-k dielectric material, which helps to reduce the parasitic capacitance between subsequent interconnect structures, thereby helping to reduce RC delay.
[0060] In this embodiment, a deposition process (e.g., chemical vapor deposition) can be used to form a dielectric layer 104 over the first substrate 100.
[0061] The conductive plug 106 is used to achieve electrical connection between the transistor in the first substrate 100 and the metal layer (not shown). For example, the conductive plug 106 is used to electrically connect the metal layer closest to the first substrate 100 and the metal interconnect layer 102.
[0062] In this embodiment, the step of forming a conductive plug 106 in the dielectric layer 104 includes: forming a trench (not shown) in the dielectric layer 104; forming a conductive material layer (not shown) to fill the trench, wherein the conductive material layer in the trench serves as the conductive plug 106.
[0063] In this embodiment, the material of the conductive plug 106 may include one or more of Ta, Cu, W, Al, TiN, TaN, and Ti.
[0064] In one specific embodiment, the conductive plug 106 is made of Ta.
[0065] See Figures 2 to 6 One or more metal stacking operations are performed on the first substrate 100. The metal stacking operations include: providing a second substrate 200; forming a metal layer (e.g., a first metal layer 202) on the second substrate 200; performing a separation operation on the second substrate 200 and the first metal layer 202; and transferring the first metal layer 202 onto the first substrate 100.
[0066] In this embodiment of the invention, a first metal layer 202 is formed on a second substrate 200, such that the formation processes of the first metal layer 202 and the first substrate 100 are independent of each other and do not affect each other. Alternatively, when multiple metal stacking operations are performed, the formation processes of each metal layer are independent of each other and do not affect each other. This helps to improve the surface smoothness of the first metal layer 202. After the first metal layer 202 is transferred to the first substrate 100, the contact effect between the first metal layer 202 and the underlying film layer is improved (for example, when multiple metal stacking operations are performed, improving the contact effect of adjacent metal layers can reduce contact resistance), thereby improving the performance of the semiconductor structure.
[0067] In this embodiment, based on different process requirements, a variety of different methods can be used to perform metal stacking operations.
[0068] In one specific embodiment, the separation operation of the second substrate 200 and the first metal layer 202 and the transfer of the first metal layer 202 onto the first substrate 100 include at least one of mechanical peeling and thermal peeling.
[0069] It should be noted that a suitable peeling method can be selected based on the specific material of the first metal layer 202.
[0070] As an example, in actual manufacturing processes, different types of metals have different adhesion to the substrate when forming a metal layer. Therefore, an appropriate peeling method can be selected based on the adhesion between the metal and the substrate. For instance, some types of metal layers have strong adhesion to the substrate, while others have weaker adhesion.
[0071] In this embodiment, a specific peeling method is selected based on the adhesion between the first metal layer 202 and the second substrate 200.
[0072] Specifically, the first metal layer 202 may include either a first type of metal layer or a second type of metal layer, and the adhesion between the first type of metal layer and the second substrate 200 is less than the adhesion between the second type of metal layer and the second substrate 200.
[0073] In this embodiment, when the first metal layer 202 is a first type of metal layer, a mechanical peeling method is used to separate the second substrate 200 and the first metal layer 202, and transfer the metal layer 202 onto the first substrate 100.
[0074] The adhesion between the first type of metal layer and the second substrate 200 is small, so the first type of metal layer and the second substrate 200 can be easily separated by mechanical peeling.
[0075] Mechanical peeling can quickly peel the first metal layer 202 off the second substrate 200, and the peeling process is simple, thus improving the peeling efficiency.
[0076] The following, in conjunction with the accompanying drawings, schematically illustrates the metal stacking operation process in the first embodiment of the present invention.
[0077] See Figure 2 Provide a second substrate 200.
[0078] The second substrate 200 is used for forming the first metal layer 202 (see...). Figure 3 It provides a process platform for the formation of ).
[0079] In this embodiment, the second substrate 200 includes a substrate made of silicon. In other embodiments, the substrate material may also include other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be a material suitable for process requirements or easy to integrate.
[0080] In this embodiment, the second substrate 200 is a semiconductor substrate. Since the thermal decomposition temperature of the semiconductor substrate is high, the semiconductor substrate can withstand the metal deposition temperature and the temperature during the subsequent thermal stripping and deposition of the first metal layer 202, thereby improving the formation quality of the semiconductor structure.
[0081] In other embodiments, the second substrate 200 may also be other types of substrates, such as a glass substrate.
[0082] See Figure 3 A first metal layer 202 is formed on the second substrate 200.
[0083] In this embodiment, the first metal layer 202 is a first type of metal layer, and the adhesion between the first type of metal layer and the second substrate 200 is relatively small.
[0084] In this embodiment, the material of the first type of metal layer includes one or more of Al, W, N, Co, Mo, Ti, Ta, TaN, and MgO.
[0085] In this embodiment, a first metal layer 202 is formed on the second substrate 200 by a deposition process.
[0086] In one specific embodiment, the appropriate deposition process can be selected based on the thickness of the first metal layer 202 to be formed.
[0087] For example, if the thickness of the first metal layer 202 is thin (e.g., on the angstrom level), an atomic layer deposition process can be used; or if the thickness of the first metal layer 202 is thick (e.g., on the nanometer level), a physical deposition process or an electroplating process can be used.
[0088] See Figure 4 The first metal layer 202 is peeled off from the second substrate 200 by the suction cup 300.
[0089] In this embodiment, the suction cup mainly consists of a suction cup body, a suction cup surface, and a vacuum source. The vacuum source generates negative pressure on the suction cup surface, creating a closed space between the suction cup surface and the first metal layer 202. Due to the pressure difference between the suction cup surface and the first metal layer 202, air flows into the suction cup from one side of the first metal layer 202, creating a flowing pressure difference. As the pressure difference gradually increases, the adsorption force between the suction cup surface and the first metal layer 202 increases. With the second substrate 200 fixed, the first metal layer 202 is adsorbed onto the suction cup surface, achieving separation between the first metal layer 202 and the second substrate 200.
[0090] In one specific embodiment, the suction cup 300 can be an electrostatic suction cup. When a high-voltage electrostatic field is generated on the surface of the electrostatic generator, static charge will be generated on the surface of the suction cup. The static charge will be distributed on the surface of the suction cup, forming an electric field gradient. When the surface of the suction cup contacts the first metal layer 202, by fixing the second substrate 200, the first metal layer 202 can be peeled off from the second substrate 200 under the action of electrostatic attraction.
[0091] It should be noted that, Figure 4 The structure of the suction cup 300 shown in the following views is for illustrative purposes only and is used to illustrate the use of a device with adsorption capabilities to achieve the peeling of the first metal layer 202 and the second substrate 200. It should not be construed as a limitation of the present invention.
[0092] See Figure 5 and Figure 6 After the first metal layer 202 is peeled off from the second substrate 200, the first metal layer 202 is transferred to the first substrate by a suction cup 300.
[0093] In this embodiment, see Figure 5 When the suction cup 300 peels the first metal layer 202 from the second substrate 200, the suction cup 300 can adsorb the first metal layer 202, and then, driven by the suction cup 300, can transfer the first metal layer 202 to the top surface of the first substrate 100. See also Figure 6 When the first metal layer 202 is placed on the top surface of the first substrate 100, the first metal layer 202 can be attached to the surface of the first substrate 100 by releasing the adsorption force between the suction cup 300 and the first metal layer 202.
[0094] It should be noted that when the first metal layer 202 is placed on the surface of the first substrate 100, the van der Waals forces between the two can achieve bonding between the first metal layer 202 and the first substrate 100. Compared with chemical bonding, this effect can better protect the lattice morphology of the first metal layer 202 and the first substrate 100, reduce the generation of disordered states at the interface, thereby reducing the Fermi pinning effect and reducing the power consumption and resistance of the device.
[0095] In other embodiments, the first metal layer 202 can be placed directly above the first substrate 100. By releasing the adsorption force between the suction cup 300 and the first metal layer 202, the first metal layer 202 will adhere to the surface of the first substrate 100 under the action of gravity.
[0096] In this embodiment, see Figure 3 After the first metal layer 202 is formed on the second substrate 200, and before performing a separation operation on the second substrate 200 and the first metal layer 202, the formation method further includes annealing the first metal layer 202.
[0097] Annealing is used to repair lattice defects in the first metal layer 202, thereby improving the lattice quality and crystallization uniformity of the first metal layer 202, and thus improving the formation quality of the first metal layer 202.
[0098] In this embodiment, by annealing the first metal layer 202 before performing the separation operation between the second substrate 200 and the first metal layer 202, on the one hand, the crystal lattice of the first metal layer 202 can be repaired, making the crystal form of the first metal layer 202 more complete; on the other hand, annealing the first metal layer 202 before performing the separation operation can reduce the impact on the existing metal layers of the first substrate 100 (for example, the crystallization temperature of each metal layer is not consistent. If the first metal layer 202 is placed on the first substrate 100 and then annealed, the crystal morphology of the existing metal layers of the first substrate 100 will be changed, and due to the effect of heat, atomic migration will occur at the contact interface between adjacent metal layers, increasing the resistance of the contact interface).
[0099] In this embodiment, when the first metal layer 202 is a second type of metal layer, a thermal stripping method is used to perform a separation operation on the second substrate 200 and the first metal layer 202, and transfer the first metal layer 202 onto the first substrate 100.
[0100] By using thermal stripping, there is no need to directly contact the first metal layer 202 and the second substrate 200, which can avoid damage to the first metal layer 202 and the second substrate 200 and improve the smoothness of the first metal layer 202 and the second substrate 200.
[0101] The following, in conjunction with the accompanying drawings, schematically illustrates the metal stacking operation process in the second embodiment of the present invention.
[0102] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that the metal layer (e.g., the second metal layer 404) is a second type of metal layer, and this embodiment uses a thermal peeling method to achieve the separation between the second substrate 400 and the second metal layer 404.
[0103] In this embodiment, the material of the second type of metal layer includes one or more of Ag, Au, Pt, Pd, CoFeB, and CoFe.
[0104] See Figure 7 In the step of providing the second substrate 400, the second substrate 400 also has a buffer layer 402, and the second metal layer 404 is located on the buffer layer 402.
[0105] In this embodiment, the second metal layer 404 is a second type of metal layer, and the adhesion between the second type of metal layer and the second substrate 400 is relatively strong. By providing a buffer layer 402 between the second metal layer 404 and the second substrate 400, the second metal layer 404 and the second substrate 400 can be isolated, thereby reducing the difficulty of peeling the second metal layer 404 from the second substrate 400.
[0106] In this embodiment, a spin coating process is used to form a buffer layer 402 on the second substrate 400.
[0107] The spin coating process can adjust the flatness of the surface of the buffer layer 402, improve the smoothness of the contact interface between the buffer layer 402 and the second metal layer 404, and control the thickness formed according to the material of the buffer layer 402.
[0108] In this embodiment, the thickness of the buffer layer 402 along the normal direction of the surface of the second substrate 400 is 100nm to 1000nm. By making the thickness of the buffer layer 402 less than or equal to 1000nm, the buffer layer 402 can play a buffering role while reducing the formation time of the buffer layer 402 and the subsequent removal time of the buffer layer 402, thereby improving the formation efficiency of the semiconductor structure.
[0109] In this embodiment, the material of the buffer layer 402 includes one or more of polypropylene carbonate, polyethylene carbonate, and highly branched polymers, wherein the material of the buffer layer 402 can be selected according to the decomposition temperature.
[0110] In one specific implementation embodiment, the buffer layer 402 comprises a highly branched polymer.
[0111] See Figure 8 The second substrate 400 is inverted on the first substrate 100, so that the second metal layer 404 is located on the first substrate 100.
[0112] See Figure 9 After the second substrate 400 is inverted on the first substrate 100, a heating operation H is performed on the second substrate 400 to decompose the buffer layer 402, thereby separating the second substrate 400 and the second metal layer 404.
[0113] By decomposing the buffer layer 402, the second metal layer 404 is separated from the second substrate 400, so that the second metal layer 404 can be attached to the surface of the first substrate 100, for example, the second metal layer 404 can contact the first metal layer 202.
[0114] It should be noted that when the second metal layer 404 is placed on the surface of the first metal layer 202, the van der Waals forces between them enable bonding between the second metal layer 404 and the first metal layer 202. Compared with chemical bonding, this bonding can better protect the lattice morphology of the second metal layer 404 and the first metal layer 202, reduce the generation of disordered states at the interface, thereby reducing the Fermi pinning effect and reducing the power consumption and resistance of the device. In some other embodiments, when the second substrate 400 is inverted, the metal layer 402 can be located above the first substrate 100 (i.e., there is an isolation between the metal layer 402 and the substrate 100 along the normal direction of the surface of the substrate 100). In this way, when the buffer layer 402 is decomposed, causing the second metal layer 404 to separate from the second substrate 400, the second metal layer 404 can adhere to the surface of the first substrate 100 under the action of gravity, for example, the second metal layer 404 can contact the first metal layer 202.
[0115] In this embodiment, during the step of performing heating operation H on the second substrate 400 to decompose the buffer layer 402, the melting point of the second metal layer 404 is higher than the decomposition temperature of the buffer layer 402. This ensures the integrity of the second metal layer 404 and avoids the problem of partial melting of the second metal layer 404 due to an excessively high decomposition temperature of the buffer layer 402 (e.g., higher than the melting point of the second metal layer 404), thereby improving the morphology of the second metal layer 404.
[0116] See Figure 7 In this embodiment, during the step of providing the second substrate 400, the second substrate also has an adhesive layer 401, which is located between the second substrate 400 and the buffer layer 402.
[0117] By providing the adhesive layer 401, the adhesion between the buffer layer 402 and the second substrate 400 can be increased, so that even under the influence of gravity, the buffer layer 402 is not easily detached from the second substrate 400 when the second substrate 400 is inverted on the first substrate 100. In this way, the probability of the second metal layer 404 falling off during the inversion of the second substrate 400 can be reduced, allowing the second metal layer 404 to be accurately placed on the first substrate 100.
[0118] In this embodiment, a chemical vapor deposition process is used to form an adhesion layer 401 on the second substrate 400.
[0119] In this embodiment, the thickness of the adhesive layer 401 along the normal direction of the surface of the second substrate 400 is 10 nm to 500 nm. By making the thickness of the adhesive layer 401 greater than or equal to 10 nm, the overall height can be reduced while increasing the adhesion between the buffer layer 402 and the second substrate 400. By making the thickness of the adhesive layer 401 less than or equal to 500 nm, it is easier to control the formation process of the adhesive layer 401, which is beneficial to improving the flatness of the surface of the adhesive layer 401.
[0120] In this embodiment, the material of the adhesive layer 401 includes one or more two-dimensional semiconductor materials selected from Ge, GaAs, IGZO, WSe2, WS2, and MoS2. It is understood that in the aforementioned embodiments, the first type of metal layer is peeled off from the second substrate by mechanical peeling, and the second type of metal layer is peeled off from the second substrate by thermal peeling. In other embodiments, the first type of metal layer can be peeled off from the second substrate by thermal peeling, or the second type of metal layer can be peeled off from the second substrate by mechanical peeling.
[0121] See Figure 10 Multiple metal stacking operations are performed to form multiple first metal layers 202 on the first substrate 100.
[0122] In this embodiment, when multiple metal stacking operations are performed, the first metal layer 202 (or the second metal layer 404) that has been transferred to the first substrate 100 is the previous metal layer, and the first metal layer 202 (or the second metal layer 404) to be transferred to the first substrate 100 is the current metal layer.
[0123] See Figure 10 As a specific embodiment, for example, if two metal stacking operations are performed, the first sub-metal layer 2021 that has been transferred to the first substrate 100 is the previous metal layer, and the second sub-metal layer 2022 that is to be transferred to the first substrate 100 is the current metal layer; as another example, if three metal stacking operations are performed, before the formation of the third sub-metal layer 2023, the second sub-metal layer 2022 that has been transferred to the first substrate 100 is the previous metal layer, and the third sub-metal layer 2023 that is to be transferred to the first substrate 100 is the current metal layer.
[0124] Here, the front metal layer refers to the metal layer that has been transferred onto the first substrate 100 and is the furthest from the first substrate 100 along the normal to the surface of the first substrate 100.
[0125] In this embodiment, during the metal stacking operation, in the step of transferring the first metal layer 202 onto the first substrate 100, when the layer metal is attached to the previous metal layer.
[0126] For example, when the second sub-metal layer 2022 is the first metal layer 202 (or the second metal layer 404) to be transferred to the first substrate, the first sub-metal layer 2021 is the previous metal layer, and the second sub-metal layer 2022 is the current metal layer. Therefore, during the metal stacking operation, the second sub-metal layer 2022 is attached to the first sub-metal layer 2021. Similarly, when the third sub-metal layer 2023 is the first metal layer 202 to be transferred to the first substrate, the second sub-metal layer 2022 is the previous metal layer, and the third sub-metal layer 2023 is the current metal layer. Therefore, during the metal stacking operation, the third sub-metal layer 2023 is attached to the second sub-metal layer 2021. On the first metal layer 2022, when the fourth sub-metal layer 2024 is the first metal layer 202 to be transferred to the first substrate, the third sub-metal layer 2023 is the previous metal layer and the fourth sub-metal layer 2024 is the current metal layer. During the metal stacking operation, the fourth sub-metal layer 2024 is attached to the third sub-metal layer 2023. When the fifth sub-metal layer 2025 is the first metal layer 202 to be transferred to the first substrate, the fourth sub-metal layer 2024 is the previous metal layer and the fifth sub-metal layer 2025 is the current metal layer. During the metal stacking operation, the fifth sub-metal layer 2025 is attached to the fourth sub-metal layer 2024.
[0127] See Figure 10 In this embodiment, five first metal layers 202 are sequentially formed on the first substrate 100 for detailed explanation. In other embodiments, depending on the performance requirements of the semiconductor structure in the actual process, other numbers of first metal layers 202 (or second metal layers 404) may be formed.
[0128] See Figure 10 Multiple metal stacking operations can be performed on the first substrate 100 to form an initial magnetic tunneling stack structure 110 composed of multiple first metal layers 202. The initial magnetic tunneling stack structure 110 includes: a magnetic orientation reference film, a tunneling oxide film and a magnetic orientation free film stacked sequentially.
[0129] In this embodiment, by making the formation processes of the magnetic reference film, the tunneling oxide film, and the magnetic free film independent of each other and not affecting each other, the contact effect between the magnetic reference film and the tunneling oxide film, as well as the contact effect between the tunneling oxide film and the magnetic free film, can be improved. This can reduce the overall contact resistance of the initial magnetic tunnel stack structure 110 and improve the quality of the final tunnel stack structure.
[0130] See Figure 10In this embodiment, multiple metal stacking operations are performed on the first substrate 100 to form an initial magnetic tunnel junction stack structure 110 consisting of a second sub-metal layer 2022, a third sub-metal layer 2023, and a fourth sub-metal layer 2024.
[0131] In other words, the second sub-metal layer 2022 can serve as a magnetically oriented reference film, the third sub-metal layer 2023 can serve as a tunneling oxide film, and the fourth sub-metal layer 2024 can serve as a magnetically oriented free film.
[0132] In this embodiment, the initial magnetic tunneling stack structure 110 is used to form a magnetic tunneling stack structure after subsequent patterning processes.
[0133] Specifically, the magnetic reference film is used to form a magnetic reference layer through subsequent patterning processes. Therefore, the magnetization direction of the magnetic reference film is fixed, allowing the subsequent magnetic reference layer to serve as a reference layer for the magnetization direction of the subsequent magnetic free layer.
[0134] The tunneling oxide film is used to form the tunneling layer through subsequent patterning processes. The tunneling layer is the core component of the magnetic tunneling stack structure, and its formation quality determines the performance of the magnetic tunneling stack structure. For example, by improving the formation quality of the tunneling oxide layer, the tunnel magnetoresistance ratio (TMR ratio) can be increased, and leakage current can be reduced. Correspondingly, the performance of the magnetic tunneling stack structure is also improved.
[0135] The magneto-free membrane is used to form a magneto-free layer through a subsequent patterning process. The magnetization direction of the magneto-free layer has two stable orientations, which are parallel or opposite to the magnetization direction of the magneto-reference layer, respectively. This allows the magnetic tunnel stack structure to be in a low-resistivity or high-resistivity state.
[0136] Therefore, in this embodiment, the material of the second sub-metal layer 2022 includes CoFeB or CoFe, the material of the third sub-metal layer 2023 includes MgO, and the material of the fourth sub-metal layer 2024 includes CoFeB or CoFe.
[0137] In this embodiment, a third sub-metal layer 2023 is formed on the first substrate 100 by mechanical peeling; a second sub-metal layer 2022 and a fourth sub-metal layer 2024 are formed on the first substrate 100 by thermal peeling.
[0138] See Figure 11 The initial magnetic tunneling stacked structure 110 is graphically represented, forming the magnetic tunneling stacked structure 130.
[0139] The magnetic tunneling stacked structure 130 includes a magnetic reference layer 131, a tunneling layer 132, and a magnetic free layer 133 stacked sequentially.
[0140] In this embodiment, a dry etching process, such as anisotropic dry etching, is used to pattern the initial magnetic properties of the initial magnetic tunneling stack 110. Anisotropic dry etching has the characteristics of anisotropic etching, providing good control over the etching profile, which is beneficial for improving the profile morphology quality of the magnetic tunneling stack 130. Furthermore, the high etching precision of dry etching is beneficial for improving the pattern transfer accuracy of the patterning process.
[0141] See Figure 10 In this embodiment, during the process of performing multiple metal stacking operations on the first substrate 100, a bottom electrode (BE) material layer composed of the first metal layer 202 can also be formed.
[0142] In one specific embodiment, the first sub-metal layer 2021 can serve as the bottom electrode material layer.
[0143] In this embodiment, the material of the first sub-metal layer 2021 includes one or more of Ti, Ta, and TaN.
[0144] In one specific embodiment, the material of the first sub-metal layer 2021 includes TaN.
[0145] In this embodiment, a first sub-metal layer 2021 is formed on the first substrate 100 by mechanical peeling.
[0146] See Figure 11 In the step of patterning the initial magnetic tunnel junction stacked structure 110, the bottom electrode material layer is also patterned to form the bottom electrode layer 120.
[0147] The bottom electrode layer 120 is used to electrically connect the conductive plug 106 and the magnetic reference layer 131 in the magnetic tunnel junction stack structure 130.
[0148] See Figure 10 In this embodiment, multiple metal stacking operations are performed on the first substrate 100 to form a top electrode (TE) material layer composed of the first metal layer 202.
[0149] In one specific embodiment, the fifth sub-metal layer 2025 can serve as the top electrode material layer.
[0150] In this embodiment, the material of the fifth sub-metal layer 2025 includes one or more of Ti, Ta, and TaN.
[0151] In one specific embodiment, the material of the fifth sub-metal layer 2025 includes TaN.
[0152] In this embodiment, a fifth sub-metal layer 2025 is formed on the first substrate 100 by mechanical peeling.
[0153] See Figure 11 In the step of patterning the initial magnetic tunnel junction stacked structure 110, the top electrode material layer is also patterned to form the top electrode layer 140.
[0154] The top electrode layer 140 is used to realize the electrical connection between the magnetically free layer 133 in the magnetic tunnel junction stacked structure 130 and external circuits or other interconnection structures and components.
[0155] In this embodiment, the metal layer 102 closest to the first substrate 100 is electrically connected to the conductive plug 106. For example, the first sub-metal layer 2021 serves as the bottom electrode material layer, and the first sub-metal layer 2021 is electrically connected to the conductive plug 106.
[0156] In some other embodiments, one or more metal stacking operations can be performed on the first substrate to form a capacitor plate consisting of one or more metal layers.
[0157] It should be noted that, depending on the actual situation, during the process of performing multiple metal stacking operations on the first substrate, all metal layers can be separated from the second substrate by mechanical peeling, all metal layers can be separated from the second substrate by thermal peeling, or some metal layers can be separated from the second substrate by mechanical peeling and the remaining metal layers can be separated from the second substrate by thermal peeling.
[0158] While this specification discloses the invention as described above, the invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of this invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide the first base; One or more metal stacking operations are performed on the first substrate, the metal stacking operations including: providing a second substrate; forming a metal layer on the second substrate; performing a separation operation on the second substrate and the metal layer, and transferring the metal layer to the first substrate.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, In the case of performing multiple metal stacking operations, the metal layer that has been transferred to the first substrate is the previous metal layer, and the metal layer to be transferred to the first substrate is the current metal layer. In the step of transferring the metal layer onto the first substrate during the metal stacking operation, the current metal layer is attached to the previous metal layer.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, The method of performing the separation operation on the second substrate and the metal layer, and transferring the metal layer onto the first substrate, includes at least one of the following: Mechanical peeling; Thermal peeling.
4. The method for forming a semiconductor structure according to claim 3, characterized in that, The metal layer includes either a first type of metal layer or a second type of metal layer, and the adhesion between the first type of metal layer and the second substrate is less than the adhesion between the second type of metal layer and the second substrate. When the metal layer is a first type of metal layer, a mechanical peeling method is used to separate the second substrate and the metal layer, and transfer the metal layer onto the first substrate; When the metal layer is a second type of metal layer, a thermal peeling method is used to separate the second substrate and the metal layer, and transfer the metal layer to the first substrate.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, The materials of the first type of metal layer include one or more of Al, W, N, Co, Mo, Ti, Ta, TaN, and MgO; The materials for the second type of metal layer include one or more of Ag, Au, Pt, Pd, CoFeB, and CoFe.
6. The method for forming a semiconductor structure according to claim 3, characterized in that, The steps of separating the second substrate and the metal layer using a mechanical peeling method and transferring the metal layer onto the first substrate include: The metal layer is peeled off from the second substrate using a suction cup; After the metal layer is peeled off from the second substrate, it is transferred to the first substrate using the suction cup.
7. The method for forming a semiconductor structure according to claim 3, characterized in that, In the step of providing the second substrate, the second substrate also has a buffer layer, and the metal layer is located on the buffer layer; The steps of performing a separation operation between the second substrate and the metal layer using a thermal peeling method, and transferring the metal layer onto the first substrate, include: The second substrate is inverted on the first substrate, such that the metal layer is located on the first substrate; After the second substrate is inverted on the first substrate, a heating operation is performed on the second substrate to decompose the buffer layer, thereby separating the second substrate from the metal layer.
8. The method for forming a semiconductor structure according to claim 7, characterized in that, The melting point of the metal layer is higher than the decomposition temperature of the buffer layer.
9. The method for forming a semiconductor structure according to claim 7, characterized in that, The material of the buffer layer includes one or more of polypropylene carbonate, polyethylene carbonate, and highly branched polymers.
10. The method for forming a semiconductor structure according to claim 7, characterized in that, Along the normal direction of the second substrate surface, the thickness of the buffer layer is 100 nm to 1000 nm.
11. The method for forming a semiconductor structure according to claim 7, characterized in that, The buffer layer is formed on the second substrate using a spin coating process.
12. The method for forming a semiconductor structure according to claim 7, characterized in that, In the step of providing the second substrate, the second substrate also has an adhesive layer located between the second substrate and the buffer layer.
13. The method for forming a semiconductor structure according to claim 12, characterized in that, The material of the adhesive layer includes one or more of Ge, GaAs, IGZO, WSe2, WS2, and MoS2.
14. The method for forming a semiconductor structure according to claim 12, characterized in that, The thickness of the adhesive layer is 10 nm to 500 nm along the normal direction of the second substrate surface.
15. The method for forming a semiconductor structure according to claim 1, characterized in that, After forming a metal layer on the second substrate, and before performing a separation operation on the second substrate and the metal layer, the forming method further includes: annealing the metal layer.
16. The method for forming a semiconductor structure according to claim 1, characterized in that, Multiple metal stacking operations are performed on the first substrate to form an initial magnetic tunneling stack structure composed of multiple metal layers. The initial magnetic tunneling stack structure includes: a magnetic orientation reference film, a tunneling oxide film, and a magnetic orientation free film stacked sequentially. The initial magnetic tunneling stack structure is graphically represented to form a magnetic tunneling stack structure.
17. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of providing the first substrate, a dielectric layer is formed on the first substrate, a conductive plug is formed within the dielectric layer, and the top of the conductive plug is exposed by the dielectric layer. The metal layer closest to the first substrate is electrically connected to the conductive plug.