Shield gate trench type transistor and manufacturing method thereof
By forming multiple control gate electrode layers in a shielded gate trench transistor, the temperature and doping concentration are reduced, the problem of inter-gate dielectric layer breakdown is solved, and the quality and reliability of the transistor are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-08
- Publication Date
- 2026-03-10
Smart Images
Figure CN121645929A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a shield gate trench transistor and a manufacturing method thereof. BACKGROUND
[0002] Shield gate trench (SGT) transistor has more and more market share in the low-voltage application field below 250V because of its low specific on-resistance, low Miller capacitance, low power loss, small parasitic capacitance, high switching speed, and good high-frequency characteristics. However, the existing shield gate trench transistor is prone to gate dielectric breakdown, which seriously affects the performance of the device. Therefore, the technical personnel in the field have been working to solve this problem. SUMMARY
[0003] The present application relates to the technical field of semiconductor, in particular to a shield gate trench transistor and a manufacturing method thereof.
[0004] In order to solve the above technical problems, the present application provides a manufacturing method of a shield gate trench transistor, which comprises:
[0005] providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate;
[0006] forming a shield gate structure in the trench, wherein the shield gate structure comprises a shield gate dielectric layer and a shield gate electrode in the shield gate dielectric layer;
[0007] forming an inter-gate dielectric layer in the trench, wherein the inter-gate dielectric layer covers the shield gate structure; and
[0008] forming a control gate structure in the trench, wherein the control gate structure comprises a control gate dielectric layer on the inter-gate dielectric layer and a control gate electrode in the control gate dielectric layer, and the control gate electrode comprises a plurality of control gate electrode layers, and the formation temperature and / or the doping concentration of each control gate electrode layer decreases from the trench sidewall to the center of the trench.
[0009] Optionally, in the manufacturing method of the shield gate trench transistor, the thickness of each control gate electrode layer increases from the trench sidewall to the center of the trench.
[0010] Optionally, in the manufacturing method of the shield gate trench transistor, the control gate electrode is formed by a furnace tube process.
[0011] Optionally, in the method for manufacturing the shielded-gate trench transistor, the forming the control gate structure in the trench comprises:
[0012] forming a control gate dielectric layer in the trench, the control gate dielectric layer covering the gate dielectric layer and the sidewall of the trench and extending to cover the surface of the semiconductor substrate;
[0013] forming a first control gate electrode layer at a first process temperature and a first doping concentration, the first control gate electrode layer covering the control gate dielectric layer;
[0014] forming a second control gate electrode layer at a second process temperature and a second doping concentration, the second control gate electrode layer covering the first control gate electrode layer;
[0015] forming a third control gate electrode layer at a third process temperature and a third doping concentration, the third control gate electrode layer covering the second control gate electrode layer and filling the trench; and,
[0016] removing the first control gate electrode layer, the second control gate electrode layer and the third control gate electrode layer on the surface of the semiconductor substrate;
[0017] wherein the control gate electrode comprises the first control gate electrode layer, the second control gate electrode layer and the third control gate electrode layer reserved in the trench; the first process temperature is higher than or equal to the second process temperature, and the second process temperature is higher than or equal to the third process temperature; the first doping concentration is greater than or equal to the second doping concentration, and the second doping concentration is greater than or equal to the third doping concentration.
[0018] Optionally, in the method for manufacturing the shielded-gate trench transistor, the first process temperature and the second process temperature are between 500℃ and 700℃, and the third process temperature is between 400℃ and 600℃.
[0019] Optionally, in the method for manufacturing the shielded-gate trench transistor, the first doping concentration is 1.1 times to 3 times of the second doping concentration, and the third doping concentration is 0.
[0020] Optionally, in the method for manufacturing the shielded-gate trench transistor, the thickness of the first control gate electrode layer is between 0.5Å and 2Å, the thickness of the second control gate electrode layer is between 1Å and 3Å, and the thickness of the third control gate electrode layer is greater than 4Å.
[0021] Optionally, in the method for manufacturing the shielded-gate trench transistor, the method for manufacturing the shielded-gate trench transistor further comprises:
[0022] forming an interlayer dielectric layer covering the control gate structure and the semiconductor substrate;
[0023] forming an opening in the interlayer dielectric layer, the opening exposing the control gate structure; and,
[0024] forming a conductive plug in the opening, the conductive plug being connected with the control gate structure.
[0025] The present application also provides a shield gate trench transistor, which comprises:
[0026] a semiconductor substrate having a trench formed therein;
[0027] a shield gate structure in the trench, the shield gate structure comprising a shield gate dielectric layer and a shield gate electrode in the shield gate dielectric layer;
[0028] an intergate dielectric layer in the trench, the intergate dielectric layer covering the shield gate structure; and,
[0029] a control gate structure in the trench, the control gate structure comprising a control gate dielectric layer on the intergate dielectric layer and a control gate electrode in the control gate dielectric layer, wherein the control gate electrode comprises a plurality of control gate electrode layers, and the formation temperature and / or the doping concentration of each of the control gate electrode layers decrease from the trench sidewall to the center of the trench.
[0030] Optionally, in the shield gate trench transistor, the thickness of each of the control gate electrode layers increases from the trench sidewall to the center of the trench.
[0031] The inventor has found that the reason why the existing shield gate trench transistor is prone to intergate dielectric layer breakdown is that the existing control gate electrode has obvious gaps inside, which makes it easy to etch the intergate dielectric layer along the gaps in the subsequent etching process, thereby causing the existing shield gate trench transistor to be prone to intergate dielectric layer breakdown.
[0032] In the shield gate trench transistor and the manufacturing method thereof provided by the present application, a control gate structure is formed in the trench, the control gate structure comprising a control gate dielectric layer on an intergate dielectric layer and a control gate electrode in the control gate dielectric layer, the control gate electrode comprising a plurality of control gate electrode layers, and the formation temperature and / or the doping concentration of each of the control gate electrode layers decrease from the trench sidewall to the center of the trench, thereby forming a high-quality control gate electrode, avoiding the formation of gaps inside the control gate electrode, and thus avoiding the etching and breakdown of the intergate dielectric layer, and improving the quality and reliability of the shield gate trench transistor. BRIEF DESCRIPTION OF DRAWINGS
[0033] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
[0034] Figure 1 is a flow chart of a manufacturing method of a shield gate trench transistor according to an embodiment of the present application.
[0035] Figures 2 to 5 is a cross-sectional view of a structure formed by performing the manufacturing method of a shield gate trench transistor according to an embodiment of the present application.
[0036] In the drawings, the following signs are used:
[0037] 100 - semiconductor substrate; 110 - trench; 120 - shield gate structure; 121 - shield gate dielectric layer; 122 - shield gate electrode; 130 - gate dielectric layer; 140 - control gate structure; 141 - control gate dielectric layer; 142 - control gate electrode; 1420 - control gate electrode layer; 1420A - first control gate electrode layer; 1420B - second control gate electrode layer; 1420C - third control gate electrode layer. DETAILED DESCRIPTION
[0038] The shield gate trench transistor and the manufacturing method thereof according to the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will be more clearly understood from the following description and claims. It should be noted that the drawings are in extremely simplified form and are not drawn to precise scale, and are merely used to facilitate, clarify and aid in the understanding of the embodiments of the present application.
[0039] The terminology used by the inventor herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The articles "a", "an", and "the" as used herein are to be construed to mean "at least one" or "one or more", unless otherwise indicated to the contrary. As used herein, the terms "first", "second", and the like do not imply any order, quantity, or importance, but are used to distinguish one element from another. Also, the terms "one", "another", and the like do not preclude the existence of more than one, unless otherwise indicated to the contrary. The terms "comprise", "comprises", and the like are to be construed as open-ended terms (meaning that the comprising items do not exclude others) unless otherwise indicated to the contrary. The terms "connect", "connected", and the like are to be construed as possibly including a physical or mechanical connection, electrical connection, or both, unless otherwise indicated to the contrary. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0040] The inventor has found that the reason why the existing shielding gate trench transistor is prone to gate dielectric layer breakdown is that the control gate electrode formed by the prior art has obvious gaps inside, which causes the gate dielectric layer to be easily etched along the gaps in the subsequent etching process, thereby causing the existing shielding gate trench transistor to be prone to gate dielectric layer breakdown.
[0041] The core idea of the present application is to provide a shielding gate trench transistor and a manufacturing method thereof. A control gate structure is formed in a trench, the control gate structure comprising a control gate dielectric layer on a gate dielectric layer and a control gate electrode in the control gate dielectric layer, the control gate electrode comprising a plurality of control gate electrode layers, the formation temperature and / or the doping concentration of each control gate electrode layer decreasing from the trench sidewall to the center of the trench. In this way, a high-quality control gate electrode can be formed, and the formation of gaps inside the control gate electrode is avoided, thereby avoiding the etching of the gate dielectric layer and the breakdown of the gate dielectric layer, and improving the quality and reliability of the shielding gate trench transistor.
[0042] Please refer to Figure 1 which is a flowchart of the manufacturing method of the shielding gate trench transistor according to an embodiment of the present application. As shown in Figure 1As shown in the embodiments of the present application, the manufacturing method of the shield gate trench transistor comprises the following steps:
[0043] Step S10: providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate;
[0044] Step S20: forming a shield gate structure in the trench, wherein the shield gate structure comprises a shield gate dielectric layer and a shield gate electrode in the shield gate dielectric layer;
[0045] Step S30: forming an inter-gate dielectric layer in the trench, wherein the inter-gate dielectric layer covers the shield gate structure; and,
[0046] Step S40: forming a control gate structure in the trench, wherein the control gate structure comprises a control gate dielectric layer on the inter-gate dielectric layer and a control gate electrode in the control gate dielectric layer, and wherein the control gate electrode comprises a plurality of control gate electrode layers, and the formation temperature and / or the doping concentration of each of the control gate electrode layers decreases from the sidewall of the trench to the center of the trench.
[0047] Please refer to Figures 2 to 5 which is a cross-sectional schematic view of the structure formed by the manufacturing method of the shield gate trench transistor according to the embodiments of the present application.
[0048] As Figure 2 shown, a semiconductor substrate 100 is provided, wherein the material of the semiconductor substrate 100 can be silicon, silicon carbide, etc. The semiconductor substrate 100 can be a single-layer structure or a multi-layer structure. For example, in some embodiments of the present application, the semiconductor substrate 100 can comprise a single-layer bulk silicon substrate; in some other embodiments of the present application, the semiconductor substrate 100 can comprise a bulk silicon substrate and an epitaxial layer on the bulk silicon substrate.
[0049] Then, a trench 110 is formed in the semiconductor substrate 100, wherein the trench 110 extends from the surface of the semiconductor substrate 100 into the semiconductor substrate 100. In some embodiments of the present application, a patterned mask layer (not shown in the figure) can be formed on the semiconductor substrate 100 first, wherein the patterned mask layer exposes part of the semiconductor substrate 100; then, the exposed semiconductor substrate 100 is etched to form the trench 110 in the semiconductor substrate 100.
[0050] Please continue to refer to Figure 2Then, a shield gate structure 120 is formed in the trench 110, the shield gate structure 120 includes a shield gate dielectric layer 121 and a shield gate electrode 122 in the shield gate dielectric layer 121. The shield gate dielectric layer 121 can be, for example, silicon oxide, and the shield gate electrode 122 can be, for example, polysilicon.
[0051] In some embodiments of the present application, a shield gate dielectric material layer (not shown in the figure) is first formed in the trench 110, the shield gate dielectric material layer covers the surface of the trench 110 and can extend to cover the surface of the semiconductor substrate 100. The shield gate dielectric material layer can be formed by a deposition process or an oxidation process. Then, a shield gate electrode material layer (not shown in the figure) is deposited in the shield gate dielectric material layer; then, the shield gate electrode material layer is etched to form the shield gate electrode 122 at the bottom of the trench 110. In some embodiments of the present application, the shield gate dielectric material layer exposed by the shield gate electrode 122 can be removed by an etching process to form the shield gate dielectric layer 121.
[0052] In embodiments of the present application, then, an inter-gate dielectric layer 130 is formed in the trench 110, the inter-gate dielectric layer 130 covers the shield gate structure 120. The inter-gate dielectric layer 130 exposes the top of the trench 110. The inter-gate dielectric layer 130 can be a single-layer structure or a multi-layer stacked structure. In some embodiments of the present application, the inter-gate dielectric layer 130 can be a dielectric material such as silicon oxide or silicon nitride, which can be formed by a deposition process.
[0053] Please refer to Figures 2 to 5 In embodiments of the present application, then, a control gate structure 140 is formed in the trench 110, the control gate structure 140 includes a control gate dielectric layer 141 on the inter-gate dielectric layer 130 and a control gate electrode 142 in the control gate dielectric layer 141. In embodiments of the present application, the control gate electrode 142 includes a plurality of control gate electrode layers 1420, and the formation temperature and / or the doping concentration of each control gate electrode layer 1420 decreases from the sidewall of the trench 110 to the center of the trench 110. The formation temperature of the control gate electrode layer 1420 near the center of the trench 110 is lower than that of the control gate electrode layer 1420 far from the center of the trench 110, and / or the doping concentration of the control gate electrode layer 1420 near the center of the trench 110 is lower than that of the control gate electrode layer 1420 far from the center of the trench 110.
[0054] For example, in some embodiments of the present application, the forming temperature of the control gate electrode layer 1420 near the center of the trench 110 is lower than that of the control gate electrode layer 1420 far from the center of the trench 110, while the doping concentration of the control gate electrode layer 1420 near the center of the trench 110 is the same as that of the control gate electrode layer 1420 far from the center of the trench 110. For another example, in some embodiments of the present application, the forming temperature of the control gate electrode layer 1420 near the center of the trench 110 is the same as that of the control gate electrode layer 1420 far from the center of the trench 110, while the doping concentration of the control gate electrode layer 1420 near the center of the trench 110 is lower than that of the control gate electrode layer 1420 far from the center of the trench 110. For yet another example, in some embodiments of the present application, the forming temperature of the control gate electrode layer 1420 near the center of the trench 110 is lower than that of the control gate electrode layer 1420 far from the center of the trench 110, and the doping concentration of the control gate electrode layer 1420 near the center of the trench 110 is lower than that of the control gate electrode layer 1420 far from the center of the trench 110.
[0055] In some embodiments of the present application, the thickness of each control gate electrode layer 1420 increases from the sidewall of the trench 110 to the center of the trench 110. That is, the thickness of the control gate electrode layer 1420 near the center of the trench 110 is thicker than that of the control gate electrode layer 1420 far from the center of the trench 110. With the decrease of the forming temperature and / or doping concentration, the control gate electrode layer 1420 has better filling performance, thereby ensuring the quality of the formed control gate electrode 142. Meanwhile, the control gate electrode layer 1420 near the sidewall of the trench 110 has higher forming temperature and / or doping concentration, which can ensure the adhesion of the control gate electrode 142 to the sidewall and the electrical performance of the formed control gate electrode 142. The film structure performance and electrical performance of the control gate electrode 142 are improved.
[0056] In some embodiments of the present application, the doping ions in the control gate electrode layer 1420 can be phosphine, for example. The control gate electrode layer 1420 near the sidewall of the trench 110 has higher phosphorus concentration, so that the phosphine containing lone pair of electrons has stronger adsorption performance, ensuring the adhesion between the control gate electrode 142 and the control gate dielectric layer 141 and the electrical performance of the control gate electrode 142. The control gate electrode layer 1420 near the center of the trench 110 has relatively low doping concentration, which is beneficial to obtain smoother and more uniform thin film, thereby improving the filling quality.
[0057] In some embodiments of this application, the control gate electrode 142 is formed using a furnace tube process. That is, forming each control gate electrode layer 1420 using a furnace tube process can further improve the film quality of the control gate electrode layer 1420 and ensure the film structure performance and electrical performance of the control gate electrode 142.
[0058] For example, in some embodiments of this application, the control gate electrode 142 includes three control gate electrode layers 1420. These three layers of control gate electrode layers 1420 can achieve optimal formation temperature and / or doping concentration, significantly improving the quality of the formed control gate electrode 142 and preventing internal gaps. Simultaneously, the process is simple and easy to control. Here, from the sidewall of the trench 110 towards the center of the trench 110, the three control gate electrode layers 1420 are respectively a first control gate electrode layer 1420A, a second control gate electrode layer 1420B, and a third control gate electrode layer 1420C.
[0059] like Figure 2 As shown, in some embodiments of this application, a control gate dielectric layer 141 is first formed in the trench 110. The control gate dielectric layer 141 covers the inter-gate dielectric layer 130 and the sidewalls of the trench 110, and extends to cover the surface of the semiconductor substrate 100. The control gate dielectric layer 141 is made of, for example, silicon oxide. In some embodiments of this application, the control gate dielectric layer 141 can be formed by a deposition process.
[0060] Next, at a first process temperature and a first doping concentration, a first control gate electrode layer 1420A is formed, which covers the control gate dielectric layer 141. Here, the first control gate electrode layer 1420A is formed by a furnace tube process, wherein the material of the first control gate electrode layer 1420A is, for example, polycrystalline silicon.
[0061] like Figure 3 As shown, next, at a second process temperature and a second doping concentration, a second control gate electrode layer 1420B is formed, which covers the first control gate electrode layer 1420A. Figure 4 As shown, then, at a third process temperature and a third doping concentration, a third control gate electrode layer 1420C is formed, which covers the second control gate electrode layer 1420B and fills the trench 110. Figure 5As shown in this embodiment, the first control gate electrode layer 1420A, the second control gate electrode layer 1420B, and the third control gate electrode layer 1420C on the surface of the semiconductor substrate 100 are then removed, leaving the first control gate electrode layer 1420A, the second control gate electrode layer 1420B, and the third control gate electrode layer 1420C in the trench 110 to form the control gate electrode 142. In some embodiments of this application, the first control gate electrode layer 1420A, the second control gate electrode layer 1420B, and the third control gate electrode layer 1420C outside the trench 110 can be removed by a polishing process. The polishing process can stop at the surface of the control gate dielectric layer 141; it can also stop at the surface of the semiconductor substrate 100, thus exposing the semiconductor substrate 100.
[0062] Wherein, the first process temperature is higher than or equal to the second process temperature, and the second process temperature is higher than or equal to the third process temperature; the first doping concentration is greater than or equal to the second doping concentration, and the second doping concentration is greater than or equal to the third doping concentration.
[0063] In the embodiments of this application, the first process temperature and the second process temperature are between 500°C and 700°C, and the third process temperature is between 400°C and 600°C. This allows for a balance between the film formation quality and film formation speed of each control gate electrode layer 1420. For example, in some embodiments of this application, the first process temperature can be 580°C, the second process temperature can be 580°C, and the third process temperature can be 500°C.
[0064] In this embodiment, the first doping concentration is 1.1 to 3 times the second doping concentration, and the third doping concentration is 0. By gradient-setting the doping concentration of each control gate electrode layer 1420, both the film structure performance and electrical performance of the formed control gate electrode 142 are guaranteed. The first doping concentration can be, for example, 2E+16 atoms / cm². 3 The second doping concentration can be, for example, 1 E+16 atoms / cm 3 The third doping concentration is 0, that is, no doping.
[0065] In this embodiment, the thickness of the third control gate electrode layer 1420C is greater than the thickness of the second control gate electrode layer 1420B, and the thickness of the second control gate electrode layer 1420B is greater than the thickness of the first control gate electrode layer 1420A, to form a high-quality, high-reliability control gate electrode 142. In some embodiments of this application, the thickness of the first control gate electrode layer 1420A is between 0.5 Å and 2 Å, the thickness of the second control gate electrode layer 1420B is between 1 Å and 3 Å, and the thickness of the third control gate electrode layer 1420C is greater than 4 Å.
[0066] In some embodiments of this application, after forming the control gate structure 140, an interlayer dielectric layer (not shown in the figure) may be further formed, which covers the control gate structure 140 and the semiconductor substrate 100; an opening is formed in the interlayer dielectric layer, which exposes the control gate structure 140; and a conductive plug (not shown in the figure) is formed in the opening, which is connected to the control gate structure 140.
[0067] In this embodiment, a control gate structure 140 is formed in the trench 110. The control gate structure 140 includes a control gate dielectric layer 141 located on the inter-gate dielectric layer 130 and a control gate electrode 142 located in the control gate dielectric layer 141. The control gate electrode 142 includes multiple control gate electrode layers 1420. From the sidewall of the trench 110 towards the center of the trench 110, the formation temperature and / or doping concentration of each control gate electrode layer 1420 decreases, thereby forming a high-quality control gate electrode 142. This avoids the formation of gaps inside the control gate electrode 142, thereby preventing the inter-gate dielectric layer 130 from being etched and broken down, and improving the quality and reliability of the shielded gate trench transistor.
[0068] Accordingly, this application also provides a shielded gate trench transistor, please refer to... Figure 5The shielded gate trench transistor includes: a semiconductor substrate 100 in which a trench 110 is formed; a shielded gate structure 120 located in the trench 110, the shielded gate structure 120 including a shielded gate dielectric layer 121 and a shielded gate electrode 122 located in the shielded gate dielectric layer 121; an inter-gate dielectric layer 130 located in the trench 110, the inter-gate dielectric layer 130 covering the shielded gate structure 120; and a control gate structure 140 located in the trench 110, the control gate structure 140 including a control gate dielectric layer 141 located on the inter-gate dielectric layer 130 and a control gate electrode 142 located in the control gate dielectric layer 141, wherein the control gate electrode 142 includes multiple control gate electrode layers 1420, and the formation temperature and / or doping concentration of each control gate electrode layer 1420 decreases from the sidewall of the trench 110 to the center of the trench 110.
[0069] In some embodiments of this application, the thickness of each control gate electrode layer 1420 increases from the sidewall of the trench 110 toward the center of the trench 110.
[0070] The shielded gate trench transistor provided in this application embodiment has a high-quality control gate electrode 142, which avoids the formation of gaps inside the control gate electrode 142, thereby preventing the inter-gate dielectric layer 130 from being etched and broken down, and improving the quality and reliability of the shielded gate trench transistor.
[0071] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A manufacturing method of a shielded gate trench transistor, characterized by, The manufacturing method of the shield gate trench transistor comprises: providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate; forming a shield gate structure in the trench, wherein the shield gate structure comprises a shield gate dielectric layer and a shield gate electrode in the shield gate dielectric layer; forming an inter-gate dielectric layer in the trench, wherein the inter-gate dielectric layer covers the shield gate structure; and forming a control gate structure in the trench, wherein the control gate structure comprises a control gate dielectric layer on the inter-gate dielectric layer and a control gate electrode in the control gate dielectric layer, and wherein the control gate electrode comprises a plurality of control gate electrode layers, and the formation temperature and / or the doping concentration of each control gate electrode layer decreases from the trench sidewall to the center of the trench.
2. The manufacturing method of a shielded gate trench transistor according to claim 1, wherein The thickness of each control gate electrode layer increases from the trench sidewall to the center of the trench.
3. The manufacturing method of a shielded gate trench transistor according to claim 1, wherein The control gate electrode is formed by a furnace tube process.
4. The manufacturing method of a shielded gate trench transistor according to claim 1, wherein The forming of the control gate structure in the trench comprises: forming a control gate dielectric layer in the trench, wherein the control gate dielectric layer covers the inter-gate dielectric layer and the sidewall of the trench, and extends to cover the surface of the semiconductor substrate; forming a first control gate electrode layer at a first process temperature and a first doping concentration, wherein the first control gate electrode layer covers the control gate dielectric layer; forming a second control gate electrode layer at a second process temperature and a second doping concentration, wherein the second control gate electrode layer covers the first control gate electrode layer; forming a third control gate electrode layer at a third process temperature and a third doping concentration, wherein the third control gate electrode layer covers the second control gate electrode layer and fills the trench; and removing the first control gate electrode layer, the second control gate electrode layer and the third control gate electrode layer on the surface of the semiconductor substrate; wherein the control gate electrode comprises the first control gate electrode layer, the second control gate electrode layer and the third control gate electrode layer remaining in the trench, the first process temperature is higher than or equal to the second process temperature, the second process temperature is higher than or equal to the third process temperature, the first doping concentration is greater than or equal to the second doping concentration, and the second doping concentration is greater than or equal to the third doping concentration.
5. The manufacturing method of a shielded gate trench transistor according to claim 4, wherein The first process temperature and the second process temperature are between 500 ℃ and 700 ℃, and the third process temperature is between 400 ℃ and 600 ℃.
6. The manufacturing method of a shielded gate trench transistor according to claim 4, wherein The first doping concentration is 1.1 times to 3 times of the second doping concentration, and the third doping concentration is 0.
7. The manufacturing method of a shielded gate trench transistor according to claim 4, wherein The thickness of the first control gate electrode layer is between 0.5 Å and 2 Å, the thickness of the second control gate electrode layer is between 1 Å and 3 Å, and the thickness of the third control gate electrode layer is greater than 4 Å.
8. The manufacturing method of the shielded gate trench transistor according to one or more of claims 1 to 7, wherein The manufacturing method of the shield gate trench transistor further comprises: forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the control gate structure and the semiconductor substrate; forming an opening in the interlayer dielectric layer, wherein the opening exposes the control gate structure; and forming a conductive plug in the opening, wherein the conductive plug is connected with the control gate structure.
9. A shielded gate trench transistor, characterized by, The shield gate trench transistor comprises: A semiconductor substrate having a trench formed therein; A shield gate structure in the trench, the shield gate structure including a shield gate dielectric layer and a shield gate electrode in the shield gate dielectric layer; An intergate dielectric layer in the trench, the intergate dielectric layer covering the shield gate structure; and A control gate structure in the trench, the control gate structure including a control gate dielectric layer on the intergate dielectric layer and a control gate electrode in the control gate dielectric layer, wherein the control gate electrode includes a plurality of control gate electrode layers, each layer of the control gate electrode layers having a decreasing formation temperature and / or doping concentration from the trench sidewall toward the center of the trench.
10. The shielded gate trench transistor of claim 9, wherein, Each layer of the control gate electrode layers has an increasing thickness from the trench sidewall toward the center of the trench.