LDMOS and manufacturing method thereof

Abstract

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) and a manufacturing method thereof, and the manufacturing method comprises the following steps: providing a substrate, forming a gate oxide layer on the surface of the substrate, and forming a drift region and a body region which are arranged at an interval in the substrate; a step gate oxide layer is formed on the gate oxide layer above the drift region, a step gate is formed on the step gate oxide layer, and the step gate at least comprises a main gate and an auxiliary gate which are spaced by a certain distance; performing secondary injection at an inclined angle on the drift region, and forming doping concentration in stepped distribution in the drift region under the combined shielding effect of the stepped gate and the stepped gate oxide layer; forming a side wall on the side wall of the step gate; and respectively forming a drain electrode and a source electrode in the drift region and the body region. According to the invention, the on-resistance is effectively reduced while the high breakdown voltage of the device is ensured, and the purpose of reducing the power consumption is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to an LDMOS and its fabrication method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) is widely used in power semiconductor integrated circuits due to its advantages such as high breakdown voltage, high integration density, strong driving capability, and low power loss. Breakdown voltage (BV) and specific on-resistance (Rsp) are two key performance parameters of LDMOS. Typically, BV and Rsp are contradictory parameters. To ensure a high BV, the concentration of the N-type drift region or P-type channel formation region must be reduced, or the spacing between them must be increased, but these methods will increase Rsp. Therefore, it is crucial to find a way to reduce power consumption while maintaining high breakdown voltage performance. Summary of the Invention

[0003] The main objective of this invention is to provide an LDMOS and its fabrication method that effectively reduces on-resistance while ensuring a high breakdown voltage.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for fabricating LDMOS is provided, including the following steps: A substrate is provided, on which a gate oxide layer is formed, and within which drift regions and body regions are formed at intervals; A stepped gate oxide layer is formed on the gate oxide layer above the drift region, and a stepped gate is formed on the stepped gate oxide layer; the stepped gate includes at least a main gate and an auxiliary gate separated by a certain distance; wherein, the stepped gate oxide layer includes a first step surface of the bottom step and a second step surface of any step above the bottom step, the main gate covers a portion of the first step surface and a portion of the second step surface adjacent to one side of the step, and the auxiliary gate covers a portion of the first step surface adjacent to the other side of the step; Tilt-angle ion implantation is performed on the drift region, and under the combined shielding effect of the stepped gate and the stepped gate oxide layer, a stepped distribution of doping concentration is formed in the drift region. Sidewalls are formed on the sidewalls of the stepped gate; The drain and source are formed in the drift region and the body region, respectively.

[0005] Following the above technical solution, the steps also include: After forming the gate oxide layer, a first patterned mask layer is formed on it to define the source and isolation regions. The isolation regions are then etched on the substrate to isolate the source.

[0006] According to the above technical solution, the formation of the stepped gate includes the following steps: forming a second patterned mask layer on the gate oxide layer, etching the gate oxide layer above the drift region using the second patterned mask layer as a mask to form a stepped gate oxide layer; removing the second patterned mask layer; forming a polysilicon layer above the stepped gate oxide layer; forming a third patterned mask layer on the polysilicon layer, etching the polysilicon layer using the third patterned mask layer as a mask to form a stepped gate; and removing the third patterned mask layer.

[0007] Following the above technical solution, the stepped gate oxide layer includes at least one step above each drift region.

[0008] Following the above technical solution, a deep well region is also provided in the substrate in the direction away from the drift region, and a well region is provided on the side away from the deep well region and spaced apart from the drift region. The doping types of the substrate, deep well region, well region and body region are all the same, and the doping type of the drift region is opposite to the doping type of the substrate.

[0009] Following the above technical solution, the tilt angle of the tilt angle ion implantation is 30°~60°.

[0010] Following the above technical solution, a substrate is provided, on which a gate oxide layer is formed, and within which drift regions and body regions are formed at intervals, including: A gate oxide layer is formed on the substrate by a thermal oxidation process; Ion implantation is performed using the gate oxide layer as a masking layer to complete the doping of the deep trap region; Different patterned mask layers are formed on the gate oxide layer, and ion implantation is performed using different mask layers as masks to sequentially form the trap region, drift region and body region.

[0011] Following the above technical solution, when performing tilted ion implantation on the drift region, the implantation is performed from two directions at a cross tilt.

[0012] The present invention also provides an LDMOS, comprising: The substrate has drift regions and volume regions spaced apart inside it; A stepped gate oxide layer is located above the drift region, and a stepped gate is provided on the stepped gate oxide layer. The stepped gate includes at least a main gate and an auxiliary gate separated by a certain distance. The stepped gate oxide layer includes a first step surface of the bottom step and a second step surface of any step above the bottom step. The main gate covers a portion of the first step surface and a portion of the second step surface adjacent to one side of the step, and the auxiliary gate covers a portion of the first step surface adjacent to the other side of the step. Sidewalls, located on the sidewalls of the stepped gate; The drain and source are located in the drift region and the bulk region, respectively; The doping concentration in the drift region is formed through two implantations, the second of which is an implantation at an angle. Under the combined shielding effect of the stepped gate and the stepped gate oxide layer, a stepped doping concentration is formed in the drift region.

[0013] Following the above technical solution, the stepped gate is formed using polysilicon.

[0014] The beneficial effects of this invention are as follows: By optimizing the ion implantation steps in the drift region, the drift region is implanted twice at different process stages. During the second implantation, the drift region is implanted at a certain angle. Combined with the combined shielding effect of the stepped gate oxide structure and the stepped gate structure, the concentration of the drift region is controlled, thereby forming a stepped concentration distribution. The unexpected effect is that it can not only ensure the withstand voltage of the device, but also reduce the on-resistance of the device. In addition, no additional photomask is added to the entire process, saving costs.

[0015] Furthermore, the main gate is stepped, with one part located on the steps of the stepped gate oxide layer and the other part located on one side of the stepped gate oxide layer; the auxiliary gate is located on the other side of the stepped gate oxide layer. By setting the main gate and the auxiliary gate at different positions, a combined field plate for ion implantation is formed. Then, the ion implantation angle is adjusted to implant ions from two directions at a cross angle, further controlling the concentration of the drift region and forming a stepped distribution of the drift region concentration.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of the LDMOS fabrication method according to an embodiment of the present invention; Figures 2-8 These are schematic diagrams of various cross-sectional structures of LDMOS during the fabrication process according to an embodiment of the present invention.

[0019] In the figure: 101, substrate; 102, gate oxide layer; 103, isolation region; 104, deep well region; 105, well region; 106, drift region; 107, body region; 108, stepped gate oxide layer; 1081, first step surface; 1082, second step surface; 109, polysilicon layer; 110, auxiliary gate; 111, main gate; 112, sidewall; 113, gate; 114, drain; 115, source; PR, mask. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] In this invention, it should also be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0023] like Figures 1-8 As shown, the method for fabricating LDMOS according to an embodiment of the present invention includes the following steps: S1. A substrate 101 is provided, on which a gate oxide layer 102 is formed, and within which a drift region 106 and a body region 107 are formed at intervals. S2. A stepped gate oxide layer 108 is formed on the gate oxide layer 102 above the drift region 106, and a stepped gate is formed on the stepped gate oxide layer 108. The stepped gate includes at least a main gate 111 and an auxiliary gate 110 spaced apart by a certain distance. The stepped gate oxide layer 108 includes a first step surface 1081 of the bottom step and a second step surface 1082 of any step above the bottom step. The main gate 111 covers a portion of the first step surface 1081 and a portion of the second step surface 1082 adjacent to one side of the step, and the auxiliary gate 110 covers a portion of the first step surface 1081 adjacent to the other side of the step. S3. Tilt-angle ion implantation is performed on the drift region. Under the combined shielding effect of the stepped gate and the stepped gate oxide layer, a stepped distribution of doping concentration is formed in the drift region. S4. A sidewall is formed on the sidewall of the stepped gate; S5. Drain and source are formed in the drift region and body region, respectively.

[0024] like Figure 2 As shown, substrate 101 is a semiconductor substrate 101, which can be a silicon substrate 101, a germanium substrate 101, a silicon germanide substrate 101, silicon-on-insulator or germanium-on-insulator, etc., or it can be a substrate 101 including other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide, etc. In this embodiment of the invention, the material of substrate 101 is silicon. When substrate 101 is a P-type substrate 101, the doping ion is boron ion; when substrate 101 is an N-type substrate 101, the doping ion is phosphorus ion. In this embodiment of the invention, a P-type substrate 101 is used.

[0025] Step S1 specifically includes the following steps: S11. A gate oxide layer 102 is formed on the substrate by a thermal oxidation process; S12. Using the gate oxide layer 102 as a masking layer, ion implantation is performed to complete the doping of the deep well region 104; S13. Different patterned mask layers are formed on the gate oxide layer, and ion implantation is performed using different mask layers as masks to sequentially form the well region 105, the drift region 106 and the body region 107.

[0026] In step S11, the gate oxide layer 102 formed on the surface of the substrate 101 is mainly formed by a thermal oxidation process. Specifically, at a high temperature (typically 800°C - 1100°C), the surface of the substrate 101 undergoes a chemical reaction with an oxygen-containing substance (such as oxygen or water vapor) to generate a high-quality silicon dioxide (SiO2) thin film. The thickness of the gate oxide layer 102 can be 800 angstroms to 1000 angstroms. This gate oxide layer 102 is mainly used for the subsequent fabrication of the stepped gate oxide layer 108. After forming the gate oxide layer 102, a patterned mask layer (not shown in the figure) can be formed on it to define the source electrode 115 and the isolation region 103. The isolation region 103 is formed on the substrate 101 to isolate the source electrode 115. The isolation region 103 is slightly higher than the surface of the substrate 101 (because the isolation region 103 is formed on the basis of the gate oxide layer 102, and the gate oxide layer will continue to be etched later, so there is a height difference). One, two or more isolation regions 103 can be provided, which can be set as needed. In this embodiment of the invention, two are provided.

[0027] like Figure 3As shown, a drift region 106 and a body region 107 are formed spaced apart inside the substrate 101. The doping type of the body region 107 is the same as that of the substrate 101, while the doping type of the drift region 106 is different from that of the substrate 101. To adapt to the P-type substrate 101 of this embodiment, the drift region 106 is an N-type drift region 106, and the body region 107 is a P-type body region 107.

[0028] like Figure 3 As shown, a deep well region 104 is also provided at the bottom of the substrate 101 in the direction away from the drift region 106. A well region 105 is provided on the side away from the deep well region 104 and spaced apart from the drift region 106. The substrate 101, deep well region 104, well region 105 and body region 107 are all doped with the same type, which is P-type in this embodiment. The doping type of the drift region 106 is opposite to that of the substrate 101. The deep well region 104 (DPW, Deep P-Well) can be formed first, and this deep well region 104 is located at the bottom of the substrate 101. Then, the well region 105 (PW, P-Well) is formed by selective doping, followed by the drift region 106 (N-drift_1, N-type drift region), and finally the body region 107 (Pbody, P-type body region) is formed. The well region 105, drift region 106 and body region 107 are all located above the deep well region 104. The body region 107 is located between the two drift regions 106, and the well region 105 is located on both sides of the drift regions 106 and in the substrate 101 below the isolation region 103.

[0029] Specifically, when forming the deep well region 104, its doping can be done across the entire surface. That is, ion implantation is performed on the substrate 101 using the gate oxide layer 102 as a masking layer to complete the doping of the deep well region 104. Subsequent doping of the well region 105, drift region 106, and body region 107 can be performed using different photomasks. For example, when doping the well region 105, photoresist is spin-coated across the entire surface. Then, the area where the well region 105 is located is exposed and developed using a photomask. The photoresist at the location of the well region 105 is removed, while the photoresist at other locations, such as the drift region 106 and body region 107, is retained. This transfers the photomask pattern onto the photoresist. Using the patterned photoresist as a mask, ion implantation is performed at the location of the well region 105. Since the photoresist remains in other locations, no doped ions will enter, thus forming the doped well region 105. After the implantation of well region 105 is completed, the photoresist, having fulfilled its purpose, is thoroughly removed by chemical stripping or plasma ashing to prepare for the next process. Then, doping is performed at drift region 106 and body region 107 in the same manner, the difference being the use of different photomasks. Different pattern definitions are achieved using different and independent photomasks, thus completing the doping at different locations.

[0030] like Figure 4As shown, the formation of the stepped gate oxide layer 108 includes the following steps: forming a photoresist layer covering the surface of the gate oxide layer 102; defining the position and size of the stepped gate oxide layer 108 using a photomask; transferring the pattern on the photomask to the photoresist layer through exposure and development; using the patterned photoresist layer as a mask, etching the gate oxide layer 102 above the drift region 106 to form the stepped gate oxide layer 108; and removing the photoresist layer after the stepped gate oxide layer 108 is formed. The stepped gate oxide layer 108 includes at least one step, with a thick gate oxide region of 800 angstroms to 1000 angstroms at the step and a thin gate oxide region of 80 angstroms to 150 angstroms at the non-stepped areas.

[0031] Alternatively, a stepped gate oxide layer 108 can be formed by using a hard mask instead of the photoresist described above. The hard mask can be an inorganic hard mask, a metal hard mask, a carbon-based hard mask, or other special materials. In this embodiment of the invention, a carbon-based hard mask is preferred. The specific process of forming the stepped gate oxide layer 108 using a carbon-based hard mask is as follows: a carbon-based hard mask layer can be formed on the gate oxide layer 102 first; photoresist is then formed on the carbon-based hard mask layer; the position and size of the stepped gate oxide layer 108 are defined by a pre-set photomask, and the pattern on the photomask is transferred to the photoresist layer by exposure and development; using the patterned photoresist layer as a mask, the carbon-based hard mask layer is etched above the drift region 106, thereby transferring the photomask pattern onto the carbon-based hard mask layer; the photoresist layer is removed; the gate oxide layer 102 is then etched using the patterned carbon-based hard mask layer as a mask to form the stepped gate oxide layer 108; after the stepped gate oxide layer 108 is formed, the carbon-based hard mask layer can be removed as needed.

[0032] The stepped gate oxide layer 108 formed by the above method, such as Figure 4 As shown, the stepped gate oxide layer 108 may include a bottom step with a surface of a first step surface 1081. The stepped gate oxide layer 108 may also include a plurality of second steps located above the bottom step (located above the drift region 106), with the surface of the second steps being a second step surface 1082.

[0033] Refer to Figure 5 A polysilicon layer 109 is formed above the stepped gate oxide layer 108, which can be formed by chemical vapor deposition. The deposition thickness of the polysilicon layer 109 is 1500 Å to 3000 Å. Since it is deposited directly on the original stepped gate oxide layer 108, the deposited polysilicon layer 109 inherits the morphology of the stepped gate oxide layer 108. Because the thickness of the deposited polysilicon layer 109 is uniform, a stepped polysilicon layer 109 is also formed above the stepped gate oxide layer 108. Next, a stepped gate is formed on the polysilicon layer 109, such as... Figure 6As shown, specifically: a photoresist layer (not shown in the figure) is formed on the polysilicon layer 109; the position and size of the stepped gate are defined by a photomask; and the pattern on the photomask is transferred to the photoresist layer by exposure; the polysilicon layer 109 is etched to form the stepped gate using the photoresist layer as a mask; and the photoresist layer is removed after the stepped gate is formed. It is understandable that a hard mask (such as an inorganic hard mask) can also be used to form the stepped gate. Specifically, an inorganic hard mask layer can be formed on the polysilicon layer 109 first; photoresist can then be formed on the inorganic hard mask layer; the position and size of the stepped gate can be defined by a pre-set photomask, and the pattern on the photomask can be transferred to the photoresist layer by exposure and development; the inorganic hard mask layer can be etched using the patterned photoresist layer as a mask, thereby transferring the photomask pattern onto the inorganic hard mask layer; the photoresist layer can be removed; the polysilicon layer 109 can be etched again using the patterned inorganic hard mask layer as a mask to form the stepped gate; after the stepped gate is formed, the inorganic hard mask layer can be removed as needed.

[0034] like Figure 6 As shown, the stepped gate formed by the above method specifically includes at least a main gate 111 and an auxiliary gate 110 spaced apart by a certain distance. The main gate 111 covers a portion of the first step surface 1081 and a portion of the second step surface 1082 adjacent to one side of the second step, and the auxiliary gate 110 covers a portion of the first step surface 1081 adjacent to the other side of the second step. That is, the main gate 111 and the auxiliary gate 110, when combined, form a high and low stepped structure.

[0035] like Figure 7 As shown, in order to form a combined shielding effect with the stepped gate oxide layer 108, the stepped gate includes at least a main gate 111 and an auxiliary gate 110 spaced apart by a certain distance, with a spacing of 1 micrometer to 2 micrometers between the main and auxiliary gates. The width of the auxiliary gate 110 is 0.9 micrometers to 2 micrometers, and the width of the main gate 111 is 3 micrometers to 5 micrometers. In a preferred embodiment of the present invention, the main gate 111 is stepped, with a portion located on the steps of the stepped gate oxide layer 108 and a portion located on one side of the steps of the stepped gate oxide layer 108; the auxiliary gate 110 is located on the other side of the steps of the stepped gate oxide layer 108. The stepped gates on the two drift regions 106 are symmetrically arranged.

[0036] The stepped gate and the stepped gate oxide layer 108 together form a combined shield, which can serve as a field plate for the second ion implantation in the drift region 106, thus playing a role in variable doping of the drift region 106. Specifically, the drift region 106 undergoes a second implantation at a certain tilt angle, forming a low-depth heavy doping. Figure 7As shown, during the second ion implantation of drift region 106, ion implantation is performed from two directions with a crisscross tilt. The tilt angle for the second implantation is 30 to 60 degrees, and the implantation concentration is approximately at the E13 level. Before the second implantation, areas that do not need implantation, including body region 107, well region 105, and isolation region 103, can be masked by forming a mask PR. Specifically, after the stepped gate etching is completed, a photoresist layer is applied to the entire surface. The location and size of the area to be implanted for the second ion implantation are defined using a photomask, and the pattern on the photomask is transferred to the photoresist layer through exposure and development. Using this patterned photoresist layer as a mask, ion implantation is performed from two directions with a crisscross tilt until the doping of drift region 106 is completed. Finally, the photoresist layer is removed.

[0037] The ion implantation was uniform, but the final concentration distribution was stepwise due to the masking effect of the gate oxide combination with different heights. After annealing, the morphology of the second ion implantation drift region 106 is as follows. Figure 8 As shown, a stepped, gradually increasing doping concentration distribution is formed, with the doping concentration increasing along the extension direction of the isolation region 103 below the stepped gate. An unexpected effect is that, under the influence of the field plate, the increased concentration in the drift region 106 enhances the conductivity and reduces the resistance of this region, thereby reducing the on-resistance. Simultaneously, when voltage is applied to the gate 113, the electric field lines are uniformly distributed, giving it higher withstand voltage performance. This achieves both high withstand voltage performance and reduced specific on-resistance, ultimately reducing power consumption.

[0038] like Figure 8 As shown, sidewall 112 is then formed to form the sidewalls of the stepped gate. Sidewall 112 protects the sidewalls of the stepped gate from implantation damage during the subsequent formation of the source 115 and drain 114. Sidewall 112 can be a single-layer or multi-layer (≥2 layers) structure, and the material of sidewall 112 includes silicon oxide, silicon nitride, or other suitable materials. Then, N+ and P+ ion implantation is performed to form the drain 114 and source 115 in the drift region 106 and body region 107, respectively. Finally, subsequent processes such as SAB (isolation air bridge) are performed to obtain the LDMOS device structure as shown. Figure 8 As shown.

[0039] In summary, this invention achieves a stepped distribution of drift region 106 concentration by injecting the drift region 106 twice at different process stages, combined with the combined shielding effect of the stepped gate oxide structure and the stepped gate structure. The unexpected effect is that the electric field is optimized, which not only ensures a high breakdown voltage but also reduces the on-resistance, thereby reducing power consumption. Furthermore, the manufacturing process of this invention does not require an additional photomask, saving costs.

[0040] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0041] The order of the steps in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0042] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for fabricating an LDMOS, characterized in that, The method comprises the following steps: providing a substrate, forming a gate oxide layer on the surface of the substrate, and forming a drift region and a body region in the substrate; forming a stepped gate oxide layer on the gate oxide layer above the drift region, and forming a stepped gate on the stepped gate oxide layer; the stepped gate comprises at least a main gate and an auxiliary gate which are spaced apart; wherein the stepped gate oxide layer comprises a first step surface of the bottommost step and a second step surface of any step above the bottommost step, the main gate covers part of the first step surface and part of the second step surface on one side of the step, and the auxiliary gate covers part of the first step surface on the other side of the step; performing ion implantation at an inclined angle on the drift region, and forming a stepped distribution of doping concentration in the drift region under the combined shielding effect of the stepped gate and the stepped gate oxide layer; forming a sidewall on the sidewall of the stepped gate; forming a drain and a source in the drift region and the body region respectively.

2. The method of claim 1, wherein, The method further comprises the following steps: after the gate oxide layer is formed, defining a source and an isolation region by forming a first patterned mask layer thereon, etching the isolation region on the substrate by taking the first patterned mask layer as a mask, and isolating the source by the isolation region.

3. The method of claim 1, wherein, The formation of the stepped gate comprises the following steps: forming a second patterned mask layer on the gate oxide layer, etching the gate oxide layer to form the stepped gate oxide layer above the drift region by taking the second patterned mask layer as a mask; removing the second patterned mask layer, forming a polysilicon layer above the stepped gate oxide layer, forming a third patterned mask layer on the polysilicon layer, etching the polysilicon layer to form the stepped gate by taking the third patterned mask layer as a mask, and removing the third patterned mask layer.

4. The method of claim 3, wherein, The stepped gate oxide layer comprises at least one step above each drift region.

5. The method of claim 1, wherein, A deep well region is further arranged in the substrate away from the drift region, and a well region is arranged on the side away from the deep well region and spaced apart from the drift region; wherein the doping types of the substrate, the deep well region, the well region and the body region are the same, and the doping type of the drift region is opposite to the doping type of the substrate.

6. The method of claim 1-5, wherein, The inclined angle of the ion implantation at an inclined angle is 30°-60°.

7. The method of claim 1, wherein, The method comprises the following steps: forming a gate oxide layer on the substrate by a thermal oxidation process; performing ion implantation by taking the gate oxide layer as a mask to complete the doping of the deep well region; forming patterned different mask layers on the gate oxide layer, and performing ion implantation by taking different mask layers as masks to form the well region, the drift region and the body region in sequence.

8. The method of claim 1, wherein, When performing ion implantation at an inclined angle on the drift region, the ion implantation is performed at an inclined angle from two directions.

9. An LDMOS characterized in that, The method comprises the following steps: providing a substrate, forming a gate oxide layer on the surface of the substrate, and forming a drift region and a body region in the substrate; forming a stepped gate oxide layer above the drift region, and forming a stepped gate on the stepped gate oxide layer; the stepped gate comprises at least a main gate and an auxiliary gate which are spaced apart; wherein the stepped gate oxide layer comprises a first step surface of the bottommost step and a second step surface of any step above the bottommost step, the main gate covers part of the first step surface and part of the second step surface on one side of the step, and the auxiliary gate covers part of the first step surface on the other side of the step; forming a sidewall on the sidewall of the stepped gate; forming a drain and a source in the drift region and the body region respectively. In which the doping concentration of the drift region is formed by two implantations, wherein the second is an angled implantation, under the combined shadowing effect of the stepped gate and stepped gate oxide, a stepped distribution of doping concentration is formed in the drift region.

10. The LDMOS of claim 9, wherein, The stepped gate is formed by polysilicon.

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