Novel field effect transistor fused with memristor and preparation method of novel field effect transistor

Abstract

The invention provides a novel field effect transistor fused with a memristor and a preparation method of the novel field effect transistor, and belongs to the technical field of integrated circuit micro-nano electronic devices. A gate electrode on the substrate; the gate dielectric layer is located on the gate electrode; the drain electrode is located on the gate dielectric layer; the channel layer is located on the drain electrode; a source electrode and a first memristive electrode, wherein the source electrode and the first memristive electrode are both located on the channel layer; wherein the drain electrode is multiplexed as a second memristive electrode, the vertical projection of the first memristive electrode and the vertical projection of the drain electrode are at least partially overlapped, and the channel layer is arranged between the source electrode and the drain electrode and between the first memristive electrode and the drain electrode. The subthreshold swing limit of a traditional transistor is broken through, the power consumption of a device is effectively reduced, and the switching performance is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit micro-nano electronic device technology, and in particular to a novel field-effect transistor incorporating memristors and its fabrication method. Background Technology

[0002] In field-effect transistors (FETs), the subthreshold swing (SS) is a crucial indicator of the device's current-switching efficiency in the subthreshold region. In traditional FETs, charge carriers enter the channel via a thermal excitation mechanism, which imposes a theoretical limit on the subthreshold swing determined by this mechanism. Specifically, at room temperature (300K), the subthreshold swing cannot be reduced below 60 mV / dec. To overcome this limit, academia and industry have proposed various novel device solutions, such as tunneling FETs and negative capacitance FETs. However, these solutions suffer from issues such as low drive current, poor material compatibility, or continued reliance on the thermal excitation mechanism.

[0003] Memristors, based on the formation and breakage mechanism of metal-ion conductive channels, exhibit significant nonlinearity during device turn-on. Existing technologies include schemes that connect memristors and field-effect transistors in series at the drain electrode, achieving lower subthreshold swing. However, this drain electrode integrated structure is essentially two discrete devices connected in series, leaving room for improvement in integration density. Furthermore, the interface between the two independent devices introduces additional parasitic effects and performance losses. Summary of the Invention

[0004] This invention provides a novel field-effect transistor with integrated memristor and its fabrication method. By integrating the memristor into the channel of the transistor, the unique nonlinear switching characteristics of the memristor are utilized to achieve voltage distribution and current modulation in the subthreshold region, thereby breaking through the subthreshold swing limit of traditional transistors, effectively reducing device power consumption and improving switching performance.

[0005] In a first aspect, the present invention provides a novel field-effect transistor incorporating a memristor, comprising: Substrate; The gate electrode is located on the substrate; A gate dielectric layer is located on the gate electrode; The drain electrode is located on the gate dielectric layer; The channel layer is located on the drain electrode; A source electrode and a first memristor electrode, both of which are located on the channel layer; The drain electrode is reused as a second memristor electrode, the vertical projections of the first memristor electrode and the drain electrode at least partially overlap, the channel layer is disposed between the source electrode and the drain electrode, and between the first memristor electrode and the drain electrode.

[0006] According to the present invention, a novel field-effect transistor incorporating a memristor is provided, wherein the source electrode and the first memristor electrode are disposed on the same layer.

[0007] According to the present invention, a novel field-effect transistor incorporating a memristor is provided, wherein the material constituting the first memristor electrode includes at least one of tellurium, copper, silver, silver-tellurium alloy, silver-copper alloy, or silver-titanium alloy.

[0008] According to the present invention, a novel field-effect transistor incorporating a memristor is provided, wherein the material constituting the channel layer includes at least one of indium gallium zinc oxide, zinc oxide, indium oxide, tellurium oxide, molybdenum disulfide, or tungsten disulfide.

[0009] According to the present invention, a novel field-effect transistor incorporating a memristor is provided, wherein the thickness of the channel layer is greater than or equal to 20 nm and less than or equal to 30 nm.

[0010] In a second aspect, the present invention also provides a method for fabricating a novel field-effect transistor incorporating a memristor, for fabricating the novel field-effect transistor incorporating a memristor as described in the first aspect, the method comprising: Provide substrate wafers; A gate electrode is formed on the substrate wafer; A gate dielectric layer is formed on the gate electrode; A drain electrode is formed on the gate dielectric layer; A channel layer is formed on the drain electrode; A source electrode and a first memristor electrode are formed on the channel layer.

[0011] According to the method for fabricating a novel field-effect transistor incorporating a memristor provided by the present invention, after forming the first memristor electrode, the method further includes: The novel field-effect transistor is processed by an annealing process to allow active metal ions in the first memristor electrode to diffuse into the channel layer.

[0012] According to a method for fabricating a novel field-effect transistor incorporating a memristor provided by the present invention, the steps of forming the gate electrode, the gate dielectric layer, the drain electrode, the channel layer, the source electrode, and the first memristor electrode all include: Photoresist is coated onto the substrate wafer; The photoresist is exposed and developed according to a preset pattern to form a hollowed-out pattern area; A corresponding film layer is formed in the hollowed-out pattern area by a deposition process; The photoresist is removed by a stripping process to obtain a patterned corresponding film layer.

[0013] According to a method for fabricating a novel field-effect transistor incorporating a memristor provided by the present invention, after forming the hollowed-out pattern region, the method further includes: The hollowed-out pattern area is treated with oxygen ions to remove residual photoresist in the hollowed-out pattern area.

[0014] Thirdly, the present invention also provides an electronic device comprising a novel field-effect transistor incorporating a memristor as described in the first aspect.

[0015] This invention achieves true device-level integration by reusing the drain electrode as a second memristor electrode and vertically integrating the memristor functional layer (i.e., the first memristor electrode, the channel layer, and the drain electrode). This avoids the parasitic resistance and capacitance caused by two independent devices connected in series, reduces process steps, and significantly improves integration density. Simultaneously, by utilizing the nonlinearity of the memristor turn-on process to modulate the subthreshold characteristics of the transistor, it provides a novel and effective technical path to overcome the theoretical limit of the subthreshold swing of traditional field-effect transistors. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic cross-sectional view of a novel field-effect transistor incorporating a memristor, provided in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram illustrating the flow of charge carriers and active metal ions in a novel field-effect transistor with integrated memristor provided in an embodiment of the present invention when it is in the non-conducting state.

[0019] Figure 3 This is a schematic diagram illustrating the flow of charge carriers and active metal ions in a novel field-effect transistor that integrates a memristor, as provided in an embodiment of the present invention, when the transistor is in the on-state.

[0020] Figure 4 This is a schematic diagram of the subthreshold swing of a conventional field-effect transistor in the prior art.

[0021] Figure 5 This is a schematic diagram of the subthreshold swing of the novel field-effect transistor with integrated memristor provided in the embodiments of the present invention.

[0022] Figure 6 This is a schematic flowchart illustrating a novel field-effect transistor incorporating a memristor, as provided by this invention.

[0023] Figure 7 This is a schematic diagram illustrating the specific process of fabricating a novel field-effect transistor incorporating a memristor, as provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] In field-effect transistors (FETs), subthreshold swing is a crucial indicator of the device's current-switching efficiency in the subthreshold region. In traditional FETs, charge carriers enter the channel via a thermal excitation mechanism, which imposes a theoretical limit on the subthreshold swing determined by this mechanism. Specifically, at room temperature (300K), the subthreshold swing cannot be reduced below 60 mV / dec. To overcome this limit, academia and industry have proposed various novel device solutions, such as tunneling FETs and negative capacitance FETs. However, these solutions suffer from issues such as low drive current, poor material compatibility, or continued reliance on the thermal excitation mechanism.

[0026] Memristors, based on the formation and breakage mechanism of metal-ion conductive channels, exhibit significant nonlinearity during device turn-on. Existing technologies include schemes that connect memristors and field-effect transistors in series at the drain electrode, achieving lower subthreshold swing. However, this drain electrode integrated structure is essentially two discrete devices connected in series, leaving room for improvement in integration density. Furthermore, the interface between the two independent devices introduces additional parasitic effects and performance losses.

[0027] In field-effect transistors (FETs), subthreshold swing is a crucial indicator of the device's current-switching efficiency in the subthreshold region. Traditional FETs allow charge carriers to enter the channel via thermal excitation, resulting in a theoretical limit to the subthreshold swing determined by this mechanism. Specifically, even at room temperature (300K), the subthreshold swing cannot be reduced below 60 mV / dec. To overcome this limit, academia and industry have proposed various novel device solutions. For example, tunneling FETs optimize subthreshold characteristics by replacing thermal excitation with band tunneling, but suffer from low drive current. Negative capacitance FETs utilize the negative capacitance effect of ferroelectric materials to enhance gate electrode coupling, achieving subthreshold voltage amplification, but face challenges related to material compatibility and stability. FETs based on two-dimensional materials improve subthreshold swing by reducing channel thickness and enhancing electrostatic control, but are still limited by the thermal excitation mechanism.

[0028] Memristors (Conductive Bridging Random Access Memory, CBRAM), based on the formation and breakage mechanism of metal-ion conductive channels, exhibit significant nonlinearity during device turn-on, i.e., the formation of conductive channels. By rationally combining memristors with field-effect transistors (FETs) and utilizing the voltage divider principle, the subthreshold characteristics of the transistor can be replaced by the turn-on characteristics of the memristor, resulting in a smaller subthreshold swing. This method differs from traditional gate-electrode-controlled approaches; instead, it leverages the inherent characteristics of series-connected devices to overcome the subthreshold swing limitation, providing a new pathway to achieve a subthreshold swing exceeding 60 mV / dec. Existing technologies integrate memristors into the drain electrode of transistors, achieving a subthreshold swing of 4 mV / dec. However, this drain electrode integration structure is essentially two discrete devices connected in series, leaving room for improvement in integration density, and the interface between the two independent devices introduces additional parasitic effects and performance losses.

[0029] To address the aforementioned technical problems, this invention innovatively proposes to directly embed the memristor into the transistor ground channel region, making it a complete device. This not only enhances the subthreshold response characteristics but also further improves the integration density, avoiding the problem of additional parasitic effects and performance loss introduced by the interface between independent devices. Figure 1 This is a schematic cross-sectional view of a novel field-effect transistor incorporating a memristor, provided in an embodiment of the present invention. A novel field-effect transistor integrating memristors includes a substrate D100, a gate electrode D200, a gate dielectric layer D300, a drain electrode D400, a channel layer D500, a source electrode D600, and a first memristor electrode D700. The gate electrode D200 is located on the substrate D100, the gate dielectric layer D300 is located on the gate electrode D200, the drain electrode D400 is located on the gate dielectric layer D300, the channel layer D500 is located on the drain electrode D400, and the source electrode D600 and the first memristor electrode D700 are both located on the channel layer D500. The drain electrode D400 is multiplexed as a second memristor electrode, and the vertical projections of the first memristor electrode D700 and the drain electrode D400 at least partially overlap. The channel layer D500 is disposed between the source electrode D600 and the drain electrode D400, and also between the first memristor electrode D700 and the drain electrode D400.

[0030] Specifically, substrate D100 is the base material supporting the entire device structure, typically a silicon wafer. Gate electrode D200 is the electrode used to apply a voltage to control the carrier concentration in channel layer D500. Gate dielectric layer D300 is an insulating layer located between gate electrode D200 and channel layer D500, serving as insulation and capacitive coupling. Drain electrode D400 is the output electrode of the field-effect transistor. Channel layer D500 is a semiconductor layer connecting source electrode D600 and drain electrode D400, whose conductivity is controlled by gate electrode D200. Source electrode D600 is the input electrode of the field-effect transistor. First memristor electrode D700 is the active electrode of the memristor, composed of an easily oxidized active metal, used to provide active metal ions for forming conductive filaments. Second memristor electrode is the inert electrode of the memristor, used to collect active metal ions and form conductive filaments. The vertical projections at least partially overlap when viewed from above, meaning that the projection of the first memristor electrode D700 onto the substrate D100 overlaps with the projection of the drain electrode D400 onto the substrate D100.

[0031] The core of this invention lies in directly embedding the memristor inside the transistor, rather than simply connecting them in series. For the operation of a field-effect transistor (FET), when a voltage is applied to the gate electrode D200, a conductive channel is induced in the channel layer D500. At this time, if a voltage is applied between the source electrode D600 and the drain electrode D400, electrons will flow from the source electrode D600 through the channel layer D500 to the drain electrode D400, forming the transistor's conduction current. The drain electrode D400 normally fulfills its function as the output electrode of the FET during this process. For the operation of the memristor, the memristor function is mainly realized between the first memristor electrode D700 and the second memristor electrode, i.e., the multiplexed drain electrode D400. When a positive voltage relative to the drain electrode D400 is applied to the first memristor electrode D700, active metal atoms, such as silver, in the first memristor electrode D700 are oxidized into metal ions, such as silver ions, and migrate to the lower channel layer D500 under the drive of the electric field. These ions gain electrons during migration, reducing to metal atoms and gradually forming a conductive filament within the channel layer D500 region between the first memristor electrode D700 and the drain electrode D400. The formation of this conductive filament is equivalent to connecting a variable resistor in parallel between the first memristor electrode D700 and the drain electrode D400. When the conductive filament is fully formed, the memristor is in a low-resistance state; when a reverse voltage is applied, the conductive filament breaks, and the memristor returns to a high-resistance state.

[0032] The switching process of a memristor synergizes with the subthreshold operating region of a field-effect transistor. In the subthreshold region, the gate voltage is low, the channel conductivity is weak, and the source-drain current is very small. At this point, the nonlinear current-voltage characteristics of the memristor, connected in series in the current path, begin to dominate the overall current response of the device. When the memristor is in the critical state before turning on, its equivalent resistance changes drastically with the voltage. This change is reflected in the gate voltage, so that a small change in gate voltage can cause a large change in source-drain current, thus achieving a subthreshold swing of less than 60 mV / dec, for example, less than 10 mV / dec.

[0033] Figure 2 This is a schematic diagram illustrating the flow of charge carriers and active metal ions in a novel field-effect transistor with integrated memristor provided in an embodiment of the present invention when it is in the non-conducting state. Figure 3 This is a schematic diagram illustrating the flow of charge carriers and active metal ions in a novel field-effect transistor that integrates a memristor, as provided in an embodiment of the present invention, when the transistor is in the on-state.

[0034] Combination Figure 1 and Figure 2 When the field-effect transistor is in the non-conducting state, a conductive circuit cannot be formed between the source electrode D600 and the drain electrode D400 through charge carriers, and a conductive filament cannot be formed between the first memristor electrode D700 and the second memristor electrode through active metal ions, such as silver ions. Figure 1 and Figure 3 When the field-effect transistor is in the on state, a conducting circuit is formed between the source electrode D600 and the drain electrode D400 through charge carriers, and a conductive filament is formed between the first memristor electrode D700 and the second memristor electrode through active metal ions, such as silver ions.

[0035] Figure 4 This is a schematic diagram of the subthreshold swing of a conventional field-effect transistor in the prior art. Figure 5 This is a schematic diagram of the subthreshold swing of the novel field-effect transistor with integrated memristor provided in the embodiments of the present invention. Figure 4 and Figure 5 The horizontal axis represents the gate-source voltage in volts, and the vertical axis represents the source-drain current in microamps. For example... Figure 4 As shown, the subthreshold swing of a conventional field-effect transistor in the prior art is greater than 60mV / dec, while the subthreshold swing of the novel field-effect transistor with integrated memristor provided in this embodiment of the invention is less than 10mV / dec.

[0036] Therefore, this invention achieves true device-level integration by reusing the drain electrode D400 as the second memristor electrode and vertically integrating the memristor functional layer, namely the first memristor electrode D700, the channel layer D500, and the drain electrode D400. This avoids the parasitic resistance and capacitance caused by two independent devices connected in series, reduces process steps, and significantly improves integration density. Simultaneously, by utilizing the nonlinearity of the memristor turn-on process to modulate the subthreshold characteristics of the transistor, it provides a new and effective technical path to break through the theoretical limit of the subthreshold swing of traditional field-effect transistors.

[0037] It should be noted that the field-effect transistor of the present invention is preferably an N-type transistor. It is understood that those skilled in the art, after reading this invention, who can obtain a P-type channel material with comparable performance, such as a specific two-dimensional material or oxide, and apply it to this fused structure, should also fall within the protection scope of this invention.

[0038] In some embodiments, such as Figure 1 As shown, the source electrode D600 and the first memristor electrode D700 can be configured to be on the same layer. Compared with configuring the source electrode D600 and the first memristor electrode D700 to be on different layers, based on the above embodiment, it is beneficial to further reduce the size of the novel field-effect transistor with integrated memristor, increase the integration density of the novel field-effect transistor with integrated memristor, and realize the miniaturization of the novel field-effect transistor with integrated memristor.

[0039] In some embodiments, the material constituting the first memristor electrode D700 includes at least one of tellurium, copper, silver, silver-tellurium alloy, silver-copper alloy, or silver-titanium alloy.

[0040] Specifically, the material constituting the first memristor electrode D700 is the substance used to form it; these substances are active metals or alloys capable of undergoing redox reactions and generating ion migration under an applied electric field. As the ion source for the memristor, the material selection for the first memristor electrode D700 is crucial. Taking silver as an example, when a positive bias is applied to the first memristor electrode D700, silver atoms lose electrons and are oxidized into silver ions. These silver ions, under the influence of the electric field, cross the interface of the channel layer D500 and migrate towards the negatively charged drain electrode D400, i.e., the second memristor electrode. During migration, the silver ions gain electrons from the channel layer D500 or the drain electrode D400 and are reduced back to silver atoms, gradually accumulating to form silver conductive filaments. Tellurium, copper, and their alloys all possess similar electrochemical activity and can effectively provide migrating ions.

[0041] Therefore, the embodiments of the present invention utilize active metals or alloys such as tellurium, copper, silver, silver-tellurium alloys, silver-copper alloys, or silver-titanium alloys to ensure the formation of stable and controllable conductive filaments, thereby enabling the memristor to possess excellent on / off ratio, cycle durability, and data retention characteristics. Furthermore, these materials exhibit good compatibility with processes such as low-temperature deposition and annealing, providing a reliable guarantee for achieving high-performance memristor functionality.

[0042] In some embodiments, the material constituting the channel layer D500 includes at least one of indium gallium zinc oxide, zinc oxide, indium oxide, tellurium oxide, molybdenum disulfide, or tungsten disulfide.

[0043] Specifically, the material constituting the channel layer D500 is the semiconductor material used to form the channel layer D500. As the channel of the field-effect transistor, the channel layer D500, composed of indium gallium zinc oxide, zinc oxide, indium oxide, tellurium oxide, molybdenum disulfide, or tungsten disulfide, possesses suitable band gaps and carrier mobilities to ensure the basic switching and amplification functions of the field-effect transistor. As the dielectric layer of the memristor, the channel layer D500, containing indium gallium zinc oxide, zinc oxide, indium oxide, tellurium oxide, molybdenum disulfide, or tungsten disulfide, contains certain vacancies and defects, providing migration channels and nucleation sites for metal ions from the first memristor electrode D700, thereby assisting in the formation and breakage of conductive filaments.

[0044] Therefore, embodiments of the present invention utilize indium gallium zinc oxide, zinc oxide, indium oxide, tellurium oxide, molybdenum disulfide, or tungsten disulfide materials to realize novel field-effect transistors integrating memristors. Furthermore, indium gallium zinc oxide, zinc oxide, indium oxide, and tellurium oxide materials are suitable for low-temperature processes, compatible with flexible electronics technology, and possess high mobility, which is beneficial for achieving high drive currents in field-effect transistors. Two-dimensional materials such as molybdenum disulfide and tungsten disulfide possess atomically flat surfaces and the characteristic of being free of dangling bonds, providing a highly controllable interface for the formation of conductive filaments, significantly improving the uniformity and reliability of memristor performance.

[0045] In some embodiments, such as Figure 1 As shown, the thickness of the channel layer D500 is greater than or equal to 20 nm and less than or equal to 30 nm.

[0046] Specifically, the thickness refers to the vertical dimension of the channel layer D500, and its thickness is a key parameter for balancing transistor and memristor performance. If the channel layer D500 is too thin, although the gate control capability is enhanced, when used as the memristor dielectric layer, it is prone to forming irreversible, excessively thick conductive filaments, causing the memristor to fail to turn off and lose its switching function. If the channel layer D500 is too thick, the control force of the gate electrode D200 over the bottom of the channel is weakened, and the subthreshold characteristics of the transistor deteriorate; at the same time, the voltage required to form the conductive filaments will increase significantly, power consumption will increase, and the filament formation path will be long, random, and the device uniformity will be poor.

[0047] Therefore, by setting the thickness of the channel layer D500 to be greater than or equal to 20 nm and less than or equal to 30 nm, this embodiment of the invention ensures that the field-effect transistor has good gate control capability and drive current, while also ensuring that the memristor forms a stable and repeatedly fractured conductive filament under a moderate voltage. This achieves synergistic optimization of transistor and memristor characteristics. Within this range, both the field-effect transistor and the memristor can exhibit optimal or near-optimal performance, working together to ultimately enable the fused device to stably achieve an extremely low subthreshold swing of less than 10 mV / dec.

[0048] This invention also provides a method for fabricating a novel field-effect transistor that integrates a memristor. Figure 6 This is a schematic flowchart illustrating a method for fabricating a novel field-effect transistor integrating a memristor, as provided by this invention. The method for fabricating this novel field-effect transistor integrating a memristor can be used to fabricate novel field-effect transistors integrating memristors as described in the above embodiments. Figure 6 As shown, the fabrication method of the novel field-effect transistor integrating memristors includes the following steps: Step 101: Provide a substrate wafer.

[0049] Step 102: Form a gate electrode on the substrate wafer.

[0050] In some embodiments, the steps of forming the gate electrode, gate dielectric layer, drain electrode, channel layer, source electrode, and first memristor electrode all include: coating photoresist on a substrate wafer; exposing and developing the photoresist according to a preset pattern to form a cutout pattern area; forming a corresponding film layer in the cutout pattern area by a deposition process; and removing the photoresist by a stripping process to obtain the patterned corresponding film layer.

[0051] Specifically, photoresist is first coated and patterned on a substrate wafer, then a functional thin film is deposited, and finally the photoresist is removed using a solvent, simultaneously peeling off the thin film covering the photoresist, leaving only the thin film within the perforated pattern areas. This peeling process is suitable for forming the finely stacked, multi-layered metal electrode patterns provided by this invention. Using the photoresist pattern as a mask, the deposited thin film adheres directly to the substrate or lower layer in the perforated pattern areas, while covering the photoresist in the non-perforated pattern areas. When the photoresist is dissolved using a solvent, the thin film covering it is washed away due to loss of support, ultimately obtaining the desired pattern. Therefore, this embodiment of the invention uses a peeling process to pattern each layer, particularly for the metal electrode layer, resulting in a film layer with clear edges and high pattern precision, which is crucial for the performance of the nanoscale devices provided by this invention.

[0052] In some embodiments, after forming the cutout pattern area, the method further includes: treating the cutout pattern area with oxygen ions to remove residual photoresist in the cutout pattern area.

[0053] Specifically, oxygen ion treatment is a process of bombarding and cleaning residual photoresist in the patterned areas using oxygen ions after the pattern has been formed. After photoresist exposure and development, trace amounts of photoresist debris may remain in the patterned areas. Oxygen ion treatment, through physical bombardment and chemical reaction, effectively decomposes and removes these residues, exposing a clean substrate or underlying film surface. This significantly improves the interface quality of subsequently deposited films, reduces interface defects, lowers contact resistance, and thus enhances the overall electrical performance, reliability, and yield of the device.

[0054] In fabricating novel field-effect transistors incorporating memristors, a silicon dioxide insulating layer is first grown by thermal oxidation on a substrate wafer, such as a silicon wafer, to provide electrical isolation between discrete devices. Silicon dioxide has the advantage of isolating external electrical interference, allowing the device to be controlled only by electrical signals from the electrodes. It should be noted that... Figure 1 The silicon dioxide insulating layer on the substrate is not shown. It can be understood that subsequent film layers starting from the gate electrode can also be located above the silicon dioxide insulating layer.

[0055] Photoresist is then coated onto the substrate wafer. The photoresist is exposed and developed according to a pre-defined pattern corresponding to the gate electrode, thereby forming a cutout pattern area for the gate electrode. Subsequently, the cutout pattern area is treated with oxygen ions to completely remove residual photoresist from the gate electrode area, thus reducing the influence of residual organic matter. A gate electrode layer is formed in the cutout pattern area using, for example, physical deposition, followed by a lift-off method to obtain the patterned gate electrode layer. Exemplarily, the gate electrode layer material can be an inert metal such as platinum, palladium, gold, ruthenium, or tungsten, or a compound such as titanium nitride, tantalum nitride, or indium tin oxide, and its thickness can be set to 20 nm to 30 nm.

[0056] Step 103: Form a gate dielectric layer on the gate electrode.

[0057] Specifically, photoresist is coated onto the gate electrode, and the photoresist is exposed and developed according to a preset pattern corresponding to the gate dielectric layer to obtain a hollow pattern area of ​​the gate dielectric layer. Subsequently, oxygen ion treatment is used to completely remove residual photoresist from the gate dielectric layer area, thereby reducing the influence of residual organic matter. In the hollow pattern area, a gate dielectric layer is formed using methods such as low-temperature atomic layer deposition and physical deposition, followed by a lift-off method to obtain the patterned gate dielectric layer. For example, the gate dielectric layer material can be a compound such as silicon oxide, hafnium oxide, titanium oxide, aluminum oxide, tantalum oxide, or hafnium aluminum oxide, and its thickness can be set to 20 nm to 30 nm. Furthermore, after forming the gate dielectric layer, the substrate wafer can be subjected to rapid annealing in an oxygen environment, for example, a rapid annealing process of 30 to 300 seconds at an annealing temperature of 300°C to 600°C.

[0058] Step 104: Form a drain electrode on the gate dielectric layer.

[0059] Specifically, photoresist is coated onto the gate dielectric layer, and the photoresist is exposed and developed according to a preset pattern corresponding to the drain electrode to obtain a hollow pattern area of ​​the drain electrode layer. Subsequently, the hollow pattern area is treated with oxygen ions to completely remove residual photoresist in the drain electrode area, thereby reducing the influence of residual organic matter. In the hollow pattern area, a drain electrode layer is formed by, for example, physical deposition, and then a stripping method is used to obtain the patterned drain electrode. Exemplarily, the drain electrode material can be metals such as aluminum, gold, copper, platinum, and chromium, and its thickness can be set to 5 nm to 10 nm.

[0060] Step 105: Form a channel layer on the drain electrode.

[0061] Specifically, photoresist is coated on the drain electrode, and the photoresist is exposed and developed according to a preset pattern corresponding to the communication layer to obtain the hollow pattern area of ​​the channel layer. Subsequently, oxygen ion treatment is used to treat the hollow pattern area to completely remove the photoresist remaining in the channel layer area, thereby reducing the influence of residual organic matter. In the hollow pattern area, the channel layer is formed by methods such as atomic layer deposition or physical deposition, and then a stripping method is used to obtain the patterned channel layer. The channel layer material can be a metal oxide semiconductor such as indium gallium zinc oxide, zinc oxide, indium oxide, or tellurium oxide, or a two-dimensional material such as molybdenum disulfide or tungsten disulfide, and its thickness can be set to 20nm to 30nm.

[0062] Step 106: Form the source electrode and the first memristor electrode on the channel layer.

[0063] Specifically, photoresist is coated onto the channel layer, and the photoresist is exposed and developed according to a preset pattern corresponding to the source electrode to obtain a hollowed-out pattern area of ​​the source electrode layer. Subsequently, oxygen ion treatment is used to completely remove residual photoresist from the source electrode area, thereby reducing the influence of residual organic matter. In the hollowed-out pattern area, a source electrode layer is formed using a method such as physical deposition, followed by a lift-off method to obtain the patterned source electrode layer. The source electrode layer material can be metals such as aluminum, gold, copper, platinum, and chromium, and its thickness can be set from 10 nm to 30 nm.

[0064] Photoresist is then coated onto the channel layer. The photoresist is exposed and developed according to a preset pattern corresponding to the first memristor electrode, thereby obtaining the active electrode of the memristor, i.e., the cutout pattern area of ​​the first memristor electrode. Subsequently, oxygen ion treatment is used to completely remove residual photoresist from the first memristor electrode area, thus reducing the influence of residual organic matter. The first memristor electrode is formed in the cutout pattern area using physical deposition, followed by a lift-off method to obtain the patterned first memristor electrode. The first memristor electrode material can be active metals such as tellurium, copper, and silver, or alloy materials such as silver-tellurium alloys, silver-copper alloys, and silver-titanium alloys, and its thickness can be set from 10 nm to 30 nm.

[0065] In some embodiments, after forming the first memristor electrode, the method further includes: processing the novel field-effect transistor by an annealing process to allow active metal ions in the first memristor electrode to diffuse into the channel layer.

[0066] Specifically, the annealing process is a short-duration, high-temperature heat treatment of the device in an inert gas environment. The annealing step is crucial for activating the memristor function. Under the thermal excitation provided by annealing, the active metal atoms in the first memristor electrode gain energy, enhancing their diffusion ability. These atoms thermally diffuse into the channel layer they contact, pre-forming a certain concentration of metal particle doping in the upper surface region of the channel layer. This process provides seeds for the formation of conductive filaments during subsequent electrical operations or lowers the formation energy barrier, making the switching behavior of the memristor easier to occur and more controllable. Therefore, in this embodiment of the invention, after forming the first memristor electrode, the annealing process can optimize the switching parameters of the memristor, such as increasing the switching speed and significantly improving the uniformity of device performance. For example, the annealing process can specifically involve placing the wafer in a nitrogen environment for rapid annealing, with annealing conditions ranging from 30s to 300s and annealing temperatures ranging from 300°C to 600°C.

[0067] Figure 7 This is a schematic diagram illustrating the specific process of fabricating a novel field-effect transistor integrating a memristor, as provided by this invention. Figure 7 As shown, the preparation method includes: S201. A silicon dioxide insulating layer is prepared on a silicon wafer using a thermal oxidation method.

[0068] S202. A gate electrode layer pattern is formed on the wafer by photolithography, the gate electrode layer is deposited and then stripped off.

[0069] S203. A gate dielectric layer pattern is formed on the wafer by photolithography, the gate dielectric layer is deposited and then stripped off.

[0070] S204. Perform rapid annealing on the wafer.

[0071] S205. A drain electrode layer pattern is formed on the wafer by photolithography, the drain electrode layer is deposited and then stripped.

[0072] S206. A trench layer pattern is formed on the wafer by photolithography, the trench layer is deposited and then stripped off.

[0073] S207. Photolithography is performed on the wafer to form the source electrode layer pattern, the source electrode layer is deposited and then stripped.

[0074] S208. The first memristor electrode layer pattern is formed on the wafer by photolithography, the electrode layer is deposited and then stripped.

[0075] S209. Perform rapid annealing on the wafer.

[0076] This invention also provides an electronic device, including a novel field-effect transistor that integrates a memristor as described in the above embodiments, and thus possesses the beneficial effects described in the above embodiments, which will not be repeated here.

[0077] Specifically, electronic devices can include circuits or systems that incorporate novel field-effect transistors (FETs) with memristors as their functional units, such as logic gates, memory cells, neuromorphic computing cores, or Internet of Things (IoT) sensing nodes. Applying the transistors provided in these embodiments to electronic devices allows for the construction of, for example, ultra-low power logic circuits using their ultra-low subthreshold swing characteristics, or the construction of in-memory computing architectures using their combined memory and switching characteristics.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A novel field effect transistor with a fusion memristor, characterized in that, The application relates to a novel field effect transistor comprising: a substrate; a gate electrode on the substrate; a gate dielectric layer on the gate electrode; a drain electrode on the gate dielectric layer; a channel layer on the drain electrode; a source electrode and a first memristive electrode, both on the channel layer; wherein the drain electrode is multiplexed as a second memristive electrode, the first memristive electrode at least partially overlaps with a vertical projection of the drain electrode, and the channel layer is disposed between the source electrode and the drain electrode and between the first memristive electrode and the drain electrode.

2. The novel fusion memristor field effect transistor of claim 1, wherein, The source electrode and the first memristive electrode are disposed in the same layer.

3. The novel fusion memristor field effect transistor according to claim 1 or 2, characterized in that, The material constituting the first memristive electrode comprises at least one of tellurium, copper, silver, silver-tellurium alloy, silver-copper alloy, or silver-titanium alloy.

4. The novel fusion memristor field effect transistor according to claim 1 or 2, characterized in that, The material constituting the channel layer comprises at least one of indium-gallium-zinc oxide, zinc oxide, indium oxide, tellurium oxide, molybdenum disulfide, or tungsten disulfide.

5. The novel fusion memristor field effect transistor according to claim 1 or 2, wherein, The thickness of the channel layer is greater than or equal to 20 nm and less than or equal to 30 nm.

6. A method of fabricating a novel field effect transistor with a fused memristor, characterized in that, A novel field effect transistor for preparing a fusion memristor as claimed in any one of claims 1-5, the preparation method comprising: providing a substrate wafer; forming a gate electrode on the substrate wafer; forming a gate dielectric layer on the gate electrode; forming a drain electrode on the gate dielectric layer; forming a channel layer on the drain electrode; forming a source electrode and a first memristive electrode on the channel layer.

7. The method of claim 6, wherein the method further comprises: After forming the first memristive electrode, further comprising: treating the novel field effect transistor through an annealing process to diffuse active metal ions in the first memristive electrode into the channel layer.

8. The method of claim 6 or 7, wherein the method further comprises: In the steps of forming the gate electrode, the gate dielectric layer, the drain electrode, the channel layer, the source electrode, and the first memristive electrode, each step comprises: coating photoresist on the substrate wafer; exposing and developing the photoresist according to a preset pattern to form a hollow pattern area; forming a corresponding film layer in the hollow pattern area through a deposition process; removing the photoresist through a stripping process to obtain a patterned corresponding film layer.

9. The method of claim 8, wherein the method further comprises: After forming the hollow pattern area, further comprising: treating the hollow pattern area with oxygen ions to remove residual photoresist in the hollow pattern area.

10. An electronic device, characterized by A novel field effect transistor comprising a fusion memristor as claimed in any one of claims 1-5.

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