Array substrate, manufacturing method thereof and flat panel detector
By optimizing the array substrate structure and increasing the photosensitive area of the photodiode, the problem of limited photosensitive area in flat panel detectors was solved, thereby improving detection sensitivity and signal-to-noise ratio and simplifying the manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-06
- Publication Date
- 2026-03-10
AI Technical Summary
The limited photosensitive area of photodiodes in existing flat panel detectors makes it difficult to improve detection sensitivity and signal-to-noise ratio.
An array substrate structure is designed, including a substrate, a first metal layer, an interlayer insulating layer, a second metal layer, an active layer, a gate insulating layer, and a third metal layer. By optimizing the layout of thin-film transistors, the footprint of the thin-film transistors is reduced, thereby increasing the photosensitive area of the photodiode.
By increasing the photosensitive area of the photodiode, the detection sensitivity and signal-to-noise ratio of the flat panel detector are improved, the manufacturing process is simplified, and the cost is reduced.
Smart Images
Figure CN121646027A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, specifically relating to an array substrate and its manufacturing method, and a flat panel detector. Background Technology
[0002] Flat X-ray Panel Detectors (FPXDs) based on thin film transistor (TFT) technology are crucial components in digital imaging technology. Due to their advantages such as fast imaging speed, good spatial and density resolution, high signal-to-noise ratio, and direct digital output, they are now widely used in industrial, medical, and aerospace fields.
[0003] The flat panel detector consists of a minimum detection unit composed of a thin-film transistor and a photodiode. The photodiode can convert visible light into an electrical signal. When the thin-film transistor is turned on, the electrical signal converted from visible light is output to the processor, which processes it to obtain image information.
[0004] The larger the photosensitive area of a photodiode, the more sensitive it is. Increasing the photosensitive area of a photodiode can improve the detection sensitivity and signal-to-noise ratio of a flat panel detector. However, the resolution of a flat panel detector limits the area occupied by the smallest detection unit, making it difficult to increase the photosensitive area of the photodiode. Summary of the Invention
[0005] The purpose of this application is to provide an array substrate and its fabrication method, as well as a flat panel detector, to increase the photosensitive area of a photodiode and thereby improve the detection sensitivity of the flat panel detector.
[0006] To achieve the above objectives, this application provides an array substrate, including a substrate and a first metal layer, wherein the first metal layer is formed on one side of the substrate, and the first metal layer includes a drain and a lower electrode connected to each other. The array substrate further includes: An interlayer insulating layer is formed on one side of the substrate and partially covers the first metal layer; A second metal layer is formed on the side of the interlayer insulating layer away from the substrate, and the second metal layer includes a source electrode. An active layer is formed on the side of the first metal layer, the interlayer insulating layer, and the source electrode away from the substrate. Both the source electrode and the drain electrode are connected to the active layer. The active layer and the drain electrode overlap in the direction parallel to the substrate and overlap in the direction perpendicular to the substrate. A gate insulating layer is formed on the side of the first metal layer, the second metal layer, and the active layer away from the substrate. A third metal layer is formed on the side of the gate insulating layer away from the substrate. The third metal layer includes a gate, which overlaps with the active layer in a direction perpendicular to the substrate.
[0007] Optionally, the angle between the interface between the active layer and the interlayer insulating layer and the substrate is greater than or equal to 70°.
[0008] Optionally, the active layer may be fabricated using a metal oxide semiconductor material, which may include indium gallium zinc oxide.
[0009] Optionally, the array substrate further includes a photoelectric conversion layer, which is formed on the side of the first metal layer away from the substrate. The interlayer insulating layer covers the edge region of the photoelectric conversion layer, and a connecting hole is formed on the interlayer insulating layer, exposing the central region of the photoelectric conversion layer.
[0010] Optionally, the array substrate further includes an upper electrode formed on the side of the photoelectric conversion layer away from the substrate. The upper electrode is made of a transparent conductive material. The third metal layer further includes a bias electrode that passes through the gate insulating layer and is connected to the upper electrode.
[0011] Optionally, the upper electrode is formed between the interlayer insulating layer and the gate insulating layer, the upper electrode covers the inner surface and surrounding area of the via, and the orthogonal projection of the bias electrode on the photoelectric conversion layer is located within the edge region of the photoelectric conversion layer covered by the interlayer insulating layer.
[0012] This application also provides a method for manufacturing an array substrate, the method comprising: A first metal layer and a photoelectric conversion layer are formed on one side of a substrate. The photoelectric conversion layer is located on the side of the first metal layer away from the substrate. The first metal layer includes a drain and a lower electrode connected to each other. An interlayer insulating layer is formed on the side of the first metal layer and the photoelectric conversion layer away from the substrate, and the interlayer insulating layer exposes the drain electrode and the central region of the photoelectric conversion layer; An upper electrode and a second metal layer are formed on the side of the photoelectric conversion layer and the interlayer insulating layer away from the substrate. The upper electrode is located on the side of the photoelectric conversion layer away from the substrate, and the second metal layer is located on the side of the interlayer insulating layer away from the substrate. The second metal layer includes a source electrode. An active layer is formed on the side of the first metal layer, the interlayer insulating layer, and the source electrode away from the substrate. Both the source electrode and the drain electrode are connected to the active layer. The active layer and the drain electrode overlap in the direction parallel to the substrate and overlap in the direction perpendicular to the substrate. A gate insulating layer is formed on the side of the first metal layer, the interlayer insulating layer, the second metal layer, the active layer, and the upper electrode away from the substrate. A third metal layer is formed on the side of the gate insulating layer away from the substrate. The third metal layer includes a gate and a bias electrode. In a direction perpendicular to the substrate, the gate overlaps with the active layer. The bias electrode passes through the gate insulating layer and is connected to the upper electrode.
[0013] Optionally, the method for forming the first metal layer and the photoelectric conversion layer includes: A first metal material layer, a semiconductor material layer, and a first photoresist layer are sequentially formed on the substrate. The first photoresist layer is exposed using a first grayscale mask, and the first photoresist layer is developed to pattern the first photoresist layer into a first region, a second region, and a third region. The first region corresponds to the light-transmitting region of the first grayscale mask, the second region corresponds to the semi-transparent region of the first grayscale mask, and the third region corresponds to the light-shielding region of the first grayscale mask. The first metal material layer and the semiconductor material layer are etched using the patterned first photoresist layer as a mask to form the first metal layer and the photoelectric conversion layer.
[0014] Optionally, the method for forming the interlayer insulating layer, the upper electrode, and the second metal layer includes: An insulating material layer is formed on the side of the first metal layer and the photoelectric conversion layer away from the substrate. The insulating material layer is etched to form the interlayer insulating layer that exposes the drain electrode, and a connecting hole is formed to expose the central region of the photoelectric conversion layer. A transparent conductive material layer, a second metal material layer, and a second photoresist layer are sequentially formed on the side of the interlayer insulating layer and the photoelectric conversion layer away from the substrate. The second photoresist layer is exposed using a second grayscale mask, and the second photoresist layer is developed to transfer the pattern of the second grayscale mask onto the second photoresist layer, forming a patterned second photoresist layer. The transparent conductive material layer and the second metal material layer are etched using the patterned second photoresist layer as a mask to form the second metal layer and the upper electrode.
[0015] This application also provides a flat panel detector, including: The array substrate; A scintillator is formed on one side of the array substrate.
[0016] The array substrate and its fabrication method disclosed in this application, as well as the flat panel detector, have the following beneficial effects: In this application, the array substrate includes a substrate, a first metal layer, an interlayer insulating layer, a second metal layer, an active layer, a gate insulating layer, and a third metal layer. The first metal layer includes a drain and a lower electrode connected together. The interlayer insulating layer is formed on one side of the substrate and partially covers the first metal layer. The second metal layer is formed on the side of the interlayer insulating layer away from the substrate and includes a source electrode. The active layer is formed on the side of the first metal layer, the interlayer insulating layer, and the source electrode away from the substrate. The gate insulating layer is formed on the side of the first metal layer, the second metal layer, and the active layer away from the substrate. The third metal layer is formed on the side of the gate insulating layer away from the substrate and includes a gate electrode. The source and drain electrodes are arranged in a direction perpendicular to the substrate, and the channel of the thin-film transistor extends longitudinally, reducing the footprint of the thin-film transistor and correspondingly increasing the photosensitive area of the photodiode, thereby improving the detection sensitivity of the flat panel detector.
[0017] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.
[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0020] Figure 1 This is a schematic diagram of the array substrate in Embodiment 1 of this application.
[0021] Figure 2 This is a flowchart of the method for fabricating the array substrate in Embodiment 2 of this application.
[0022] Figure 3 This is a schematic diagram of the formation of the first photoresist layer in Embodiment 2 of this application.
[0023] Figure 4 This is a schematic diagram of the patterned first photoresist layer in Embodiment 2 of this application.
[0024] Figure 5 This is a schematic diagram of the formation of the first metal layer and the photoelectric conversion layer in Embodiment 2 of this application.
[0025] Figure 6 This is a schematic diagram of the formation of an interlayer insulating layer in Embodiment 2 of this application.
[0026] Figure 7 This is a schematic diagram of the formation of a transparent conductive material layer and a second metal layer in Embodiment 2 of this application.
[0027] Figure 8 This is a schematic diagram of the formation of the active layer in Embodiment 2 of this application.
[0028] Figure 9 This is a schematic diagram of the formation of the gate insulating layer and the third metal layer in Embodiment 2 of this application.
[0029] Figure 10 This is a schematic diagram of the structure of the flat panel detector in Embodiment 3 of this application.
[0030] Explanation of reference numerals in the attached figures: 10. Array substrate; 20. Scintillator; 100, Substrate; 201, First metal material layer; 210, First metal layer; 211, Drain; 212, Lower electrode; 220, Second metal layer; 221, Source; 230, Third metal layer; 231, Gate; 232, Bias electrode; 310, Interlayer insulating layer; 320, Gate insulating layer; 330, Passivation layer; 340, Planarization layer; 400, Active layer; 410, First contact portion; 420, Second contact portion; 430, Connecting portion; 500, Photoelectric conversion layer; 501, Semiconductor material layer; 510, N-type doped semiconductor layer; 520, Intrinsic semiconductor layer; 530, P-type doped semiconductor layer; 600, Transparent conductive material layer; 610, Upper electrode; 710, First photoresist layer; 711, First region; 712, Second region; 713, Third region. Detailed Implementation
[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.
[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.
[0033] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.
[0034] Example 1 See Figure 1 As shown, in this embodiment, the array substrate 10 includes a substrate 100, a first metal layer 210, an interlayer insulating layer 310, a second metal layer 220, an active layer 400, a gate insulating layer 320, and a third metal layer 230. The first metal layer 210 is formed on one side of the substrate 100. The substrate 100 can be a transparent substrate such as a glass substrate, and the first metal layer 210 is made of metal materials such as aluminum, copper, molybdenum, and their alloys. The first metal layer 210 includes a drain 211 and a lower electrode 212 connected to each other.
[0035] An interlayer insulating layer 310 is formed on one side of the substrate 100 and partially covers the first metal layer 210, that is, the interlayer insulating layer 310 covers the area of the first metal layer 210 other than the drain 211. The interlayer insulating layer 310 can be made of insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride. A second metal layer 220 is formed on the side of the interlayer insulating layer 310 away from the substrate 100, and the second metal layer 220 includes a source 221. The second metal layer 220 is made of metallic materials such as aluminum, copper, molybdenum, and their alloys.
[0036] An active layer 400 is formed on the side of the first metal layer 210, the interlayer insulating layer 310, and the source electrode 221 away from the substrate 100. Both the source electrode 221 and the drain electrode 211 are connected to the active layer 400. The active layer 400 and the drain electrode 211 overlap in the direction parallel to the substrate 100, and the active layer 400 overlaps with the source electrode 221 in the direction perpendicular to the substrate 100.
[0037] Specifically, the active layer 400 includes a first contact portion 410, a second contact portion 420, and a connecting portion 430. The first contact portion 410 is located on the side of the source electrode 221 away from the substrate 100, the second contact portion 420 is located on the side of the drain electrode 211 away from the substrate 100, and the connecting portion 430 is located on the side of the interlayer insulating layer 310 and the source electrode 221 and connects the first contact portion 410 and the second contact portion 420.
[0038] A gate insulating layer 320 is formed on the side of the first metal layer 210, the second metal layer 220, and the active layer 400 away from the substrate 100. The gate insulating layer 320 may be made of a material with a high dielectric constant, such as hafnium dioxide, silicon dioxide, and aluminum oxide. A third metal layer 230 is formed on the side of the gate insulating layer 320 away from the substrate 100. The third metal layer 230 includes a gate 231, which overlaps with the active layer 400 in a direction perpendicular to the substrate 100. The third metal layer 230 may be made of a metal material such as aluminum, copper, molybdenum, or their alloys.
[0039] In addition, the array substrate 10 also includes a passivation layer 330 and a planarization layer 340. The passivation layer 330 is formed on the side of the third metal layer 230 and the gate insulating layer 320 away from the substrate 100, and the planarization layer 340 is formed on the side of the passivation layer 330 away from the substrate 100. The passivation layer 330 can be made of insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, and the planarization layer 340 can be made of transparent organic materials such as polyimide.
[0040] The array substrate 10 includes a minimum detection unit composed of a thin film transistor and a photodiode. The thin film transistor includes a gate 231, a source 221, a drain 211 and an active layer 400. The source 221 and the drain 211 are arranged in a direction perpendicular to the substrate 100, that is, the channel of the thin film transistor extends longitudinally.
[0041] The larger the photosensitive area of a photodiode, the more sensitive it is. Increasing the photosensitive area of a photodiode can improve the detection sensitivity and signal-to-noise ratio of a flat panel detector. However, the resolution of a flat panel detector limits the area occupied by the smallest detection unit, making it difficult to increase the photosensitive area of the photodiode.
[0042] In this embodiment, the array substrate 10 includes a substrate 100, a first metal layer 210, an interlayer insulating layer 310, a second metal layer 220, an active layer 400, a gate insulating layer 320, and a third metal layer 230. The first metal layer 210 is formed on one side of the substrate 100 and includes a drain 211 and a lower electrode 212 connected to each other. The interlayer insulating layer 310 is formed on one side of the substrate 100 and partially covers the first metal layer 210. The second metal layer 220 is formed on the side of the interlayer insulating layer 310 away from the substrate 100 and includes... The source electrode 221 and the active layer 400 are formed on the side of the first metal layer 210, the interlayer insulating layer 310, and the source electrode 221 away from the substrate 100. Both the source electrode 221 and the drain electrode 211 are connected to the active layer 400. The gate insulating layer 320 is formed on the side of the first metal layer 210, the second metal layer 220, and the active layer 400 away from the substrate 100. The third metal layer 230 is formed on the side of the gate insulating layer 320 away from the substrate 100. The third metal layer 230 includes the gate electrode 231. In the direction perpendicular to the substrate 100, the gate electrode 231 overlaps with the active layer 400. The source electrode 221 and the drain electrode 211 are arranged in the direction perpendicular to the substrate 100. The channel of the thin-film transistor extends longitudinally, reducing the footprint of the thin-film transistor. The photosensitive area of the photodiode is correspondingly increased, thereby improving the detection sensitivity of the flat panel detector.
[0043] In some embodiments, the angle between the interface between the active layer 400 and the interlayer insulating layer 310 and the substrate 100 is greater than or equal to 70°, and the connection portion 430 between the interlayer insulating layer 310 and the active layer 400 is in contact, that is, the slope angle of the interlayer insulating layer 310 below the source electrode 221 is greater than or equal to 70°. The source electrode 221 is also in contact with the connection portion 430 of the active layer 400, and the interface between the source electrode 221 and the connection portion 430 is coplanar with the interface between the interlayer insulating layer 310 and the connection portion 430, that is, the slope angle of the side of the source electrode 221 near the connection portion 430 is greater than or equal to 70°.
[0044] The larger the slope angle of the interlayer insulating layer 310 below the source 221, the smaller the footprint of the thin-film transistor and the larger the photosensitive area of the photodiode. It should be understood that the slope angle of the interlayer insulating layer 310 below the source 221 can be equal to 90°, and the connection portion 430 of the active layer 400 can be perpendicular to the substrate 100.
[0045] In some embodiments, the active layer 400 is made of a metal oxide semiconductor material, including indium gallium zinc oxide (IGZO).
[0046] The active layer 400 of the thin-film transistor is made of metal oxide semiconductor material. Thin-film transistors have higher mobility and can better meet the requirements of fast dynamic detection, enabling high frame rate dynamic and high signal-to-noise ratio imaging.
[0047] It should be noted that the active layer 400 of the thin-film transistor can be made of metal oxide semiconductor material, but is not limited to this. The thin-film transistor of the thin-film transistor can also be made of semiconductor materials such as amorphous silicon (i.e., A-Si) or polycrystalline silicon (i.e., P-Si), depending on the specific situation.
[0048] In some embodiments, the array substrate 10 further includes a photoelectric conversion layer 500, which is formed on the side of the first metal layer 210 away from the substrate 100. An interlayer insulating layer 310 covers the edge region of the photoelectric conversion layer 500, and a connecting hole is formed on the interlayer insulating layer 310, exposing the central region of the photoelectric conversion layer 500.
[0049] A photoelectric conversion layer 500 is disposed on the lower electrode 212. The photoelectric conversion layer 500 can adopt a PN structure or a PIN structure. Specifically, the PIN structure photoelectric conversion layer 500 includes an N-type doped semiconductor layer 510 (N), an undoped intrinsic semiconductor layer 520 (I), and a P-type doped semiconductor layer 530 (P) stacked sequentially. The N-type doped semiconductor layer 510 is located on the side of the intrinsic semiconductor layer 520 closer to the lower electrode 212, and the P-type doped semiconductor layer 530 is located on the side of the intrinsic semiconductor layer 520 away from the lower electrode 212. The PN structure photoelectric conversion layer 500 does not include the intrinsic semiconductor layer 520 (I).
[0050] The active layer 400 of the thin-film transistor is fabricated using a metal-oxide-semiconductor (MOS) material. If the active layer 400 is fabricated before the photoelectric conversion layer 500 of the photodiode, the fabrication process of the photoelectric conversion layer 500 will introduce a large number of hydrogen atoms. Excessive hydrogen atoms will degrade the switching characteristics of the thin-film transistor. In this application, the photoelectric conversion layer 500 can be fabricated before the interlayer insulating layer 310, and the active layer 400 can be fabricated after the interlayer insulating layer 310. This design avoids the introduction of a large number of hydrogen atoms during the fabrication process of the photoelectric conversion layer 500, which would otherwise degrade the switching characteristics of the thin-film transistor.
[0051] In some embodiments, the array substrate 10 further includes an upper electrode 610, which is formed on the side of the photoelectric conversion layer 500 away from the substrate 100. The upper electrode 610 is made of a transparent conductive material, including indium tin oxide (ITO). The third metal layer 230 further includes a bias electrode 232, which passes through the gate insulating layer 320 and is connected to the upper electrode 610. The photodiode includes the upper electrode 610, the photoelectric conversion layer 500, and the lower electrode 212.
[0052] The upper electrode 610 is made of a transparent conductive material, and the bias electrode 232 is made of a metal material. Compared with the scheme of using indium tin oxide to make the bias electrode 232, the circuit impedance can be reduced.
[0053] In some embodiments, the upper electrode 610 is formed between the interlayer insulating layer 310 and the gate insulating layer 320, and the upper electrode 610 covers the inner surface and surrounding area of the via. The orthogonal projection of the bias electrode 232 on the photoelectric conversion layer 500 is located within the edge region of the photoelectric conversion layer 500 covered by the interlayer insulating layer 310.
[0054] The orthogonal projection of the bias electrode 232 onto the photoelectric conversion layer 500 is located within the edge region of the photoelectric conversion layer 500 covered by the interlayer insulating layer 310, which can reduce the obstruction of the photoelectric conversion layer 500 by the bias electrode 232 and increase the photosensitive area of the photoelectric conversion layer 500.
[0055] Example 2 This application also provides a method for fabricating an array substrate 10, which is used to fabricate the array substrate 10 disclosed in Embodiment 1. See also Figures 2 to 9 As shown, the method for fabricating the array substrate 10 includes: S100: A first metal layer 210 and a photoelectric conversion layer 500 are formed on one side of the substrate 100. The photoelectric conversion layer 500 is located on the side of the first metal layer 210 away from the substrate 100. The first metal layer 210 includes a drain 211 and a lower electrode 212 connected to each other. S200: An interlayer insulating layer 310 is formed on the side of the first metal layer 210 and the photoelectric conversion layer 500 away from the substrate 100, and the interlayer insulating layer 310 exposes the drain 211 and the central region of the photoelectric conversion layer 500. S300: An upper electrode 610 and a second metal layer 220 are formed on the side of the photoelectric conversion layer 500 and the interlayer insulating layer 310 away from the substrate 100. The upper electrode 610 is located on the side of the photoelectric conversion layer 500 away from the substrate 100, and the second metal layer 220 is located on the side of the interlayer insulating layer 310 away from the substrate 100. The second metal layer 220 includes a source electrode 221. S400: An active layer 400 is formed on the side of the first metal layer 210, the interlayer insulating layer 310 and the source electrode 221 away from the substrate 100. The source electrode 221 and the drain electrode 211 are both connected to the active layer 400. The active layer 400 and the drain electrode 211 overlap in the direction parallel to the substrate 100. The active layer 400 and the source electrode 221 overlap in the direction perpendicular to the substrate 100. S500: A gate insulating layer 320 is formed on the side of the first metal layer 210, the interlayer insulating layer 310, the second metal layer 220, the active layer 400 and the upper electrode 610 away from the substrate 100. S600: A third metal layer 230 is formed on the side of the gate insulating layer 320 away from the substrate 100. The third metal layer 230 includes a gate 231 and a bias electrode 232. In the direction perpendicular to the substrate 100, the gate 231 overlaps with the active layer 400. The bias electrode 232 passes through the gate insulating layer 320 and is connected to the upper electrode 610.
[0056] The photoelectric conversion layer 500 is fabricated before the interlayer insulating layer 310, and the active layer 400 is fabricated after the interlayer insulating layer 310. This avoids the introduction of a large number of hydrogen atoms during the fabrication process of the photoelectric conversion layer 500, which would lead to a deterioration in the switching characteristics of the thin-film transistor.
[0057] It should be noted that the method for fabricating the array substrate 10 includes: sequentially forming a passivation layer 330 and a planarization layer 340 on the side of the gate insulating layer 320 and the third metal layer 230 away from the substrate 100, and etching the passivation layer 330 and the planarization layer 340 to expose the metal bonding region of the array substrate 10.
[0058] In some embodiments, the method of forming the first metal layer 210 and the photoelectric conversion layer 500 includes: A first metal material layer 201, a semiconductor material layer 501, and a first photoresist layer 710 are sequentially formed on a substrate 100. The first photoresist layer 710 is exposed using a first grayscale mask, and the first photoresist layer 710 is developed to pattern the first photoresist layer 710 into a first region 711, a second region 712, and a third region 713. The first region 711 corresponds to the light-transmitting region of the first grayscale mask, the second region 712 corresponds to the semi-transparent region of the first grayscale mask, and the third region 713 corresponds to the light-shielding region of the first grayscale mask. Using the patterned first photoresist layer 710 as a mask, the first metal material layer 201 and the semiconductor material layer 501 are etched to form the first metal layer 210 and the photoelectric conversion layer 500.
[0059] The semiconductor material layer 501 is a stack of N-type doped semiconductor material, undoped intrinsic semiconductor material, and P-type doped semiconductor material, or a stack of N-type doped semiconductor material and P-type doped semiconductor material. When etching the semiconductor material layer 501 and the first metal material layer 201, the areas of the semiconductor material layer 501 and the first metal material layer 201 without photoresist protection, i.e., the portion corresponding to the first region 711, can be removed first to form the first metal layer 210. Then, the photoresist is etched, the photoresist in the second region 712 is completely removed, the thickness of the photoresist in the third region 713 is reduced, and finally, the remaining semiconductor material layer 501 is etched to form the photoelectric conversion layer 500.
[0060] The first metal layer 210 and the photoelectric conversion layer 500 are fabricated using a single mask process, which can reduce the manufacturing cost of the array substrate 10.
[0061] In some embodiments, the method of forming the interlayer insulating layer 310, the upper electrode 610, and the second metal layer 220 includes: An insulating material layer is formed on the side of the first metal layer 210 and the photoelectric conversion layer 500 away from the substrate 100. The insulating material layer is etched to form an interlayer insulating layer 310 that exposes the drain electrode 211, and at the same time, a connecting hole is formed that exposes the central region of the photoelectric conversion layer 500. A transparent conductive material layer 600, a second metal material layer, and a second photoresist layer are sequentially formed on the side of the interlayer insulating layer 310 and the photoelectric conversion layer 500 away from the substrate 100. The second grayscale mask is used to expose the second photoresist layer, and the second photoresist layer is developed to transfer the pattern of the second grayscale mask onto the second photoresist layer, forming a patterned second photoresist layer. Using a patterned second photoresist layer as a mask, a transparent conductive material layer 600 and a second metal material layer are etched to form a second metal layer 220 and an upper electrode 610.
[0062] When etching the transparent conductive material layer 600 and the second metal material layer, the connection between the portion of the transparent conductive material layer 600 below the second metal layer 220 and the upper electrode 610 is broken.
[0063] The second metal layer 220 and the upper electrode 610 are fabricated using a single mask process, which can reduce the manufacturing cost of the array substrate 10.
[0064] In this application, the formation of the first metal layer 210 and the photoelectric conversion layer 500 adopts one mask process, the formation of the interlayer insulating layer 310 adopts one mask process, the formation of the second metal layer 220 and the upper electrode 610 adopts one mask process, the formation of the active layer 400 adopts one mask process, the formation of the gate insulating layer 320 adopts one mask process, the formation of the third metal layer 230 adopts one mask process, and the etching of the passivation layer 330 and the planarization layer 340 to expose the metal bonding area adopts one mask process. The entire fabrication process of the array substrate 10 uses a total of 7 mask processes, which simplifies the fabrication process of the array substrate 10 and reduces the fabrication cost of the array substrate 10.
[0065] Example 3 This application also provides a flat panel detector, see [link to application]. Figure 10 As shown, the flat panel detector includes the array substrate 10 disclosed in Embodiment 1 and the scintillator 20, with the scintillator 20 formed on one side of the array substrate 10.
[0066] The flat panel detector includes an array substrate 10, which includes a substrate 100, a first metal layer 210, an interlayer insulating layer 310, a second metal layer 220, an active layer 400, a gate insulating layer 320, and a third metal layer 230. The first metal layer 210 is formed on one side of the substrate 100 and includes a drain 211 and a lower electrode 212 connected to each other. The interlayer insulating layer 310 is formed on one side of the substrate 100 and partially covers the first metal layer 210. The second metal layer 220 is formed on the side of the interlayer insulating layer 310 away from the substrate 100. The thin-film transistor (TFT) includes a source electrode 221. An active layer 400 is formed on the side of the first metal layer 210, the interlayer insulating layer 310, and the source electrode 221 away from the substrate 100. Both the source electrode 221 and the drain electrode 211 are connected to the active layer 400. A gate insulating layer 320 is formed on the side of the first metal layer 210, the second metal layer 220, and the active layer 400 away from the substrate 100. A third metal layer 230 is formed on the side of the gate insulating layer 320 away from the substrate 100. The third metal layer 230 includes a gate electrode 231. In a direction perpendicular to the substrate 100, the gate electrode 231 overlaps with the active layer 400. The source electrode 221 and the drain electrode 211 are arranged in a direction perpendicular to the substrate 100. The channel of the thin-film transistor extends longitudinally, reducing the footprint of the thin-film transistor. The photosensitive area of the photodiode is correspondingly increased, thereby improving the detection sensitivity of the flat panel detector.
[0067] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0068] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0069] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0070] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.
Claims
1. An array substrate comprising a substrate and a first metal layer formed on one side of the substrate, the first metal layer comprising a drain electrode and a lower electrode connected to each other, characterized in that, The array substrate further comprises: an interlayer insulating layer formed on the substrate and partially covering the first metal layer; a second metal layer formed on the side of the interlayer insulating layer away from the substrate, the second metal layer comprising a source electrode; an active layer formed on the side of the first metal layer, the interlayer insulating layer and the source electrode away from the substrate, the source electrode and the drain electrode both being connected to the active layer, the active layer and the drain electrode overlapping in the direction parallel to the substrate, and the active layer and the source electrode overlapping in the direction perpendicular to the substrate; a gate insulating layer formed on the side of the first metal layer, the second metal layer and the active layer away from the substrate; a third metal layer formed on the side of the gate insulating layer away from the substrate, the third metal layer comprising a gate electrode, the gate electrode and the active layer overlapping in the direction perpendicular to the substrate.
2. The array substrate of claim 1, wherein, The angle between the interface between the active layer and the interlayer insulating layer and the substrate is greater than or equal to 70°.
3. The array substrate of claim 1, wherein, The material of the active layer comprises a metal oxide semiconductor material, and the metal oxide semiconductor material comprises indium gallium zinc oxide.
4. The array substrate of claim 3, wherein, The array substrate further comprises a photoelectric conversion layer formed on the side of the first metal layer away from the substrate, the interlayer insulating layer covering the edge region of the photoelectric conversion layer, and a through hole being formed in the interlayer insulating layer to expose the central region of the photoelectric conversion layer.
5. The array substrate of claim 4, wherein, The array substrate further comprises an upper electrode formed on the side of the photoelectric conversion layer away from the substrate, the upper electrode being made of transparent conductive material, and the third metal layer further comprising a bias electrode connected to the upper electrode through the gate insulating layer.
6. The array substrate of claim 5, wherein, The upper electrode is formed between the interlayer insulating layer and the gate insulating layer, the upper electrode covering the inner surface and the surrounding region of the through hole, and the orthographic projection of the bias electrode on the photoelectric conversion layer being located in the edge region of the photoelectric conversion layer covered by the interlayer insulating layer.
7. A manufacturing method of an array substrate, characterized by, The method for manufacturing the array substrate comprises: forming a first metal layer and a photoelectric conversion layer on the side of a substrate, the photoelectric conversion layer being located on the side of the first metal layer away from the substrate, and the first metal layer comprising a drain electrode and a lower electrode connected to each other; forming an interlayer insulating layer on the side of the first metal layer and the photoelectric conversion layer away from the substrate, the interlayer insulating layer exposing the drain electrode and the central region of the photoelectric conversion layer; forming an upper electrode and a second metal layer on the side of the photoelectric conversion layer and the interlayer insulating layer away from the substrate, the upper electrode being located on the side of the photoelectric conversion layer away from the substrate, and the second metal layer being located on the side of the interlayer insulating layer away from the substrate, the second metal layer comprising a source electrode. An active layer is formed on a side of the first metal layer, the interlayer insulating layer and the source electrode away from the substrate, the source electrode and the drain electrode are connected with the active layer, the active layer and the drain electrode overlap in a direction parallel to the substrate, and the active layer and the source electrode overlap in a direction perpendicular to the substrate; A gate insulating layer is formed on a side of the first metal layer, the interlayer insulating layer, the second metal layer, the active layer and the upper electrode away from the substrate; A third metal layer is formed on a side of the gate insulating layer away from the substrate, the third metal layer comprises a gate electrode and a bias electrode, the gate electrode and the active layer overlap in a direction perpendicular to the substrate, and the bias electrode is connected with the upper electrode through the gate insulating layer.
8. The method of manufacturing an array substrate according to claim 7, wherein The method for forming the first metal layer and the photoelectric conversion layer comprises: A first metal material layer, a semiconductor material layer and a first photoresist layer are sequentially formed on the substrate; The first photoresist layer is exposed by using a first gray-tone mask, and the first photoresist layer is developed to be patterned to form a first region, a second region and a third region, the first region corresponds to a light-transmitting region of the first gray-tone mask, the second region corresponds to a semi-transparent region of the first gray-tone mask, and the third region corresponds to a light-blocking region of the first gray-tone mask; The first metal material layer and the semiconductor material layer are etched by using the patterned first photoresist layer as a mask to form the first metal layer and the photoelectric conversion layer.
9. The method of manufacturing an array substrate according to claim 7, wherein The method for forming the interlayer insulating layer, the upper electrode and the second metal layer comprises: An insulating material layer is formed on a side of the first metal layer and the photoelectric conversion layer away from the substrate, and the insulating material layer is etched to form the interlayer insulating layer exposing the drain electrode and a communication hole exposing a central region of the photoelectric conversion layer; A transparent conductive material layer, a second metal material layer and a second photoresist layer are sequentially formed on a side of the interlayer insulating layer and the photoelectric conversion layer away from the substrate; The second photoresist layer is exposed by using a second gray-tone mask, and the second photoresist layer is developed to transfer a pattern of the second gray-tone mask onto the second photoresist layer to form a patterned second photoresist layer; The transparent conductive material layer and the second metal material layer are etched by using the patterned second photoresist layer as a mask to form the second metal layer and the upper electrode.
10. A flat panel detector, characterized by, The array substrate comprises: The array substrate according to any one of claims 1-6; The scintillator is formed on a side of the array substrate.