Method and device for realizing radar data processing

Abstract

The invention discloses a method and a device for realizing radar data processing, which adopt a parallel computing architecture, perform data throughput with multiple parallelism degrees, optimize a data access mode, further improve throughput rate, improve efficiency and flexibility of data access in a radar sliding window detection process, reduce cache overhead and improve data access efficiency. High-speed, parallel and clear-structure neighborhood data extraction operation is realized, and rapid and accurate data access support is provided for target detection.

Description

Technical Field

[0001] This application relates to, but is not limited to, radar signal processing technology, and in particular to a method for radar data processing and a two-dimensional detector. Background Technology

[0002] As chip integration and manufacturing processes advance, radar signal processing and post-processing technologies are increasingly facing challenges in handling large-scale data detection tasks, particularly in terms of data throughput, computational complexity, detection adaptability, and real-time performance. This is especially true in the field of automotive radar, where the application of 4D imaging radar is becoming increasingly widespread. Its high angular resolution requires detection logic to expand from the traditional single Doppler and range dimensions to range-angle, Doppler-angle, and even higher dimensions.

[0003] This trend has led to a dramatic increase in throughput and computation, making the design of detectors for algorithms or hardware modules used to identify target signals and distinguish noise more challenging. The detection results of the detectors directly affect the accuracy of target classification. Summary of the Invention

[0004] This application provides a method and apparatus for radar data processing, which can optimize data access methods, improve throughput, and thus provide fast and accurate data access support for target detection.

[0005] This invention provides a method for radar data processing, comprising: The input multidimensional data is divided into multiple two-dimensional data sub-regions; Configure a data buffer unit for sliding window access based on the sliding window detection requirements, and divide the data buffer unit into multiple parallel data channels by column; During the initialization phase of the detection process, some historical data is pre-read from the two-dimensional data sub-region and written into the data buffer unit. According to the sliding window order, the data required for current processing is extracted from the data buffer unit through multiple configured parallel data channels to construct the sliding window view. During data access, access addresses for neighboring data are generated based on the logical position of the center of the constructed sliding window view in order to extract target data within the sliding window area.

[0006] Optionally, it also includes: extracting the historical neighborhood data required by the sliding window based on the address wraparound mechanism to ensure the completion and alignment of the target data.

[0007] Optionally, the extraction of historical neighborhood data required for the sliding window based on the address wraparound mechanism includes: When the sliding window is processing the boundary, it detects that the window needs to access the data in the previous row. Based on the address wraparound mechanism, it jumps to the end of the cache through address modulo operation to complete the access to the previous batch and realize the data extraction of row-by-row alignment and vector alignment.

[0008] Optionally, it also includes: using a hierarchical circular caching structure and a data partial update mechanism, so that the sliding window only performs buffered refresh on newly added areas during the sliding process.

[0009] Optionally, the hierarchical circular cache structure includes: The first cache is used for quickly writing the current data and temporarily stores the sliding window data currently read from the data buffer unit; A second buffer for storing data above and below the current frame in a sliding window, the second buffer includes: a first data buffer for storing the frame where the center of the sliding window is located; and a second data buffer for storing the previous frame or the previous row of the sliding window.

[0010] Optionally, the input multidimensional data includes: two-dimensional amplitude spectrum data generated by the radar system front-end after processing; The process of dividing the input multidimensional data into multiple two-dimensional data sub-regions includes: The input data is divided into multiple two-dimensional data sub-regions in the format of Batch×Vector. Batch corresponds to the Doppler dimension, representing a continuous set of rows in the two-dimensional input data; Vector corresponds to the angular dimension, representing a continuous set of columns in the two-dimensional input data. Each of the data channels is a column-oriented data buffer unit, corresponding to a column of data in the sliding window.

[0011] Optionally, the data buffer unit is a parallel column cache module (PBUF).

[0012] Optionally, the parallel read structure configuration of the PBUF includes 8-way, 16-way, or 32-way.

[0013] Optionally, for a 2D object detection scenario, constructing the sliding window view includes: During the initialization phase of the detection process, historical data is pre-read from each of the two-dimensional data sub-regions and written into the internal data buffer unit according to the requirements of the sliding window structure. This includes prioritizing the loading of the previous batch of Batch N-1 data, and then sequentially loading data from Batch 0 to Batch N-2 to construct the continuous buffer area required for the sliding window view; where N is the number of batches initially loaded.

[0014] Optionally, for a one-dimensional 1D object detection scenario, constructing the sliding window view includes: During the initialization phase of the detection process, based on the sliding window structure requirements, the data required for the current processing is extracted from a batch within a single two-dimensional data sub-region according to a fixed window width to construct the sliding window view.

[0015] Optionally, the access address for generating neighborhood data includes: For each sliding window center position, based on the sliding window center position and window size, and combined with the current Batch and Vector index, the access address of the corresponding neighborhood data is dynamically generated.

[0016] Optionally, it further includes: performing extreme value comparisons on each data point in the target data in parallel, and merging the multiple extreme value comparison results to obtain extreme value flag information.

[0017] Optionally, it also includes: passing the data judgment flag information from the end of the previous Batch of the Batch where the center point of the current sliding window is located to the current Batch, and logically completing the splicing and judgment consistency of the extreme value bitmap.

[0018] Optionally, it also includes: For the current local extreme point, calculate the amplitude difference between its left and right adjacent data points, as well as the weighted difference between the current local extreme point and its two adjacent data points; Non-zero detection and sign flag extraction are performed on the calculated amplitude difference and weighted difference, respectively; Extract the most significant bit (MSB) of the calculated amplitude difference and weighted difference, and align them to a preset position to achieve numerical normalization. Based on the high-order truncation value of the normalized weighted difference, its reciprocal approximation value is obtained from the lookup table; The obtained reciprocal approximation value is multiplied by the normalized amplitude value to obtain the initial interpolation value; Based on the displacement difference between the normalized amplitude value and the weighted difference, the initial interpolation value is corrected for positional difference. Optionally, it also includes: truncating and rounding the corrected interpolated value.

[0019] Optionally, it also includes: performing saturation constraint processing on the interpolated values ​​after the truncation and rounding processes; Based on the extracted symbol flag, output the signed fixed-point interpolation offset.

[0020] This application also provides an apparatus for radar data processing, applied to the parallel detection of radar data, the apparatus comprising: The data input interface is configured to receive parallel input radar data streams; The local extremum detection unit is configured to compare the current data in the radar data stream with its neighboring data in at least one dimension, and output the extremum judgment result according to the predefined extremum judgment logic; A threshold comparison unit is configured to compare the current data with at least one configurable threshold value; A logic operation unit is configured to receive the extreme value judgment result and the threshold comparison result, and perform a logical AND operation to obtain a detection result; and The data output interface is configured to output the detection results.

[0021] Optionally, it also includes: The storage system, including an internal cache unit, is configured to cache the input radar data stream.

[0022] Optionally, it also includes: The address generation unit is configured to generate specific read and write address sequences to enable wrapping access of data in the storage system. The local extremum detection unit is connected to the internal cache unit and is also configured to perform extremum comparison of two-dimensional data based on loopback access.

[0023] Optionally, the address sequence is configured so that when performing two-dimensional data detection, the device processes data in batches, first reading the last batch of data and storing it in the internal cache unit, and then reading the zeroth, first and subsequent batches of data in sequence to achieve data looping in the batch dimension, so that when processing the current batch of data, it is possible to access the data of its adjacent batches.

[0024] Optionally, the internal cache unit includes a two-level cache, and the data update mechanism of the two-level cache includes: As data moves alternately between the two-level caches, at any given moment, the cache simultaneously contains the data to be processed and its adjacent data in the two-dimensional plane, thus supporting two-dimensional local extremum comparisons with minimal data caching and read overhead.

[0025] Optionally, the predefined extremum judgment logic used by the local extremum detection unit is configured as follows: For a data point x1 in a one-dimensional sequence, if it is simultaneously greater than its preceding data point x0 and greater than or equal to its following data point x2, then the data point x1 is determined to be a local extremum.

[0026] Optionally, the local extremum detection unit includes: A first comparator is used to compare the size between the data point x0 and the data point x1; A second comparator is used to compare the size between data point x1 and data point x2; A NAND gate logic circuit, whose input is connected to the output of the first comparator and the second comparator, is used to output the judgment result of the local extremum.

[0027] Optionally, it also includes: The tag processing unit is configured to receive an externally input tag signal and perform a Boolean operation on the tag signal and the output of the logic operation unit to generate a final valid detection tag; The tagging signal received by the tagging processing unit is associated with the scene or area information of the radar data.

[0028] Optionally, it also includes: The interpolation unit is configured to perform interpolation calculations on the data points corresponding to the valid detection identifier; The data output interface is also configured to output the data points corresponding to the valid detection identifiers after interpolation.

[0029] Optionally, the interpolation unit includes a divider, which is configured to: Use a lookup table to calculate the reciprocal of the divisor, where the lookup table covers the range of values ​​[0.5, 1). Perform non-zero checks and sign bit checks on the numerator and denominator, and save the XOR result of the sign bit; Identify the first significant bit of the numerator and denominator, and move that significant bit to the highest significant bit, while recording the position difference between the significant bits of the numerator and denominator; According to the preset bit width, the numerator and denominator after shifting are truncated; Obtain the reciprocal of the truncated denominator by looking up a table; Multiply the reciprocal by the truncated numerator to obtain a preliminary product; Based on the position difference, extract the integer and fractional parts representing the final result from the preliminary product; Rounding and saturation of the decimal part; and The sign of the final result is recovered from the XOR result of the sign bit.

[0030] This application provides another method for radar signal processing, which uses the apparatus described in any one of the above claims to achieve parallel detection of radar data.

[0031] This application embodiment also provides a computer-readable storage medium storing computer-executable instructions, which are used to execute the radar data processing method described in any of the above claims.

[0032] The method for realizing radar data processing provided by the embodiments of the present application adopts a parallel computing architecture, performs data throughput with multiple parallel degrees, optimizes the data access mode, and further improves the throughput rate, thereby increasing the efficiency and flexibility of data access during the radar sliding window detection process, reducing the cache overhead, and realizing a high-speed, parallel, and clearly structured neighborhood data extraction operation, providing fast and accurate data access support for target detection.

[0033] Furthermore, the data reading / address generation method adopted by the embodiments of the present application is naturally compatible with the wrap-around mode in the address generation in terms of its access order, ensuring that no data is lost when the sliding window reaches the boundary, enabling the wrap-around address wrap-around mechanism to automatically jump to the tail or head of the cache when accessing beyond the Batch boundary, while maintaining column (vector) alignment and row-by-row correspondence, thereby ensuring the integrity and consistent position of the comparison data in the entire sliding window, improving the detection accuracy, and simplifying the control logic.

[0034] Furthermore, the embodiments of the present application control the buffer data update rhythm, enabling the reused loaded data, significantly reducing the internal cache pressure and external bandwidth overhead, while ensuring the data integrity and alignment accuracy in the sliding window processing.

[0035] The embodiments of the present application have at least the following significant advantages: 1. High parallelism and high throughput: By adopting a multi-data parallel input and processing architecture, the embodiments of the present application greatly improve the data throughput rate, capable of meeting the real-time processing requirements of massive data for applications such as 4D imaging radar.

[0036] 2. Efficient two-dimensional processing ability: Through a unique address generation and two-level cache update mechanism, the embodiments of the present application achieve seamless loopback access and local extreme value comparison of two-dimensional data at a very small on-chip cache cost, solving the core bottleneck of multi-dimensional data processing.

[0037] 3. Flexible configurability: By introducing the Marker mechanism, the device in the embodiments of the present application can dynamically change the detection strategy according to external instructions, easily realizing the classification detection of targets in different scenarios and different regions, with extremely high application flexibility.

[0038] 4. Hardware resource optimization: The embodiments of the present application adopt an improved extreme value definition (x0 <x1≥ x2) and a serial-parallel comparison architecture, saving approximately 50% of the number of comparators and significantly reducing the consumption of logic resources.

[0039] 5. Low-cost serial-parallel interpolator design: Through LUT, MSB alignment, and truncation techniques, the embodiments of the present application simplify complex division operations into table look-up and multiplication, significantly reducing the hardware implementation cost while ensuring accuracy.

[0040] 6. High scalability: The embodiments of this application can efficiently process two-dimensional data and seamlessly adapt to one-dimensional data streams of unlimited scale, and have strong versatility and scalability.

[0041] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0042] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0043] Figure 1 This is a schematic diagram of a data access mode for angle FFT calculation in radar signal processing. Figure 2 This is a flowchart illustrating the method for radar data processing in an embodiment of this application. Figure 3 This is a schematic diagram illustrating an example of a data access process based on 2D target detection in an embodiment of this application; Figure 4 This is a schematic diagram illustrating an example of a data access process based on 1D target detection in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the implementation process of the buffer update mechanism in the embodiments of this application; Figure 6 This is a schematic diagram of a logical structure embodiment for a series-parallel joint sliding window extreme value judgment in this application. Figure 7 This is a complete flowchart of the two-dimensional target detection method in the embodiments of this application; Figure 8 This is an application flowchart for a one-dimensional detection scenario (such as a unidirectional sliding window) in the embodiments of this application; Figure 9 This is a schematic diagram of the structural composition of an embodiment of the radar data processing apparatus in this application. Figure 10 This is a schematic diagram of the composition structure of another embodiment of the apparatus for implementing radar data processing in this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0045] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0047] It is understood that the terms "first" and "second" used in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0048] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0050] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0051] With the increase in the number of antennas and the improvement in resolution, the amount of raw data that radar systems need to process grows exponentially. On the one hand, the scale of data per frame increases dramatically as the system expands from traditional two-dimensional range-Doppler data to three-dimensional range-Doppler-angle data, and even further to four-dimensional range-Doppler-angle-elevation data. This not only requires higher storage bandwidth but also places higher demands on the processor's computing power. In vehicle scenarios, this surge in data poses a significant challenge to existing computing architectures due to the need to ensure millisecond-level real-time processing capabilities. On the other hand, in traditional one-dimensional constant false alarm rate (CFAR) detection algorithms, the computational complexity of sliding window operations is relatively controllable. However, when the detection dimension expands to two, three, or even four dimensions, the computational complexity increases from linear to quadratic, cubic, or even higher order. Furthermore, in practical applications, different scenarios present different target types and noise environments, and a single fixed detection threshold is often insufficient. However, most CFAR solutions in related technologies are based on globally fixed thresholds or single-dimensional adaptive thresholds, making it difficult to dynamically adjust the detection strategy for different scenarios. This results in persistently high false positive and false negative rates in certain complex environments, affecting the accuracy of target classification. This is particularly true when processing high-dimensional data, where there is a significant risk of false positives and false negatives. Furthermore, while some 2D CFAR solutions improve detection accuracy to some extent, their relatively fixed hardware architecture lacks flexibility and makes them difficult to adapt to different application requirements.

[0052] In radar signal processing, especially in angular fast Fourier transform (Angle FFT) calculations, the system needs to read a large amount of data from memory and perform calculations according to a specific pattern. Figure 1 This diagram illustrates a data access mode for angle FFT calculation in radar signal processing, including its data reading method and storage structure. This method has already been adopted in some radar systems (such as TI and NXP architectures), such as... Figure 1 As shown, the vertical direction represents the Doppler dimension, and the horizontal direction represents the beams (Angle). Figure 1 The grid area in the upper left represents the complete LogAbs Values ​​of Angle FFTs. SRCAINDX and SRCBINDX represent different index positions where the data was read. Figure 1This paper demonstrates a method for progressively reading data and computing 2D FFTs to reduce storage requirements and accommodate FFT computations of varying sizes. In each computation cycle, the system reads four consecutive samples from memory, each 16 bits long, for a total of 64 bits. This operation is repeated three times to acquire a specific range of data: reading the first set of four consecutive samples (64 bits), the second set of four consecutive samples (64 bits), and the third set of four consecutive samples (64 bits). Figure 1 The data access pattern shown is executed repeatedly for each Doppler vector, i.e., traversing the entire 2D plane to obtain the complete bit-mode output for FFT or signal analysis. However, as... Figure 1 As shown, since the data is stored in a grid structure with Doppler and angular dimensions, accessing boundary data may involve data wrap-around. That is, data that exceeds the storage range will be remapped to the relative boundary position. For example, if the accessed index exceeds the right boundary (i.e., the maximum angular index Max_Angle), the data will wrap around to the leftmost side (index 0) to ensure integrity.

[0053] Figure 1 The data access mode shown reads data directly from memory without relying on additional cache or intermediate storage space (No Buffer), reducing storage requirements. Furthermore, because it uses a step-by-step access mode instead of loading the entire matrix at once, it can support FFT calculations of different sizes and is not limited by a fixed dimension. However, since only four samples can be read per cycle and the process needs to be repeated three times to obtain complete data, the data processing rate is relatively low. Especially in high-resolution radar systems (such as 4D imaging radar), this method may not meet real-time requirements, particularly in large-scale target detection or high-dimensional FFT calculations. Moreover, because data access involves multiple independent memory reads, it may introduce additional access latency during large-scale data processing, reducing overall computational efficiency. This latency can affect system response speed, especially in applications with high real-time requirements (such as autonomous driving radar). Such a mode makes it difficult to guarantee target detection capabilities, which is detrimental to improving target detection accuracy while simultaneously considering real-time performance and system adaptability.

[0054] To optimize data access methods, improve throughput, and thus provide fast and accurate data access support for target detection, embodiments of this application provide a method for radar data processing, such as... Figure 2 As shown, it may include: Step 200: Divide the input multidimensional data into multiple two-dimensional data sub-regions.

[0055] In this embodiment, the input multidimensional data refers to the two-dimensional amplitude spectrum data generated by the radar system front-end through processing such as FFT, including but not limited to angle-Doppler maps, range-Doppler maps, or range-angle maps, etc., and the data is organized in the form of a two-dimensional array. It should be noted that the input multidimensional data can be two-dimensional or have a structure of three dimensions or more. The sliding window access and cache scheduling operations in the data access processing of this application are both processed based on the selected two-dimensional plane. In three-dimensional range-Doppler-angle data, the Doppler-angle plane can be selected as the detection dimension for processing.

[0056] In one exemplary instance, dividing the input multidimensional data into multiple two-dimensional data sub-regions may include: dividing the input data into multiple two-dimensional data sub-regions according to a Batch×Vector format. In one embodiment, Batch corresponds to the Doppler dimension or distance dimension, representing a vertical block in the two-dimensional input data, that is, a continuous set of rows; Vector corresponds to the angular dimension, representing a horizontal block in the two-dimensional input data, that is, a continuous set of columns.

[0057] For example, suppose the input multidimensional data is a 128×64 matrix, with 128 rows (representing Doppler directions) and 64 columns (representing angular directions). Assuming each batch contains 8 rows and each vector contains 8 columns, the entire large matrix is ​​divided into 16 batches (128 ÷ 8) and 8 vectors (64 ÷ 8), resulting in a total of 16×8 = 128 small blocks, each an 8×8 two-dimensional data sub-region. A batch represents a vertically sliding unit in data caching and scheduling, such as reading 8 rows of data in one batch in this embodiment; a vector represents processing several columns of data horizontally in parallel each time, such as reading 8 columns in parallel in this embodiment.

[0058] Step 201: Configure a data buffer unit for sliding window access based on the sliding window detection requirements, and divide the data buffer unit into multiple parallel data channels by column.

[0059] In one exemplary instance, the data buffer unit may include a parallel column buffer (PBUF), or simply a parallel buffer structure. The PBUF may be constructed prior to step 200.

[0060] The configuration of the data buffer unit is determined based on the sliding window detection requirements, such as the sliding window width, sliding step size, access direction, historical data dependencies, and parallel access capabilities, to ensure the continuous accessibility and efficiency of key data during the sliding window scrolling process. The sliding window width W is the number of columns or batches covered by the sliding window at one time, that is, the width of the data range that needs to be processed in parallel in each detection cycle. For example, if a detection requires looking at 5 consecutive columns, then W=5.

[0061] In some embodiments, to support different sliding window widths and processing requirements, the parallel read structure of PBUF can be flexibly configured, such as 8-way, 16-way, or 32-way. Each data channel structure supports fast access and updating of the data in that column. Each data channel has a column-oriented data cache structure with independent address management and update mechanisms, which can continuously read new data and replace old data during the sliding window scrolling process, thereby maintaining the dynamic update of the sliding window.

[0062] In one exemplary instance, each data channel is a column-oriented data buffer unit, corresponding to a column of data in the sliding window. Multiple column-oriented data buffer units that can be read and written simultaneously (i.e. in parallel) enable parallel extraction and processing of data within the sliding window area.

[0063] In this embodiment, to meet the parallel access requirements for multiple columns of data in sliding window detection, the system configures a data buffer unit that supports column-wise parallel reading before sliding window initialization. This data buffer unit, based on the column-by-column data retrieval characteristic of the sliding window structure, adopts a column-divided PBUF structure to improve data access efficiency within the sliding window area. In one embodiment, taking a sliding window width of W columns (e.g., W=8) as an example, each detection requires simultaneous access to W consecutive columns of data within the sliding window, and each column contains multiple vertical samples (e.g., from multiple rows or multiple batches). Therefore, the data buffer unit has W independent data channels, each corresponding to one column of data within the sliding window. These data channels can be read and written simultaneously, thereby supporting parallel extraction and processing of the sliding window.

[0064] Step 202: During the initialization phase of the detection process, some historical data is pre-read from the two-dimensional data sub-region and written into the data buffer unit. According to the sliding window order, the data required for current processing is extracted from the data buffer unit through multiple configured parallel data channels to construct the sliding window view.

[0065] In one exemplary instance, for a two-dimensional (2D) target detection scenario, during the initialization phase of the detection process, historical data is pre-read from each 2D data sub-region and written into the internal data buffer unit according to the preset sliding window structure requirements. This includes prioritizing the loading of the previous batch (Batch N-1) of data, followed by sequentially loading data from Batch 0 to Batch N-2 to construct the continuous buffer area required for the sliding window view. In one embodiment, this may include: first, writing the data of the last batch into the data buffer unit as historical reference data, and then sequentially reading the data of subsequent batches (Batch 0, 1, ...) to complete the initial filling of the sliding window's initial phase. N is the number of batches initially loaded, representing the total number of batches that the system must pre-load into the buffer before detection so that the sliding window can scroll continuously from the beginning. N is typically greater than or equal to W.

[0066] In the process of constructing the sliding window view, based on the set parallel data channel division method, the data columns covered by the current sliding window area are extracted from the data buffer unit in a column-to-parallel manner, realizing the parallel extraction and alignment of data within the sliding window, and providing a complete and continuous sliding window view for subsequent data access and processing.

[0067] For example, such as Figure 3 As shown, PBUF represents the storage system, and each row (column) represents the parallelism of that storage system. Figure 3 The illustrated embodiment can read and write 8 data items per clock cycle (clk). Figure 3In the code, Data read, clk 0~3 indicates data reading, clock 0~3; Data read, clk 4~7 indicates data reading, clock 4~7; Data read, clk 8~11 indicates data reading, clock 8~11; Data read, clk 4(N-1)-4 To clk 4(N-1)-1 indicates data reading, clock 4(N-1)-4 to 4(N-1)-1; Data read, clk 4(N-1)+0 To clk 4(N-1)+3 indicates data reading, clock 4(N-1)+0 to 4(N-1)+3; Data read, clk 4(N-1)+4 To clk 4(N-1)+7 indicates data reading, clock 4(N-1)+4 to 4(N-1)+7. According to the data flow of radar signal processing, the data can be divided into two dimensions, referred to as Batch and Vector, respectively. In this embodiment, the last Batch, Batch N-1, is read first and stored in the internal buffer. Then, Batch 0, Batch 1, ... Batch N-2 are read sequentially. 2D target detection places certain demands on the buffer. To reduce the required buffer, the data access method in this embodiment requires the first and last batches to be processed twice. The system inserts a bubble period during the data throughput process, allowing the first and last batches to be read twice. That is, the first and last batches are read once, and then normal reading continues. In this way, the data can be reused without adding another buffer to store it, thus ensuring data integrity and sliding window continuity without increasing buffer resources.

[0068] Since the current detection data needs to be compared with the corresponding position data of the previous batch, which requires wrapping, the data access method provided in this application embodiment ensures that when the current detection window starts at Batch 0, the previous batch is Batch N-1. This ensures that the current window detection point can be compared with the corresponding position data of the previous batch, even if the previous batch is already at the end of the buffer (such as Batch N-1), thus enabling smooth access to the corresponding position data of Batch N-1 and supporting wrapping access.

[0069] To support sliding window-based 2D target detection, a continuous cached sliding window view is pre-constructed during the detection process initialization phase, via step 201. Specifically, the previous batch (Batch N-1) of data is loaded into the internal cache first, followed by sequentially reading data from Batch 0 to Batch N-2 to complete the initialization of the sliding window structure. This continuous cached view ensures the ordered arrangement of multiple adjacent data batches within the internal cache, thus providing a technical guarantee for efficiently accessing historical and current data in the sliding window at a fixed pace in subsequent cycles, enabling continuous sliding window scrolling and detection calculations.

[0070] In an exemplary instance, for a one-dimensional (1D) target detection scenario, during the initialization phase of the detection process, based on the requirements of the sliding window structure, data required for current processing is extracted from a batch within a single two-dimensional data sub-region according to a fixed window width (e.g., 3 frames) to construct a sliding window view. In one embodiment, this may include: first reading data starting from the last row of the batch, and then sequentially loading data from row 0, row 1, up to the penultimate row of the batch, forming logically continuous data segments, which are then written to an internal data buffer unit. To support comparison operations between historical data and current detection data in the sliding window, an address wrapping mechanism is introduced during loading, allowing adjacent data to be extracted from the tail of the batch even when the sliding window reaches the beginning of the batch, ensuring the integrity and neighborhood alignment of the sliding window region. After the sliding window view is constructed, multiple configured parallel data channels can be used to extract the data points covered by the current sliding window from the data buffer unit, achieving parallel reading frame by frame and providing continuous, precisely aligned one-dimensional sliding window data for subsequent processing.

[0071] like Figure 4 As shown in the example, in 1D object detection, it can be viewed as a sliding window storing three frames of data. Starting from the last row of data in a single batch, the system reads the 0th and 1st rows of that batch, and so on. After completing the reading of the data for that batch, the above behavior is repeated to start reading the next batch. Generating data access addresses according to this data access method enables 1D object detection without limiting the data dimension, even with a very small finite cache.

[0072] Step 203: During the data access process, the access address of the neighborhood data is generated based on the logical position of the center of the constructed sliding window view in order to extract the target data within the sliding window area.

[0073] In one exemplary instance, step 203 may include: dynamically generating the access address of the corresponding neighborhood data for each sliding window center position. In one embodiment, the dynamic generation of the neighborhood data access address is calculated based on the sliding window center position and window size, combined with the current Batch and Vector indexes. That is, data access is performed around the logical position of the sliding window center, by calculating the neighborhood offset in combination with the sliding window size, and then dynamically generating the actual memory address by combining the Batch and Vector indexes, so as to achieve automatic access to all points in the sliding window region.

[0074] Because sliding window detection not only processes the current (center) point, but also accesses the surrounding data (i.e., the neighborhood) above, below, left, right, front, and back of that center point. Since the positions of these neighborhood points are offset relative to the center point, the actual access address of the neighborhood can be dynamically calculated from the position of the sliding window center. In other words, the neighborhood data access address is dynamically generated in each detection cycle by adding a predefined neighborhood offset to the logical coordinates of the sliding window center. This allows for the reading of all target data within the sliding window's coverage area.

[0075] The dynamic generation mechanism of the access address of the neighborhood data provided in step 203 ensures that the system can still accurately and in real time access the corresponding local data area to obtain the target data when the center of the sliding window changes over time or space. In the process of using the sliding window to achieve detection, the relevant data points around the center of the sliding window are correctly read, providing the necessary input data support for subsequent target detection algorithms, such as local extremum judgment and threshold comparison.

[0076] The radar data processing method provided in this application adopts a parallel computing architecture, performs data throughput with multiple degrees of parallelism, optimizes the data access method, thereby improving the throughput, improving the efficiency and flexibility of data access in the radar sliding window detection process, reducing cache overhead, and realizing high-speed, parallel, and structurally clear neighborhood data extraction operations, providing fast and accurate data access support for target detection.

[0077] In one exemplary instance, when access exceeds a predefined boundary, that is, when the sliding window crosses the batch boundary, the method for implementing radar data processing provided in this application embodiment may further include: Step 204: Extract the historical neighborhood data required by the sliding window based on the address wrap-around mechanism to ensure that the extracted target data is complete and aligned.

[0078] In this step, when the sliding window crosses the Batch boundary, it will access the historical neighborhood data based on the address wrap-around mechanism. That is, it will perform a modulo operation on the Batch index and automatically jump to the tail or head of the cache to extract the comparison data required when the sliding window crosses the boundary, and maintain the column alignment of the data in the sliding window area in the vector dimension and the row correspondence in the Batch dimension.

[0079] If the detection window crosses a boundary, such as when the sliding window is processing a boundary (e.g., Batch 0), the detection window needs to access the data in the previous Batch N-1. In order to ensure the integrity of the sliding window structure and the correctness of the comparison operation, in this embodiment, based on the wrap-around address wrapping mechanism, the address modulo operation is used to jump to the end of the cache, automatically complete the access to the previous Batch and realize the data extraction of row-by-row alignment + vector (column) alignment, thereby ensuring that the data in the detection window is complete and in the correct position.

[0080] Because of the data reading / address generation method adopted in this application embodiment, such as first loading the last batch (Batch N-1) as historical data, and then loading Batch 0, 1, ... in sequence to form a sliding window initialization dataset, this access order is naturally compatible with the wrap-around mode in address generation. This ensures that the sliding window can access Batch N-1 without losing data even when it is at the boundary (such as Batch 0). This allows the wrap-around address wrapping mechanism to automatically jump to the tail or head of the cache when accessing beyond the Batch boundary, while maintaining column (vector) alignment and row-by-row correspondence. This ensures that the comparison data in the entire sliding window is complete and the position is consistent, thereby improving detection accuracy and simplifying control logic.

[0081] In this embodiment, when the detection sliding window is located at a boundary position (e.g., the center of the sliding window is located in Batch 0), and the sliding window simultaneously needs to access data in the previous Batch (i.e., Batch N-1), the system performs address wrap-around processing. This mechanism uses a modulo operation on the Batch index to automatically jump to the end of the cache when the access logic crosses the boundary, thereby completing the extraction of data from the previous Batch and avoiding data loss. Through this mechanism, compensatory access to historical data in sliding window detection can be achieved without additional boundary processing logic, thereby improving the accuracy of the detection results and reducing implementation complexity.

[0082] In 2D sliding window detection, each sliding window operation requires accessing data from a two-dimensional window region. This data is a two-dimensional structure arranged in batches and vectors. Each sliding window operation only introduces a portion of the new data, while the majority remains data from the overlapping area of ​​the previous position. Reloading all window data with each sliding window operation would result in significant redundancy and waste. Therefore, this application proposes updating only the necessary portions and reusing existing data. In one exemplary instance, the radar data processing method provided in this application may further include: Step 205: Through a hierarchical circular caching structure and a partial data update mechanism, the sliding window only performs buffered refresh on newly added areas during the sliding process.

[0083] In one exemplary instance, the hierarchical circular cache structure may include: a first cache for quickly writing current data, which may be a small buffer temporarily storing sliding window data currently read from external sources or PBUF; and a second cache for storing data above and below the current frame in the sliding window, which is the main working buffer. In one embodiment, the second cache may include: a first data buffer for storing the frame where the center of the sliding window is located (the current frame), the data in the first data buffer being used as the main input data for the detection logic; and a second data buffer for storing the previous frame or previous row of the sliding window (historical data), the data in the second data buffer being used for comparison or interpolation with the current data.

[0084] like Figure 5 As shown, Figure 5 The upper part displays a 2D data map, showing the current detection center point 10 of the sliding window, with its neighbors being 4, 20, etc. It should be noted that... Figure 5 Each number in the table does not represent a single data point, but rather a number of parallel data points, i.e., a data column within a parallel data channel. Figure 5 The lower half is a timing diagram that shows the process of data progressing cycle by cycle in three buffers (first buffer RBUF_L0, first data buffer RBUF_2D_L1, and second data buffer RBUF_2D_L2). Figure 5 The horizontal axis represents the time period (clk), and each row represents the state of the data content in a certain level of buffer in the current period. For example: Figure 5The comment box in the upper right corner shows "'0' in RBUF_2D_L1 is processed, and compute interpolation / comparison with '4' in RBUF_L0 and '20' in RBUF_2D_L2". This means that the "0" in RBUF_2D_L1 is processed and interpolated / compared with the "4" in RBUF_L0 and the "20" in RBUF_2D_L2. When clk=7, 0 is loaded into the first data buffer of the second buffer, RBUF_2D_L1. Simultaneously, 4 is already loaded into the first buffer, RBUF_L0, and 20 is loaded into the second data buffer, RBUF_2D_L2. This satisfies the three sets of data (L0, L1, L2) required for the sliding window to process 0. For example: Figure 5 The comment box in the lower right corner shows "'6' in RBUF_2D_L1 is processed, and compute interpolation / comparison with '10' in RBUF_L0 and '2', in RBUF_2D_L2". This means that the "6" in RBUF_2D_L1 is processed and interpolated / compared with the "10" in RBUF_L0 and the "2" in RBUF_2D_L2.

[0085] In this embodiment, each buffer does not continuously expand but reuses a fixed-size space. Data moves forward like a conveyor belt, and the write pointer advances over time. Each time new data arrives, it pushes out the oldest data, continuously overwriting it. This is equivalent to a sliding window moving through the data space, and the buffers scroll synchronously to achieve the sliding window effect. When the sliding window slides one step, only one row or column contains new data; the remaining rows / columns are still covered by the current window. Therefore, only the newly entered row / column is updated. Figure 5As shown, at clk=4, RBUF_2D_L0 loads a new set of data with dimension N-4. At clk=5 and clk=6, the contents of RBUF_2D_L0 appear to be shifting to the right (indicated by arrows in the diagram), but the entire buffer is not completely cleared or refreshed; it only shifts without completely refreshing. When processing the current data, the sliding window only needs to index three buffers: previous frame data: RBUF_2D_L2 (e.g., 20), current frame data: RBUF_2D_L1 (e.g., 0), and for compensation / comparison: RBUF_2D_L0 (e.g., 4). Each data load is delayed by one cycle for use by the next sliding window stage. For example, when clk=7, the new data 0 is written to RBUF_2D_L1. The system does not immediately perform sliding window processing on it; instead, it waits until the data is aligned before participating in the sliding window comparison at clk=8. This ensures that the data at each position within the sliding window is aligned and not misaligned or out of order.

[0086] In summary, Figure 5 This application demonstrates an efficient sliding window buffer structure. The embodiment uses three fixed-size buffers (first buffer RBUF_L0, first data buffer RBUF_2D_L1, and second data buffer RBUF_2D_L2). Each buffer cyclically updates data over time, maintaining the continuity of the sliding window content by updating only the newly entered row. During data sliding, most historical data is retained in the cache for reuse, significantly reducing refresh counts and bandwidth consumption. Furthermore, this embodiment ensures consistent data alignment across sliding window layers, achieving high throughput and low latency sliding window processing. Figure 5 In this context, "Data process" refers to data processing; "Start to process" means to begin processing; and "1 cycle latency" means a delay of one cycle.

[0087] Step 205 of this embodiment controls the update rhythm of buffered data, enabling the reuse of loaded data, which greatly reduces internal cache pressure and external bandwidth overhead, while ensuring data integrity and alignment accuracy in sliding window processing.

[0088] pass Figure 2 The radar data processing method shown provides the core of data access and cache scheduling for the entire target detection method. The data access and address generation mechanism adopted, as a pre-step in sliding window detection, is responsible for dynamically extracting the center point and its neighborhood data. This provides an efficient, high-speed, and low-resource data source for subsequent extreme value judgment, threshold comparison, marker triggering, and interpolation positioning, and is a key support for achieving high-precision radar target detection.

[0089] In one exemplary instance, the method for implementing radar data processing provided in this application embodiment may further include: The extreme value comparison is performed on each data point in the extracted target data in parallel, and the results of multiple extreme value comparisons are merged to obtain the extreme value flag information.

[0090] In one exemplary instance, the method further includes: passing the data judgment flag information from the end of the previous batch of the batch containing the center point of the current sliding window into the current batch, and logically completing the splicing and judgment consistency of the extreme value bitmap, so as to avoid missing extreme values ​​due to breakage at the window boundary.

[0091] In this embodiment, all data points to be compared in the sliding window are compared simultaneously in the same frame. Each data point is independently compared with neighboring data to determine its extreme value, thereby quickly obtaining the extreme value comparison result. Then, the extreme value flag bitmap is output through Boolean and NOT logic combination, which improves the processing efficiency of potential target points in the positioning window.

[0092] For example, for each data point in the sliding window, such as data point x1 (center point), we extract its two adjacent points, such as data point x0 (left value) and data point x2 (right value). These data are retrieved from the sliding window cache (RBUF_2D_Lx). The condition for determining whether data point x1 is an extremum is: x0 < x1, that is, the left value is less than the center point, and x1 ≥ x2, that is, the center point is not less than the right value (equality is allowed). Traditional local extremum detection methods are usually based on a strict mathematical definition, that is, the center point must be greater than all its adjacent points. However, in radar applications, due to physical characteristics, measurement errors, or multipath echoes, target point values ​​often have multiple adjacent points with the same value, leading to missed detections by the traditional extremum definition. At the same time, conventional methods require comparing each detection point with multiple points in its neighborhood one by one, which has high resource overhead and high latency in hardware implementation and is not suitable for high parallelism systems. The local extremum detection method optimized in this application adopts improved extremum judgment logic and combines a serial-parallel hybrid comparison structure. By simplifying the number of comparators used through logic gates (AND and NOT), it achieves rapid target point location in a two-dimensional data structure and is suitable for parallel radar detection systems.

[0093] In one embodiment, each data point can be configured with a corresponding comparison logic module, such as two comparators and an AND gate. The comparison can be completed within one clock cycle. After parallel computation, the comparison results of each extreme value are synthesized, i.e., an extreme value flag bitmap is obtained by combining Boolean and NOT logic, and the output shows whether each point is an extreme value. The comparison results of all data points are executed in parallel.

[0094] Figure 6The figure shows a schematic diagram of an embodiment of the logical structure of serial-parallel combined sliding window extreme value judgment in an embodiment of the present application. In Figure 6 In the shown hardware parallel structure of serial-parallel combined sliding window extreme value judgment, the process of performing local extreme value judgment (such as local maximum detection) on a set of consecutive data and encoding the judgment result into a bitmap (bit map) for output is demonstrated. Taking the bit width of 8 bits as an example, as Figure 6 shown in the shaded small grid part, the input of serial-parallel combined sliding window extreme value judgment comes from the data of two buffers, namely the sliding window data RBUF_2D_L of the current frame (8 data to be processed this time) and the historical frame RBUF_L0 (from the previous Batch). There is a number in each small grid, indicating the data number corresponding to each column (channel) in the current sliding window, such as 0 - 7, 8 - 15, etc. Extreme value judgment is performed on each data point and its adjacent points on the left and right (such as x0 < x1 && x1 ≥ x2). Finally, an 8-bit extreme value bitmap (bit map) is output to indicate which points in this set of data are extreme values. It should be noted that the bit width can be configured, and it can be 8 bits, 16 bits, 32 bits, or even larger, depending on the parallelism of the sliding window (i.e., the number of parallel data channels) and the actual application requirements.

[0095] As Figure 6 shown in the upper part, the triangle symbol represents a comparator, which is used to read three adjacent data from the cache, namely the current data point x[i], the left adjacent data point x[i - 1] of the current data point, and the right adjacent data point x[i + 1] of the current data point, and judge whether the extreme value condition is satisfied. Each group of triangles contains two comparators: x[i - 1] < x[i] → judge whether the center point is larger than the left side, x[i] < x[i + 1] → judge whether the center point is smaller than the right side. The &&! logic block is a Boolean combination logic, which is used to perform extreme value judgment according to the comparison result and output 1 bit (whether it is an extreme value). The extreme value judgment condition = (x[i - 1] < x[i]) &&!(x[i] < x[i + 1]) = (x[i - 1] < x[i]) && (x[i] ≥ x[i + 1]). This logical judgment result (such as Figure 6 the sign in) is 1 or 0, indicating whether the data point, that is, the current data point x[i], is an extreme value. Figure 6 shows 8 groups of such extreme value judgment modules, numbered from 0 to 7 (arranged from right to left). Each group processes one data point in the sliding window, and all 8 groups work simultaneously. That is to say, the extreme value judgment of 8 data points can be completed in one beat (one clock cycle). Each judgment module outputs an extreme value judgment result of 1 bit indicating whether it is an extreme value (such as Figure 6The 8-bit extreme value judgment results are combined to form an 8-bit bitmap (e.g., 1 indicates an extreme value, 0 indicates a non-extreme value). Figure 6 The "Sign to the next 8pts data" is used in subsequent modules (such as target extraction, data packaging, etc.). The parallel comparison method provided in this application embodiment is suitable for parallel continuous comparison. Compared with the method of performing two comparisons between every two numbers to determine the extreme value, it saves half of the comparators.

[0096] To solve the problem of sliding window extreme value determination across batch boundaries, such as Figure 6 The portion of the current frame's sliding window data RBUF_2D_L and the historical frame's RBUF_L0 will pass the bit map and boundary point extremum flag signals to the next batch of processing to ensure that extrema of boundary data (such as at the end or beginning of a batch) are not missed. Figure 6 As shown, the left triangle (with the number 15) represents the output of the last data channel in the sliding window. For example, the extreme value judgment result numbered 15 comes from the last bit (the rightmost point) of the current 8-bit output. The middle triangle with "..." indicates that there is a pipeline or delay structure between multiple signal channels, used for judgment flags carried over from the previous batch. "Sign from the last batch" in the diagram is the boundary position information passed from the previous batch. The middle &&! box is used for the judgment logic of the current boundary point, that is, to combine the current extreme value result and the continuation signal of the previous batch for judgment. In this way, if an extreme value point is judged across the batch boundary, the result is still valid, so that the extreme value point will not be missed because the sliding window breaks at the boundary. The rightmost triangle with "Sign to the next batch" transmits this boundary judgment result (sign) to the processing unit of the next batch of data to ensure that the next batch can also receive the data judgment information from the end of the previous batch, thus ensuring that the sliding window is logically continuous.

[0097] The extreme value judgment structure in this embodiment supports cross-batch extreme value judgment, realizing the cross-batch boundary transfer and continuity judgment of extreme value judgment results. By passing the data judgment flag information at the end of the previous batch to the current batch, and logically completing the splicing of the extreme value bitmap and the consistency of judgment, it avoids missing extreme value points due to breakage at the window boundary, and ensures detection integrity and parallel efficiency.

[0098] In radar systems, to improve detection accuracy, interpolation calculations are often performed on local extrema to obtain more precise position estimates. Interpolation operations only perform fine position estimates on data that have been confirmed as potentially extrema, thereby improving detection accuracy and reducing overall computational resource overhead.

[0099] Because the amplitude of a single-frequency function is a bell-shaped function, and after taking the logarithm, it becomes a quadratic function, quadratic interpolators are widely used due to their lower cost. The interpolation formula for three-point extrema is (commonly used for detecting signal peak positions): ,in, , and It is the amplitude of three adjacent points in the sliding window, where the center point is... These are extreme points, data points. and data points The center point is respectively The left and right adjacent data points. Here, Indicates the center point data points on the left and adjacent data points on the right The amplitude difference Indicates the center point The weighted difference between the data points and their adjacent data points. The division operation in this interpolation algorithm consumes significant hardware resources, has high power consumption and long processing time, and is difficult to scale, especially when multiple points need to be processed in parallel. To reduce circuit resource consumption while maintaining interpolation accuracy, the radar data processing method provided in this application embodiment may further include: First, for the current local extreme point, calculate the amplitude difference between its left and right adjacent data points, as well as the weighted difference between the current local extreme point and its two adjacent data points; Next, non-zero detection and sign flag extraction are performed on the calculated amplitude difference and weighted difference, respectively. In one embodiment, non-zero detection is performed by performing an OR operation on the input values ​​to determine if all values ​​are 0, thus avoiding interpolation of invalid or zero differences. Sign flag extraction involves reading the sign flag (such as the most significant bit of fixed-point two's complement) of the amplitude difference and weighted difference to record the positive or negative sign of the calculation result. In this embodiment, non-zero detection skips invalid interpolation tasks in parallel computation, reducing redundant computational load.

[0100] Next, the most significant bit (MSB) of the calculated amplitude difference and weighted difference is extracted and aligned to a preset position to achieve numerical normalization. In one embodiment, a priority encoder can be used to detect the position where the most significant bit in the input data is 1, and the amplitude difference and weighted difference are shifted to the left respectively, so that their MSBs are aligned to a uniform high-order position (such as the Nth bit), and the alignment offset of the amplitude difference and weighted difference is recorded. Here, normalization means adjusting their values ​​to a fixed range, such as the interval [0.5, 1).

[0101] Next, based on the high-order truncation value of the normalized weighted difference, its reciprocal approximation value is obtained from a lookup table (LUT). In one embodiment, the high-order truncation value of the aligned weighted difference (e.g., taking 10 bits) is used as the address to find the reciprocal approximation value corresponding to the normalized weighted difference from the lookup table. In one embodiment, the lookup table stores the reciprocal (approximation) of the input within the range of [0.5, 1). In this embodiment, by replacing the divider with a lookup table reciprocal, the hardware complexity of the interpolation operation is significantly reduced, making it well-suited for large-scale parallel deployment.

[0102] Next, the obtained reciprocal approximation value is multiplied by the normalized amplitude value to obtain the initial interpolation value.

[0103] Next, the initial interpolation value is corrected for positional differences based on the shift difference between the normalized amplitude value and the weighted difference. In this step, if the alignment offsets of the amplitude difference and the weighted difference are different, it indicates that the initial interpolation value has been additionally scaled. In this case, the product result, i.e., the initial interpolation value, is shifted to the right or left by the corresponding number of bits according to the shift difference to restore the correct proportion. This ensures that the numerical accuracy of the final offset is not affected by the normalization disturbance.

[0104] The corrected interpolated value may be a fixed-point number with decimals; therefore, the process may further include truncation and rounding of the corrected interpolated value. In one embodiment, decimal rounding may include truncating the decimal places to a preset precision, and rounding up if a carry condition is met. Further, if the processed interpolated value exceeds the allowed representation range (e.g., exceeding ±1 or the maximum offset bit width), to prevent overflow and numerical anomalies, the process may further include: continuing saturation limiting processing, i.e., trimming to boundary values ​​according to saturation logic; simply put, if it exceeds the maximum value, output the maximum value; if it is less than the minimum value, output the minimum value.

[0105] Finally, based on the extracted sign flag, the signed fixed-point interpolation offset is output.

[0106] The interpolation method for local extrema in this application is a low-cost, parallel implementation suitable for interpolation calculation. It uses a lookup table with reciprocal operations instead of traditional division, avoiding the high complexity of conventional dividers. Combined with bit-width control and sign processing, it achieves a scalable, low-resource interpolation calculation structure, reducing circuit resource consumption while maintaining interpolation accuracy. The interpolation calculation method provided in this application, while retaining the standard interpolation calculation framework, constructs a hardware-friendly, low-cost interpolator structure through MSB alignment normalization, LUT reciprocal lookup, shift compensation, and skipping mechanisms. It is particularly suitable for resource-, area-, and power-sensitive system scenarios in parallel extrema detection.

[0107] Figure 7 This is a complete flowchart of the two-dimensional target detection method in the embodiments of this application, as shown below. Figure 7 As shown, this illustrates the entire process from loading two-dimensional data, determining extreme values ​​and thresholds, marker control (such as extreme points, interpolation completion points, boundary points, etc.), interpolation processing to outputting detection results; Figure 8 This is an application flowchart for a one-dimensional detection scenario (such as a unidirectional sliding window) in the embodiments of this application. The structure is similar to... Figure 7 While consistent, the logic is simpler, reflecting the configurability and flexibility of the radar data processing method implemented in this application. The target detection method using the radar data processing method provided in this application can cover both two-dimensional and one-dimensional detection tasks, and can be used individually or deployed in combination as needed.

[0108] Figure 7This diagram illustrates the control process of a two-dimensional sliding window for extreme value detection and interpolation post-processing. It describes how, starting from the input data stream pattern, the process proceeds through sliding window detection, condition judgment, marker control, reference judgment (REF), extreme value confirmation, and interpolation processing, ultimately generating an index (IDX) and interpolated output (ITP) stream for the extreme points. Simultaneously, a structured control signal stream (Map / Marker / Ref Pattern) is generated to support subsequent data alignment and termination. The general process includes: the input data stream sequentially loads sliding window data, sliding one column (or more) at a time; after initial candidate points are determined by the marker, threshold comparison is performed. Points that meet the extreme value determination criteria are marked with a detection flag, and precise offsets are calculated through interpolation, ultimately outputting a structured IDX / ITP stream. Simultaneously, the accompanying control bitmap (Map Output Stream) and reference bitmap (Ref Pattern) help maintain the integrity of the data stream and the continuity of the sliding window structure, including operations such as boundary wrapping and termination condition judgment. This application demonstrates the method for radar data processing provided in the embodiments of this application, showcasing the actual implementation of key aspects such as data organization, control mechanism, extreme value detection, and interpolation output, and illustrating a complete processing path for low-cost, high-efficiency sliding window detectors. Figure 7 In this context, EXT COND represents the extended condition; THR COND represents the threshold condition; MRKCOND represents the label condition; NOT UNIT represents the non-unit condition; Output Stream Pattern represents a structured IDX / ITP stream; Updated represents updated; Undetected / Detected represents undetected / detected; Same as Input represents the same as the input.

[0109] Figure 8 The diagram illustrates the control process of one-dimensional sliding window extreme value detection and interpolation post-processing. It specifically demonstrates how the entire one-dimensional detection path, from input stream loading to sliding window construction, extreme value judgment, interpolation generation, index output, and control state feedback, is completed in an orderly manner through the Ref mechanism, Map control, sliding window advancement, and termination control. It well reflects the extreme point detection and interpolation calculation output process based on a sliding window under one-dimensional sliding window construction in the radar data processing method provided in the embodiments of this application.

[0110] This application also proposes an apparatus for implementing radar data processing, such as... Figure 9 As shown, it includes at least a cache scheduling module; the cache scheduling module includes: a configuration unit, a loading unit, and a first processing unit; wherein, A configuration unit is used to divide the input multidimensional data into multiple two-dimensional data sub-regions; a data buffer unit for sliding window access is configured based on the sliding window detection requirements, and the data buffer unit is divided into multiple parallel data channels by column; The loading unit is used to pre-read some historical data from the two-dimensional data sub-region and write it into the data buffer unit during the initialization phase of the detection process. According to the sliding window order, the data required for current processing is extracted from the data buffer unit through multiple configured parallel data channels to construct the sliding window view. The first processing unit is used to generate access addresses for neighboring data based on the logical position of the center of the constructed sliding window view during the data access process, so as to extract target data within the sliding window area.

[0111] The radar data processing apparatus provided in this application adopts a parallel computing architecture, performs data throughput with multiple degrees of parallelism, optimizes the data access method, thereby improving the throughput, increasing the efficiency and flexibility of data access during radar sliding window detection, reducing cache overhead, and realizing high-speed, parallel, and structurally clear neighborhood data extraction operations, providing fast and accurate data access support for target detection.

[0112] In one exemplary instance, when access exceeds a predefined boundary, that is, when the sliding window crosses the batch boundary, the apparatus for implementing radar data processing provided in this application embodiment may further include: a second processing unit, configured to: Historical neighborhood data required for the sliding window is extracted based on the address wrap-around mechanism to ensure that the extracted target data is complete and aligned.

[0113] The data reading / address generation method used in this application embodiment has an access order that is naturally compatible with the wrap-around mode in address generation. This ensures that even when the sliding window is at the boundary (such as Batch 0), it can still access Batch N-1 without losing data. This allows the wrap-around address wrapping mechanism to automatically jump to the tail or head of the cache when accessing beyond the Batch boundary, while maintaining column (vector) alignment and row-by-row correspondence. This ensures that the comparison data in the entire sliding window is complete and the position is consistent, thereby improving detection accuracy and simplifying control logic.

[0114] In one exemplary instance, to reduce redundancy and waste, this application embodiment proposes updating only the parts that need updating and reusing existing data. The radar data processing apparatus provided in this application embodiment may further include: an update unit, used for: By using a hierarchical circular caching structure and a partial data update mechanism, the sliding window only performs buffered refreshes on newly added areas during the sliding process.

[0115] This application embodiment controls the update rhythm of buffered data, enabling the reuse of loaded data, which greatly reduces internal cache pressure and external bandwidth overhead, while ensuring data integrity and alignment accuracy in sliding window processing.

[0116] In one exemplary embodiment, the apparatus for implementing radar data processing provided in this application may further include an extreme value comparison module, used for: The extreme value comparison is performed on each data point in the extracted target data in parallel, and the results of multiple extreme value comparisons are merged to obtain the extreme value flag information.

[0117] In one embodiment, the extreme value comparison module is further configured to: pass the data judgment flag information of the end of the previous Batch of the Batch where the center point of the current sliding window is located to the current Batch, and logically complete the splicing and judgment consistency of the extreme value bitmap.

[0118] In one exemplary embodiment, the apparatus for implementing radar data processing provided in this application may further include an interpolation calculation module, used for: For the current local extreme point, calculate the amplitude difference between its left and right adjacent data points, as well as the weighted difference between the current local extreme point and its two adjacent data points; perform non-zero detection and sign flag extraction on the calculated amplitude difference and weighted difference respectively; extract the most significant bit (MSB) of the calculated amplitude difference and weighted difference, and align it to a preset position to achieve numerical normalization; based on the high-order truncation value of the normalized weighted difference, obtain its reciprocal approximation value from the lookup table; multiply the obtained reciprocal approximation value with the normalized amplitude value to obtain the initial interpolation value; perform position difference correction on the initial interpolation value according to the displacement difference between the normalized amplitude value and the weighted difference.

[0119] In one embodiment, the interpolation calculation module is further configured to: truncate and round the corrected interpolation value.

[0120] In one embodiment, the interpolation calculation module is further configured to: perform saturation constraint processing on the interpolated values ​​after truncation and rounding; and output a signed fixed-point interpolation offset based on the extracted sign flag.

[0121] This application also proposes an apparatus for radar data processing, applied to the parallel detection of radar data, such as... Figure 10 As shown, it includes at least: The data input interface is configured to receive parallel input radar data streams (two-dimensional or three-dimensional unfolded to a two-dimensional plane); in one embodiment, the bit width of the data input interface can be configured as 12–16 bits per channel.

[0122] The local extremum detection unit is configured to compare the current data in the radar data stream with its neighboring data in at least one dimension, and output the extremum judgment result according to the predefined extremum judgment logic; A threshold comparison unit is configured to compare the current data with at least one configurable threshold value; A logic operation unit is configured to receive the extreme value judgment result and the threshold comparison result, and perform a logical AND operation to obtain a detection result; and The data output interface is configured to output the detection results.

[0123] In one exemplary embodiment, the apparatus for implementing radar data processing provided in this application further includes: The storage system, including an internal cache unit, is configured to cache the radar data stream input to the data input interface.

[0124] In one exemplary embodiment, the apparatus for implementing radar data processing provided in this application further includes: The address generation unit is configured to generate specific read and write address sequences to enable wrapping access of data in the storage system. The local extremum detection unit is connected to the internal cache unit in the storage system and is configured to perform extremum comparison of two-dimensional data based on loopback access.

[0125] In one exemplary instance, the address sequence is configured so that when performing two-dimensional data detection, the device processes data in batches, first reading the data of the last batch and storing it in the internal cache unit, and then reading the data of the zeroth, first and subsequent batches in sequence to achieve data looping in the batch dimension, so that when processing the current batch of data, it is possible to access the data of its adjacent batches.

[0126] The address generation unit in this embodiment achieves wraparound access through batch index modulo operation, ensuring data continuity across batch boundaries without requiring additional boundary processing logic. This allows for a trade-off between bandwidth and cache resources when the cache is insufficient, by inserting idle cycles (Bubble) to reduce hardware costs. Providing a unified read / write address sequence simplifies the control logic of subsequent units, improving the system's implementation simplicity and stability.

[0127] In one exemplary instance, the internal caching unit includes a two-level cache, the data update mechanism of which includes: When data moves alternately between two levels of cache, the cache simultaneously contains the data to be processed and its adjacent data in the two-dimensional plane at any given time, thus supporting two-dimensional local extremum comparisons with minimal data caching and read overhead.

[0128] The system in this embodiment adopts a column-oriented parallel cache structure, which ensures that multiple columns of data can be accessed simultaneously, thus improving throughput. The internal cache uses a cyclic update mechanism, refreshing only the newly entered row / column of the sliding window, significantly reducing redundant access and bandwidth overhead.

[0129] In one exemplary instance, the predefined extremum judgment logic that the local extremum detection unit can employ is configured as follows: For a data point x1 in a one-dimensional sequence, if it is simultaneously greater than its preceding data point x0 and greater than or equal to its following data point x2, then the data point x1 is determined to be a local extremum.

[0130] In one exemplary instance, the local extremum detection unit may include: The first comparator is used to compare the size between data point x0 and data point x1; The second comparator is used to compare the size between data point x1 and data point x2; A NAND gate logic circuit, whose input is connected to the output of the first comparator and the second comparator, is used to output the judgment result of the local extremum.

[0131] The local extremum detection unit in this embodiment performs extremum judgment on multiple data points in parallel within the same clock cycle, significantly shortening the detection latency and improving the computation speed. This unit employs a two-comparator + AND-NOT logic structure, reducing the number of comparators compared to traditional methods, thus lowering hardware resource overhead and power consumption. Simultaneously, its extremum judgment logic allows the center point to be determined as an extremum even if it has an equal relationship with adjacent points, enhancing robustness and detection accuracy in real-world radar scenarios with noise and multipath interference. By outputting a bitmap of extremum judgment results in parallel, the local extremum detection unit directly cooperates with the threshold comparison unit and the marker processing unit, forming a high-throughput, low-latency target detection processing link, thereby achieving fast and reliable local extremum search under limited hardware resource conditions.

[0132] In one exemplary embodiment, the apparatus for implementing radar data processing provided in this application further includes: a marker processing unit configured to: It receives an externally input tag signal and performs a Boolean operation on the tag signal and the output of the logic operation unit to generate the final valid detection tag; The tagging signal received by the tagging processing unit is associated with the scene or area information of the radar data, enabling the device to apply different detection parameters to different scenes or areas by loading different tagging signals, thereby achieving multi-target classification function.

[0133] In one exemplary instance, the apparatus for implementing radar data processing provided in this application embodiment further includes: an interpolation unit configured to perform interpolation calculations on the data points corresponding to the valid detection identifier; Correspondingly, the data output interface is also configured to output the data points corresponding to the valid detection identifiers after interpolation.

[0134] In this embodiment, an external labeling signal is introduced through a labeling processing unit, which can load different detection parameters for different regions / targets, thus forming a multi-target classification capability. The combination of labels and logical results improves the configurability and scene adaptability of the detection.

[0135] In one exemplary instance, the interpolation unit includes a divider, which is configured to: Use a lookup table to calculate the reciprocal of the divisor, where the lookup table covers the range of values ​​[0.5, 1). Perform non-zero checks and sign bit checks on the numerator and denominator, and save the XOR result of the sign bit; Identify the first significant bit of the numerator and denominator, and move that significant bit to the highest significant bit, while recording the position difference between the significant bits of the numerator and denominator; According to the preset bit width, the numerator and denominator after shifting are truncated; Obtain the reciprocal of the truncated denominator by looking up a table; Multiply the reciprocal by the truncated numerator to obtain a preliminary product; Based on the position difference, extract the integer and fractional parts representing the final result from the preliminary product; Rounding and saturation of the decimal part; and The sign of the final result is recovered from the XOR result of the sign bit.

[0136] In this embodiment, the interpolation unit replaces the large-width divider with the reciprocal of the LUT plus shift compensation, significantly reducing resources and power consumption. It maintains high accuracy in extreme point location estimation and is suitable for large-scale parallel deployment. Furthermore, the interpolation unit also provides numerical protection mechanisms such as truncation / rounding / saturation to ensure the numerical stability and robustness of the results.

[0137] This application embodiment further provides a radar signal processing method, employing, as follows: Figure 10 The apparatus described in any one of the above can be used to perform parallel detection of radar data.

[0138] When the embodiments of this application are applied to radar signal processing, the device for radar data processing receives parallel data streams from front-end processing units (such as FFT, DBF, etc.) through a data input interface. After the data flows into the device, it can first be stored in the storage system (PBUF) or internal buffer (RBUF) under the control of the address generation unit.

[0139] like Figures 3-4 As shown, during two-dimensional detection, the address generation unit organizes the data into multiple batches and vectors. The device first reads the data from the last batch (e.g., Batch N-1) and pre-stores it in an internal buffer, then reads Batch 0, 1, 2... in sequence, forming a loop wrapping to ensure that each data point can be compared with its neighbors above, below, left, and right.

[0140] like Figure 3 As shown in the figure, in order to reduce the required cache storage space when performing 2D (two-dimensional) detection, the address generation method shown in the figure can be adopted, that is, the first batch is processed twice, so as to use the throughput bubble to avoid the extra cache required for the first data, thereby achieving the above-mentioned caching purpose. Figure 4 The middle section shows the logical order of memory address throughput that can be used to reduce the required cache storage space when performing 1D (one-dimensional) detection. This address generation method enables one-dimensional detection without limiting the data dimension to be achieved with a small finite cache.

[0141] like Figure 5 As shown, the update mechanism of the two-level internal caches RBUF_2D_L1 and RBUF_2D_L2 is as follows: Figure 5 As shown, data moves in the cache at a specific rhythm. For example, at time T, RBUF_2D_L1 stores Row N data, and RBUF_2D_L2 stores Row N+1 data. When new data Row N+2 arrives, it is moved into RBUF_2D_L2, while the original data in RBUF_2D_L2 (Row N+1) is moved into RBUF_2D_L1, and the original data in RBUF_2D_L1 (Row N) is moved out. In this way, two rows of data are always kept on-chip for comparison with the current row, greatly reducing the number of accesses to external storage.

[0142] Figure 5This illustrates a method for generating a logical array, specifically for memory caches such as large caches with two levels, like RBUF_2D_L1 and RBUF_2D_L2, and small caches for reading data (i.e., the storage space of the small cache is smaller than that of the large cache), such as RBUF_L0. The internal data update format of this memory cache can be... Figure 5 The method shown in the figure (each number in the figure indicates the number of parallel data) allows for 2D (two-dimensional) detection using a buffer that is twice the size of the vector.

[0143] In one embodiment, the local extremum detection unit may employ... Figure 6 The circuit shown is Figure 6 The circuit architecture diagram of a Local Peak Comparator is shown, as follows: Figure 6 As shown, the comparator architecture is a serial-parallel joint comparison architecture. Comparator 1 determines x0 < x1, and comparator 2 determines x1 ≥ x2. The outputs of the two comparators are connected to a NAND gate. Only when both comparison results are true (logic 1), the NAND gate outputs 0, which, after inversion, outputs 1, indicating that x1 is an extreme point. This structure uses only two comparators to complete the extreme value judgment of three data points, saving one comparator compared to the traditional method.

[0144] The threshold comparison unit compares the data with the configured threshold values ​​in parallel. The result is then ANDed with the extreme value judgment result in the logic operation unit. In other words, only points that are both extreme values ​​and exceed the threshold are initially considered valid points.

[0145] The Marker processing unit receives externally input Marker signals (e.g., high-order bits represent the region ID, and low-order bits represent the applicable threshold index for that region). The Marker processing unit further filters or marks the initial valid points based on the Marker signals, thereby achieving classification. The processed result triggers the interpolation unit.

[0146] In one embodiment, the interpolation unit, for valid points, can employ methods such as... Figure 7 The process shown performs secondary interpolation. Its core is to approximate the division using a LUT table (which stores the reciprocals of numbers between 0.5 and 1). By aligning the MSB and truncating the bit width (e.g., truncating to 12 bits), the numerator and denominator are normalized to a smaller dynamic range. Then, the reciprocal of the denominator is obtained through the LUT, multiplied by the numerator, and finally, a shift operation is used to correct the scaling effect caused by MSB alignment, yielding the final interpolation result. This process replaces a large-bit-width divider with a smaller multiplier, significantly reducing costs.

[0147] In another alternative embodiment, to further save chip area, the capacity of the internal cache can be reduced to be insufficient to store data for the entire dimension. In this case, the address generation unit inserts several idle cycles (bubble) after processing a data block to wait for the next data block to be loaded into the cache. In this way, a trade-off can be struck between processing efficiency and hardware cost.

[0148] The embodiments of this application provide a parallel detection device and method for radar signal processing, which can realize high-speed parallel processing of radar two-dimensional data, and has the capabilities of local extremum search, multi-threshold comparison, flexible target classification and low-cost interpolation. It also has the advantages of high throughput, low latency and low hardware cost.

[0149] The technical solutions provided in the embodiments of this application can be used to solve technical problems such as high data throughput, complex detection logic, and multi-target classification faced in fields such as radar signal processing. Specifically, high-speed multi-point parallel processing detection is achieved through techniques such as multi-parallel processing, two-dimensional plane detection, local extremum comparison, data stream markers, and multiple triggering. Local extrema and threshold comparisons are performed on a two-dimensional plane, effectively addressing the challenges brought by the expansion of data dimensions in fields such as 4D imaging radar. Furthermore, this invention also proposes a low-cost lookup table interpolation method to reduce detector costs and improve processing efficiency.

[0150] The technical features described in this application, such as multi-parallel processing capabilities, two-dimensional plane detection, local extremum comparison, data stream markers, and multiple triggering, as well as the technical solutions formed by their combinations, constitute the core advantages of this application. These features and solutions effectively solve technical problems in radar signal processing, such as high data throughput, complex detection logic, and multi-target classification, and have significant technical advantages and application value. For example, a data addressing method described in this application can achieve local extremum comparison and data processing in a two-dimensional plane with relatively low buffering costs, while also supporting flexible adaptation to one-dimensional and two-dimensional detection.

[0151] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. The technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, or network device, etc.) to execute the methods described above according to the embodiments of this application.

[0152] Software products may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0153] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0154] Program code for performing the operations of this application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0155] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A method for radar data processing, characterized in that, include: The input multidimensional data is divided into multiple two-dimensional data sub-regions; Configure a data buffer unit for sliding window access based on the sliding window detection requirements, and divide the data buffer unit into multiple parallel data channels by column; During the initialization phase of the detection process, some historical data is pre-read from the two-dimensional data sub-region and written into the data buffer unit. According to the sliding window order, the data required for current processing is extracted from the data buffer unit through multiple configured parallel data channels to construct the sliding window view. During data access, access addresses for neighboring data are generated based on the logical position of the center of the constructed sliding window view in order to extract target data within the sliding window area.

2. The method according to claim 1, further comprising: Historical neighborhood data required by the sliding window is extracted based on the address wraparound mechanism to ensure the completion and alignment of the target data.

3. The method according to claim 2, wherein, The extraction of historical neighborhood data required for the sliding window based on the address wraparound mechanism includes: When the sliding window is processing the boundary, it detects that the window needs to access the data in the previous row. Based on the address wraparound mechanism, it jumps to the end of the cache through address modulo operation to complete the access to the previous batch and realize the data extraction of row-by-row alignment and vector alignment.

4. The method according to claim 1, further comprising: Through a hierarchical circular caching structure and a partial data update mechanism, the sliding window only performs buffered refreshes on newly added areas during the sliding process.

5. The method according to claim 4, wherein, The hierarchical circular cache structure includes: The first cache is used for quickly writing the current data and temporarily stores the sliding window data currently read from the data buffer unit; A second buffer for storing data above and below the current frame in a sliding window, the second buffer includes: a first data buffer for storing the frame where the center of the sliding window is located; and a second data buffer for storing the previous frame or the previous row of the sliding window.

6. The method according to claim 1, 3 or 4, wherein, The input multidimensional data includes: two-dimensional amplitude spectrum data generated by the radar system front-end after processing; The process of dividing the input multidimensional data into multiple two-dimensional data sub-regions includes: The input data is divided into multiple two-dimensional data sub-regions in the format of Batch×Vector. Batch corresponds to the Doppler dimension, representing a continuous set of rows in the two-dimensional input data; Vector corresponds to the angular dimension, representing a continuous set of columns in the two-dimensional input data. Each of the data channels is a column-oriented data buffer unit, corresponding to a column of data in the sliding window.

7. The method according to claim 1, 3 or 4, wherein, The data buffer unit is a parallel column structured cache module PBUF.

8. The method according to claim 7, wherein, The parallel read structure configuration of the PBUF includes 8-way, 16-way, or 32-way.

9. The method according to claim 7, wherein, For 2D object detection scenarios, constructing the sliding window view includes: During the initialization phase of the detection process, historical data is pre-read from each of the two-dimensional data sub-regions and written into the internal data buffer unit according to the requirements of the sliding window structure. This includes prioritizing the loading of the previous batch Batch N-1 data, and then sequentially loading data from Batch 0 to Batch N-2 to construct the continuous buffer area required for the sliding window view; where N is the number of batches initially loaded.

10. The method according to claim 7, wherein, For a one-dimensional (1D) object detection scenario, the construction of the sliding window view includes: During the initialization phase of the detection process, based on the sliding window structure requirements, the data required for the current processing is extracted from a batch within a single two-dimensional data sub-region according to a fixed window width to construct the sliding window view.

11. The method according to claim 1, 2 or 4, wherein, The access address for generating neighborhood data includes: For each sliding window center position, based on the sliding window center position and window size, and combined with the current Batch and Vector index, the access address of the corresponding neighborhood data is dynamically generated.

12. The method according to claim 1, 2 or 4, further comprising: The extreme value comparison is performed on each data point in the target data in parallel, and the results of multiple extreme value comparisons are merged to obtain extreme value flag information.

13. The method of claim 12, further comprising: The data judgment flag information at the end of the previous Batch where the center point of the current sliding window is located is passed to the current Batch, and the splicing and judgment consistency of the extreme value bitmap are logically completed.

14. The method of claim 12, further comprising: For the current local extreme point, calculate the amplitude difference between its left and right adjacent data points, as well as the weighted difference between the current local extreme point and its two adjacent data points; Non-zero detection and sign flag extraction are performed on the calculated amplitude difference and weighted difference, respectively; Extract the most significant bit (MSB) of the calculated amplitude difference and weighted difference, and align them to a preset position to achieve numerical normalization. Based on the high-order truncation value of the normalized weighted difference, its reciprocal approximation value is obtained from the lookup table; The obtained reciprocal approximation value is multiplied by the normalized amplitude value to obtain the initial interpolation value; The initial interpolation value is corrected for position difference based on the displacement difference between the normalized amplitude value and the weighted difference.

15. The method of claim 14, further comprising: The corrected interpolated values ​​are then truncated and rounded.

16. The method of claim 15, further comprising: The interpolated values ​​after truncation and rounding are subjected to saturation constraint processing; Based on the extracted symbol flag, output the signed fixed-point interpolation offset.

17. An apparatus for processing radar data, characterized in that, The device, used for parallel detection of radar data, includes: The data input interface is configured to receive parallel input radar data streams; The local extremum detection unit is configured to compare the current data in the radar data stream with its neighboring data in at least one dimension, and output the extremum judgment result according to the predefined extremum judgment logic; A threshold comparison unit is configured to compare the current data with at least one configurable threshold value; A logic operation unit is configured to receive the extreme value judgment result and the threshold comparison result, and perform a logical AND operation to obtain a detection result; and The data output interface is configured to output the detection results.

18. The apparatus of claim 17, further comprising: The storage system, including an internal cache unit, is configured to cache the input radar data stream.

19. The apparatus of claim 18, further comprising: The address generation unit is configured to generate specific read and write address sequences to enable loopback access of data in the storage system. The local extremum detection unit is connected to the internal cache unit and is also configured to perform extremum comparison of two-dimensional data based on loopback access.

20. The apparatus according to claim 19, wherein, The address sequence is configured so that when performing two-dimensional data detection, the device processes data in batches, first reading the last batch of data and storing it in the internal cache unit, and then reading the zeroth, first and subsequent batches of data in sequence to achieve data looping in the batch dimension, so that when processing the current batch of data, it can access the data of its adjacent batches.

21. The apparatus according to claim 18, wherein, The internal caching unit includes a two-level cache, and the data update mechanism for the two-level cache includes: As data moves alternately between the two-level caches, at any given moment, the cache simultaneously contains the data to be processed and its adjacent data in the two-dimensional plane, thus supporting two-dimensional local extremum comparisons with minimal data caching and read overhead.

22. The apparatus according to claim 17 or 19, wherein, The predefined extremum judgment logic used by the local extremum detection unit is configured as follows: For a data point x1 in a one-dimensional sequence, if it is simultaneously greater than its preceding data point x0 and greater than or equal to its following data point x2, then the data point x1 is determined to be a local extremum.

23. The apparatus according to claim 22, wherein, The local extremum detection unit includes: A first comparator is used to compare the size between the data point x0 and the data point x1; A second comparator is used to compare the size between data point x1 and data point x2; A NAND gate logic circuit, whose input is connected to the output of the first comparator and the second comparator, is used to output the judgment result of the local extremum.

24. The apparatus of claim 17, further comprising: The tag processing unit is configured to receive an externally input tag signal and perform a Boolean operation on the tag signal and the output of the logic operation unit to generate a final valid detection tag; The tagging signal received by the tagging processing unit is associated with the scene or area information of the radar data.

25. The apparatus of claim 24, further comprising: The interpolation unit is configured to perform interpolation calculations on the data points corresponding to the valid detection identifier; The data output interface is also configured to output the data points corresponding to the valid detection identifiers after interpolation.

26. The apparatus according to claim 25, wherein, The interpolation unit includes a divider, which is configured to: Use a lookup table to calculate the reciprocal of the divisor, where the lookup table covers the range of values ​​[0.5, 1). Perform non-zero checks and sign bit checks on the numerator and denominator, and save the XOR result of the sign bit; Identify the first significant bit of the numerator and denominator, and move that significant bit to the highest significant bit, while recording the position difference between the significant bits of the numerator and denominator; According to the preset bit width, the numerator and denominator after shifting are truncated; Obtain the reciprocal of the truncated denominator by looking up a table; Multiply the reciprocal by the truncated numerator to obtain a preliminary product; Based on the position difference, extract the integer and fractional parts representing the final result from the preliminary product; Rounding and saturation processing are performed on the decimal part; as well as The sign of the final result is recovered from the XOR result of the sign bit.

27. A method for radar signal processing, characterized in that, Parallel detection of radar data is achieved using the apparatus described in any one of claims 17-26.

28. A computer-readable storage medium storing computer-executable instructions for performing the method for implementing radar data processing as described in any one of claims 1-16 and 27.

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