Signal acquisition monitoring equipment for DSI3 bus

Abstract

The invention discloses a signal acquisition monitoring device for a DSI3 bus, and the signal acquisition monitoring device for the DSI3 bus can be directly connected to the DSI3 bus when in use, and directly acquires and monitors data information in the DSI3 bus through a voltage signal acquisition circuit module and a current signal acquisition circuit module. Each module circuit of the signal acquisition monitoring equipment of the DSI3 bus is designed by adopting an independent discrete element, the circuit is simple, the hardware cost is low, the detection precision is high, the normal communication of the DSI3 bus is not influenced, and the requirements of testing personnel on testing and monitoring master and slave equipment connected with the DSI3 bus can be better met.

Description

Technical Field

[0001] This invention relates to the field of data communication technology, and in particular to a signal acquisition and monitoring device specifically designed for the DSI3 bus. Background Technology

[0002] Currently, driver assistance systems (ADAS) are becoming increasingly important in daily automotive use. The safe and normal operation of ADAS relies on sensors throughout the vehicle to capture the surrounding environment in real time and transmit the data to the vehicle's main controller. This data allows the driver to obtain driving information and make judgments, or the controller to autonomously intervene in the driving process. Ultrasonic radar sensors play a crucial role in various driving scenarios within ADAS systems. A car equipped with ADAS features multiple ultrasonic radar sensors located throughout its body. In scenarios such as low-speed parking, reversing, steering control, and emergency braking, ultrasonic radar sensors provide vital information to the vehicle's controller.

[0003] The new generation of ultrasonic radar sensors uses the DSI3 interface protocol. DSI3 (Distributed System Interface) is a powerful and universal bus protocol. Communication between the master (DSI3 Master) and slave (DSI3 Slave) devices is achieved via a single data signal line. The DSI3 Master transmits data to the DSI3 Slave via voltage, while the Slave replies to the master via current. The normality of data transmission on the DSI3 bus directly affects the vehicle's normal operation. Therefore, it is sometimes necessary to monitor the data on the DSI3 bus while ensuring normal communication to determine the communication between the ultrasonic radar sensor and the master control device. However, there is no dedicated device that can acquire the data on the DSI3 bus in real time without affecting normal communication. Currently, to acquire the data on the DSI3 bus in real time, an oscilloscope and current probe are typically used. This method is cumbersome, has poor measurement accuracy, and cannot directly obtain specific data information. While some existing simulation devices can mimic the signal input and output of the DSI3 bus, the number of ADC or DAC modules they use for signal conversion and sampling can interfere with normal DSI3 bus communication if directly connected to the bus. Therefore, they cannot acquire real-time data information from the DSI3 bus while ensuring normal DSI3 bus communication. Thus, it is necessary to design a dedicated device for real-time acquisition and monitoring of DSI3 bus data transmission. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a device capable of real-time acquisition and monitoring of DSI3 bus transmission data during normal DSI3 bus communication. To solve the above technical problems, this invention adopts the following technical solution: A signal acquisition and monitoring device for a DSI3 bus, wherein the DSI3 bus is used to connect a DSI3 master device and a DSI3 slave device, the signal acquisition and monitoring device includes: a voltage signal acquisition circuit module, the signal input terminal of which is connected to the DSI3 bus, and the voltage signal acquisition circuit module is used to acquire voltage signals sent by the DSI3 master device to the DSI3 slave device; a current signal acquisition circuit module, the current signal acquisition circuit module including a sampling resistor connected in series in the DSI3 bus, the current signal acquisition circuit module is used to acquire the current passing through the sampling resistor and convert it into a corresponding digital level signal; and an FPGA module, the FPGA module being connected to the signal output terminals of the voltage signal acquisition circuit module and the current signal acquisition circuit module, the FPGA module being used to parse and encode the output signals of the voltage signal acquisition circuit module and the current signal acquisition circuit module.

[0005] Preferably, the voltage signal acquisition circuit module includes a first operational amplifier and a first comparator. The positive input terminal of the first operational amplifier is connected to the DSI3 bus. The negative input terminal of the first operational amplifier is connected to a first resistor and a second resistor, respectively. The first resistor is grounded. The second resistor is connected to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is connected to the negative input terminal of the first comparator. The positive input terminal of the first comparator is connected to a third resistor and a fourth resistor, respectively. The third resistor is connected to a first reference voltage input terminal. The fourth resistor is connected to the output terminal of the first comparator. The output terminal of the first comparator is connected to the FPGA module.

[0006] Preferably, the current signal acquisition circuit module further includes a second operational amplifier and a third operational amplifier. The positive input terminal of the second operational amplifier is connected to one end of the sampling resistor connected to the DSI3 master device. The positive input terminal of the third operational amplifier is connected to one end of the sampling resistor connected to the DSI3 slave device. The negative input terminal of the second operational amplifier is connected to its output terminal. The negative input terminal of the third operational amplifier is connected to its output terminal. The output terminal of the second operational amplifier is connected to the positive input terminal of a fourth operational amplifier through a fifth resistor. The output terminal of the third operational amplifier is connected to the negative input terminal of the fourth operational amplifier through a sixth resistor. The positive input terminal of the fourth operational amplifier is grounded through a seventh resistor. The negative input terminal of the fourth operational amplifier is connected to its output terminal through an eighth resistor. The output of the fourth operational amplifier is connected to the positive input of the fifth operational amplifier. The negative input of the fifth operational amplifier is connected to the ninth and tenth resistors. The ninth resistor is grounded. The tenth resistor is connected to the output of the fifth operational amplifier. The output of the fifth operational amplifier is connected to the negative inputs of the second and third comparators, respectively. The positive input of the second comparator is connected to the eleventh and twelfth resistors. The eleventh resistor is connected to the second reference voltage input. The twelfth resistor is connected to the output of the second comparator. The output of the second comparator is connected to the FPGA module. The positive input of the third comparator is connected to the thirteenth and fourteenth resistors. The thirteenth resistor is connected to the third reference voltage input. The fourteenth resistor is connected to the output of the third comparator. The output of the third comparator is connected to the FPGA module.

[0007] Preferably, it further includes a reference voltage generation module, which includes three reference voltage generation circuits, and the three reference voltage generation circuits are respectively connected to the first reference voltage input terminal, the second reference voltage input terminal, and the third reference voltage input terminal.

[0008] Preferably, the reference voltage generation module is connected to the FPGA module. The reference voltage generation circuit includes an RC filter circuit. The input terminal of the RC filter circuit is connected to the FPGA module. The output terminal of the RC filter circuit is connected to the positive input terminal of the sixth operational amplifier. The negative input terminal of the sixth operational amplifier is connected to the sixteenth and seventeenth resistors. The sixteenth resistor is grounded. The seventeenth resistor is connected to the output terminal of the sixth operational amplifier. The output terminal of the sixth operational amplifier is connected to the reference voltage input terminal.

[0009] Preferably, the FPGA module generates a PWM signal and inputs it to the input terminal of the RC filter circuit. The FPGA module adjusts the corresponding reference voltage by controlling the duty cycle of the PWM signal.

[0010] Preferably, it further includes a communication module, through which the FPGA module communicates with the host computer.

[0011] The above technical solution has the following beneficial effects: The signal acquisition and monitoring device for the DSI3 bus can be directly connected to the DSI3 bus during use. It can directly acquire and monitor the data information in the DSI3 bus through the voltage signal acquisition circuit module and the current signal acquisition circuit module. Each module of the signal acquisition and monitoring device for the DSI3 bus is designed with separate discrete components. The circuit is simple, the hardware cost is low, the detection accuracy is high, and it will not affect the normal communication of the DSI3 bus. It can better meet the needs of testers to test and monitor the master and slave devices connected to the DSI3 bus. Attached Figure Description

[0012] Figure 1 This is an overall block diagram of the signal acquisition and monitoring equipment according to an embodiment of the present invention.

[0013] Figure 2 This is a circuit diagram of the voltage signal acquisition circuit module in an embodiment of the present invention.

[0014] Figure 3 This is a schematic diagram of the slave device's feedback current signal format on the DSI3 bus.

[0015] Figure 4 This is a circuit diagram of the current signal acquisition circuit module in an embodiment of the present invention.

[0016] Figure 5 This is a circuit diagram of the reference voltage generation module in an embodiment of the present invention.

[0017] Figure 6 This is a circuit diagram of the power supply module for the device in an embodiment of the present invention. Detailed Implementation

[0018] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0019] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make the invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention may be practiced by omitting one or more of the specific details, or other methods, components, apparatus, steps, etc., may be employed.

[0020] This invention discloses a signal acquisition and monitoring device for the DSI3 bus, primarily used for acquiring and monitoring data information on the DSI3 bus during normal communication. The DSI3 bus mainly connects DSI3 master devices and DSI3 slave devices. The DSI3 master device transmits data to the DSI3 slave device via voltage, while the DSI3 slave device replies with data information to the DSI3 master device via current signals. Figure 1 As shown, the signal acquisition and monitoring equipment mainly includes a voltage signal acquisition circuit module 1, a current signal acquisition circuit module 2, an FPGA module 3, and a reference voltage generation module 4.

[0021] The voltage signal acquisition circuit module 1 has its signal input terminal connected to the DSI3 bus. Module 1 acquires the voltage signal sent from the DSI3 master device to the DSI3 slave device, converts the voltage signal into a suitable voltage signal, and sends it to the FPGA module 3. The current signal acquisition circuit module 2 includes a sampling resistor R0 connected in series in the DSI3 bus. It acquires the current passing through the sampling resistor R0, converts it into a corresponding digital signal level, and sends it to the FPGA module 3. The FPGA module 3 analyzes and encodes the received output signals from the voltage and current signal acquisition circuit modules, converting the acquired signals to obtain the communication data from the DSI3 bus. This communication data can be directly displayed on a display device connected to the FPGA module or uploaded to a host computer for display, providing a clearer and more intuitive understanding of the data information on the DSI3 bus.

[0022] like Figure 2As shown in the figure, in a specific embodiment of the present invention, the voltage signal acquisition circuit module 1 includes a first operational amplifier A1 and a first comparator U1. The positive input terminal of the first operational amplifier A1 is connected to the DSI3 bus as the signal input terminal. The negative input terminal of the first operational amplifier A1 is connected to a first resistor R1 and a second resistor R2 respectively. The first resistor R1 is grounded. The second resistor R2 is connected to the output terminal of the first operational amplifier A1. The output terminal of the first operational amplifier A1 is connected to the negative input terminal of the first comparator U1. The positive input terminal of the first comparator U1 is connected to a third resistor R3 and a fourth resistor R4 respectively. The third resistor R3 is connected to the first reference voltage input terminal Vref1. The fourth resistor R4 is connected to the output terminal of the first comparator U1. The output terminal of the first comparator U1 is connected to the FPGA module 3.

[0023] The voltage signal acquisition circuit module 1 introduces the voltage signal on the DSI3 bus into the DSI3 Master input terminal. Since the DSI3 bus has multiple voltage ranges, the maximum and minimum voltage on the DSI3 bus is usually 5V and the maximum voltage is 10V. Therefore, the voltage on the DSI3 bus needs to be processed to a suitable voltage value by an operational amplifier before further processing. The first operational amplifier A1 can reduce the DSI3 bus voltage signal to a suitable voltage signal range. The voltage signal obtained after processing by the first operational amplifier A1 is input to the first comparator U1 through the negative input terminal. The first comparator U1 is a hysteresis comparator. The first comparator U1 is set with a suitable comparison voltage through the external third resistor R3 and fourth resistor R4 to ensure the accuracy of the comparator. The first comparator U1 compares the voltage signal input to the negative input terminal with the reference voltage input to the positive input terminal to obtain the DSI3 voltage signal with a level standard of 0-3.3V, and sends it to the FPGA module 3. The FPGA module 3 can then obtain the voltage signal sent by the DSI3 master device on the DSI3 bus. The FPGA module 3 parses and encodes the acquired voltage signal and converts it into Manchester encoding. In this way, the specific data information sent by the DSI3 master device to the DSI3 slave device can be obtained.

[0024] like Figure 3 As shown, the DSI3 slave device on the DSI3 bus replies to the DSI3 master device using a three-level encoded current signal. The encoding logic of the DSI3 current signal is as follows: in the default state, the static current Iq on the DSI3 bus represents 0, Iq plus Iresp represents 1, Iq plus twice Iresp represents 2, one current state represents one chip, and three current states (chips) represent one three-level encoded data (symbol). According to the symbol mapping table, one three-level encoded data (symbol) represents a four-digit hexadecimal number.

[0025] like Figure 4 As shown, in order to more accurately measure the three-level coded current signal on the DSI3 bus, the current signal acquisition circuit module 2 of this invention is designed with multiple independent operational amplifiers, comparators, and resistors. It includes a second operational amplifier A2 and a third operational amplifier A3. The positive input terminal of the second operational amplifier A2 is connected to one end of the sampling resistor R10 connected to the DSI3 master device, and the positive input terminal of the third operational amplifier A3 is connected to one end of the sampling resistor R10 connected to the DSI3 slave device. The sampling resistor R10 is connected in series in the DSI3 bus. The negative input terminal of the second operational amplifier A2 is connected to its output terminal, and the negative input terminal of the third operational amplifier A3 is connected to its output terminal.

[0026] The output of the second operational amplifier A2 is connected to the positive input of the fourth operational amplifier A4 through the fifth resistor R5. The output of the third operational amplifier A3 is connected to the negative input of the fourth operational amplifier A4 through the sixth resistor R6. The positive input of the fourth operational amplifier A4 is grounded through the seventh resistor R7. The negative input of the fourth operational amplifier A4 is connected to the output of the fourth operational amplifier A4 through the eighth resistor R8. The output of the fourth operational amplifier A4 is connected to the positive input of the fifth operational amplifier A5.

[0027] The negative input terminal of the fifth operational amplifier A5 is connected to the ninth resistor R9 and the tenth resistor R10. The ninth resistor R9 is grounded, and the tenth resistor R10 is connected to the output terminal of the fifth operational amplifier A5. The output terminal of the fifth operational amplifier A5 is connected to the negative input terminals of the second comparator U2 and the third comparator U3, respectively.

[0028] The positive input of the second comparator U2 is connected to the eleventh resistor R11 and the twelfth resistor R12. The eleventh resistor R11 is connected to the second reference voltage input Vref2. The twelfth resistor R12 is connected to the output of the second comparator U2. The output of the second comparator U2 is connected to the FPGA module 3. The positive input of the third comparator U3 is connected to the thirteenth resistor R13 and the fourteenth resistor R14. The thirteenth resistor R13 is connected to the third reference voltage input Vref3. The fourteenth resistor R14 is connected to the output of the third comparator U3. The output of the third comparator U3 is connected to the FPGA module 3.

[0029] In the current signal acquisition circuit module 2, the sampling resistor R10 is connected in series to the DSI3 bus. The second operational amplifier A2 and the third operational amplifier A3, acting as followers, are connected to the DSI3 master and slave terminals respectively. The second and third operational amplifiers A2 and A3 provide isolation and protection, preventing device circuitry from interfering with normal DSI3 bus communication. The output signal of the second operational amplifier A2 is connected to the positive input terminal of the fourth operational amplifier A4 through the fifth resistor R5, and the output signal of the third operational amplifier A3 is connected to the negative input terminal of the fourth operational amplifier A4 through the sixth resistor R6. The fourth operational amplifier A4 converts the current signal flowing through the sampling resistor R10 into a voltage signal. The fourth operational amplifier A4 converts the static current Iq on the DSI3 bus into the corresponding voltage value Vq, Iq+Iresp into the corresponding voltage value V1, and Iq+2Iresp into the corresponding voltage value V2. The fourth operational amplifier A4 outputs three voltage signal waveforms with levels Vq, V1, and V2.

[0030] The voltage waveform signals Vq, V1, and V2, which vary at three different levels, are input to the non-inverting input of the fifth operational amplifier A5 for voltage amplification. In order not to affect the normal communication of the DSI3 bus, the sampling resistor R0 is selected with a very small resistance value. Therefore, the voltage signal value obtained after passing through the fourth operational amplifier A4 is small. In order to ensure signal accuracy, voltage amplification is required. After the three voltage waveform signals with varying levels are amplified by the fifth operational amplifier A5, a three-level voltage waveform signal with appropriate level is obtained.

[0031] The three-level voltage waveform signal, amplified by the fifth operational amplifier A5, is input to the negative input terminals of the second comparator U2 and the third comparator U3, respectively. By setting the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14, the second reference voltage value Vref2 of the second comparator U2 is positioned between Vq and V1, and the third reference voltage value Vref3 of the third comparator U3 is positioned between V1 and V2. The second comparator U2 is used to determine whether the input three-level voltage waveform signal is greater than the second reference voltage value Vref2. If it is less than the second reference voltage value Vref2, the output of the second comparator U2 is high. Similarly, since the third reference voltage value Vref3 is greater than the second reference voltage value Vref2, the output of the third comparator U3 is also high. When both comparator outputs are high, it indicates that the voltage of the three-level voltage waveform signal is Vq, that is, the current on the DSI3 bus is Iq.

[0032] If the second comparator U2 determines that the input three-level voltage waveform signal value is greater than the second reference voltage Vref2, then the second comparator U2 outputs low. Simultaneously, the third comparator U3 determines whether the current three-level voltage waveform signal value is greater than the third reference voltage value Vref3. If it is less than the third reference voltage value Vref3, then the third comparator U3 outputs low. At this point, the two comparator outputs are high and low respectively, indicating that the current value of the three-level voltage waveform signal is V1, meaning the current on the DSI3 bus is Iq + Iresp. If the second comparator U2 outputs low, and the third comparator U3 determines that the current three-level voltage waveform signal value is greater than the third reference voltage value Vref3, then the third comparator U3 outputs low. At this point, both comparator outputs are low, indicating that the current value of the three-level voltage waveform signal is V2, meaning the current on the DSI3 bus is Iq + 2Iresp.

[0033] The signals output by the second comparator U2 and the third comparator U3 are given to the FPGA module 3. The FPGA module 3 merges the information sent by the second comparator U2 and the third comparator U3, and then performs data parsing and encoding to obtain the specific information of the current signal returned by the DSI3 slave device on the DSI3 bus. If both comparator outputs are high (11) at the same time, it actually means that the current data on the DSI3 bus is 0. If one comparator outputs high and the other low (10), it means that the current data on the DSI3 bus is 1. If both comparator outputs are low (00), it means that the current data on the bus is 2. This circuit is composed of multiple discrete independent components. The circuit design is simple and low-cost. It can directly convert data and can more accurately collect and monitor the current value on the DSI3 bus without affecting the normal communication of the DSI3 bus.

[0034] As a specific embodiment of the present invention, the signal acquisition and monitoring device further includes a reference voltage generation module 4, which includes three reference voltage generation circuits. These three circuits provide reference voltages to the first reference voltage input terminal Vref1, the second reference voltage input terminal Vref2, and the third reference voltage input terminal Vref3, respectively. Figure 5 As shown, the reference voltage generation circuit includes an RC filter circuit 6. The RC filter circuit 6 includes a fifteenth resistor R15 and a capacitor C. The input terminal of the fifteenth resistor R15 is connected to the FPGA module 3, and its output terminal is connected to the capacitor C and the positive input terminal of the sixth operational amplifier A6. The negative input terminal of the sixth operational amplifier A6 is connected to the sixteenth resistor R16 and the seventeenth resistor R17. The sixteenth resistor R16 is grounded, and the seventeenth resistor R17 is connected to the output terminal of the sixth operational amplifier A6. The output terminal of the sixth operational amplifier A6 is connected to the corresponding reference voltage input terminal.

[0035] During voltage output, the PWM signal output by FPGA module 3 is filtered by RC filter circuit 6 and then amplified by the sixth operational amplifier A6 to the required reference voltage value. This reference voltage is then provided to the corresponding comparators in voltage signal acquisition circuit module 1 and current signal acquisition circuit module 2. This module can adjust the reference voltage value output by the operational amplifier by setting the duty cycle of the PWM signal through FPGA module 3. The reference voltage value can be flexibly adjusted according to the actual situation, which has the advantages of lower circuit complexity and lower component cost compared to the method of generating voltage values ​​using a DAC.

[0036] In a preferred embodiment, the device further includes a communication module (such as an Ethernet interface module). The FPGA module 3 can communicate with the host computer 5 through this communication module. The FPGA module 3 can directly upload the collected communication data to the host computer 5, and the test personnel can monitor the communication data of the DSI3 bus through the host computer 5. At the same time, the FPGA module 3 can accept commands from the host computer 5 to adjust the parameters of each module of the DSI3 bus signal acquisition and monitoring device. In this way, the host computer 5 can control the FPGA module 3 to adjust the reference voltage of each module in real time according to the actual situation.

[0037] As a specific embodiment of the present invention, the signal acquisition and monitoring device also includes a power supply module circuit. For example... Figure 6 As shown, it includes two TI DC-DC power supply chips TPS565201 and one LDO chip AMS1117. After an external DC 12V input, it is supplied to the two power supply chips TPS565201, which output 5V and 3.3V respectively. The 5V mainly powers the operational amplifiers and other devices in the voltage and current signal acquisition module and the reference voltage generation module in the device, while the 3.3V powers the FPGA module and the Ethernet interface module. The 5V is converted to 1.2V by the chip AMS1117 to power the core voltage VCCINT of the FPGA module.

[0038] This signal acquisition and monitoring device for the DSI3 bus can be directly connected to the DSI3 bus during use. It directly acquires and monitors the data information in the DSI3 bus through voltage signal acquisition circuit modules and current signal acquisition circuit modules. Each module of this DSI3 bus signal acquisition and monitoring device is designed with separate discrete components, which makes the circuit simple, the hardware cost low, the detection accuracy high, and does not affect the normal communication of the DSI3 bus. It can better meet the needs of testers to test and monitor master and slave devices connected to the DSI3 bus.

[0039] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A signal acquisition and monitoring device for a DSI3 bus, wherein the DSI3 bus is used to connect a DSI3 master device and a DSI3 slave device, characterized in that, The signal acquisition and monitoring equipment includes: A voltage signal acquisition circuit module, wherein the signal input terminal of the voltage signal acquisition circuit module is connected to the DSI3 bus, and the voltage signal acquisition circuit module is used to acquire the voltage signal sent by the DSI3 master device to the DSI3 slave device; A current signal acquisition circuit module includes a sampling resistor connected in series in the DSI3 bus. The current signal acquisition circuit module is used to acquire the current passing through the sampling resistor and convert it into a corresponding digital signal level. An FPGA module is connected to the signal output terminals of the voltage signal acquisition circuit module and the current signal acquisition circuit module. The FPGA module is used to parse and encode the output signals of the voltage signal acquisition circuit module and the current signal acquisition circuit module.

2. The signal acquisition and monitoring device for DSI3 bus according to claim 1, characterized in that: The voltage signal acquisition circuit module includes a first operational amplifier and a first comparator. The positive input terminal of the first operational amplifier is connected to the DSI3 bus. The negative input terminal of the first operational amplifier is connected to a first resistor and a second resistor, respectively. The first resistor is grounded. The second resistor is connected to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is connected to the negative input terminal of the first comparator. The positive input terminal of the first comparator is connected to a third resistor and a fourth resistor, respectively. The third resistor is connected to the first reference voltage input terminal. The fourth resistor is connected to the output terminal of the first comparator. The output terminal of the first comparator is connected to the FPGA module.

3. The signal acquisition and monitoring device for DSI3 bus according to claim 2, characterized in that: The current signal acquisition circuit module further includes a second operational amplifier and a third operational amplifier. The positive input terminal of the second operational amplifier is connected to one end of the sampling resistor connected to the DSI3 master device. The positive input terminal of the third operational amplifier is connected to one end of the sampling resistor connected to the DSI3 slave device. The negative input terminal of the second operational amplifier is connected to its output terminal. The negative input terminal of the third operational amplifier is connected to its output terminal. The output terminal of the second operational amplifier is connected to the positive input terminal of a fourth operational amplifier through a fifth resistor. The output terminal of the third operational amplifier is connected to the negative input terminal of the fourth operational amplifier through a sixth resistor. The positive input terminal of the fourth operational amplifier is grounded through a seventh resistor. The negative input terminal of the fourth operational amplifier is connected to its output terminal through an eighth resistor. The output of the fourth operational amplifier is connected to the positive input of the fifth operational amplifier. The negative input of the fifth operational amplifier is connected to the ninth and tenth resistors. The ninth resistor is grounded. The tenth resistor is connected to the output of the fifth operational amplifier. The output of the fifth operational amplifier is connected to the negative inputs of the second and third comparators, respectively. The positive input of the second comparator is connected to the eleventh and twelfth resistors. The eleventh resistor is connected to the second reference voltage input. The twelfth resistor is connected to the output of the second comparator. The output of the second comparator is connected to the FPGA module. The positive input of the third comparator is connected to the thirteenth and fourteenth resistors. The thirteenth resistor is connected to the third reference voltage input. The fourteenth resistor is connected to the output of the third comparator. The output of the third comparator is connected to the FPGA module.

4. The signal acquisition and monitoring device for DSI3 bus according to claim 3, characterized in that, It also includes a reference voltage generation module, which includes three reference voltage generation circuits, and the three reference voltage generation circuits are respectively connected to the first reference voltage input terminal, the second reference voltage input terminal, and the third reference voltage input terminal.

5. The signal acquisition and monitoring device for DSI3 bus according to claim 4, characterized in that, The reference voltage generation module is connected to the FPGA module. The reference voltage generation circuit includes an RC filter circuit. The input terminal of the RC filter circuit is connected to the FPGA module. The output terminal of the RC filter circuit is connected to the positive input terminal of the sixth operational amplifier. The negative input terminal of the sixth operational amplifier is connected to the sixteenth and seventeenth resistors. The sixteenth resistor is grounded. The seventeenth resistor is connected to the output terminal of the sixth operational amplifier. The output terminal of the sixth operational amplifier is connected to the reference voltage input terminal.

6. The signal acquisition and monitoring device for DSI3 bus according to claim 5, characterized in that, The FPGA module generates a PWM signal and inputs it to the input terminal of the RC filter circuit. The FPGA module adjusts the corresponding reference voltage by controlling the duty cycle of the PWM signal.

7. The signal acquisition and monitoring device for DSI3 bus according to claim 1, characterized in that, It also includes a communication module, through which the FPGA module communicates with the host computer.

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