Memory management method and memory controller

Abstract

The present disclosure provides a memory management method and a memory controller. The method comprises: receiving a continuous mapping table recording a mapping relationship between a starting logical address and a starting physical address corresponding to a continuous super page group, the continuous super page group comprising a plurality of super pages; sequentially obtaining a target super page group to be parsed from the starting physical address; for each target super page group, performing a mapping unfolding operation, comprising: obtaining a super page group logical address and a super page group physical address; determining a physical page number and a mapping unit number of the target super page group based on a page type of the target super page group and whether the target super page group comprises a check page; and determining a super page group physical address of a next target super page group to be parsed based on whether the target super page group comprises a check page.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a memory management method and memory controller for processing map table expansion. Background Technology

[0002] In data storage systems, to optimize the space utilization of random access memory (RAM), when the host system continuously writes large blocks of data, the memory controller typically uses a continuous mapping table to record the data mapping relationships. Compared to a regular mapping table that records mapping relationships at 4KB granularity, a continuous mapping table only needs to record the starting logical address, the starting physical address, and the data length, thereby significantly reducing the storage overhead of metadata.

[0003] However, when the host system performs a partial overwrite of the aforementioned contiguous data, the original contiguous mapping relationship is disrupted. The memory controller needs to expand the compressed contiguous mapping table into a detailed ordinary mapping table to manage non-contiguous data segments. In existing technical solutions, this expansion process mainly relies on the controller's internal firmware to perform software calculations.

[0004] With the development of storage media technology, the layout of physical storage space has become increasingly complex. For example, to improve performance and reliability, memory modules typically employ multi-channel and multi-plane parallel architectures, introducing the concepts of superpages and superpage groups. Furthermore, different physical blocks may be configured with different page types (such as SLC, MLC, or TLC), resulting in inconsistent physical address strides. Simultaneously, for data protection, RAID parity pages are interspersed within the physical address space; these parity pages occupy physical space but do not store user data. Faced with this complex physical layout, existing software calculation methods require frequent conditional checks and address calculations, leading to excessive processor load, increased system latency, and consequently, impacting the overall write performance of the storage device. Summary of the Invention

[0005] In view of this, the present disclosure provides a memory management method and a memory controller. By pre-establishing a page type distribution table and a parity page distribution table, the mapping table parsing circuit of the memory controller can autonomously determine the number of physical pages and the number of mapping units based on the page type of the target superpage group and whether it includes a parity page, and allocate the target logical address and the target physical address accordingly. This allows the continuous mapping table expansion operation to be completed in one go, reducing the number of iterative interactions between software and hardware, reducing firmware overhead, and solving the above-mentioned technical problems.

[0006] This disclosure provides one or more embodiments of a memory management method applied to a memory controller for managing a storage device configured with memory modules. The method includes: receiving a continuous mapping table, wherein the continuous mapping table records the mapping relationship between the starting logical address and the starting physical address of corresponding consecutive superpage groups, wherein the consecutive superpage groups include multiple superpage groups; sequentially obtaining target superpage groups to be resolved starting from the starting physical address; and performing a mapping expansion operation for each target superpage group, including: obtaining the superpage group logical address and the superpage group physical address of the target superpage group; determining the number of physical pages and the number of multiple mapping units of the target superpage group based on the page type of the target superpage group and whether it includes a parity page; allocating multiple target logical addresses from the superpage group logical address and multiple target physical addresses from the superpage group physical address based on the number of mapping units; generating and outputting the mapping relationship between the multiple target logical addresses and the multiple target physical addresses; and determining the superpage group physical address of the next target superpage group to be resolved based on whether the target superpage group includes a parity page.

[0007] This disclosure provides a memory controller in one or more embodiments for controlling a storage device configured with a memory module. The memory controller includes: a buffer memory; a memory interface control circuit electrically connected to the memory module; a data management circuit electrically connected to a host system; a mapping table parsing circuit; and a processor electrically connected to the memory interface control circuit, the buffer memory, the data management circuit, and the mapping table parsing circuit. The processor is configured to instruct the mapping table parsing circuit to perform a mapping unpacking operation on a corresponding contiguous mapping table. The mapping table parsing circuit is configured to: receive a contiguous mapping table, wherein the contiguous mapping table records the mapping relationship between the starting logical address and the starting physical address of a corresponding contiguous superpage group, wherein the contiguous superpage group includes multiple superpage groups; sequentially obtain the target superpage groups to be parsed starting from the starting physical address; for each target superpage group, perform a mapping unpacking operation, including: obtaining the superpage group logical address and superpage group physical address of the target superpage group; determining the number of physical pages and mapping units of the target superpage group based on the page type of the target superpage group and whether it includes a parity page; allocating multiple target logical addresses from the superpage group logical address and multiple target physical addresses from the superpage group physical address based on the number of mapping units; generating and outputting the mapping relationship between the multiple target logical addresses and the multiple target physical addresses; and determining the superpage group physical address of the next target superpage group to be parsed based on whether the target superpage group includes a parity page.

[0008] Based on the above, the memory management method and memory controller provided in this disclosure, by receiving a continuous mapping table and sequentially obtaining the target superpage groups to be resolved starting from the starting physical address, enable the memory controller to perform mapping expansion operations on a superpage group basis, reducing the number of processing loops. During the mapping expansion operation, the memory controller determines the number of physical pages and mapping units based on the page type of the target superpage group and whether it includes a parity page. Through a dual confirmation mechanism using a page type distribution table and a parity page distribution table, it accurately determines the number of physical pages actually used for storing user data in each target superpage group. Furthermore, by autonomously calculating the address of the next target superpage group to be resolved through hardware, the memory controller can expand the continuous mapping table into a normal mapping table containing complete mapping relationships in one go, reducing the number of iterative interactions between software and hardware and lowering firmware overhead. Attached Figure Description

[0009] Figure 1 This is a block diagram of a host system and storage device according to embodiments of the present disclosure;

[0010] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure;

[0011] Figure 3 This is a schematic diagram of the architecture of a mapping table parsing circuit according to an embodiment of the present disclosure;

[0012] Figure 4 This is a schematic diagram showing the expansion of a continuous mapping table into a regular mapping table according to an embodiment of this disclosure;

[0013] Figure 5 This is a schematic diagram of the physical page distribution of a contiguous superpage group corresponding to a contiguous mapping table, according to an embodiment of the present disclosure;

[0014] Figure 6 This is a schematic diagram of the encoding rules for a page type distribution table according to an embodiment of this disclosure;

[0015] Figure 7 This is a schematic diagram of the verification page distribution table and the internal structure of the superpage group according to an embodiment of this disclosure;

[0016] Figure 8 This is a detailed flowchart illustrating the mapping expansion operation according to an embodiment of the present disclosure. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0019] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, a buffer memory 214, and a mapping table parsing circuit 215.

[0020] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0021] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0022] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0023] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0024] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0025] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the memory management method provided in this disclosure.

[0026] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0027] Furthermore, processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, processor 211 is configured to instruct mapping table parsing circuit 215 to perform a mapping unpacking operation on a corresponding contiguous mapping table. When processor 211 receives a request to unpack a contiguous mapping table into a normal mapping table, processor 211 passes the contiguous mapping table to mapping table parsing circuit 215 and instructs mapping table parsing circuit 215 to sequentially obtain the target superpage groups to be parsed, starting from the starting physical address, and perform a mapping unpacking operation for each target superpage group. The mapping unpacking operation includes: obtaining the superpage group logical address and superpage group physical address of the target superpage group; determining the number of physical pages and the number of mapping units of the target superpage group based on the page type of the target superpage group and whether it includes a parity page; allocating multiple target logical addresses from the superpage group logical address and multiple target physical addresses from the superpage group physical address based on the number of mapping units; generating and outputting the mapping relationship between the multiple target logical addresses and the multiple target physical addresses; and determining the superpage group physical address of the next target superpage group to be parsed based on whether the target superpage group includes a parity page.

[0028] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0029] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0030] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 receives instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation according to a read instruction from the host system 10, reading data from one or more physical units of the memory module 220 via the memory interface control circuit 213 and writing the read data to the host system 10 via the connection interface circuit 230. In one embodiment, when the host system 10 continuously writes multiple data items to the storage device 20, the data management circuit 212 works with the processor 211 to establish a continuous mapping table. This continuous mapping table records the mapping relationship between the starting logical address and the starting physical address of corresponding consecutive superpage groups, thereby reducing the storage space occupied by the mapping table.

[0031] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming) operations, read operations, or erase operations on the memory module 220.

[0032] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0033] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to find the physical unit mapped to a logical unit (e.g., find the physical page mapped to a logical page; find the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to find the logical unit mapped to a physical unit (e.g., find the logical page mapped to a physical page; find the logical address mapped to a physical address).

[0034] In this embodiment, when the host system 10 continuously writes data, the memory controller 210 can use a contiguous mapping table to record the mapping relationship between the starting logical address and the starting physical address of consecutive superpage groups, instead of creating an independent mapping entry for each physical page. For example, assuming the host system 10 continuously writes 1024 data blocks of 4KB mapping units, and the logical addresses of these data blocks are LA0, LA1, LA2, ... LA1023, corresponding to physical addresses PA0, PA1, PA2, and PA1023 respectively. PA1023. Since these data are written sequentially, the memory controller 210 only needs to record the mapping relationship between the starting logical address LA0 and the starting physical address PA0 in the sequential mapping table, and the data volume is 1024×4KB, without having to create 1024 independent mapping entries for 1024 mapping units. When the host system 10 needs to read data at logical address LA24, the memory controller 210 can calculate the physical address corresponding to LA24 as PA24 based on the mapping relationship between the starting logical address LA0 and the starting physical address PA0 through the offset.

[0035] When host system 10 performs a write operation on data within the address range covered by the continuous mapping table, memory controller 210 needs to expand the continuous mapping table into a normal mapping table to completely record the mapping relationship between the target logical address and the target physical address of each mapping unit. For example, suppose host system 10 performs a write operation on data at logical address LA100. The written data will be stored at a new physical address PA2000, instead of the original physical address PA100. At this time, the originally continuous physical address sequence becomes discontinuous, and memory controller 210 can no longer calculate the physical address corresponding to LA100 using a single starting address and offset. Therefore, memory controller 210 needs to expand the continuous mapping table into a normal mapping table, recording LA0 corresponding to PA0, LA1 corresponding to PA1, etc., in the normal mapping table. LA99 corresponds to PA99, LA100 corresponds to PA2000, and LA101 corresponds to PA101. The mapping relationship between LA1023 and PA1023.

[0036] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this embodiment, buffer memory 214 is also used to store the contiguous mapping table, page type distribution table, parity page distribution table, and mapping relationships generated by mapping unrolling operations required by this disclosure. The page type distribution table indicates the page type of each superpage group in a contiguous superpage group, and the parity page distribution table indicates whether one or more specific superpage groups include parity pages.

[0037] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 includes multiple channels and multiple planes. The memory controller 210 maps the storage pages of the multiple channels and multiple planes within the memory module 220 to superpage groups, and organizes the multiple superpage groups into contiguous superpage groups as the management object for contiguous mapping table and mapping unpacking operations. It should be noted that the contiguous mapping table is a mapping table established for logically contiguous data, recording the mapping relationship between the starting logical address and the starting physical address in the contiguous superpage group.

[0038] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0039] In another embodiment, the memory cells in memory module 220 may have different page types, including Single Level Cell (SLC), Multi Level Cell (MLC), Triple Level Cell (TLC), and Quad Level Cell (QLC). Different page types have different numbers of physical pages: a single-level cell corresponds to 1 physical page, a multi-level cell corresponds to 2 physical pages, a triple-level cell corresponds to 3 physical pages, and a quad-level cell corresponds to 4 physical pages. When performing the mapping unpacking operation, memory controller 210 needs to determine the number of physical pages based on the page type of the target superpage group.

[0040] In another embodiment, the memory module 220 may be configured with a RAID (Redundant Array of Independent Disks) parity mechanism, and some superpage groups include parity pages for storing parity data. The parity pages are located at the end of the corresponding superpage group to provide data redundancy protection. When the target superpage group includes a parity page, the memory controller 210 needs to deduct the physical pages occupied by the parity page from the number of physical pages when performing the mapping unrolling operation to ensure that the target logical address and target physical address are allocated only to user data.

[0041] Figure 5 This is a schematic diagram of the physical page distribution of a continuous superpage group corresponding to a continuous mapping table, according to an embodiment of the present disclosure.

[0042] Reference Figure 5 In this embodiment, the memory module 220 includes a memory bank (e.g., a chip) Bank0, which includes channels CH0 and CH1. Each channel includes planes P0, P1, P2, and P3. The memory controller 210 maps multiple memory pages in the same string that span channels CH0 and CH1 and planes P0 to P3 into a superpage group.

[0043] Specifically, in Figure 5In the illustrated embodiment, string 0 has a page type of Single-Level Unit Page (SLC), spanning planes P0 to P3 (physical page numbers 0, 1, 2, 3) of channel CH0 and planes P0 to P3 (physical page numbers 4, 5, 6, 7) of channel CH1, totaling 8 physical pages forming a physical page group that constitutes superpage 1 (SP1), and also constitutes superpage group 1 (SPG1) containing only one superpage. Similarly, string 1 has a page type (Page_Type) of Single-Level Unit Page (SLC), spanning planes P0 to P3 (physical page numbers 8, 9, 10, 11) of channel CH0 and planes P0 to P3 (physical page numbers 12, 13, 14, 15) of channel CH1, totaling 8 physical pages forming a physical page group that constitutes superpage 2 (SP2), and also constitutes superpage group 2 (SPG2) containing only one superpage.

[0044] The page types for strings 2 and 3 are Multi-Level Cellular (MLC). Since a MLC corresponds to two physical pages, Superpage Group 3 (SPG) includes the two rows of storage pages for string 2, consisting of Superpage 3 (SP3) and Superpage 4 (SP4), namely, two physical page groups: physical page numbers 16 to 19 and 24 to 27 (a total of 16 physical pages) and physical page numbers 20 to 23 and 28 to 31 (a total of 16 physical pages). Similarly, the two rows of storage pages for string 3 constitute Superpage Group 4 (SPG4), including Superpage 5 (SP5) and Superpage 6 (SP6) (i.e., two physical page groups), where physical page numbers P43 and P47 are parity pages, indicated by bold boxes.

[0045] The page type for string 4 is Three-Level Cell Page (TLC). Since a three-level cell page corresponds to three physical pages, superpage group 5 (SPG5) includes the three rows of storage pages for string 4, consisting of superpage 7 (SP7), superpage 8 (SP8), and superpage 9 (SP9). These correspond to physical page numbers 48-51 and 60-62, physical page numbers 52-55 and 64-66, and physical page numbers 56-59 and 68-70, totaling three physical page groups. Physical page numbers P63, P67, and P71 are parity pages.

[0046] In this embodiment, the physical pages in the superpage group can be divided into two types: data pages and parity pages. Data pages are used to store user data written by the host system 10. There is a mapping relationship between the physical address and logical address of each mapping unit. The host system 10 can access the user data in the data page through the logical address. Parity pages are used to store parity data generated based on the RAID (Redundant Array of Independent Disks) algorithm. The parity data is a redundancy error correction code calculated based on the user data of multiple data pages. Since the parity page stores parity data rather than user data, the host system 10 will not directly access the parity page. Therefore, the parity page does not have a corresponding logical address. The memory controller 210 needs to skip the physical address corresponding to the parity page when performing the mapping unrolling operation.

[0047] In another embodiment, the verification data stored in the verification page can be used for data recovery. For example, suppose the superpage group SPG4 includes 7 data pages and 1 verification page. The 7 data pages store user data D0, D1, D2, D3, D4, D5, and D6 respectively, and the verification page stores verification data P, where the verification data P is obtained by performing an XOR operation on the user data D0 to D6. When the data page storing user data D3 in memory module 220 fails or becomes corrupted, memory controller 210 can read user data D0, D1, D2, D4, D5, and D6 from the remaining six data pages, as well as check data P from the check page, and perform an XOR operation. This allows the lost user data D3 to be recovered. Through this method, the checksum page provides redundant protection for user data in the superpage group, thereby improving the data reliability of the storage device 20.

[0048] By mapping pages from multiple channels and planes to superpage groups, the memory controller 210 can manage data in units of superpage groups. When the host system 10 writes data continuously, the memory controller 210 maps consecutive logical addresses to consecutive superpage groups and organizes multiple superpage groups into consecutive superpage groups. The memory controller 210 only records the mapping relationship between the starting logical address and the starting physical address of the consecutive superpage group in the consecutive mapping table, thereby reducing the storage space occupied by the mapping table.

[0049] It is worth noting that, although Figure 5The configuration of superpage groups is illustrated using specific page type arrangements (such as a mixture of SLC, MLC, and TLC) and a specific number of physical pages, but this is only for illustrative purposes and is not intended to limit the scope of this disclosure. In practical applications, the configuration of consecutive superpage groups may vary depending on the specific specifications of the memory module 220 or the firmware management strategy. For example, consecutive superpage groups may consist of a single type of superpage group (such as all TLC) or use different mixing ratios. Furthermore, the number of physical pages contained in each superpage group may also be adjusted according to the number of channels or planes. The mapping table parsing circuit 215 of this disclosure can dynamically adapt to various superpage group configurations by reading the page type distribution table and the check page distribution table, without being limited by... Figure 5 The specific example shown.

[0050] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure.

[0051] Please refer to Figure 2 The memory management method provided in this embodiment is applicable to Figure 1 The memory controller 210 shown performs the main computational steps, in particular through the mapping table resolution circuit 215 configured therein, to reduce the load on the processor 211.

[0052] First, in step S210, the mapping table parsing circuit 215 receives the continuous mapping table. Specifically, the memory management method in this embodiment is typically triggered by a write operation from the host system. When the memory controller 210 receives a write instruction from the host system, the processor 211 parses the write logical address contained in the instruction and determines whether the write logical address falls within the address range covered by the currently established continuous mapping table. If the determination result is yes, it means that the host system intends to overwrite a segment of data that was originally stored continuously and compressed. At this time, the original continuous mapping relationship will no longer be applicable, and a detailed version of the L2P mapping table is needed to handle the changes in the local mapping relationship.

[0053] Therefore, processor 211 triggers a mapping unpacking process, transmitting a contiguous mapping table containing the mapping relationships of the data segment to mapping table parsing circuit 215. This contiguous mapping table records the starting logical address and starting physical address corresponding to a contiguous superpage group in a simplified format, where a contiguous superpage group is a collection of multiple superpage groups in memory module 220. Through this mechanism, memory controller 210 only converts the contiguous mapping table into a regular mapping table containing detailed mapping relationships when necessary (i.e., when a rewrite occurs), and otherwise maintains a compressed state to significantly reduce the space occupied by buffer memory 214.

[0054] To ensure that the mapping unrolling operation can correctly adapt to the complex physical structure of the memory module 220, the mapping table parsing circuit 215, after receiving the continuous mapping table, will further obtain the corresponding page type distribution table and check page distribution table based on the continuous mapping table. For example, it can read the page type distribution table and check page distribution table from the memory module 220 or the buffer memory through the bus interface.

[0055] These two distribution tables provide crucial information about the internal physical characteristics of consecutive superpage groups, forming the basis for address calculations performed by the hardware circuitry. Specifically, the page type distribution table indicates the specific page type (e.g., SLC, MLC, or TLC) of each superpage group within the consecutive superpage groups, determining the number of physical pages in each superpage group and the number of mapping units (i.e., the number of mapped addresses). The parity page distribution table indicates which one or more specific superpage groups contain parity pages, allowing the circuitry to identify the physical space that needs to be skipped (physical pages that are parity pages are skipped). By combining the information from these two distribution tables, the mapping table parsing circuitry 215 can accurately reconstruct the nonlinear physical address mapping relationship in subsequent iterative calculations.

[0056] Next, in step S220, the mapping table parsing circuit 215 sequentially obtains the target superpage groups to be parsed, starting from the initial physical address, and performs a mapping expansion operation for each target superpage group. This means that the mapping table parsing circuit 215 will automatically perform iterative calculations through hardware logic, on a superpage group basis, until the detailed mapping relationship of multiple physical pages in all superpage groups of the consecutive superpage groups is parsed.

[0057] In the mapping unpacking operation for each target superpage group, step S221 is first executed to obtain the superpage group logical address and superpage group physical address of the current target superpage group. For the first target superpage group, its address is the starting logical address and starting physical address received in step S210; for subsequent target superpage groups, their addresses are determined based on the calculation results of the previous superpage group. It should be noted that the first resolved initial superpage group has the same superpage group logical address and superpage group physical address as the starting logical address and starting physical address of the consecutive superpage groups, and does not require calculation.

[0058] Subsequently, in step S222, the mapping table parsing circuit 215 determines the actual number of physical pages and the specific number of mapping units contained in the target superpage group based on the page type of the target superpage group and whether it includes a check page.

[0059] After determining the number of valid mapping units, step S223 is executed. Based on this number of mapping units, the mapping table parsing circuit 215 allocates multiple target logical addresses starting from the current superpage group logical address, and allocates multiple target physical addresses starting from the superpage group physical address. Specifically, the circuit calculates the logical and physical locations corresponding to each mapping unit within the superpage group one by one, based on the size of the mapping unit (e.g., 4KB) and the calculated number of mapping units.

[0060] Next, in step S224, the mapping table parsing circuit 215 generates and outputs the mapping relationships between the multiple target logical addresses and the multiple target physical addresses. These generated mapping relationships are the expanded ordinary mapping table entries. To optimize transmission efficiency, the mapping table parsing circuit 215 can temporarily store these entries in an internal output buffer, and then write them in batches to the buffer memory 214 after the data volume reaches a certain threshold for subsequent use by the processor 211.

[0061] Finally, in step S225, the mapping table parsing circuit 215 determines the physical address of the next target superpage group to be parsed based on whether the target superpage group includes a parity page. This is a crucial step in achieving automatic physical address skipping. If the current target superpage group contains a parity page (usually located at the end of the superpage group), the mapping table parsing circuit 215 adds the product of the number of parity pages and the physical page size when calculating the starting physical address of the next superpage group. In this way, the hardware can automatically skip the physical space occupied by the parity page, ensuring that the physical address of the next superpage group points to the correct user data area without the need for complex address correction by software intervention. At the same time, the logical address of the next superpage group is immediately following the logical address corresponding to the mapping unit of the last physical page of the current superpage group, maintaining logical continuity.

[0062] Figure 3 This is a schematic diagram of the architecture of a mapping table parsing circuit according to an embodiment of the present disclosure.

[0063] Reference Figure 3 , Figure 3 A schematic diagram of the internal architecture of a mapping table parsing circuit 215 according to an embodiment of the present disclosure is shown. The mapping table parsing circuit 215 is electrically connected to a processor 211, a memory module 220, and a buffer memory 214 to perform the mapping unpacking operation provided in this disclosure.

[0064] In this embodiment, the mapping table parsing circuit 215 includes a microcontroller 2151, a register group 2152, a parsing engine 2153, a bus interface 2154, an input buffer 2155, and an output buffer 2156. The parsing engine 2153 includes a page type parsing unit 2153a, a page verification unit 2153b, an address calculation unit 2153c, a mapping generation unit 2153d, and a state machine 2153e.

[0065] Regarding the connections between the components, the microcontroller 2151 is electrically connected to the register set 2152 and the parsing engine 2153 to coordinate the operation of the components within the mapping table parsing circuit 215. The register set 2152 is electrically connected to the parsing engine 2153 to store the parameters and intermediate calculation results required for the mapping unpacking operation. The page type parsing unit 2153a, page check unit 2153b, address calculation unit 2153c, mapping generation unit 2153d, and state machine 2153e in the parsing engine 2153 are connected in sequence to form the processing pipeline for the mapping unpacking operation. The input buffer 2155 and the output buffer 2156 are both electrically connected to the parsing engine 2153 and the bus interface 2154. The bus interface 2154 is electrically connected to the memory module 220 and the buffer memory 214 to transfer data between the mapping table parsing circuit 215 and external components.

[0066] In terms of the functions of each component, the microcontroller 2151 receives instructions from the processor 211 and initializes the relevant parameters for the mapping unpacking operation based on the continuous mapping table passed in by the processor 211. When the processor 211 instructs the mapping table parsing circuit 215 to perform the mapping unpacking operation, it writes the trigger instruction and the starting logical address and starting physical address from the continuous mapping table into the register group 2152. Based on the trigger instruction, the microcontroller 2151 starts the parsing engine 2153 and provides the starting logical address and starting physical address. The register group 2152 can be used to store various parameters during the mapping unpacking operation, including the superpage group logical address, superpage group physical address, number of physical pages, and number of generated mapping entries.

[0067] The parsing engine 2153 is used to perform the core computational logic for mapping unrolling operations.

[0068] Figure 4 This is a schematic diagram showing the expansion of a continuous mapping table into a regular mapping table according to an embodiment of this disclosure.

[0069] Please refer to Figure 4 In one embodiment, the mapping unpacking operation A41 performed by the mapping table parsing circuit 215 is intended to convert a highly compressed contiguous mapping table SMT into a detailed unpacked mapping table L2P.

[0070] Specifically, the continuous mapping table SMT only records the starting logical address (e.g., LA0), starting physical address (e.g., PA0), and data size (e.g., 1024 4KB data units) corresponding to a continuous superpage group. While this recording method saves storage space, it cannot be directly used for accessing non-contiguous data. Therefore, the mapping table parsing circuit 215 parses sequentially starting from the starting physical address PA0 through the aforementioned iterative calculations. During the expansion process, for regular data areas that do not contain check pages or are located before check pages, the mapping table parsing circuit 215 generates the expanded general mapping table L2P based on the determined number and size of physical pages, as shown by arrow A41. This L2P contains detailed linearly corresponding mapping relationships, such as LA0 corresponding to PA0, LA1 corresponding to PA1, and so on, up to LA7 corresponding to PA7, as shown in the figure.

[0071] It is worth noting that, Figure 4 The expanded L2P mapping table on the right clearly demonstrates the special mechanism for handling parity pages in this disclosure. When the mapping table parsing circuit 215 reaches the end of a superpage group (e.g., the position corresponding to physical address PA7), if the parity page distribution table determines that the superpage group contains a parity page, the mapping table parsing circuit 215 will automatically perform a skip operation. For example... Figure 4 As shown, although the target logical address increases continuously from LA7 to LA8, the corresponding target physical address jumps from PA7 to PA12. This indicates that PA8 to PA11 in the physical address space are identified as parity pages (a total of 4 mapping units), which are located at the end of the superpage group and do not store user data. Therefore, when determining the superpage group physical address of the next target superpage group to be resolved, the mapping table parsing circuit 215 adds the physical page data span and the parity page span to PA7 (or the base address of this segment), thus directly pointing to the next valid data storage location PA12. Through this hardware-automated address jump, the generated expanded mapping table L2P can accurately reflect the address discontinuity caused by parity pages in the physical storage medium, ensuring that subsequent data access operations are error-free.

[0072] In one embodiment, the page type parsing unit 2153a is used to obtain the page type of the target superpage group according to the page type distribution table, and determine the basic number of physical pages and the physical page size of the target superpage group based on the page type.

[0073] Figure 6 This is a schematic diagram of the encoding rules for a page type distribution table according to an embodiment of this disclosure.

[0074] Reference Figure 6 In this embodiment, the page type distribution table is a bitmap structure used to indicate the page type of each superpage group in a continuous superpage group.

[0075] To accurately identify the physical resources actually used for storing user data in each target superpage group, the mapping table parsing circuit 215 executes a parsing process based on the distribution table. Specifically, the parsing engine 2153 first accesses the page type distribution table and, by detecting bit value flips, obtains the number of one or more target bits with the same value corresponding to the current target superpage group. This number of bits directly reflects the physical properties of the storage medium (e.g., three consecutive bits correspond to a TLC architecture). Based on this number of bits and the preset superpage group basic configuration, the parsing engine 2153 can determine the theoretical basic number of physical pages and the physical page size of the target superpage group.

[0076] Subsequently, the parsing engine 2153 further refines the calculation by incorporating information from the check page distribution table. If the target superpage group is determined to include check pages, this means that a portion of the physical space (usually the tail) of each superpage (i.e., each physical page group) is used to store checksums instead of user data. Therefore, the parsing engine 2153 performs a subtraction operation, subtracting the predetermined number of check pages from the previously calculated base number of physical pages, and using the result as the final number of physical pages. Through this step, the circuit can accurately identify the multiple physical pages actually corresponding to the target superpage group, ensuring that the subsequently generated mapping only covers the valid user data area.

[0077] In this embodiment, adjacent superpage groups use the first bit and the second bit to represent their corresponding page types, respectively. In other words, if the current superpage group uses the first bit (e.g., bit value 0) to represent its page type, then the next superpage group needs to use the second bit (e.g., bit value 1) to represent its page type, and so on, alternating between the two.

[0078] By alternating the use of the first and second bits as described above, the page type resolution unit 2153a can identify the boundary between adjacent superpage groups by detecting changes in bit values, thereby correctly resolving the page type of each superpage group.

[0079] Reference Figure 6 Table T61 in the table shows the page types and their corresponding bitmap bits for superpage groups 0 to 8. Superpage group 0 has a single-level unit page as its page type, and its bitmap bits are a single first bit (0). Superpage group 1 also has a single-level unit page as its page type. Since superpage group 1 is adjacent to superpage group 0, superpage group 1 uses a second bit (1) to represent its page type. Therefore, the bitmap bits of superpage group 1 are a single second bit (1).

[0080] Superpage group 2 is a multi-level unit page. Since it is adjacent to superpage group 1, superpage group 2 uses the first bit to represent its page type, and a multi-level unit page corresponds to two consecutive bits. Therefore, the bitmap of superpage group 2 consists of two consecutive first bits (0, 0). Superpage group 3 is also a multi-level unit page. Superpage group 3 uses the second bit to represent its page type, so the bitmap of superpage group 3 consists of two consecutive second bits (1, 1). Similarly, superpage groups 4 and 5 are also multi-level unit pages, and their bitmaps are (0, 0) and (1, 1), respectively.

[0081] Superpage group 6 has a three-level-unit page type. Since a three-level-unit page corresponds to three consecutive bits, and superpage group 6 uses the first bit to represent its page type, its bitmap consists of three consecutive first bits (0, 0, 0). Superpage group 7 also has a three-level-unit page type, and it uses the second bit to represent its page type; therefore, its bitmap consists of three consecutive second bits (1, 1, 1). Superpage group 8 also has a three-level-unit page type, and it uses the first bit to represent its page type; therefore, its bitmap consists of three consecutive first bits (0, 0, 0).

[0082] Reference Figure 6 The complete bitmap sequence on the right, arranged sequentially by the bitmap bits of each superpage group in Table T61, yields the complete bitmap sequence for the page type distribution table. The first row of the bitmap sequence includes the bitmap bits of superpage groups SPG0 to SPG5, in the order 0, 1, 0, 0, 1, 1, 0, 0, 1, 1. Among them, superpage group SPG0 corresponds to 1 bit (0), superpage group SPG1 corresponds to 1 bit (1), superpage group SPG2 corresponds to 2 bits (0, 0), superpage group SPG3 corresponds to 2 bits (1, 1), superpage group SPG4 corresponds to 2 bits (0, 0), and superpage group SPG5 corresponds to 2 bits (1, 1). The second row of bitmap sequences includes the bitmap bits of superpage groups SPG6 to SPG8, in the order of 0, 0, 0, 1, 1, 1, 0, 0, 0. Among them, superpage group SPG6 corresponds to 3 bits (0, 0, 0), superpage group SPG7 corresponds to 3 bits (1, 1, 1), and superpage group SPG8 corresponds to 3 bits (0, 0, 0).

[0083] In this embodiment, the page type parsing unit 2153a parses the page type distribution table as follows: The page type parsing unit 2153a reads the current bit from the bitmap sequence of the page type distribution table and continues to read subsequent bits until a change in bit value is detected. The page type parsing unit 2153a counts the number of consecutive and identical bits and uses this number as the N value corresponding to the page type of the current superpage group. N consecutive identical bits indicate that the corresponding page type is an N-level unit page, where N=1 represents a single-level unit page, N=2 represents a multi-level unit page, N=3 represents a three-level unit page, and N=4 represents a four-level unit page.

[0084] For example, after the page type resolution unit 2153a reads the first bit (0) in the bitmap sequence, it reads the second bit (1). Since the second bit is different from the first bit, the page type resolution unit 2153a determines that the number of consecutive identical bits in the first superpage group (superpage group SPG0) is 1. Therefore, the page type of superpage group SPG0 is a single-level unit page. The page type resolution unit 2153a continues to read the third bit (0). Since the third bit is different from the second bit, the page type resolution unit 2153a determines that the number of consecutive identical bits in the second superpage group (superpage group SPG1) is 1. Therefore, the page type of superpage group SPG1 is also a single-level unit page. Page type resolution unit 2153a continues to read the fourth bit (0). Since the fourth bit is the same as the third bit, page type resolution unit 2153a continues to read the fifth bit (1). Since the fifth bit is different from the fourth bit, page type resolution unit 2153a determines that the number of consecutive identical bits in the third superpage group (superpage group SPG2) is 2. Therefore, the page type of superpage group SPG2 is multi-level unit page.

[0085] The above encoding method has the following technical features. Since the number of consecutive identical bits exactly corresponds to the number of page types (i.e., N levels of unit pages correspond to N physical pages), the page type parsing unit 2153a can determine the basic number of corresponding physical pages simultaneously with determining the page type, without requiring additional table lookup operations. For example, the number of bits corresponding to each superpage group is the number of physical page groups for that superpage group, such as... Figure 5 The SPG3 has two physical page groups (superpages) corresponding to "String2", each with 8 physical pages, for a total of 16 (2 x 8 = 16). This number of 16 is the basic number of physical pages.

[0086] Furthermore, by alternating the use of the first and second bits in adjacent superpage groups, the page type distribution table can be stored using a compact bitmap structure. Compared to using a fixed number of bits (such as 2 or 3 bits) to encode the page type for each superpage group, the above encoding method can reduce the storage space occupied by the page type distribution table.

[0087] In the operation of the parsing engine 2153, determining the actual number of physical pages available for storing user data within the target superpage group is a crucial step involving multiple judgments. First, the page type parsing unit 2153a parses out the number of consecutive identical bits representing the current target superpage group (e.g., three consecutive bits represent TLC) based on the page type distribution table. Based on this number of bits and the preset superpage group basic configuration, the parsing engine 2153 can calculate the theoretically achievable number of physical pages and the number of mapping units that the target superpage group can accommodate.

[0088] Next, the check page determination unit 2153b intervenes, determining whether the target superpage group includes check pages based on the check page distribution table. If the check page distribution table indicates that the current target superpage group does not contain check pages, then the aforementioned basic number of physical pages is the final number of physical pages. However, if it indicates that check pages are included, this means that the tail space of each superpage in the superpage group is used to store redundant check codes instead of user data. In this case, the check page determination unit 2153b performs deduction logic, subtracting the predetermined number of check pages from the basic number of physical pages to obtain the corrected number of physical pages. Through this dual confirmation mechanism based on page type and check attribute, the mapping table parsing circuit 215 can accurately define the multiple physical pages corresponding to each superpage group, ensuring that the subsequently generated mapping relationship only points to the valid user data area, while automatically avoiding the check area.

[0089] Figure 7 This is a schematic diagram of the verification page distribution table and the internal structure of the superpage group shown in an embodiment of this disclosure.

[0090] Reference Figure 7 , Figure 7 A check page distribution table and a schematic diagram of the internal structure of a superpage group according to an embodiment of this disclosure are shown. In this embodiment, the check page distribution table is a bitmap structure used to indicate whether one or more specific superpage groups in a series of consecutive superpage groups include check pages.

[0091] Reference Figure 7 Table T71 on the left shows the check page distribution table for superpage groups 0 to 5. Figure 5 For example, the bitmap structure of the parity page distribution table is based on the order of multiple superpage groups, recording multiple bits sequentially. Each bit indicates whether the corresponding superpage group includes a parity page. Specifically, a bit value of 0 indicates that the corresponding superpage group does not include a parity page; a bit value of 1 indicates that the corresponding superpage group includes a parity page.

[0092] Reference Figure 7The internal structure of the superpage group in the upper right corner is 710. Figure 7 The internal structure of a superpage group including a check page is illustrated using superpage group 6 as an example. In this embodiment, the check page is located at the end of the corresponding superpage group. Specifically, superpage group 4 (MLC) includes two physical page groups, each with multiple physical pages, namely physical page 0, physical page 1, and physical page 2. Physical page N-2 and check page, wherein the check page is located at the last physical page position of each physical page group in superpage group 4.

[0093] In the embodiment shown in Table T71, the bit values ​​of superpage groups 0 to 3 are all 0, indicating that superpage groups 0, 1, 2, and 3 do not include a parity page. The bit values ​​of superpage groups 4 to 5 are all 1 (indicated in gray), indicating that superpage groups 4 and 5 both include a parity page.

[0094] Reference Figure 7 The bitmap sequence 720 on the right arranges the bit values ​​of each superpage group in table T71 sequentially, resulting in a complete parity page distribution table bitmap sequence. This bitmap sequence is in the order of "0, 0, 0, 1, 1", corresponding to superpage groups SPG0 to superpage SPG5, respectively. When performing the mapping expansion operation, the parity page determination unit 2153b reads the corresponding bit value from the bitmap sequence of the parity page distribution table according to the index of the current target superpage group, thus determining whether the current target superpage group includes a parity page.

[0095] Address calculation unit 2153c is used to calculate the target logical address and target physical address allocated to each mapping unit based on the superpage group logical address, superpage group physical address, number of physical pages and number of mapping units.

[0096] In one embodiment, when the address calculation unit 2153c calculates the superpage group physical address of the next target superpage group to be resolved, the address calculation unit 2153c needs to consider whether the current target superpage group includes a parity page. If the current target superpage group includes a parity page, the superpage group physical address of the next target superpage group needs to be based on the physical address of the mapping unit of the last physical page of the current target superpage group, with the physical address space occupied by the parity page skipped.

[0097] like Figure 7As shown in the diagram below, the verification pages for superpage group 4 correspond to physical page numbers P43 and P47, and the verification pages for superpage group 5 correspond to physical page numbers P63, P67, and P71. Since the verification pages are located at the end of each physical page group within the superpage group in this embodiment, the verification page determination unit 2153b, after determining that the target superpage includes a verification page, can directly identify the last physical page of each physical page group within that superpage group as the verification page, without requiring additional location lookup operations.

[0098] However, this disclosure is not limited thereto. In other embodiments, the position of the parity page in the superpage group can be any pre-set position, or dynamically determined according to a specific parity algorithm (e.g., the rotating parity distribution of RAID 5). In these variant embodiments, the address calculation unit 2153c is configured to acquire or calculate the specific location information of the parity page, and perform a skip operation for that specific location during address allocation to ensure that the generated mapping correctly avoids the physical space occupied by the parity page.

[0099] In this embodiment, the check page determination unit 2153b determines whether the target superpage group includes a check page based on the check page distribution table, and then transmits the determination result to the address calculation unit 2153c. When the target superpage group does not include a check page, the address calculation unit 2153c directly uses the basic number of physical pages as the number of physical pages for subsequent address allocation calculations. When the target superpage group includes a check page, the address calculation unit 2153c uses the result of subtracting the number of check pages from the basic number of physical pages as the number of physical pages.

[0100] For example, assuming that the page type of superpage group 4 is a 2-level unit page, the corresponding basic number of physical pages is 16 physical pages (i.e., 8 planes multiplied by 2 levels), and superpage group 4 includes 2 parity pages (each level has one parity page), then the address calculation unit 2153c determines the number of physical pages to be 14 physical pages (i.e., 16 minus 2). The address calculation unit 2153c only allocates target logical addresses and target physical addresses to these 14 data pages, skipping the physical addresses corresponding to the parity pages (i.e., P43, P47).

[0101] The mapping generation unit 2153d generates a mapping relationship between target logical addresses and target physical addresses based on multiple target logical addresses and multiple target physical addresses calculated by the address calculation unit 2153c. The state machine 2153e controls the operating state of the parsing engine 2153, coordinates the execution order of the page type parsing unit 2153a, the page verification unit 2153b, the address calculation unit 2153c, and the mapping generation unit 2153d, and determines whether there are still unprocessed target superpage groups to decide whether to continue iterative processing.

[0102] Input buffer 2155 is used to temporarily store the page type distribution table and check page distribution table data read from buffer memory 214. Output buffer 2156 is used to temporarily store the mapping relationship generated by mapping generation unit 2153d. Bus interface 2154 is used to transfer data between mapping table parsing circuit 215, buffer memory 214, and memory module 220 via AXI (Advanced eXtensible Interface) bus or other suitable bus protocol.

[0103] Regarding the interaction between the components, when the processor 211 instructs the mapping table parsing circuit 215 to perform a mapping unpacking operation, the microcontroller 2151 first initiates the data acquisition process. Given that the page type distribution table and the parity page distribution table may contain large amounts of data, the mapping table parsing circuit 215 employs a block-based reading and caching mechanism to optimize internal storage resources and improve bus utilization. Specifically, the microcontroller 2151 uses the bus interface 2154 to read the page type distribution table and the parity page distribution table in batches into the input cache 2155, which serves as an internal cache.

[0104] For example, the input buffer 2155 can be configured to have a capacity of 32 bytes, and the bus interface 2154 reads 16 bytes of data into the input buffer 2155 at a time. When the 16 bytes of data used in the input buffer 2155 are consumed by the parsing engine 2153, the bus interface 2154 will immediately read the next 16 bytes of data to fill the gap. This pipelined data reading method ensures that the parsing engine 2153 can continuously obtain the required data, thereby significantly reducing the waiting time.

[0105] After the data is ready, the microcontroller 2151 writes the starting logical address and starting physical address from the continuous mapping table into register group 2152. The state machine 2153e then sets the state of the parsing engine 2153 to the start state and triggers each functional unit sequentially. The page type parsing unit 2153a reads data from the page type distribution table from the input buffer 2155, obtains the page type of the current target superpage group, and writes the page type and the corresponding basic number of physical pages into register group 2152. The page verification unit 2153b reads data from the page verification distribution table from the input buffer 2155, determines whether the current target superpage group includes a verification page, and determines the number of physical pages accordingly. The address calculation unit 2153c reads the superpage group logical address, superpage group physical address, number of physical pages, and number of mapping units from register group 2152, and calculates multiple target logical addresses and multiple target physical addresses.

[0106] Subsequently, the mapping generation unit 2153d generates mapping relationships between multiple target logical addresses and multiple target physical addresses based on the calculation results of the address calculation unit 2153c, and temporarily stores the generated mapping relationships in the output buffer 2156. During this process, the state machine 2153e continuously monitors the amount of data in the output buffer 2156. When the amount of data in the temporarily stored mapping relationships in the output buffer 2156 reaches a preset threshold, the state machine 2153e triggers the bus interface 2154 to perform a batch output operation, writing the mapping relationships in the output buffer 2156 to the buffer memory 214 of the storage device all at once. Through the above batch output method, the mapping table parsing circuit 215 does not need to wait for all mapping relationships to be generated before outputting them all at once, thereby significantly reducing the capacity requirement of the output buffer 2156 and reducing the instantaneous bandwidth pressure on the system bus.

[0107] After the mapping unpacking operation of the current target superpage group is completed, state machine 2153e determines whether there are any unprocessed target superpage groups. If a preset number (e.g., 1024) of mapping entries have not yet been generated, state machine 2153e calculates the superpage group logical address and superpage group physical address of the next target superpage group to be resolved, based on whether the current target superpage group includes a check page, and updates the calculation results to register group 2152. Subsequently, it triggers the parsing engine 2153 to perform the mapping unpacking operation on the next target superpage group. When all target superpage groups have been processed or the preset number of mapping entries have been generated, state machine 2153e sets the state of parsing engine 2153 to the completed state and sends a completion signal to microcontroller 2151. Microcontroller 2151 then reports to processor 211 that the mapping unpacking operation has been completed.

[0108] also, Figure 3 The internal module division of the mapping table parsing circuit 215 shown is only a schematic diagram of a logical function, intended to clearly illustrate the cooperative relationship of each part in the mapping expansion operation, and this disclosure is not limited thereto. In actual hardware circuit design (such as ASIC or FPGA implementation), the above modules can be integrated, split, or reorganized according to design requirements. For example, the function of microcontroller 2151 can be integrated into the state machine 2153e of parsing engine 2153, or replaced by a simpler logic circuit; input buffer 2155 and output buffer 2156 ( Figure 3The input cache marked 2156 (which should be understood as the output cache) can be merged into a single shared memory resource, and data reading and writing can be managed through address partitioning; the page type resolution unit 2153a, the page check unit 2153b, and the address calculation unit 2153c can also be integrated into a unified arithmetic logic unit (ALU). As long as the hardware circuit can operate independently of the processor 211 and perform the expansion of the continuous mapping table and the skipping of the check page according to the method of this disclosure, it is within the protection scope of this disclosure.

[0109] Figure 8 This is a detailed flowchart illustrating the mapping expansion operation according to an embodiment of the present disclosure.

[0110] Reference Figure 8 In this embodiment, the mapping unpacking operation is performed by the mapping table parsing circuit 215 to unpack the continuous mapping table into a normal mapping table containing complete mapping relationships.

[0111] In step S810, the mapping table parsing circuit 215 receives the continuous mapping table, obtains the starting logical address and the starting physical address, and obtains the page type distribution table and the check page distribution table.

[0112] Specifically, when processor 211 instructs mapping table parsing circuit 215 to perform a mapping unpacking operation, processor 211 passes a contiguous mapping table to mapping table parsing circuit 215. The contiguous mapping table records the mapping relationship between the starting logical address and the starting physical address of a corresponding contiguous superpage group, where the contiguous superpage group includes multiple superpage groups. Mapping table parsing circuit 215 obtains the corresponding page type distribution table and parity page distribution table based on the contiguous mapping table. The page type distribution table indicates the page type of each superpage group in the contiguous superpage group, and the parity page distribution table indicates whether one or more specific superpage groups among the multiple superpage groups include a parity page. Mapping table parsing circuit 215 reads the page type distribution table and parity page distribution table from buffer memory 214 through bus interface 2154 and temporarily stores the read data in input buffer 2155.

[0113] In step S820, the mapping table parsing circuit 215 acquires the unprocessed target superpage group and determines its superpage group logical address and superpage group physical address. At the start of the mapping unpacking operation, the mapping table parsing circuit 215 uses the starting logical address in the continuous mapping table as the superpage group logical address of the first target superpage group and the starting physical address as the superpage group physical address of the first target superpage group. For subsequent target superpage groups, the mapping table parsing circuit 215 determines the superpage group logical address and superpage group physical address based on the result calculated in step S890.

[0114] In step S830, the mapping table parsing circuit 215 determines the page type of the target superpage group according to the page type distribution table. Specifically, the page type parsing unit 2153a reads the bitmap data of the page type distribution table from the input cache 2155 and obtains the number of one or more target bits with the same value in the target superpage group. Since the page type distribution table uses the number of consecutive and identical bits to represent the corresponding page type, the page type parsing unit 2153a determines the page type of the target superpage group by counting the number of consecutive identical bits, where N consecutive identical bits indicate that the corresponding page type is an N-level unit page. Specifically, one consecutive identical bit represents a single-level unit page, two consecutive identical bits represent a multi-level unit page, three consecutive identical bits represent a three-level unit page, and four consecutive identical bits represent a four-level unit page.

[0115] In step S840, the mapping table parsing circuit 215 determines the basic number of physical pages and the number of mapping units based on the page type and the superpage group basic configuration. The superpage group basic configuration includes parameters such as the number of channels and planes spanned by the superpage group. The page type parsing unit 2153a calculates the basic number of physical pages for the target superpage group based on the number of layers corresponding to the page type (i.e., the number of consecutive identical bits) and the superpage group basic configuration. Specifically, the number of bits corresponding to each superpage group is the number of physical page groups for that superpage group, and the basic number of physical pages is equal to the number of physical page groups multiplied by the number of physical pages in each physical page group. For example, referring to... Figure 5 Assuming the basic configuration of the superpage group is 2 channels multiplied by 4 planes (a total of 8 planes), and the page type of the target superpage group SPG3 is a multi-level cell page (corresponding to 2 consecutive identical bits), then the superpage group SPG3 has 2 physical page groups, each containing 8 physical pages. Therefore, the basic number of physical pages is 8 physical pages. The number of mapping units is determined according to the specifications of the memory module 220. For example, if the size of each mapping unit is 4KB and each physical page is 16KB, then the number of mapping units for the superpage is 32.

[0116] In step S850, the mapping table parsing circuit 215 determines whether the target superpage group includes a check page based on the check page distribution table. Specifically, the check page determination unit 2153b reads the bitmap data of the check page distribution table from the input buffer 2155 and obtains the corresponding bit value according to the index of the target superpage group. When the bit value is 1, the check page determination unit 2153b determines that the target superpage group includes a check page; when the bit value is 0, the check page determination unit 2153b determines that the target superpage group does not include a check page.

[0117] If the target superpage group includes a checksum page, the process proceeds to step S851. In step S851, the mapping table parsing circuit 215 subtracts the checksum page count from the base physical page count as the physical page count. In this embodiment, the checksum page is located at the end of each physical page group of the corresponding superpage group, therefore the checksum page count is equal to the physical page group count. For example, referring to... Figure 5 and Figure 7 Assuming the page type of superpage group SPG4 is multi-level unit page, with 2 physical page groups and a basic number of 16 physical pages, and that superpage group SPG4 includes 2 check pages (corresponding to physical page numbers P43 and P47 respectively, located at the end of each physical page group), then the number of physical pages is 16 minus 2 equals 14 physical pages. Through this method, the mapping table parsing circuit 215 can ensure that only the data page containing the user data is allocated the target logical address and the target physical address, while skipping the physical address corresponding to the check page.

[0118] If the target superpage group does not include a checksum page, the process proceeds to step S852. In step S852, the mapping table parsing circuit 215 directly uses the basic number of physical pages as the number of physical pages. Since all physical pages in the target superpage group are used to store user data, there is no need to deduct the number of checksum pages. For example, refer to... Figure 5 and Figure 7 The parity page distribution table bit values ​​for superpage groups SPG0 to SPG3 are all 0, indicating that these superpage groups do not include parity pages, so their physical page count is equal to the basic physical page count.

[0119] In step S860, the mapping table parsing circuit 215 allocates multiple target logical addresses and target physical addresses based on the number of physical pages and the number of mapping units. Specifically, the address calculation unit 2153c calculates the target logical address allocated to each mapping unit based on the superpage group logical address, the number of physical pages, and the number of mapping units. The address calculation unit 2153c also calculates the target physical address allocated to each mapping unit based on the superpage group physical address, the number of physical pages, and the number of mapping units. During the calculation process, the address calculation unit 2153c needs to skip the physical address corresponding to the check page. For example, referring to... Figure 4 Assuming the logical address of a superpage group is LA0 and the physical address is PA0, when processing reaches the end of a superpage group, if that superpage group contains a parity page, although the target logical address increments continuously from LA7 to LA8, the corresponding target physical address jumps from PA7 to PA12. This indicates that PA8 to PA11 in the physical address space are identified as parity pages and skipped. The physical address PA12 will be mapped to the logical address LA8. In other words, logical addresses are generally ordered consecutively, while physical addresses may jump due to the presence of parity pages.

[0120] In step S870, the mapping table parsing circuit 215 generates and outputs the mapping relationship between the target logical address and the target physical address. Specifically, the mapping generation unit 2153d generates multiple mapping entries based on the multiple target logical addresses and multiple target physical addresses calculated by the address calculation unit 2153c. Each mapping entry records the mapping relationship between a target logical address and its corresponding target physical address. The mapping generation unit 2153d writes the generated mapping relationship into the output buffer 2156. The state machine 2153e monitors the amount of data in the output buffer 2156. When the amount of mapping relationship data temporarily stored in the output buffer 2156 reaches a preset threshold, the state machine 2153e triggers the bus interface 2154 to output the mapping relationships in the output buffer 2156 in batches to the buffer memory 214. Through the above batch output method, the mapping table parsing circuit 215 does not need to wait for all mapping relationships to be generated before outputting them all at once, thereby reducing the capacity requirement of the output buffer 2156.

[0121] In step S880, the mapping table parsing circuit 215 determines whether there are any unprocessed superpage groups. Specifically, state machine 2153e determines whether the mapping unpacking operation is complete based on the number of generated mapping items. If the number of generated mapping items reaches a preset number (e.g., 1024 mapping items), or all superpage groups in a consecutive superpage group have been processed, the process ends, and the mapping table parsing circuit 215 reports to the processor 211 that the mapping unpacking operation is complete. If the preset number of mapping items has not been generated and there are still unprocessed superpage groups, the process proceeds to step S890.

[0122] In step S890, the mapping table parsing circuit 215 calculates the superpage group logical address and superpage group physical address of the next target superpage group. Specifically, the address calculation unit 2153c obtains the last target logical address and last target physical address of the mapping unit corresponding to the last physical page of the current target superpage group. The superpage group logical address of the next target superpage group to be parsed is the next logical address after the last target logical address. For the calculation of the superpage group physical address, the address calculation unit 2153c needs to consider whether the current target superpage group includes a parity page. If the current target superpage group does not include a parity page, then the superpage group physical address of the next target superpage group is the next physical address after the last target physical address. If the current target superpage group includes a parity page, then the superpage group physical address of the next target superpage group needs to be based on the last target physical address, skipping the physical address space occupied by the parity page. For example, refer to... Figure 5Assuming the physical address of the last data page of superpage group SPG4 is 46, and superpage group SPG4 includes a check page (corresponding to P47), then the starting physical address of the next target superpage group (i.e., superpage group SPG5) is 48, not 47.

[0123] After completing step S890, the process returns to step S820, where the mapping table parsing circuit 215 continues to obtain the next target superpage group and perform the mapping expansion operation until a preset number of mapping items are generated or all superpage groups in a series of superpage groups are processed.

[0124] Through the above process, the mapping table parsing circuit 215 can expand a continuous mapping table into a normal mapping table containing complete mapping relationships in one go. Compared with traditional software processing methods or multiple iterative interactions between hardware and software, the mapping expansion operation provided in this disclosure is completed autonomously by the mapping table parsing circuit 215. The processor 211 only needs to pass in the continuous mapping table and related parameters at the beginning of the mapping expansion operation, without frequent intervention during the expansion process, thereby reducing the number of iterative interactions between software and hardware and reducing firmware overhead.

[0125] It is worth mentioning that, in one embodiment, the state machine 2153e is also configured with exception handling logic to handle possible exceptions during the mapping unfolding process. Specifically, when controlling the parsing engine 2153 to perform pipeline operations, the state machine 2153e continuously monitors the data availability of the input buffer 2155 and the operation status of each functional unit.

[0126] For example, if the page type resolution unit 2153a finds during the resolution process that the page type distribution table data in the input cache 2155 is insufficient to complete the resolution of the current target superpage group (e.g., bitmap data is unexpectedly interrupted before the superpage group boundary), and the bus interface 2154 fails to successfully read subsequent data from the buffer memory 214 within a preset timeout period (e.g., read timeout due to bus congestion or address configuration error), the state machine 2153e will switch the resolution engine 2153 from the running state to the error paused state.

[0127] At this point, state machine 2153e records the specific error type (such as data acquisition timeout, bitmap encoding error, or output buffer overflow) in a specific status register of register group 2152 and sends an exception interrupt signal to microcontroller 2151. In response to this exception interrupt signal, microcontroller 2151 suspends the current mapping unrolling operation and reports the error status to processor 211. Processor 211 can then take appropriate recovery measures, such as reconfiguring the distribution table address or resetting the mapping table resolution circuit 215, thereby avoiding system stalls caused by hardware deadlock and improving the reliability of the memory controller.

[0128] This embodiment also provides a computer program product, including computer-readable code or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the memory management method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0129] Based on the above, the memory management method and memory controller provided in this disclosure automate the generation of mapping tables by receiving a continuous mapping table and performing a mapping unrolling operation for each target superpage group in a continuous superpage group. Specifically, after obtaining the superpage group logical address and superpage group physical address of the target superpage group, the method of this disclosure can accurately identify the actual number of usable physical pages and the number of mapping units within the superpage group based on the page type of the target superpage group and whether it includes a parity page. This mechanism enables the memory controller to adapt to storage environments with mixed page types (such as SLC, MLC, TLC), dynamically adjust the address allocation strategy according to different physical page capacities, and ensure that the generated mapping relationship matches the characteristics of the actual physical storage medium.

[0130] Furthermore, after generating and outputting the mapping relationship of the current target superpage group, the method of this disclosure further determines the physical address of the next target superpage group to be resolved based on whether the target superpage group includes a parity page. This step solves the problem of discontinuous physical addresses in RAID protection scenarios by automatically skipping the physical space occupied by the parity page during the calculation process. Compared with the traditional software method of comparing addresses one by one, this disclosure uses hardware logic to directly handle the jumping of physical addresses, avoiding cumbersome firmware intervention, thereby effectively improving the speed of mapping table expansion, reducing system latency when processing data rewriting, and freeing up processor computing resources to process other core tasks.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method applied to a memory controller, the memory controller being used to manage a storage device configured with memory modules, characterized in that, The method includes: Receive a contiguous mapping table, wherein the contiguous mapping table records the mapping relationship between the starting logical address and the starting physical address of a corresponding contiguous superpage group, wherein the contiguous superpage group includes multiple superpage groups; Starting from the initial physical address, the target superpage groups to be resolved are obtained sequentially. For each target superpage group, a mapping expansion operation is performed, including: Obtain the superpage group logical address and superpage group physical address of the target superpage group; The number of mapping units for the target superpage group is determined based on the page type of the target superpage group and whether it includes a validation page; Based on the number of mapping units, multiple target logical addresses are allocated from the superpage group logical address, and multiple target physical addresses are allocated from the superpage group physical address; Generate and output the mapping relationship between the plurality of target logical addresses and the plurality of target physical addresses; Based on whether the target superpage group includes the check page, determine the physical address of the next target superpage group to be resolved.

2. The method according to claim 1, characterized in that, The method further includes: The corresponding page type distribution table and check page distribution table are obtained according to the continuous mapping table, wherein the page type distribution table is used to indicate the page type of each superpage group in the continuous superpage group, and the check page distribution table is used to indicate whether one or more specific superpage groups in the plurality of superpage groups include the check page.

3. The method according to claim 2, characterized in that, The page type distribution table is a bitmap structure, and the bitmap structure records multiple first bits and second bits sequentially based on the order of the multiple superpage groups. The number of consecutive and identical bits is used to represent the page type of the corresponding superpage group. The consecutive N identical bits indicate that the corresponding page type is an N-level unit page, and adjacent superpage groups use the first bit and the second bit to represent the corresponding page type, respectively.

4. The method according to claim 3, characterized in that, The check page distribution table is a bitmap structure, and the bitmap structure records multiple bits sequentially based on the order of the multiple superpage groups, wherein each bit is used to indicate whether the corresponding superpage group includes the check page.

5. The method according to claim 4, characterized in that, The step of determining the number of mapping units in the target superpage group based on the page type of the target superpage group and whether the verification page is included includes: Based on the page type distribution table, obtain the number of bits of one or more target bits with the same value in the target superpage group; Based on the number of bits and the basic configuration of the superpage group, determine the basic number of physical pages and the physical page size of the target superpage group; Based on whether the target superpage group includes the check page, the physical page size, and the basic number of physical pages, the number of physical pages in the target superpage group and the corresponding number of mapping units are determined. If the target superpage group includes the check page, the result of subtracting the number of check pages from the basic number of physical pages is taken as the number of physical pages.

6. The method according to claim 5, characterized in that, The steps of allocating the plurality of target logical addresses from the superpage group logical address and allocating the plurality of target physical addresses from the superpage group physical address based on the number of mapping units include: Based on the superpage group logical address and the number of mapping units, calculate the target logical address allocated to each mapping unit; Based on the physical address of the superpage group and the number of mapping units, the target physical address allocated to each mapping unit is calculated.

7. The method according to claim 6, characterized in that, The verification page is located at the end of the corresponding superpage group.

8. The method according to claim 7, characterized in that, The step of determining the physical address of the next target superpage group to be resolved based on whether the target superpage group includes the check page includes: Obtain the last target physical address of the mapping unit of the last physical page corresponding to the target superpage group; Based on the final target physical address and the number of check pages, calculate the physical address of the next target superpage group to be resolved. The superpage group logical address of the next target superpage group to be resolved is the next logical address of the last target logical address of the mapping unit corresponding to the last physical page.

9. The method according to claim 1, characterized in that, The mapping unrolling operation is performed by the mapping table parsing circuit.

10. The method according to claim 9, characterized in that, The mapping table parsing circuit is configured with an internal buffer and an output buffer, and the mapping unpacking operation further includes: The page type distribution table and the check page distribution table are read into the internal cache in blocks via the bus interface; The generated mapping relationship is temporarily stored in the output buffer; Monitor the amount of data in the output buffer, and when the amount of data reaches a preset threshold, output the mapping relationship in batches to the buffer memory of the storage device.

11. The method according to claim 1, characterized in that, The method further includes: Receive a write instruction, wherein the write instruction contains a write logical address; Determine whether the written logical address falls within the address range covered by the starting logical address recorded in the continuous mapping table; If the written logical address falls within the address range, the step of receiving the continuous mapping table and performing the mapping expansion operation is triggered to convert the continuous mapping table into a normal mapping table containing the mapping relationship.

12. A memory controller for controlling a storage device configured with a memory module, characterized in that, The memory controller includes: Buffer memory; A memory interface control circuit is electrically connected to the memory module; Data management circuitry, used for electrical connection to the host system; Mapping table parsing circuit; and The processor is electrically connected to the memory interface control circuit, the buffer memory, the data management circuit, and the mapping table parsing circuit. The processor is configured to instruct the map table parsing circuit to perform a mapping unpacking operation on the corresponding consecutive map tables; The mapping table parsing circuit is configured to: Receive the continuous mapping table, wherein the continuous mapping table records the mapping relationship between the starting logical address and the starting physical address of the corresponding continuous superpage group, wherein the continuous superpage group includes multiple superpage groups; Starting from the initial physical address, the target superpage groups to be resolved are obtained sequentially. For each target superpage group, the mapping expansion operation is performed, including: Obtain the superpage group logical address and superpage group physical address of the target superpage group; Based on the page type of the target superpage group and whether it includes a verification page, determine the number of physical pages and the number of mapping units of the target superpage group; Based on the number of mapping units, multiple target logical addresses are allocated from the superpage group logical address, and multiple target physical addresses are allocated from the superpage group physical address; Generate and output the mapping relationship between the plurality of target logical addresses and the plurality of target physical addresses; and Based on whether the target superpage group includes the check page, determine the physical address of the next target superpage group to be resolved.

13. The memory controller according to claim 12, characterized in that, The mapping table parsing circuit is also configured to: The corresponding page type distribution table and check page distribution table are obtained according to the continuous mapping table, wherein the page type distribution table is used to indicate the page type of each superpage group in the continuous superpage group, and the check page distribution table is used to indicate whether one or more specific superpage groups in the plurality of superpage groups include the check page.

14. The memory controller according to claim 13, characterized in that, The page type distribution table is a bitmap structure, and the bitmap structure records multiple first bits and second bits sequentially based on the order of the multiple superpage groups. The number of consecutive and identical bits is used to represent the page type of the corresponding superpage group. The consecutive N identical bits indicate that the corresponding page type is an N-level unit page, and adjacent superpage groups use the first bit and the second bit to represent the corresponding page type, respectively.

15. The memory controller according to claim 14, characterized in that, The check page distribution table is a bitmap structure, and the bitmap structure records multiple bits sequentially based on the order of the multiple superpage groups, wherein each bit is used to indicate whether the corresponding superpage group includes the check page.

16. The memory controller according to claim 15, characterized in that, When determining the number of mapping units for the target superpage group based on its page type and whether it includes the check page, the mapping table parsing circuit is configured to: Based on the page type distribution table, obtain the number of bits of one or more target bits with the same value in the target superpage group; Based on the number of bits and the basic configuration of the superpage group, determine the basic number of physical pages and the physical page size of the target superpage group; as well as Based on whether the target superpage group includes the check page, the physical page size, and the basic number of physical pages, the number of physical pages in the target superpage group and the corresponding number of mapping units are determined. If the target superpage group includes the check page, the result of subtracting the number of check pages from the basic number of physical pages is taken as the number of physical pages.

17. The memory controller according to claim 16, characterized in that, When allocating the plurality of target logical addresses from the superpage group logical address and the plurality of target physical addresses from the superpage group physical address based on the number of mapping units, the mapping table resolution circuit is configured to: Based on the superpage group logical address and the number of mapping units, calculate the target logical address allocated to each mapping unit; as well as Based on the physical address of the superpage group and the number of mapping units, the target physical address allocated to each mapping unit is calculated.

18. The memory controller according to claim 17, characterized in that, The verification page is located at the end of the corresponding superpage group.

19. The memory controller according to claim 18, characterized in that, When determining the physical address of the next target superpage group to be resolved based on whether the target superpage group includes the check page, the mapping table resolution circuit is configured to: Obtain the last target physical address of the mapping unit of the last physical page corresponding to the target superpage group; Based on the final target physical address and the number of check pages, calculate the physical address of the next target superpage group to be resolved. The superpage group logical address of the next target superpage group to be resolved is the next logical address of the last target logical address of the mapping unit corresponding to the last physical page.

20. The memory controller according to claim 12, characterized in that, The mapping table parsing circuit is configured with internal buffer and output buffer, and the mapping table parsing circuit is further configured to: The page type distribution table and the check page distribution table are read into the internal cache in blocks via the bus interface; The generated mapping relationship is temporarily stored in the output buffer; as well as Monitor the amount of data in the output buffer, and when the amount of data reaches a preset threshold, output the mapping relationship to the buffer memory in batches.

21. The memory controller according to claim 12, characterized in that, The processor is also configured to: Receive a write instruction, wherein the write instruction contains a write logical address; Determine whether the written logical address falls within the address range covered by the starting logical address recorded in the continuous mapping table; and If the written logical address falls within the address range, the step of instructing the mapping table parsing circuit to perform the mapping expansion operation of the corresponding continuous mapping table is triggered, so as to convert the continuous mapping table into a normal mapping table containing the mapping relationship.

Images