Access instruction sending method and device, storage medium, electronic equipment and computer program product

Abstract

The application discloses a sending method and device of an access instruction, a storage medium, an electronic device and a computer program product, and relates to the computer field, wherein the method comprises the following steps: in the case that a first notification message sent by a network card is received, reading control section data of a target message to a first-level cache and a second-level cache of a central processor, wherein the first notification message is used for indicating that the network card has received the control section data completely; determining an access instruction according to the control section data in the central processor, and sending the access instruction to a target hard disk, so as to instruct the target hard disk to read data section data of the target message saved in the network card to the target hard disk through a direct-connection communication channel between the network card and the target hard disk.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular to methods and apparatus for sending access instructions, storage media, electronic devices, and computer program products. Background Technology

[0002] In the information age, the explosive growth of data volume has placed higher demands on storage systems. Traditional storage systems, especially those based on centralized architectures, are often limited by high latency and low bandwidth, making them unsuitable for high-performance computing and big data processing. In recent years, hyperconverged storage systems have gradually gained widespread attention as an emerging storage solution. Hyperconverged storage integrates computing resources (such as central processing units (CPUs)) with storage resources (such as hard drives) within the same node, achieving a tighter combination of computing and storage, aiming to provide higher data processing performance and lower latency.

[0003] Currently, most hyperconverged storage system optimizations focus on the software level, improving system performance through algorithm improvements and data structure optimization. While these methods improve data processing efficiency to some extent, they often overlook the potential of the hardware level, especially the insufficient resource coordination between the CPU, network interface card (NIC), and hard drive. This results in the CPU's L1 and L2 caches not being effectively utilized, and the performance of the NIC and hard drive being limited.

[0004] Therefore, the problem of insufficient resource coordination among the central processing unit, network card, and hard drive in related technologies, which leads to the ineffective utilization of the central processing unit's L1 and L2 caches and the limited performance of the network card and hard drive, has not yet been effectively solved. Summary of the Invention

[0005] This application provides a method and apparatus for sending access instructions, a storage medium, an electronic device, and a computer program product, to at least solve the problem in related technologies where server display output schemes only support display output through onboard devices or through all non-onboard devices, and cannot specify a particular device for display output.

[0006] This application provides a method for sending an access instruction, comprising: upon receiving a first notification message sent by a network interface card (NIC), reading the control segment data of a target packet into the L1 and L2 caches of a central processing unit (CPU), wherein the first notification message is used to indicate that the NIC has finished receiving the control segment data; determining an access instruction based on the control segment data in the CPU, and sending the access instruction to a target hard disk, so as to instruct the target hard disk to read the data segment data of the target packet stored in the NIC into the target hard disk through a direct communication channel between the NIC and the target hard disk.

[0007] This application also provides an access instruction sending device, comprising: a reading module, configured to read the control segment data of a target packet into the L1 cache and L2 cache of a central processing unit upon receiving a first notification message sent by a network interface card (NIC), wherein the first notification message is used to indicate that the NIC has finished receiving the control segment data; and a sending module, configured to determine an access instruction based on the control segment data in the central processing unit and send the access instruction to a target hard disk, thereby instructing the target hard disk to read the data segment data of the target packet stored in the NIC into the target hard disk through a direct communication channel between the NIC and the target hard disk.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of sending any of the above-described access instructions when executing the computer program.

[0009] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of sending any of the above-described access instruction methods.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of sending any of the above-described access instructions.

[0011] In this application, upon receiving a first notification message from the network interface card (NIC), the control segment data of the target packet is read into the L1 and L2 caches of the central processing unit (CPU). The first notification message indicates that the NIC has received the control segment data. An access instruction is determined based on the control segment data in the CPU and sent to the target hard disk. This instructs the target hard disk to read the data segment data of the target packet stored on the NIC from the NIC via a direct communication channel between the NIC and the target hard disk. In other words, in this embodiment, the control segment data and data segment data of the target packet are processed separately. Specifically, the control segment data is cached in the L1 and L2 caches of the CPU, fully utilizing both caches. Furthermore, the data segment data is written to the target hard disk (e.g., a Non-Volatile Memoryexpress (NVMe) hard disk) via a direct communication channel (peer-to-peer, P2P communication channel), reducing CPU memory usage and improving the performance of the NIC and hard disk. Therefore, this solves the problem of insufficient resource coordination between the central processing unit, network card, and hard drive in related technologies, which leads to the ineffective utilization of the central processing unit's L1 and L2 caches and the limited performance of the network card and hard drive. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a hardware structure block diagram of a computer terminal for a method of sending an access instruction according to an embodiment of this application.

[0014] Figure 2 This is a flowchart of a method for sending an access instruction according to an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of remote data scheduling according to an optional embodiment of this application;

[0016] Figure 4 This is a schematic diagram of the node's internal instructions and memory scheduling according to an embodiment of this application;

[0017] Figure 5 This is a frame diagram of an access instruction sending device according to an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0019] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0020] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The specific application environment architecture or specific hardware architecture on which the execution of the access command sending method depends is described here.

[0022] The methods and embodiments provided in this application can be executed on server devices, mobile terminals, computer terminals, or similar computing devices. Taking running on a computer terminal as an example, Figure 1 This is a hardware structure block diagram of a computer terminal for a method of sending an access command according to an embodiment of this application. For example... Figure 1 As shown, a computer terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a central processing unit (CPU), microprocessor unit (MPU), or programmable logic device (PLD)) and a memory 104 for storing data are also shown. The computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0023] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the method for determining the interaction state in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0024] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0025] Figure 2 This is a flowchart of an access instruction sending method according to an embodiment of this application, which can be applied to... Figure 1 In computer terminals, such as Figure 2 As shown, the process includes the following steps:

[0026] Step S202: Upon receiving the first notification message sent by the network card, the control segment data of the target packet is read into the first-level cache and the second-level cache of the central processing unit, wherein the first notification message is used to indicate that the network card has finished receiving the control segment data;

[0027] It should be noted that the target message includes a control segment and a data segment. The control segment contains message metadata and processing instructions, while the data segment contains the actual data to be transmitted.

[0028] The network interface card (NIC) identifies and processes the control segment data. Once completed, it sends a first notification message to the CPU, informing it that the control segment data is ready and can be directly cached without requiring additional unpacking work from the CPU. By storing the control segment data in the CPU's L1 and L2 caches, the CPU's processing speed can be significantly improved and latency reduced, since cache access is faster than memory access.

[0029] Step S204: Determine an access instruction based on the control segment data in the central processing unit, and send the access instruction to the target hard disk to instruct the target hard disk to read the data segment data of the target packet stored in the network card to the target hard disk through the direct communication channel between the network card and the target hard disk.

[0030] The CPU parses the control segment data to determine the data's storage location and access requirements, generating access instructions that specify the hard drive location where the data segment should be written to or read. These instructions are sent to the target hard drive, instructing it on how to process the data segment. A direct connection (e.g., a P2P direct connection) between the hard drive and the network interface card (NIC) allows data segments to be transferred directly from the NIC to the hard drive without passing through the CPU's memory. This P2P communication mechanism reduces data transmission latency and memory bandwidth usage, while also reducing the CPU load, allowing it to focus on control flow processing.

[0031] Through the above steps, upon receiving the first notification message from the network card, the control segment data of the target packet is read into the L1 and L2 caches of the central processing unit (CPU). The first notification message indicates that the network card has received the control segment data. An access instruction is determined based on the control segment data in the CPU and sent to the target hard disk. This instructs the target hard disk to read the data segment data of the target packet stored on the network card through a direct communication channel between the network card and the target hard disk. In other words, in this embodiment, the control segment data and data segment data of the target packet are processed separately. Specifically, the control segment data is cached in the CPU's L1 and L2 caches, fully utilizing both caches. Furthermore, the data segment data is written to the target hard disk (e.g., an NVMe hard disk) through a direct communication channel (P2P communication channel), reducing CPU memory usage and improving the performance of both the network card and the hard disk. Therefore, this solves the problem of insufficient resource coordination between the central processing unit, network card, and hard drive in related technologies, which leads to the ineffective utilization of the central processing unit's L1 and L2 caches and the limited performance of the network card and hard drive.

[0032] Optionally, reading the control segment data of the target message into the L1 and L2 caches of the central processing unit includes: registering a portion of memory for the network interface card (NIC) in the central processing unit to obtain the registered memory of the NIC, wherein the storage area of ​​the registered memory is mapped to the address space of the NIC; configuring the NIC with direct access permission to the registered memory, so that the NIC with the configured permission can cache the control segment data into the registered memory through the mapping relationship; and upon receiving the first notification message sent by the NIC, reading the control segment data cached in the registered memory into the L1 and L2 caches of the central processing unit.

[0033] To efficiently cache the control segment data of target packets in the CPU's L1 and L2 caches, specific memory regions need to be registered in the CPU for the Network Interface Card (NIC). These registered memory regions are mapped to the NIC's address space. By registering memory, the NIC can directly place control segment data in the registered memory regions without resorting to complex memory copying mechanisms, thus reducing data transmission latency and CPU resource consumption.

[0034] In this embodiment, the network interface card (NIC) is also configured with direct access to the memory region. Configuring direct access to the memory region allows the NIC to cache control segment data in registered memory after receiving a packet, based on a pre-established mapping relationship. This reduces CPU intervention in the traditional data path, enabling faster data transfer and caching, and improving data processing efficiency.

[0035] When the network interface card (NIC) has finished caching the control segment data and sends the first notification message to the CPU, it can be read by the CPU. The CPU reads the control segment data from registered memory into its L1 and L2 caches. The control segment data cached in L1 and L2 is parsed and processed to generate specific hard disk access instructions, ensuring the accuracy and efficiency of data transmission.

[0036] In other words, the Remote Direct Memory Access (RDMA) network card is programmed to recognize and process different parts of a target packet, such as the control and data segments. Specifically, a portion of memory is registered in the CPU for the RDMA network card; this memory is called the network card's registered memory. A mapping relationship is established between the registered memory's storage area and the network card's address space, allowing the network card to directly access this memory without going through the operating system kernel, thus reducing data processing latency and CPU load. Next, the network card's permissions are configured to allow direct access to the registered memory. When the network card receives a target packet containing a control segment, it automatically caches the control segment data in the registered memory according to the pre-defined mapping relationship, without having to copy it to main memory or cache it in a higher-level cache. Subsequently, when the CPU detects the first notification message sent by the network card, the CPU reads the control segment data in the registered memory and caches it in its own L1 and L2 caches. This ensures that the data can be accessed and processed quickly, which greatly improves the speed and efficiency of control message processing, reduces the pressure on the CPU's L1 and L2 caches, and allows the CPU to execute more tasks with minimal latency, thereby improving the overall system performance.

[0037] Optionally, a high-speed memory region close to the CPU can be selected as part of the memory registered for the network card to minimize the physical data transmission path and ensure high-speed reading. Simultaneously, the size of the registered memory can be set based on the expected amount of control segment data to avoid cache overflow and maximize cache utilization efficiency.

[0038] In this embodiment, by reducing CPU involvement, utilizing the high-speed access characteristics of L1 and L2 caches, and the hardware offloading capabilities of network cards and hard drives, the problems of insufficient resource coordination and inadequate release of hardware performance in traditional storage systems are overcome.

[0039] Optionally, the control segment data cached in the registered memory is read into the L1 and L2 caches of the central processing unit, including: receiving a first notification message triggered by the network card when the network card determines that the control segment data has been transferred to the registered memory; and continuously reading the control segment data cached in the registered memory into the L1 and L2 caches in batch mode when the first notification message sent by the network card is received.

[0040] A dedicated memory segment is registered in the CPU for the network interface card (NIC). This segment is called registration memory. Once the NIC has completed data transfer and determined that the control segment data has been processed, it sends a first notification message to the CPU. After the CPU receives this first notification message, indicating that the control segment data is already in the registration memory awaiting processing, it will use a batch method to continuously read the control segment data from the registration memory into its L1 and L2 caches.

[0041] It should be noted that batch read strategies can significantly improve data transfer efficiency and reduce the cache miss cost caused by reading each data packet individually. Continuous read operations can maintain the continuity and consistency of the CPU cache, ensuring that control segment data can be efficiently managed and utilized in the L1 and L2 caches.

[0042] In other words, after an RDMA communication connection is established between the two nodes, the network card (NIC) recognizes that the received packet contains control segment data. The NIC transfers the control segment data to a pre-registered memory area and simultaneously triggers a first notification message to the CPU. Upon receiving the first notification message, the CPU uses a batch processing method to continuously read the control segment data from the registered memory into its L1 and L2 caches, thereby accelerating the processing speed of the control segment and improving the overall system performance. During this process, the processing of the control segment data does not involve a large amount of data transfer; it mainly utilizes the CPU's cache characteristics to improve processing efficiency and reduce the consumption of system resources.

[0043] Optionally, if the data segment data has been successfully written to the target hard disk, a second notification message is received from the target hard disk, wherein the second notification message is used to indicate that the data segment data has been successfully written to the target hard disk; the on-chip memory in the network card used to store the data segment data is determined; the on-chip memory is released, and the status of the on-chip memory is determined to be available.

[0044] Once the data segment is successfully written to the target hard drive, a second notification message is received from the target hard drive, verifying that the data segment write operation has been successfully completed without requiring additional confirmation checks from the CPU. Subsequently, the on-chip memory area on the network interface card (NIC) used to store the data segment is identified. After the memory is identified, an on-chip memory release operation is performed, changing the status of the memory area from "in use" to "available." This indicates that the memory can be reallocated for subsequent data transfer or processing tasks, avoiding idle and wasted memory resources and ensuring the cyclical utilization of on-chip memory.

[0045] Memory release mechanisms include updating memory state and reconfiguring the Memory Management Unit (MMU) to support rapid storage and access of new data. Through dynamic management by the MMU, fine-grained control of on-chip memory can be achieved, ensuring rapid memory reclamation and allocation in high-concurrency environments, thereby maintaining stable system operation and high performance.

[0046] In other words, the two servers establish a high-speed communication channel via RDMA network cards. When one server needs to transfer a large amount of data to the other, it first divides the data into control and data segments. The control segment contains destination hard drive information and metadata for the data segments, while the data segments are stored directly in the on-chip memory of the sending network card. The sending server sends control segment instructions to the CPU of the receiving server. After parsing the instructions, the CPU determines the target hard drive and configures a P2P direct communication channel between the target hard drive and the receiving network card. Subsequently, the CPU of the receiving server instructs the target hard drive to read the data segments through this P2P channel. The data segments are read directly from the on-chip memory of the receiving network card to the target hard drive without going through the host memory, thereby reducing memory bandwidth usage and improving data transfer efficiency. Once the data segments are successfully written to the target hard drive, the target hard drive sends a second notification message to the CPU of the receiving server via a communication mechanism, confirming the successful data write. Upon receiving this message, the CPU updates the management status of the on-chip memory of the network card, marking the on-chip memory previously used to store the data segments as "available" for subsequent data segment transmissions.

[0047] In this embodiment, the efficient confirmation mechanism and dynamic memory management strategy not only ensure the reliability and integrity of data transmission, but also achieve optimized utilization of hardware resources.

[0048] Optionally, before reading the control segment data of the target message into the CPU's L1 and L2 caches, the method further includes: obtaining the cache size of the L1 cache and the cache size of the L2 cache; and determining the amount of control segment data that the L1 and L2 caches are allowed to process based on the cache size of the L1 cache and the cache size of the L2 cache.

[0049] Specifically, the amount of control segment data that the L1 and L2 caches are allowed to process is determined based on the cache size of the L1 cache and the cache size of the L2 cache, including: the amount of control segment data that the L1 and L2 caches are allowed to process is determined by the following formula: CPU_I / O: CPU_I / O=(CPU_L1+CPU_L2)×(1-α), where CPU_L1 is the cache size of the L1 cache, CPU_L2 is the cache size of the L2 cache, and α is the first system preset coefficient.

[0050] In this embodiment, the amount of control segment data that the L1 and L2 caches can process is determined by the CPU_I / O formula: CPU_I / O = (CPU_L1 + CPU_L2) × (1 - α). Here, CPU_L1 represents the size of the L1 cache, CPU_L2 represents the size of the L2 cache, and α is a system-preset coefficient used to adjust the amount of data the CPU processes. This formula enables the CPU to efficiently process control flow information, while simultaneously offloading the data stream directly to the network and NVMe hard drive via P2P technology, reducing memory usage and I / O processing time.

[0051] For example, in a high-performance hyperconverged storage system, the system default coefficient α is 0.2. Assume the CPU's L1 cache is 32KB and its L2 cache is 256KB. According to the formula CPU_I / O = (CPU_L1 + CPU_L2) × (1 - α), the amount of control segment data that the CPU_I / O can process is calculated to be (32KB + 256KB) × (1 - 0.2) = 288KB × 0.8 = 230.4KB. That is, during system operation, as long as the amount of control segment data does not exceed 230.4KB, the CPU's L1 and L2 caches can be fully utilized for fast processing, thereby improving system processing efficiency.

[0052] The above technical solutions can significantly improve the performance of hyperconverged storage systems without increasing additional hardware costs, including improving bandwidth utilization, reducing I / O latency, and reducing resource consumption.

[0053] Optionally, before sending the access command to the target hard disk to instruct the target hard disk to read the data segment of the target packet stored in the network card to the target hard disk through the direct communication channel between the network card and the target hard disk, the method further includes: obtaining the bandwidth of the direct communication channel and the bandwidth of the network card; and determining the allowable data transfer amount of the direct communication channel based on the bandwidth of the direct communication channel and the bandwidth of the network card.

[0054] Specifically, the allowable data transfer amount Data_Transfer for the direct communication channel is determined by the following formula: Data_Transfer=(PCIe_Bandwidth+Net_Bandwidth)×(1-β), where PCIe_Bandwidth is the bandwidth of the direct communication channel, Net_Bandwidth is the bandwidth of the network card, and β is the second system preset coefficient.

[0055] The actual bandwidth (PCIe_Bandwidth) of the direct communication channel and the network card's bandwidth (Net_Bandwidth) can be obtained by directly accessing the hardware performance monitoring module or running a dedicated speed test tool. Based on the bandwidth of the direct communication channel and the network card, the allowable data transfer amount (Data_Transfer) of the direct communication channel is determined by the following formula: Data_Transfer: Data_Transfer=(PCIe_Bandwidth+Net_Bandwidth)×(1-β), where β is a second system preset coefficient used to balance the actual bandwidth utilization of the channel and the safety margin for data transfer. Using this formula, the data transfer amount can be dynamically adjusted according to the current hardware conditions and system load, ensuring efficient channel utilization without overload.

[0056] Optionally, the β coefficient can be set based on historical data, performance test results, or preset security policies.

[0057] The above solution not only fully utilizes the high-speed data transmission capabilities of the Peripheral Component Interconnect Express (PCIe) bus, but also takes into account the transmission rate of the network card. This ensures that in data-intensive application scenarios, such as hyperconverged storage environments, data segments can be quickly and accurately transferred to the target hard drive, reducing reliance on the CPU and accelerating I / O operations.

[0058] For example, in a high-performance hyperconverged storage system, assuming the direct communication channel bandwidth (PCIe_Bandwidth) is 16GB / s, the network interface card (NIC) bandwidth (Net_Bandwidth) is 200GB / s, and the system default coefficient β is 0.1, according to the formula Data_Transfer=(PCIe_Bandwidth+Net_Bandwidth)×(1-β), the data transfer volume is calculated as (16GB / s+200GB / s)×(1-0.1)=207.6GB / s. That is, in this system, the allowable data transfer volume during P2P data transmission via the direct communication channel and NIC is 207.6GB / s.

[0059] Optionally, after sending the access command to the target hard disk to instruct the target hard disk to read the data segment data of the target packet stored in the network card to the target hard disk through the direct communication channel between the network card and the target hard disk, the method further includes: obtaining the power consumption of the central processing unit, the power consumption of the network card, and the power consumption of the target hard disk; and determining the current offloading capability value of the hardware based on the power consumption of the central processing unit, the power consumption of the network card, and the power consumption of the target hard disk.

[0060] Specifically, the current offloading capacity value of the hardware, Hardware_Offload, is determined by the following formula: Hardware_Offload=(CPU_Power+Net_Power+Disk_Power)(1-γ), where CPU_Power is the power consumption of the central processing unit, Net_Power is the power consumption of the network card, Disk_Power is the power consumption of the target hard disk, and γ is a preset coefficient of the third system. The hardware includes: central processing unit, network card and target hard disk.

[0061] In this embodiment of the application, three power consumption data points, CPU_Power (power consumption of the central processing unit), Net_Power (power consumption of the network card), and Disk_Power (power consumption of the target hard disk), are obtained through hardware monitoring interfaces or sensors, reflecting the energy consumption status of each hardware component under the current working task.

[0062] γ is a preset power utilization factor for the system. By multiplying it by (1-γ), the proportion of power that the hardware components can use for offloading or additional processing without sacrificing stability is estimated. This ensures that while making full use of hardware capabilities, system instability or damage caused by overuse can also be avoided.

[0063] Once the hardware's offload capacity is determined, the system can intelligently allocate tasks based on that capacity. For example, it can select which data transmission tasks are suitable for processing through a direct communication channel, which control flow tasks are more suitable for processing by the CPU, or how to improve the parallel processing efficiency of the network card and hard drive without increasing additional power consumption.

[0064] Optionally, determining the access instruction based on the control segment data in the central processing unit includes: parsing the control segment data to obtain a parsing result; determining the data segment data corresponding to the control segment data based on the parsing result, and determining the target hard disk from multiple hard disks, as well as the storage offset of the target hard disk; and generating an access instruction based at least on the identification information and storage offset of the data segment data.

[0065] Once the control segment data is acquired, it is parsed to extract key information, including but not limited to the data segment identifier, storage requirements, and corresponding hard drive information. Based on the parsing results, the specific location of the data segment corresponding to the control segment data is further determined, and a suitable target hard drive for storing this data is identified from the available hard drives.

[0066] Determining a suitable target hard drive from available hard drives for storing the data includes, but is not limited to, determining a suitable target hard drive based on the hard drive's current available space, past write patterns, and hard drive health status. Furthermore, determining the storage offset of the target hard drive, which is the data's internal storage location on the hard drive.

[0067] In other words, when the central processing unit (CPU) receives a network packet with a specific identifier, it first parses the control segment data of the packet to extract the necessary operation information, such as read or write operations, and the associated data segment identifier. Assuming the control segment data indicates a write operation, it contains the unique identifier of the target data segment and destination information. Based on this parsing result, the processor determines the destination of the data segment data—that is, the target hard disk and its specific storage offset within the hard disk. Subsequently, the processor generates an access instruction. This instruction not only contains the data segment's identifier information but also specifies the storage location on the target hard disk, ensuring that the data can be accurately written to the specified hard disk area.

[0068] In this embodiment, the efficient storage process between the data segment and multiple hard drives is coordinated, reducing resource consumption in intermediate steps and improving the data processing capability and response speed of the entire hyperconverged storage system.

[0069] Optionally, before sending the access command to the target hard drive to instruct the target hard drive to read the data segment of the target packet stored in the network card to the target hard drive through the direct communication channel between the network card and the target hard drive, the method further includes: obtaining the peripheral component interconnect address of the network card and the peripheral component interconnect address of the target hard drive; and configuring communication based on the peripheral component interconnect address of the network card and the peripheral component interconnect address of the target hard drive to build a direct communication channel.

[0070] Obtain the Peripheral Component Interconnect (PCI) address of the network interface card (NIC) and the target hard drive. The PCI address can be understood as a unique identifier for a hardware device within a network, indicating its specific location on the system bus and the detailed access path. After obtaining the PCI addresses, the location of the NIC and the target hard drive within the network architecture can be determined.

[0071] After obtaining the PCI addresses of the network card and the target hard drive, communication configuration is performed. This configuration is typically handled by the system's Hardware Abstraction Layer (HAL) or the underlying driver. Based on the PCI address information, the HAL or driver adjusts the PCI bus settings and configures necessary hardware resources, such as the Direct Memory Access Controller (DMA) and Memory Management Unit (MMU), to support P2P data transmission. P2P communication configuration allows the network card and the target hard drive to directly exchange data, bypassing the host's CPU and main memory, significantly reducing data processing latency and increasing data throughput.

[0072] When the CPU receives an I / O request and parses the control and data flow, it determines the target hard drive location for the data flow. Subsequently, the CPU sends an access command to the target hard drive, which includes the storage location information of the data segment on the network interface card (NIC). Before the target hard drive begins reading the data segment, it first obtains the PCIe addresses of both the NIC and the target hard drive. Based on these two addresses, a PCIe direct connection communication channel is configured, allowing the target hard drive to directly access the data segment on the NIC without CPU intervention, thus achieving high-speed data segment transfer and offloading. In this scenario, such as when handling a large file transfer task, the CPU only needs to send the access command to the target hard drive and establish P2P communication with the help of the PCIe address. The subsequent data reading and writing processes are automatically completed by the direct connection channel, significantly improving data processing speed and efficiency.

[0073] The above communication configuration establishes a direct communication channel between the network card and the target hard drive. This direct communication channel improves data transmission speed and efficiency.

[0074] Optionally, sending an access command to the target hard disk to instruct the target hard disk to read the data segment data of the target packet stored in the network card to the target hard disk through the direct communication channel between the network card and the target hard disk includes: sending an access command to the target hard disk to instruct the target hard disk to initiate a direct memory access operation to the network card through the direct communication channel; and writing the data segment data accessed from the network card into the memory of the target hard disk.

[0075] When data segments are transferred from the network interface card (NIC) to the target hard drive, the CPU generates an access command. This command includes necessary information for data transfer, such as the data segment identifier, source address (the NIC's memory address), destination address (the target hard drive's storage location), and the size of the data to be transferred. The access command is sent to the target hard drive's controller. Upon receiving the command, the target hard drive initiates a Direct Memory Access (DMA) operation with the NIC via a direct communication channel. DMA is a mechanism that allows hardware devices to directly access system memory without CPU intervention, significantly improving data transfer speed. A DMA operation means the target hard drive controller can directly access the data segments stored in the NIC's memory without CPU assistance. In other words, after the communication channel is configured, the hard drive can recognize the data on the NIC and automatically perform data reading operations.

[0076] After the read operation is complete, the data segment will be written to the target hard drive's storage. Write operations can also utilize DMA technology, directly transferring data from the network card's on-chip memory to the hard drive's storage medium via a PCIe direct connection, further avoiding the involvement of the CPU and main memory, thus reducing data processing time overhead.

[0077] The embodiments of this application can ensure the smoothness of data transmission and the efficiency of storage operations.

[0078] Optionally, the data segment data accessed from the network card is written to the memory of the target hard disk, including: writing the data segment data to the dynamic random access memory of the target hard disk; in the event of an abnormal event, the data segment data stored in the dynamic random access memory is flushed to the flash memory of the target hard disk through a supercapacitor installed in the target hard disk, wherein the supercapacitor is connected to the dynamic random access memory and the flash memory respectively.

[0079] When data segments arrive at the target hard drive from the network card via the direct communication channel, the data is temporarily stored in the hard drive's built-in Dynamic Random Access Memory (DRAM) and is not directly written to the relatively slower Flash Memory. Because DRAM can provide faster data access speeds than Flash Memory, data segments can be cached quickly, thereby greatly shortening data transmission time and improving system response speed and data throughput.

[0080] However, DRAM is a volatile memory, and the data stored in DRAM will be lost when the power is turned off. Therefore, a supercapacitor is installed in the target hard drive as an emergency power source. Supercapacitors can store and release a large amount of electrical energy in a short time. Compared with ordinary batteries, they charge faster and have a longer cycle life, making them suitable for data protection in the event of a sudden power outage.

[0081] When an abnormal event (such as a power outage) occurs, the supercapacitor is immediately activated to provide temporary power to the DRAM and to initiate an emergency data flush process, which quickly transfers the data segment stored in the DRAM to the flash memory.

[0082] The above approach, combining DRAM with supercapacitors, not only improves the efficiency of data transmission and writing, but also provides a reliable guarantee for persistent data storage.

[0083] Optionally, before sending the access command to the target hard disk to instruct the target hard disk to read the data segment data of the target packet stored in the network card to the target hard disk through the direct communication channel between the network card and the target hard disk, the method further includes: determining the on-chip memory in the network card for caching the data; and caching the data segment data in the target packet to the on-chip cache in the network card when the network card receives the target packet.

[0084] The on-card memory on the network card is used to temporarily store data received from the network so that it can be directly transferred to the target hard drive later, thereby improving the overall data processing speed and system efficiency.

[0085] When the network card receives a target packet, the DMA controller in the network card will identify and process the data segment data contained in the packet and load it into the on-chip cache of the network card. The on-chip cache is located in a high-speed storage area inside the network card, and its access speed is higher than that of the main system memory, which can significantly reduce the latency of data loading and transmission.

[0086] The use of on-chip cache accelerates the initial reception and storage of data. After the CPU processes the control segment information of the target message and determines the target hard disk of the data segment, a direct communication channel is established, enabling the target hard disk to directly access the on-chip cache in the network card and read the data segment data into the memory of the target hard disk through P2P communication mode, without having to go through the CPU and main memory for further processing and transfer, which greatly saves system resources and processing time.

[0087] Optionally, before reading the control segment data of the target message into the L1 and L2 caches of the central processing unit, the method further includes: distinguishing control segment data and data segment data from the target message according to a keyword matching method, wherein the control segment data is used to be read into the L1 and L2 caches, and the data segment data is used to be written to the target hard disk.

[0088] Keyword matching is a highly efficient data identification technology used to quickly distinguish between control segment data and data segment data in target messages, ensuring that different types of data are processed appropriately, avoiding resource waste, and improving processing efficiency.

[0089] When an RDMA network card receives a target packet, the microprocessor on the card performs initial parsing. Using pre-defined keywords, it can distinguish which parts of the packet are control data and which are data data.

[0090] Control segment data is read into the CPU's L1 and L2 caches. CPU caches are high-speed storage areas located inside the CPU, used to temporarily store recently or frequently used data to reduce the number of accesses to main memory and improve computation speed. By reading control segment data into the L1 and L2 caches, the CPU can directly retrieve instructions and metadata from these caches without waiting for a response from main memory, thus significantly accelerating the control flow processing speed and improving system responsiveness and processing efficiency.

[0091] To better understand the process of sending the access command described above, the implementation flow of the method will be further explained below with reference to optional embodiments, but this is not intended to limit the technical solution of the embodiments of this application.

[0092] This application provides a method for sending an access command, such as... Figure 3 and Figure 4 As shown, it specifically includes:

[0093] Step 1: Establish a dedicated connection channel between the Remote Direct Memory Access (RDMA) network card and the NVMe hard drive, and register the host system memory to the network card.

[0094] Step 1 establishes an environment that supports RDMA network communication, ensuring that both parties can exchange data directly and efficiently.

[0095] Step 2: Program the RDMA network card to enable it to recognize different types of packets, distinguish between data segments and control segments based on packet content, and then adopt differentiated processing strategies.

[0096] Metadata segments are preferentially placed in RDMA registered memory for easy CPU scheduling; data segments reside directly in network card memory, avoiding unnecessary data copying, saving host memory resources, and significantly reducing data processing and transmission latency.

[0097] Step 3: When the host detects that the network card has successfully received the event of the control segment, it will enable the batch alignment acceleration mechanism of L1 and L2 caches, cache the control segment in the high-speed cache, and use the CPU's concurrent processing capability to quickly process the task commands in the control segment.

[0098] Step 4: After receiving the control segment information, the CPU converts it into a Non-Volatile Memory Express (NVMe) instruction set and sends it directly to the NVMe device. Simultaneously, it configures a P2P data transfer channel between the network card and the NVMe device, supporting direct data interaction between the NVMe hard drive and the network card. This minimizes direct CPU involvement and achieves efficient data transmission and processing.

[0099] Step 5: After receiving the converted instructions, the NVMe hard drive accesses the on-chip memory area located on the network card through the PCIe bus and writes the data segment to the NVMe hard drive.

[0100] Step 6: After the data segment is successfully written to the NVMe hard drive, notify the CPU to perform resource scheduling and clean up the data segments in the memory on the network card to avoid performance bottlenecks caused by data accumulation.

[0101] Through the above steps, this method effectively improves data transfer speed in hyperconverged storage environments, reduces I / O processing latency, and significantly reduces CPU and main memory resource consumption.

[0102] In this embodiment, by separating numerical control from control, the CPU can process a small amount of control flow I / O, giving full play to the CPU's L1 and L2 cache capabilities; by offloading network and NVMe hard drive data transmission through P2P, the PCIe channel and network card capabilities are fully utilized; and by leveraging hardware offloading capabilities and its own capabilities, high-bandwidth, low-latency hyperconverged storage is achieved.

[0103] The formula for CNC separation is CPU_I / O = (CPU_L1 + CPU_L2) (1-α); The formula for offloading P2P data transmission is Data_Transfer=(PCIe_Bandwidth+Net_Bandwidth) (1-β); The formula for hardware offload capability and its own capability is Hardware_Offload=(CPU_Power+Net_Power+Disk_Power). (1-γ), where CPU_L1 is the cache size of the L1 cache, CPU_L2 is the cache size of the L2 cache, α is the first system preset coefficient, PCIe_Bandwidth is the bandwidth of the direct communication channel, Net_Bandwidth is the bandwidth of the network card, β is the second system preset coefficient, CPU_Power is the power consumption of the central processing unit, Net_Power is the power consumption of the network card, Disk_Power is the power consumption of the target hard disk, and γ is the third system preset coefficient.

[0104] By registering data in memory, the network transmission between nodes is offloaded, and the data segment and control segment are separated. The data segment and control segment are stored in different memory segments on the target host, freeing up the CPU of the sending end and reducing the resource consumption of network transmission.

[0105] Optionally, the data segment and control segment can be stored in different memory segments on the target host, including: marking the packet when sending it over the network, performing preliminary processing of the network packet through network card programming, and when a control segment packet is detected, placing the control segment packet into the host memory through the RDMA memory registered at the receiving end, which can be directly accessed by the host CPU; when a data segment is detected, it is placed directly into the on-chip memory of the network card, without going through the host memory, thus reducing the use of host memory.

[0106] Optionally, the control segment messages can be placed in the host memory, including: since the control segment memory is relatively small, the CPU's L1 and L2 memory can be accelerated, and the L1 and L2 hit rate can be improved through batch submission by the network card and batch processing by the CPU, so as to make full use of every clock cycle of the CPU for control message processing.

[0107] Optionally, control message processing is performed, including: performing local I / O calculations based on the write position and write data segment in the control message, calculating the offset of the NVMe hard drive and the disk platter where the I / O is stored, converting the control message into NVMe commands, and sending the NVMe commands to the NVMe hard drive.

[0108] Optionally, NVMe commands are sent to the NVMe hard disk, including: the command sends the network card address and the corresponding data segment, the NVMe on-chip system can perform P2P network interaction configuration according to the physical location of the network card in the host, and then perform remote memory access to store the data in the NVMe hard disk.

[0109] Optionally, P2P network interaction configuration can be performed based on the physical location of the network card on the host, including: configuring PCIe to PCIe communication based on the PCI addresses of the hard drive and the network card, supporting message exchange between PCIe buses for dual PCIe devices, directly utilizing the bus bandwidth, and bypassing the kernel to reduce CPU resource consumption.

[0110] Optionally, remote memory access is stored in the NVMe hard drive, including: interacting between the network card and the NVMe device according to the configured P2P channel, directly performing DMA operation on the data segments stored in the network card, and writing them into the NAND of the NVMe hard drive to complete the solidification of the data packets.

[0111] Optionally, writing to the NAND of the NVMe hard drive includes: accelerating I / O by directly writing I / O to the on-disk memory of the NVMe hard drive through the PMR feature of NVMe, and caching and flushing to the NAND through the supercapacitor of the NVMe hard drive, thereby reducing the time spent by the NVMe hard drive from on-disk memory to NAND storage and speeding up I / O processing.

[0112] Optionally, the data packet is solidified, including: the data is stored in a non-volatile storage medium, and then the CPU is notified to perform message interaction, the message is notified to complete the processing, and the network card is notified to reclaim the on-chip memory, thereby reducing the CPU's involvement and allowing the CPU to focus on calculation and location translation.

[0113] Optionally, the data is stored in a non-volatile storage medium, and then the CPU is notified to perform message interaction, including: the completion of the instruction requires scheduling by the CPU, the CPU schedules the sending of the RDMA return message, and the network card offloads the return message, thereby reducing the CPU's performance consumption.

[0114] Optionally, the control segment data can be placed in the host memory, including continuous processing through control segment memory registration and memory callback, supporting direct batch continuous caching of the CPU into L1 and L2, thereby accelerating the control segment processing speed.

[0115] Optionally, the data segment and control segment can be placed separately, including: using the system on the network card to perform packet preprocessing, and identifying the content of the control segment and data segment based on logic such as keyword matching, thereby accelerating the speed of packet problem handling.

[0116] Optionally, the data segment memory can be placed directly in the memory on the network card, including: by actively programming, using part of the on-chip system on the network card as a data cache to directly store the data segment, and managing the memory through the MMU to improve the utilization of on-chip memory.

[0117] Optionally, the NVMe hard drive where I / O is stored and its location are calculated, including: through consistent hash calculation, through full CPU calculation, reducing the consumption of metadata access, improving the disk determination speed, and accelerating I / O distribution.

[0118] Optionally, the NVMe hard drive and its location for I / O storage are calculated, including: finding free locations through NVMe hard drive metadata management and Append I / O to store data segments, thus avoiding data loss after power failure.

[0119] Optionally, free space can be found through append I / O, including: reducing the performance impact of garbage collection within the NVMe hard drive through proactive space reclamation and merging, and fully leveraging the performance of the NVMe hard drive.

[0120] Optionally, P2P communication between the hard drive and the network card is supported, including: when the NVMe hard drive recognizes the location of the data stored on the network card, it can perform memory copying across PCI to copy the data to the on-chip memory of the NVMe hard drive.

[0121] Optionally, Kernel Bypass reduces CPU resource consumption by enabling interaction between two on-chip systems on the PCI channel via P2P message access, bypassing kernel calls directly without CPU involvement, and fully utilizing the capabilities of the PCI channel.

[0122] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0123] This embodiment also provides an access instruction sending device, which is used to implement the above embodiments and preferred embodiments, and will not be repeated hereafter. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0124] Figure 5 This is a frame diagram of an access instruction sending device according to an embodiment of this application, such as... Figure 5 As shown, the device includes:

[0125] The reading module 52 is used to read the control segment data of the target packet into the first-level cache and the second-level cache of the central processing unit when it receives the first notification message sent by the network card, wherein the first notification message is used to indicate that the network card has finished receiving the control segment data;

[0126] The sending module 54 is used to determine an access instruction based on the control segment data in the central processing unit and send the access instruction to the target hard disk, so as to instruct the target hard disk to read the data segment data of the target packet stored in the network card to the target hard disk through the direct communication channel between the network card and the target hard disk.

[0127] Upon receiving a first notification message from the network interface card (NIC), the control segment data of the target packet is read into the L1 and L2 caches of the central processing unit (CPU). The first notification message indicates that the NIC has received the control segment data. An access instruction is determined based on the control segment data in the CPU and sent to the target hard disk. This instructs the target hard disk to read the data segment data of the target packet stored on the NIC from the NIC via a direct communication channel between the NIC and the target hard disk. In other words, in this embodiment, the control segment data and data segment data of the target packet are processed separately. Specifically, the control segment data is cached in the CPU's L1 and L2 caches, fully utilizing both caches. Furthermore, the data segment data is written to the target hard disk (e.g., an NVMe hard disk) via a direct communication channel (P2P communication channel), reducing CPU memory usage and improving the performance of both the NIC and the hard disk. Therefore, this solves the problem of insufficient resource coordination between the central processing unit, network card, and hard drive in related technologies, which leads to the ineffective utilization of the central processing unit's L1 and L2 caches and the limited performance of the network card and hard drive.

[0128] In one embodiment of this application, a reading module is used to register a portion of memory for the network card in the central processing unit (CPU) to obtain the registered memory of the network card, wherein the storage area of ​​the registered memory has a mapping relationship with the address space of the network card; configure the network card with direct access permission to the registered memory, so that the network card with the configured permission can cache control segment data in the registered memory through the mapping relationship; and upon receiving a first notification message sent by the network card, read the control segment data cached in the registered memory into the CPU's L1 cache and L2 cache.

[0129] In one embodiment of this application, the reading module is used to receive a first notification message triggered by the network card when the network card determines that the control segment data has been transferred to the registered memory; and upon receiving the first notification message sent by the network card, continuously read the control segment data cached in the registered memory into the first-level cache and the second-level cache in a batch manner.

[0130] In one embodiment of this application, the above-mentioned device further includes: a determining module, configured to receive a second notification message from the target hard disk when the data segment data has been successfully written to the target hard disk, wherein the second notification message is used to indicate that the data segment data has been successfully written to the target hard disk; determine the on-chip memory in the network card used to store the data segment data; release the on-chip memory and determine the status of the on-chip memory as available.

[0131] In one embodiment of this application, a reading module is used to obtain the cache size of the first-level cache and the cache size of the second-level cache; and to determine the amount of control segment data that the first-level cache and the second-level cache are allowed to process based on the cache size of the first-level cache and the cache size of the second-level cache.

[0132] In one embodiment of this application, the reading module is used to determine the amount of control segment data that can be processed by the L1 cache and L2 cache using the following formula: CPU_I / O=(CPU_L1+CPU_L2)×(1-α), where CPU_L1 is the cache size of the L1 cache, CPU_L2 is the cache size of the L2 cache, and α is a first system preset coefficient.

[0133] In one embodiment of this application, a reading module is used to obtain the bandwidth of the direct communication channel and the bandwidth of the network card; and to determine the allowable data transfer amount of the direct communication channel based on the bandwidth of the direct communication channel and the bandwidth of the network card.

[0134] In one embodiment of this application, the reading module is used to determine the allowable data transfer amount Data_Transfer of the direct communication channel using the following formula: Data_Transfer=(PCIe_Bandwidth+Net_Bandwidth)×(1-β), where PCIe_Bandwidth is the bandwidth of the direct communication channel, Net_Bandwidth is the bandwidth of the network card, and β is a second system preset coefficient.

[0135] In one embodiment of this application, a reading module is used to acquire the power consumption of the central processing unit, the power consumption of the network card, and the power consumption of the target hard disk; and to determine the current offloading capability value of the hardware based on the power consumption of the central processing unit, the power consumption of the network card, and the power consumption of the target hard disk.

[0136] In one embodiment of this application, the reading module is used to determine the current offloading capability value of the hardware, Hardware_Offload, using the following formula: Hardware_Offload=(CPU_Power+Net_Power+Disk_Power)(1-γ), where CPU_Power is the power consumption of the central processing unit, Net_Power is the power consumption of the network card, Disk_Power is the power consumption of the target hard disk, and γ is a third system preset coefficient. The hardware includes: a central processing unit, a network card, and a target hard disk.

[0137] In one embodiment of this application, the sending module is used to parse control segment data to obtain a parsing result; determine the data segment data corresponding to the control segment data based on the parsing result, and determine the target hard disk and the storage offset of the target hard disk from multiple hard disks; and generate an access instruction based at least on the identification information and storage offset of the data segment data.

[0138] In one embodiment of this application, a sending module is used to obtain the peripheral interconnect address of the network card and the peripheral interconnect address of the target hard disk; and to perform communication configuration based on the peripheral interconnect address of the network card and the peripheral interconnect address of the target hard disk to build a direct communication channel.

[0139] In one embodiment of this application, a sending module is used to send an access command to the target hard disk, instructing the target hard disk to initiate a direct memory access operation to the network card through a direct communication channel; and to write the data segment data accessed from the network card into the memory of the target hard disk.

[0140] In one embodiment of this application, the above-mentioned device further includes: a writing module, used to write data segment data into the dynamic random access memory of the target hard disk; in the event of an abnormal event, the data segment data stored in the dynamic random access memory is flushed to the flash memory of the target hard disk through a supercapacitor installed in the target hard disk, wherein the supercapacitor is connected to the dynamic random access memory and the flash memory respectively.

[0141] In one embodiment of this application, the sending module is used to determine the on-chip memory for caching data from the network card; when the network card receives a target packet, it caches the data segment data in the target packet into the on-chip cache of the network card.

[0142] In one embodiment of this application, the writing module is used to distinguish control segment data and data segment data from the target message according to a keyword matching method, wherein the control segment data is used to be read into the first-level cache and the second-level cache, and the data segment data is used to be written to the target hard disk.

[0143] It should be noted that the description of the features in the embodiment corresponding to the access instruction sending device can be found in the relevant description of the embodiment corresponding to the access instruction sending method, and will not be repeated here.

[0144] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-described methods for sending access instructions.

[0145] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described methods for sending access instructions when it is run.

[0146] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0147] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described methods for sending access instructions.

[0148] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described methods for sending access instructions.

[0149] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0150] The above provides a detailed description of a method for sending an access instruction provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for sending an access command, characterized in that, include: Upon receiving the first notification message sent by the network card, the control segment data of the target packet is read into the L1 and L2 caches of the central processing unit, wherein the first notification message is used to indicate that the network card has finished receiving the control segment data; The access instruction is determined based on the control segment data in the central processing unit, and the access instruction is sent to the target hard disk to instruct the target hard disk to read the data segment data of the target packet stored in the network card to the target hard disk through the direct communication channel between the network card and the target hard disk; The process of reading the control segment data of the target packet into the L1 and L2 caches of the central processing unit includes: registering a portion of memory for the network interface card (NIC) in the central processing unit to obtain the registered memory of the NIC, wherein the storage area of ​​the registered memory is mapped to the address space of the NIC; configuring the NIC with direct access permission to the registered memory, so that the NIC with the configured permission can cache the control segment data into the registered memory through the mapping relationship; receiving the first notification message triggered by the NIC when the NIC determines that the control segment data has been transferred to the registered memory; and continuously reading the control segment data cached in the registered memory into the L1 and L2 caches in batches upon receiving the first notification message from the NIC.

2. The method for sending an access command according to claim 1, characterized in that, After sending the access command to the target hard disk to instruct the target hard disk to read the data segment of the target packet stored on the network card to the target hard disk through the direct communication channel between the network card and the target hard disk, the method further includes: If the data segment has been successfully written to the target hard disk, a second notification message is received from the target hard disk, wherein the second notification message is used to indicate that the data segment has been successfully written to the target hard disk; Identify the on-chip memory in the network interface card used to store the data segment data; Release the on-chip memory and determine the status of the on-chip memory as available.

3. The method for sending an access command according to claim 1, characterized in that, Before reading the control segment data of the target message into the CPU's L1 and L2 caches, the method further includes: Obtain the cache size of the first-level cache and the cache size of the second-level cache; The amount of control segment data that the first-level cache and the second-level cache are allowed to process is determined based on the cache size of the first-level cache and the cache size of the second-level cache.

4. The method for sending an access command according to claim 3, characterized in that, The amount of control segment data that the first-level cache and the second-level cache are allowed to process is determined based on the cache size of the first-level cache and the cache size of the second-level cache, including: The amount of control segment data that the L1 and L2 caches are allowed to process (CPU_I / O) is determined by the following formula: CPU_I / O = (CPU_L1 + CPU_L2) × (1 - α), where CPU_L1 is the cache size of the L1 cache, CPU_L2 is the cache size of the L2 cache, and α is a first system preset coefficient.

5. The method for sending an access command according to claim 1, characterized in that, Before sending the access command to the target hard disk to instruct the target hard disk to read the data segment data of the target packet stored on the network card to the target hard disk through the direct communication channel between the network card and the target hard disk, the method further includes: Obtain the bandwidth of the direct communication channel and the bandwidth of the network card; The allowable data transfer amount of the direct communication channel is determined based on the bandwidth of the direct communication channel and the bandwidth of the network card.

6. The method for sending an access command according to claim 5, characterized in that, The allowed data transfer volume of the direct communication channel is determined based on the bandwidth of the direct communication channel and the bandwidth of the network interface card, including: The allowed data transfer amount, Data_Transfer, for the direct communication channel is determined using the following formula: Data_Transfer=(PCIe_Bandwidth+Net_Bandwidth)×(1-β), where PCIe_Bandwidth is the bandwidth of the direct communication channel, Net_Bandwidth is the bandwidth of the network card, and β is a second system preset coefficient.

7. The method for sending an access command according to claim 1, characterized in that, After sending the access command to the target hard disk to instruct the target hard disk to read the data segment of the target packet stored on the network card to the target hard disk through the direct communication channel between the network card and the target hard disk, the method further includes: Obtain the power consumption of the central processing unit, the power consumption of the network card, and the power consumption of the target hard disk; The current offloading capability value of the hardware is determined based on the power consumption of the central processing unit, the power consumption of the network card, and the power consumption of the target hard disk.

8. The method for sending an access command according to claim 7, characterized in that, The current offloading capability value of the hardware is determined based on the power consumption of the central processing unit, the power consumption of the network card, and the power consumption of the target hard drive, including: The hardware's current offload capability value, Hardware_Offload, is determined using the following formula: Hardware_Offload=(CPU_Power+Net_Power+Disk_Power)*(1-γ), where CPU_Power is the power consumption of the central processing unit, Net_Power is the power consumption of the network card, Disk_Power is the power consumption of the target hard disk, and γ is a third system preset coefficient. The hardware includes: the central processing unit, the network card, and the target hard disk.

9. The method for sending an access command according to claim 1, characterized in that, Determine access instructions based on control segment data in the central processing unit, including: The control segment data is parsed to obtain the parsing results; Based on the parsing results, determine the data segment data corresponding to the control segment data, determine the target hard disk from multiple hard disks, and the storage offset of the target hard disk; The access instruction is generated based at least on the identification information of the data segment and the storage offset.

10. The method for sending an access command according to claim 1, characterized in that, Before sending the access command to the target hard disk to instruct the target hard disk to read the data segment data of the target packet stored on the network card to the target hard disk through the direct communication channel between the network card and the target hard disk, the method further includes: Obtain the peripheral component interconnection address of the network card and the peripheral component interconnection address of the target hard disk; Communication configuration is performed based on the peripheral component interconnection address of the network card and the peripheral component interconnection address of the target hard disk to construct the direct communication channel.

11. The method for sending an access command according to claim 1, characterized in that, Sending the access command to the target hard drive to instruct the target hard drive to read the data segment of the target packet stored on the network card and then to the target hard drive via the direct communication channel between the network card and the target hard drive, including: The access command is sent to the target hard disk to instruct the target hard disk to initiate a direct memory access operation to the network card through the direct communication channel; The data segment accessed from the network card is written into the memory of the target hard disk.

12. The method for sending an access command according to claim 11, characterized in that, Writing the data segment data accessed from the network card into the memory of the target hard disk includes: Write the data segment data into the dynamic random access memory of the target hard disk; In the event of an abnormal event, the data segment stored in the dynamic random access memory is flushed to the flash memory of the target hard drive through the supercapacitor installed in the target hard drive. The supercapacitor is connected to both the dynamic random access memory and the flash memory.

13. The method for sending an access command according to claim 1, characterized in that, Before sending the access command to the target hard disk to instruct the target hard disk to read the data segment data of the target packet stored on the network card to the target hard disk through the direct communication channel between the network card and the target hard disk, the method further includes: Identify the on-chip memory from the network interface card (NIC) used for caching data; When the network interface card (NIC) receives the target packet, the data segment data in the target packet is cached in the on-chip cache of the NIC.

14. The method for sending an access command according to claim 1, characterized in that, Before reading the control segment data of the target message into the CPU's L1 and L2 caches, the method further includes: The control segment data and the data segment data are distinguished from the target message based on the keyword matching method. The control segment data is used to be read into the first-level cache and the second-level cache, and the data segment data is used to be written to the target hard disk.

15. A means for sending an access command, characterized in that, include: The reading module is used to read the control segment data of the target packet into the L1 cache and L2 cache of the central processing unit upon receiving a first notification message sent by the network card, wherein the first notification message is used to indicate that the network card has finished receiving the control segment data; The sending module is used to determine an access instruction based on the control segment data in the central processing unit and send the access instruction to the target hard disk, so as to instruct the target hard disk to read the data segment data of the target packet stored in the network card to the target hard disk through the direct communication channel between the network card and the target hard disk; The reading module is configured to register a portion of memory for the network interface card (NIC) in the central processing unit (CPU) to obtain the registered memory of the NIC, wherein the storage area of ​​the registered memory is mapped to the address space of the NIC; configure the NIC with direct access permission to the registered memory, so that the NIC with the configured permission can cache the control segment data to the registered memory through the mapping relationship; when the NIC determines that the control segment data has been transferred to the registered memory, receive the first notification message triggered by the NIC; and upon receiving the first notification message sent by the NIC, continuously read the control segment data cached in the registered memory into the first-level cache and the second-level cache in batches.

16. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the method for sending the access instruction as described in any one of claims 1 to 14 when executing the computer program.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the method for sending the access instruction according to any one of claims 1 to 14.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method for sending the access instruction as described in any one of claims 1 to 14.

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