ARM NEON to RISC-V vector extension assembly code translation method and system

Abstract

The invention discloses an assembly code translation method and system for vector extension from ARM NEON to RISC-V, and belongs to the technical field of computer software cross-architecture translation. The method comprises the following steps of: improving an ARM NEON instruction into an equivalent LLVM IR expression form by utilizing a pre-designed mapping rule; performing general intermediate code optimization and special optimization oriented to RISC-V vector extension characteristics on the LLVM IR expression form; and reducing the optimized LLVM IR to a target code of the RISC-V vector extension platform. According to the method, the mapping rule beneficial to LLVM compiler instruction generation is constructed while specific optimization is performed for the RISC-V vector extension architecture, so that the instruction coverage rate is increased.

Description

Technical Field

[0001] This invention relates to the field of computer software cross-architecture translation technology, and in particular to a method and system for translating assembly code from ARM NEON to RISC-V vector extensions. Background Technology

[0002] RISC-V Vector Extensions (VLAS) are vector extensions of the RISC-V instruction set, effectively improving its ability to perform parallel computations. In recent years, the potential of RISC-V VLAS in high-performance computing (HPC) has become increasingly apparent, with research driving its applications in astrophysical simulations, machine learning, linear algebra computation, and genome analysis. However, the widespread adoption of RISC-V in HPC currently faces significant software ecosystem bottlenecks. On the one hand, while mainstream Linux distributions (Ubuntu, Fedora, etc.) and domestic operating systems (Kylin, Euler, DragonLizard, etc.) provide basic support, there is still a noticeable lag in adaptation to critical application layers (such as Docker and Kubernetes) and foundational software (such as MongoDB and TiDB). On the other hand, support for RISC-V VLAS in many mainstream open-source computing libraries remains incomplete, such as OpenCV, eigen, TensorFlow Lite, x264 / x265, FFmpeg, libjpeg-turbo, sonic-go, and XNNPACK. Therefore, there is an urgent need for practical and feasible solutions to accelerate the improvement and development of the RISC-V software ecosystem.

[0003] Porting ARM NEON code to the RISC-V vector extension architecture presents numerous challenges. First, from a vector programming perspective, ARM NEON uses a fixed-length vector instruction set, with its vector registers fixed at 64 or 128 bits; while RISC-V vector extension uses a variable-length vector instruction set, where the vector register length is determined by the underlying hardware microarchitecture, making it impossible to determine the register length from the instructions themselves during the software development phase. Second, regarding vector register organization, ARM NEON can only operate on 32, 64, or 128-bit vector registers at a time; while RISC-V vector extension supports more flexible register grouping, allowing operations at granularities of 1 / 8, 1 / 4, 1 / 2, 1, 2, 4, or 8 physical registers. Finally, from an instruction semantics perspective, ARM NEON and RISC-V vector extension architectures each have their own architecturally specific instructions, such as ARM NEON's inversion instructions `rev` and transpose instructions `trn`, and RISC-V vector extension's sequence number memory access instructions `vloxei` / `vsoxei`, etc. These differences further increase the porting difficulty.

[0004] Instruction translators based on the LLVM compiler framework decouple the instruction translation process into two stages: first, the source platform instructions are promoted to LLVM IR, and then the LLVM compiler backend is reused to downgrade the LLVM IR to the target platform's instructions. This approach allows for the reuse of the LLVM compiler backend, enabling tool developers to focus solely on the source instruction set promotion to LLVM IR stage. Currently, many open-source instruction promotion tools are available, such as Rellume, McSema, llvm-mctoll, retdec, and revng.

[0005] However, existing solutions offer limited support for vector instructions in terms of functionality. Current solutions achieve cross-platform migration by constructing mapping rules, while each platform has a vast instruction set; for example, x86 has nearly 1000 basic instructions and over 3600 extended instructions including MMX, SSE, and AVX. Currently, most open-source tools do not support vector instructions, with only a few covering some commonly used vector instruction sets (such as SSE and NEON). The highest support rate for ARM NEON in open-source tools is only about 120 / 404, indicating limited overall support.

[0006] In terms of performance, existing instruction mapping rules are inadequate. Downgrading from LLVM IR to the target platform is essentially instruction generation based on rule matching. Therefore, different mapping rules lead to different LLVM IRs generated during translation, resulting in varying performance of the final target code. However, existing open-source tools, within their supported vector instruction range, generally suffer from instruction sequence bloat in the target code generated according to their mapping rules, resulting in poor performance.

[0007] Furthermore, existing solutions lack specific optimizations for RISC-V vector extensions. Since an ARM NEON instruction can only operate on a maximum of one 128-bit vector register, the LLVM IR code boosted from ARM NEON may contain combinations of multiple 128-bit computation instructions, and the generated target code will also contain such instructions. However, unlike ARM NEON, RISC-V vector extensions feature register grouping, supporting simultaneous operation on multiple vector registers by a single instruction. However, current LLVM optimizers lack transformations to merge short vectors into long vectors. These issues result in a lack of optimizations for the RISC-V vector extension register grouping feature in translators based on the LLVM compilation framework. Summary of the Invention

[0008] This invention discloses an assembly code translation method and system for ARM NEON to RISC-V vector extension. While making specific optimizations for the RISC-V vector extension architecture, it constructs mapping rules that are beneficial to the instruction generation of the LLVM compiler, thereby improving instruction coverage.

[0009] To achieve the above objectives, the technical solution of the present invention includes the following:

[0010] A method for translating assembly code from ARM NEON to RISC-V vector extensions, the method comprising: By using pre-designed mapping rules, ARM NEON instructions are elevated to equivalent LLVM IR expressions; General intermediate code optimization and special optimization for RISC-V vector extension features are performed on the LLVM IR representation. The optimized LLVM IR is demoted to target code for the RISC-V Vector Extensions platform.

[0011] Furthermore, the process of constructing the mapping rules includes: The target C++ source code is compiled to generate ARM NEON code and LLVM IR code respectively; during the compilation process, the -g option is enabled to preserve the line numbers and variable information of the target C++ source code; The .loc tags in the ARM NEON code and the !dbg metadata in the LLVM IR code are parsed to extract the ARM NEON code snippets and LLVM IR code snippets corresponding to the same source code lines in the target C++ source code, and to establish a structured mapping relationship between line numbers, ARM NEON code snippets and LLVM IR code snippets; Reconstruct the ARM NEON code snippet and the LLVM IR code snippet corresponding to the same source code line into small verification code, and verify the equivalence of the ARM NEON code snippet and the LLVM IR code snippet; When ARM NEON code snippets and LLVM IR code snippets are equivalent, the ARM NEON code snippet, the LLVM IR code snippet, and the structured mapping relationship are treated as a single mapping rule and entered into the mapping rule library. Generalize the mapping rules in the mapping rule base.

[0012] Furthermore, the generation of ARM NEON code and LLVM IR code includes: Use the command clang++ -S -g -march=armv8-a+simd to obtain the ARM NEON code; Use the command clang++ -S -emit-llvm -g to obtain the LLVM IR code.

[0013] Furthermore, the equivalence of the ARM NEON code snippet and the LLVM IR code snippet is verified, including: The ARM NEON code snippet and the LLVM IR code snippet were compiled independently to obtain the first program and the second program; Input the same input information into the first program and the second program respectively, and determine whether the first program and the second program output the same result; If the first and second programs output the same result, the ARM NEON code snippet and the LLVMIR code snippet are considered equivalent.

[0014] Furthermore, the generalization of mapping rules in the mapping rule base includes: The operational characteristics of ARM NEON code snippets are analyzed to identify ARM NEON instructions containing specific operational modes; wherein, the specific operational modes include: saturation operation mode, halving operation mode, doubling operation mode, rounding mode, pairing mode, and reduction mode; Extract semantic features of ARM NEON instructions containing specific operating modes; wherein, the semantic features include: operand range, overflow or saturation handling strategy, rounding method, pairing or reduction logic, and precision control of output results; The semantic features are encapsulated into instruction templates for operation modes.

[0015] Furthermore, the LLVM IR representation is optimized specifically for the RISC-V vector extension characteristics, including: By traversing and scanning the basic blocks of the objective function at the LLVM IR level, we can identify whether the LLVM IR expression contains short vector operation instructions. When the LLVM IR representation contains short vector operation instructions, perform data flow analysis on the LLVM IR representation to obtain the memory operations of each vector operation instruction; Based on the memory operations, the type consistency, memory continuity, computational semantic similarity, and data dependency among the vector operation instructions are calculated; wherein, type consistency includes checking whether the data types of the source vector and the target vector are the same, memory continuity checks whether the source operands come from contiguous or aligned memory regions, computational semantic similarity checks whether they are the same or equivalent operations, and data dependency checks whether there are no cross-instruction conflicts. Based on type consistency, memory continuity, computational semantic similarity, and data dependency, determine whether at least two vector operation instructions should be merged, and obtain the merged LLVM IR representation. Based on the obtained merged LLVM IR representation, the process of traversing and scanning the basic blocks of the objective function at the LLVM IR level is re-executed until the merged LLVM IR representation does not contain short vector operation instructions.

[0016] An assembly code translation system from ARM NEON to RISC-V vector extension, the system comprising: An instruction booster is used to boost ARM NEON instructions into equivalent LLVMIR expressions using pre-designed mapping rules; An intermediate optimizer is used for general intermediate code optimization of LLVM IR representations and specialized optimizations for RISC-V vector extension features; The LLVM backend is used to reduce the optimized LLVM IR to target code for the RISC-V vector extension platform.

[0017] An electronic device includes: a processor and a memory storing computer program instructions; the processor, when executing the computer program instructions, implements the assembly code translation method for ARMNEON to RISC-V vector extension based on the LLVM compilation framework as described above.

[0018] A computer-readable storage medium, characterized in that the computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the assembly code translation method for ARM NEON to RISC-V vector extension as described above.

[0019] A computer program product, characterized in that, when the computer program product is run on a computer device, it causes the computer device to execute the assembly code translation method for ARM NEON to RISC-V vector extension as described above.

[0020] Compared with the prior art, the present invention has at least the following beneficial effects.

[0021] This invention can reuse the powerful intermediate representation LLVM IR to express semantically complex vector operations, and use the LLVM optimizer to perform optimizations such as intermediate redundancy elimination and dead code removal.

[0022] This invention uses the LLVM compiler to automatically build.<ARM NEON, LLVM IR> Mapping rules. On the one hand, automated construction of mapping rules can effectively reduce manual development workload; on the other hand, the process of upgrading from ARM NEON assembly to LLVM IR is essentially the reverse process of LLVM compiler backend instruction generation, and the mapping rules constructed in this way...<ARM NEON, LLVMIR> Mapping rules not only ensure semantic correctness, but also help LLVM to generate instructions efficiently.

[0023] The operation mode-based mapping rule generalization of the present invention can learn more rules from a limited training program, effectively improving instruction coverage and reducing learning costs.

[0024] This invention uses data flow analysis technology to detect short vector operations and their corresponding memory load operations in LLVM IR, and determines whether they can be merged into long vector operations. This allows multiple short vector operations to be merged into one long vector operation, thereby utilizing the register grouping feature of RISC-V vector extension instructions to achieve more efficient parallel computing. Attached Figure Description

[0025] Figure 1 System architecture diagram.

[0026] Figure 2 Mapping rules based on LLVM are automatically constructed.

[0027] Figure 3 Flowchart of LLVM optimization method. Detailed Implementation

[0028] To make the objectives, features, and advantages of this invention more apparent and understandable, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0029] This system mainly consists of three core modules: an instruction booster, an intermediate optimizer, and an LLVM backend. Figure 1 The overall system architecture diagram is shown.

[0030] I. Instruction Lifter.

[0031] The input is an ARM NEON assembly program. First, it identifies and parses ARM NEON instructions. Then, it uses pre-designed efficient mapping rules to accurately elevate ARM NEON instructions into equivalent LLVM IR expressions. This module contains two components: automatic construction of LLVM-based mapping rules and generalization of mapping rules.

[0032] Mapping rules based on LLVM are automatically constructed.

[0033] The process of this module is as follows: Figure 2 As shown, the specific steps are as follows: First, the target C++ source code is compiled, generating ARM NEON format assembly code and LLVM IR code respectively. During compilation, the -g option is enabled to preserve line numbers and variable information in the source code. Specifically, clang++ -Sg -march=armv8-a+simd is used to obtain the ARM NEON code, and clang++ -S -emit-llvm -g is used to obtain the LLVM IR code.

[0034] Then, the script is used to parse the .loc tags in the ARM NEON code and the !dbg metadata in the LLVM IR file, thereby extracting the ARM NEON and LLVM IR fragments corresponding to the same source code line and establishing a structured mapping relationship between line numbers, ARM NEON instructions and LLVM IR fragments.

[0035] After extracting the fragments, the ARM NEON and LLVM IR instruction fragments corresponding to the same source code lines are reconstructed into small verification codes. After being compiled and executed independently, they are verified to produce the same calculation results for the same input, thereby determining the equivalence between the two.

[0036] Finally, the verified fragments and their mapping relationships between ARM NEON instructions and LLVM IR sequences are entered into the mapping rule base.

[0037] 1.2 Generalization of mapping rules.

[0038] For ARM NEON instructions with pre-defined mapping rules, their operational characteristics are analyzed to identify instruction types containing specific operational modes, including but not limited to Q (saturation mode), H (halving mode), D (doubling mode), R (rounding mode), P (pairing mode), and V (reduction mode). For instructions containing these operational modes, their corresponding semantic features are extracted, including operand range, overflow or saturation handling strategies, rounding methods, pairing or reduction logic, and precision control of the output result. After extracting the semantic features of the operational modes, they are encapsulated into instruction templates for those modes.

[0039] II. Intermediate Optimizer.

[0040] It is responsible for further optimizing the LLVM IR generated by the instruction booster. The method includes two parts: general intermediate code optimization and special optimization for RISC-V vector extension features.

[0041] General intermediate code optimization includes intermediate redundancy elimination and dead code elimination, which reuses the optimizer in the LLVM compiler.

[0042] Dedicated optimizations based on RISC-V vector extensions include register allocation optimization based on the grouping characteristics of vector extension registers. This involves analyzing the length, type, and data dependencies of vector operations to rationally group vector registers and optimize register utilization. For example... Figure 3 As shown, the dedicated optimizations for RISC-V vector extension features include the following steps.

[0043] First, the basic blocks of the objective function are traversed and scanned at the LLVM IR level to identify short vector operations with an operation width of 128 bits. Arithmetic and logical operation instructions are extracted, including but not limited to floating-point addition (fadd) and floating-point multiplication (fmul), and detection tags are established.

[0044] Then, for the marked short vector operations, data flow analysis is performed using the Static Single Assignment (SSA) structure provided by the LLVM framework to determine the data source of each vector operation instruction and track the corresponding vector loading operations.

[0045] Subsequently, the vector merging conditions are determined from multiple dimensions, including type consistency, memory continuity, computational semantic similarity, and data dependency. Type consistency includes checking whether the data types of the source and target vectors are the same. Memory continuity checks whether the source operands come from contiguous or aligned memory regions. Computational semantic similarity checks whether they are the same or equivalent operations. Data dependency checks whether there are no cross-instruction conflicts. If the detection results show that all conditions are met, the corresponding marked instructions are merged to generate optimized vector operation code. If the detection results show that some conditions are not met, the current merging operation is abandoned, and step (1) is returned to continue detecting and marking subsequent IR instructions until all basic blocks are traversed.

[0046] III. LLVM Backend.

[0047] It reuses the RISC-V backend of the LLVM compiler, which is responsible for reducing the optimized LLVM IR to target code for the RISC-V Vector Extensions platform.

[0048] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the principles and scope of the present invention. The protection scope of the present invention should be determined by the claims.

Claims

1. A method for translating assembly code from ARM NEON to RISC-V vector extension, characterized in that, The method includes: By using pre-designed mapping rules, ARM NEON instructions are elevated to equivalent LLVM IR expressions; General intermediate code optimization and special optimization for RISC-V vector extension features are performed on the LLVM IR representation. The optimized LLVM IR is demoted to target code for the RISC-V Vector Extensions platform.

2. The method according to claim 1, characterized in that, The process of constructing the mapping rules includes: The target C++ source code is compiled to generate ARM NEON code and LLVM IR code respectively; during the compilation process, the -g option is enabled to preserve the line numbers and variable information of the target C++ source code; The .loc tags in the ARM NEON code and the !dbg metadata in the LLVM IR code are parsed to extract the ARM NEON code snippets and LLVM IR code snippets corresponding to the same source code lines in the target C++ source code, and to establish a structured mapping relationship between line numbers, ARM NEON code snippets and LLVM IR code snippets; Reconstruct the ARM NEON code snippet and the LLVM IR code snippet corresponding to the same source code line into small verification code, and verify the equivalence of the ARM NEON code snippet and the LLVM IR code snippet; When ARM NEON code snippets and LLVM IR code snippets are equivalent, the ARM NEON code snippet, the LLVM IR code snippet, and the structured mapping relationship are treated as a single mapping rule and entered into the mapping rule library. Generalize the mapping rules in the mapping rule base.

3. The method according to claim 2, characterized in that, The generation of ARM NEON code and LLVM IR code includes: Use the command clang++ -S -g -march=armv8-a+simd to obtain the ARM NEON code; Use the command clang++ -S -emit-llvm -g to obtain the LLVM IR code.

4. The method according to claim 2, characterized in that, Verify the equivalence of the ARM NEON code snippet and the LLVM IR code snippet, including: The ARM NEON code snippet and the LLVM IR code snippet were compiled independently to obtain the first program and the second program; Input the same input information into the first program and the second program respectively, and determine whether the first program and the second program output the same result; If the first and second programs output the same result, the ARM NEON code snippet and the LLVM IR code snippet are considered equivalent.

5. The method according to claim 2, characterized in that, The generalization of mapping rules in the mapping rule base includes: The operational characteristics of ARM NEON code snippets are analyzed to identify ARM NEON instructions containing specific operational modes; wherein, the specific operational modes include: saturation operation mode, halving operation mode, doubling operation mode, rounding mode, pairing mode, and reduction mode; Extract semantic features of ARM NEON instructions containing specific operating modes; wherein, the semantic features include: operand range, overflow or saturation handling strategy, rounding method, pairing or reduction logic, and precision control of output results; The semantic features are encapsulated into instruction templates for operation modes.

6. The method according to claim 1, characterized in that, Specific optimizations for the LLVM IR representation to accommodate RISC-V vector extension features include: By traversing and scanning the basic blocks of the objective function at the LLVM IR level, we can identify whether the LLVM IR expression contains short vector operation instructions. When the LLVM IR representation contains short vector operation instructions, perform data flow analysis on the LLVM IR representation to obtain the memory operations of each vector operation instruction; Based on the memory operations, the type consistency, memory continuity, computational semantic similarity, and data dependency among the vector operation instructions are calculated; wherein, type consistency includes checking whether the data types of the source vector and the target vector are the same, memory continuity checks whether the source operands come from contiguous or aligned memory regions, computational semantic similarity checks whether they are the same or equivalent operations, and data dependency checks whether there are no cross-instruction conflicts. Based on type consistency, memory continuity, computational semantic similarity, and data dependency, determine whether at least two vector operation instructions should be merged, and obtain the merged LLVM IR representation. Based on the obtained merged LLVM IR representation, the process of traversing and scanning the basic blocks of the objective function at the LLVM IR level is re-executed until the merged LLVM IR representation does not contain short vector operation instructions.

7. An assembly code translation system from ARM NEON to RISC-V vector extension, characterized in that, The system includes: An instruction booster is used to boost ARM NEON instructions into equivalent LLVM IR expressions using pre-designed mapping rules; An intermediate optimizer is used for general intermediate code optimization of LLVM IR representations and specialized optimizations for RISC-V vector extension features; The LLVM backend is used to reduce the optimized LLVM IR to target code for the RISC-V vector extension platform.

8. An electronic device, characterized in that, The electronic device includes: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, it implements the assembly code translation method for ARMNEON to RISC-V vector extension as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the assembly code translation method for ARMNEON to RISC-V vector extension as described in any one of claims 1-6.

10. A computer program product, characterized in that, When the computer program product is run on a computer device, the computer device performs the assembly code translation method for ARM NEON to RISC-V vector extension as described in any one of claims 1-6.

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