Integrated circuit and wake-up recovery method thereof

Abstract

The invention discloses an integrated circuit and a wake-up recovery method thereof, and the method comprises the steps: receiving a sleep signal through a direct access unit in the integrated circuit under the condition that at least one peripheral unit in the integrated circuit is powered on; in response to the sleep signal, the first configuration value is read from the first configuration register through the direct access unit before the at least one peripheral unit is powered off, and the first configuration value is stored in the internal storage unit; under the condition that the at least one peripheral unit is powered off, receiving a wake-up signal through the direct access unit; and in response to the wake-up signal, after the at least one peripheral unit is powered on, reading the at least one first configuration value from the memory unit through the direct access unit, and respectively writing the first configuration value into the corresponding first configuration register so as to recover the at least one peripheral unit. According to the scheme, the CPU does not need to participate in the configuration value reading and writing operation of the peripheral, and the configuration recovery of the sleep wake-up process can be completed only through the hardware-level direct access unit, so that the configuration consistency before and after the peripheral is powered off is ensured.

Description

Technical Field

[0001] This disclosure relates to integrated circuits, and more specifically to an integrated circuit and a wake-up recovery method thereof. Background Technology

[0002] When the chip is in sleep mode, the configuration registers of the peripheral units within the chip will revert to their default values ​​when the chip is powered off. When waking the chip from sleep mode, the values ​​of the configuration registers need to be restored to ensure that the peripheral units function normally afterward.

[0003] In related technologies, during the process of waking up the startup chip, the processor, such as the central processing unit (CPU), initializes the configuration registers of the peripheral unit. However, it cannot be guaranteed that the value of the configuration register of the peripheral unit after waking up is consistent with the value of the configuration register before hibernation.

[0004] Therefore, a wake-up method is urgently needed to ensure that the configuration values ​​of the peripheral unit are restored to their state before hibernation after wake-up. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides an integrated circuit and its wake-up recovery method, which ensures that the value of the configuration register of the peripheral unit after wake-up is consistent with the value of the configuration register before hibernation.

[0006] In one aspect, a wake-up recovery method for an integrated circuit is provided, the method comprising:

[0007] When at least one peripheral unit in the integrated circuit is powered on, a sleep signal is received through the direct access unit in the integrated circuit.

[0008] In response to the sleep signal, before the at least one peripheral unit is powered down, the first configuration value is read from the first configuration register of each peripheral unit through the direct access unit, and at least one of the first configuration values ​​is stored in the memory unit of the integrated circuit; wherein, the first configuration value of the first configuration register is the configuration value of the first configuration register before the peripheral unit is powered down;

[0009] When at least one peripheral unit in the integrated circuit is powered down, a wake-up signal is received through the direct access unit;

[0010] In response to the wake-up signal, after the at least one peripheral unit is powered on, at least one of the first configuration values ​​is read from the memory unit through the direct access unit, and the at least one of the first configuration values ​​read is written into the corresponding first configuration registers to restore the at least one peripheral unit.

[0011] In another aspect, an integrated circuit is provided, comprising: at least one peripheral unit, a direct access unit, and a memory unit; wherein,

[0012] The direct access unit is configured to receive a sleep signal when at least one peripheral unit is powered on; and in response to the sleep signal, before the at least one peripheral unit is powered off, read a first configuration value from the first configuration register of each peripheral unit, and store at least one of the first configuration values ​​in the memory unit; wherein the first configuration value of the first configuration register is the configuration value of the first configuration register before the peripheral unit is powered off.

[0013] The memory unit is used to store the first configuration value of the first configuration register of each of the peripheral units;

[0014] The direct access unit is further configured to receive a wake-up signal when the at least one peripheral unit is powered down; and in response to the wake-up signal, read at least one of the first configuration values ​​from the memory unit after the at least one peripheral unit is powered on; and write the at least one of the first configuration values ​​read into the corresponding first configuration registers to restore the at least one peripheral unit.

[0015] In another aspect, embodiments of this disclosure provide a computer program product that, when an instruction processor in the computer program product is executed, performs the wake-up and recovery method for integrated circuits proposed in the above embodiments.

[0016] In another aspect, embodiments of this disclosure provide an electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the wake-up recovery method for an integrated circuit as described above; or, the electronic device comprising the integrated circuit described in the above embodiments.

[0017] The technical solution provided in this disclosure, when a peripheral in an integrated circuit is powered on, responds to a received sleep signal and, before the peripheral is powered off, reads the configuration value from the configuration register of each peripheral through a direct access unit and stores it in a memory unit that is not lost upon power-off. Since the valid configuration of the peripheral before power-off is pre-stored in the memory unit, when the peripheral is powered off, responding to a received wake-up signal, the configuration value of the configuration register of each peripheral is read from the memory unit through the direct access unit and then written back to the configuration register of each peripheral, thereby ensuring that all peripherals are restored to the same configuration before power-off. Thus, this solution eliminates the need for the CPU to participate in the reading and writing of peripheral configuration values; the configuration recovery process of the sleep-wake-up procedure can be completed solely through the hardware-level direct access unit, ensuring configuration consistency before and after peripheral power-off. Furthermore, compared to traditional technologies that restore configuration through the processor, this solution directly wakes up and restores the configuration of each peripheral through a dedicated DMA controller, improving the efficiency of saving and restoring a large number of peripheral registers. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of an integrated circuit provided in an exemplary embodiment of this disclosure.

[0019] Figure 2 This is a schematic flowchart of a wake-up recovery method for an integrated circuit provided in an exemplary embodiment of this disclosure.

[0020] Figure 3 This is a flowchart illustrating a wake-up recovery method for an integrated circuit provided in another exemplary embodiment of this disclosure.

[0021] Figure 4 This is a flowchart illustrating a wake-up recovery method for an integrated circuit provided in another exemplary embodiment of this disclosure.

[0022] Figure 5 This is a flowchart illustrating a wake-up recovery method for an integrated circuit provided in yet another exemplary embodiment of this disclosure.

[0023] Figure 6 This is a flowchart illustrating a wake-up recovery method for an integrated circuit provided in yet another exemplary embodiment of this disclosure.

[0024] Figure 7 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0025] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0026] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0027] Application Overview

[0028] As mentioned earlier, the relevant technology cannot guarantee that the value of the configuration register of the peripheral unit after wake-up is consistent with the value of the configuration register before hibernation during the process of waking up the startup chip.

[0029] The applicant discovered that, in order to solve the above problems, related technologies also involve a processor, such as a CPU, saving the configuration values ​​of peripheral registers to non-volatile memory before hibernation. Upon wake-up, the saved configuration values ​​are rewritten from this memory to the corresponding peripheral registers. However, with the development of integrated circuits, their scale has become increasingly larger, resulting in a large number of peripheral units within them. Consequently, upon wake-up, a large number of peripheral registers need to be reconfigured. Since the CPU has many tasks to schedule, saving and restoring thousands of registers through the CPU significantly reduces the chip's wake-up speed.

[0030] Based on the aforementioned technical problems, the technical solution provided in this disclosure, when a peripheral device in an integrated circuit is powered on, responds to a received sleep signal and, before the peripheral device is powered off, reads the configuration value from the configuration register of each peripheral device via a Direct Memory Access (DMA) unit and stores it in a memory unit that is not lost upon power-off. Since the valid configuration of the peripheral device before power-off is pre-stored in the memory unit, when the peripheral device is powered off, responds to a received wake-up signal and reads the configuration value of each peripheral device's configuration register from the memory unit via the DMA unit and writes it back to the configuration register of each peripheral device, thereby ensuring that all peripheral devices are restored to the same configuration before power-off. Thus, this solution eliminates the need for the CPU to participate in the peripheral device configuration value reading and writing operations; the configuration recovery of the sleep-wake process can be completed solely through the hardware-level DMA unit, ensuring configuration consistency before and after peripheral device power-off.

[0031] Moreover, compared to traditional technologies that restore configurations through the processor, this case directly wakes up and restores the configurations of each peripheral device through a dedicated DMA controller, which improves the efficiency of saving and restoring a large number of peripheral registers.

[0032] Exemplary System

[0033] Figure 1 This is a schematic diagram of the structure of an integrated circuit provided in an exemplary embodiment of this disclosure.

[0034] For example, such as Figure 1As shown, the integrated circuit described above may include at least one peripheral unit 100, a direct access unit 200, and a memory unit 300.

[0035] The direct access unit 200 can be used to receive a sleep signal when at least one peripheral unit is powered on; and in response to the sleep signal, before at least one peripheral unit is powered off, read a first configuration value from the first configuration register of each peripheral unit and store at least one first configuration value in a memory unit; wherein the first configuration value of the first configuration register is the configuration value of the first configuration register before the peripheral unit is powered off.

[0036] In some embodiments, the direct access unit 200 is an independent hardware circuit module in the integrated circuit. The direct access unit does not directly reuse the original DMA controller in the integrated circuit, but is a dedicated DMA controller designed for the integrated circuit. The direct access unit is used to restore the peripheral units in the integrated circuit without the involvement of the processor.

[0037] For example, such as Figure 1 As shown, the integrated circuit includes N peripheral units, each peripheral unit including a first configuration register, that is, the integrated circuit includes N first configuration registers, which are Register 0 to Register(N-1). When the direct access unit responds to the received sleep signal, before the N peripheral units are powered down, the first configuration value can be read from Register 0 to Register(N-1) respectively.

[0038] In some embodiments, the direct access unit 200 includes at least one second configuration register and a third configuration register; wherein, the at least one second configuration register is used to configure the register address of the corresponding first configuration register, and the third configuration register is used to configure the target base address of at least one first configuration value stored in the memory unit.

[0039] For example, such as Figure 1 As shown, the direct access unit 200 includes at least one second configuration register, namely ModuleRegister 0 to Module Register (N-1), and the direct access unit 200 includes a third configuration register, MemoryAddress Base.

[0040] In some embodiments, the direct access unit 200 may be specifically configured to: determine the target configuration order of the first configuration registers of each peripheral unit; wherein the target configuration order is used to indicate the correspondence between at least one second configuration register and at least one first configuration register of the direct access unit; determine the register address of the first configuration register of each peripheral unit; and, based on at least one register address, read the first configuration value from the first configuration register corresponding to each register address in accordance with the target configuration order through the direct access unit.

[0041] In some embodiments, the direct access unit 200 may also be specifically used to: determine at least one target storage address corresponding to at least one first configuration value in the address space of the memory unit; and store the first configuration values ​​of the first configuration registers of each peripheral unit read by the direct access unit at the target storage addresses corresponding to the at least one target storage address.

[0042] Memory unit 300 can be used to store the first configuration value of the first configuration register of each peripheral unit.

[0043] For example, the memory unit 300 is a non-volatile memory, that is, after the system is powered off, the first configuration values ​​of the first configuration registers of each peripheral unit stored in the memory unit 300 will not be lost.

[0044] For example, such as Figure 1 As shown, the address space of memory unit 300 includes N target storage addresses, which are Address Base, Address Base+1*(0x4), ... Address Base+(N-1)*(0x4), respectively. That is, the first configuration value of the first configuration register of each peripheral unit is stored in the above N target storage addresses of the memory unit.

[0045] The direct access unit 200 can also be used to receive a wake-up signal when at least one peripheral unit is powered down; and in response to the wake-up signal, to read at least one first configuration value from a memory unit after at least one peripheral unit is powered on; and to write the read at least one first configuration value into a corresponding first configuration register to restore at least one peripheral unit.

[0046] In some embodiments, the direct access unit 200 may also be specifically used to: determine at least one target storage address corresponding to at least one first configuration value in the address space of the memory unit; and read the first configuration value of the first configuration register of each peripheral unit from the at least one target storage address through the direct access unit.

[0047] In some embodiments, the direct access unit 200 may also be specifically used to: determine a target base address based on a third configuration value of a third configuration register of the direct access unit; determine an address offset corresponding to a first configuration register of each peripheral unit based on an index of a first configuration register of each peripheral unit; and determine at least one target storage address corresponding to at least one first configuration value based on the target base address and the corresponding address offset.

[0048] In some embodiments, the direct access unit 200 may be specifically used to: determine the register address of the first configuration register of each peripheral unit; and, based on at least one register address, write at least one first configuration value read by the direct access unit into the first configuration register corresponding to each register address.

[0049] In some embodiments, the direct access unit 200 may further be specifically configured to: determine a second configuration value of at least one second configuration register of the direct access unit; wherein the second configuration value is the register address of the first configuration register; determine a target configuration order of the first configuration registers of each peripheral unit; wherein the target configuration order is used to indicate the correspondence between at least one second configuration register and at least one first configuration register; and determine the register address of the first configuration register of each peripheral unit based on the target configuration order and the second configuration value of at least one second configuration register.

[0050] In some embodiments, the direct access unit 200 may also be specifically used to: determine the arrangement order of at least one second configuration register; determine the first configuration register corresponding to each second configuration register based on the target configuration order; and, through the direct access unit, sequentially write at least one first configuration value read into the first configuration register corresponding to each second configuration register according to the arrangement order of at least one second configuration register.

[0051] For example, consider a 32-bit peripheral register. Before each peripheral unit goes to sleep, the value of Register 0 is written to the memory location at Address Base. Since each 32-bit register occupies 4 bytes, the value of Register 1 is written to the memory location at Address Base + 1 * (0x4), and so on, until the value of Register (N-1) is written to the memory location at Address Base + (N-1) * (0x4).

[0052] During the sleep-wake process, the Direct Access DMA (DMA) unit can start moving data from the base address of the memory cell that is not lost when power is off. After each peripheral unit wakes up, the value at address Base in the memory cell is written to peripheral register Register 0 filled in Module Register 0, and the value at address Base+1*(0x4) in the memory cell is written to peripheral register Register 1 filled in Module Register 1, and so on, until the value at address Base+(N-1)*(0x4) in the memory cell is written to peripheral register Register (N-1) filled in Module Register (N-1).

[0053] In other embodiments, the integrated circuit may further include a hardware firewall. The hardware firewall unit detects the identifier of the direct access unit. When the identifier of the direct access unit matches a pre-stored identifier, the direct access unit is allowed to access the memory unit 300. Thus, the memory unit 300, which is not lost when power is off, can be securely managed through the hardware firewall, allowing only the direct access unit 200 in this solution to access it, while disallowing other DMA access, thereby ensuring data security.

[0054] For a detailed description of the above embodiments, please refer to the detailed description in the following method embodiments. The embodiments disclosed herein will not be repeated here.

[0055] The technical solution provided in this disclosure, when a peripheral in an integrated circuit is powered on, responds to a received sleep signal and, before the peripheral is powered off, reads the configuration value from the configuration register of each peripheral through a direct access unit and stores it in a memory unit that is not lost upon power-off. Since the valid configuration of the peripheral before power-off is pre-stored in the memory unit, when the peripheral is powered off, responding to a received wake-up signal, the configuration value of the configuration register of each peripheral is read from the memory unit through the direct access unit and written back to the configuration register of each peripheral, thereby ensuring that all peripherals are restored to the same configuration before power-off. Thus, this solution eliminates the need for the CPU to participate in the reading and writing of peripheral configuration values; the configuration recovery process of the sleep-wake-up procedure can be completed solely through the hardware-level direct access unit, ensuring configuration consistency before and after peripheral power-off, thereby enhancing the functional safety and reliability of the chip. Furthermore, compared to traditional technologies that restore configuration through the processor, this solution directly wakes up and restores the configuration of each peripheral through a dedicated DMA controller, improving the efficiency of saving and restoring a large number of peripheral registers.

[0056] Exemplary methods

[0057] Figure 2This is a schematic flowchart of a wake-up recovery method for an integrated circuit provided in an exemplary embodiment of this disclosure. This embodiment can be applied to the above-described... Figure 1 The integrated circuit shown, or applied to the above-mentioned... Figure 1 The integrated circuit shown is used in electronic devices (e.g., vehicles), such as... Figure 2 As shown, the above method may include the following steps:

[0058] Step 201: When at least one peripheral unit in the integrated circuit is powered on, a sleep signal is received through the direct access unit in the integrated circuit.

[0059] In some embodiments, the integrated circuit described above can be a system-on-a-chip (SOC), for example, an integrated cockpit-drone chip or an intelligent driving chip. The integrated circuit may include at least one peripheral unit and a direct access unit; the embodiments of this disclosure do not limit the number of peripheral units and direct access units included in the integrated circuit.

[0060] In some embodiments, the at least one peripheral unit may be a hardware circuit unit with a specific function. The functions of the at least one peripheral unit may be the same or different, and the at least one peripheral unit may be all the peripheral units in the integrated circuit; or it may be a portion of the peripheral units in the integrated circuit, which may be any portion of the peripheral units or a specific peripheral unit among all the peripheral units in the integrated circuit. The specific details can be determined according to actual use, and the embodiments disclosed herein do not limit this.

[0061] For example, based on different functional requirements, the integrated circuit may include peripheral units with different functions. For instance, at least one of the aforementioned peripheral units may include pins and clocks, etc.

[0062] In some embodiments, the Direct Memory Access (DMA) unit is an independent hardware circuit module in the integrated circuit. The DMA unit does not directly reuse the original DMA controller in the integrated circuit, but is a dedicated DMA controller designed for the integrated circuit. The DMA unit is used to restore the peripheral units in the integrated circuit without the participation of the Central Processing Unit (CPU).

[0063] In some examples, the aforementioned suspend signal is used to trigger a system hibernation save process to save the configuration of each peripheral unit. This suspend signal can be an interrupt signal triggered by the CPU in the integrated circuit, or a signal triggered by an external pin of the integrated circuit. For example, an external device setting the level of a pin of the integrated circuit to a low level triggers a suspend signal. Alternatively, a suspend signal may be generated when the device is forcibly shut down, or the system may automatically generate a suspend signal. Of course, the suspend signal can also have other sources, and this disclosure does not limit this.

[0064] In some embodiments, powering on at least one peripheral unit can be understood as at least one peripheral unit being in a normal working or idle state; when at least one peripheral unit is powered on, if a hibernation signal is generated, the hibernation signal can be received through the direct access unit and the system hibernation save process can be triggered, i.e., the following step 202 is executed.

[0065] Step 202: In response to the sleep signal, before at least one peripheral unit is powered down, a first configuration value is read from the first configuration register of each peripheral unit through the direct access unit, and at least one first configuration value is stored in the memory cell of the integrated circuit.

[0066] The first configuration value of the first configuration register is the configuration value of the first configuration register before the peripheral unit is powered down.

[0067] In some examples, the first configuration register of the aforementioned peripheral unit is used to configure the peripheral unit. Therefore, the first configuration register is a register that stores the core configuration of the peripheral unit, and not other registers used to store data to be transmitted or received data. The first configuration value in the first configuration register is the last set of valid configuration parameters before the peripheral unit is powered down. That is to say, the Direct Access Unit (DMA) in the embodiments of this disclosure is used to move the configuration values ​​of the configuration register of the peripheral unit, and not to move the data stored in the data register of the peripheral unit.

[0068] For example, if the peripheral unit is a general-purpose input / output pin (GPIO), the first configuration register of the GPIO pin is the direction register of the GPIO. This direction register is used to configure the data transmission direction of the GPIO pin, that is, the first configuration value is the data transmission direction. As another example, if the peripheral unit is a clock peripheral, the first configuration register of the clock peripheral is a frequency register. This frequency register is used to configure the frequency of the clock peripheral, that is, the first configuration value is the frequency.

[0069] In some examples, the memory cells described above are non-volatile memory (NVM) that is not lost when power is off. For example, the memory cells can be flash memory.

[0070] In some embodiments, the direct access unit can interact with each peripheral unit via an on-chip bus. In response to a sleep signal, the direct access unit accesses the first configuration register of each peripheral unit one by one according to the register address of the first configuration register of each peripheral unit, so as to read the first configuration value from the first configuration register of each peripheral unit, and then writes all the first configuration values ​​into a pre-allocated storage area in non-volatile memory (i.e., memory unit).

[0071] In other embodiments, when the first configuration value in the first configuration register of all peripheral units has been successfully stored in the memory unit, a save completion signal is generated by direct access unit, and at least one peripheral unit is powered down according to the save completion signal, that is, the system enters hibernation.

[0072] Step 203: When at least one peripheral unit in the integrated circuit is powered down, a wake-up signal is received through the direct access unit.

[0073] In some examples, the aforementioned wake-up signal is used to trigger the system wake-up and recovery process to wake up and restore various peripheral units. This wake-up signal can be an interrupt signal triggered by the CPU in the integrated circuit, or a signal triggered by an external pin of the integrated circuit. For example, an external device setting the level of a pin of the integrated circuit to a high level triggers a wake-up signal. Alternatively, a wake-up signal may be generated when the device is forcibly powered on, or the system may automatically generate a wake-up signal. Of course, the wake-up signal can also have other sources, and this disclosure does not limit this.

[0074] In some embodiments, powering down at least one peripheral unit can be understood as turning off the power supply to at least one peripheral unit, at which time at least one peripheral unit is in a sleep state; when at least one peripheral unit is powered down, if a wake-up signal is generated, the wake-up signal can be received through the direct access unit and the system wake-up recovery process can be triggered, that is, the following step 204 is executed.

[0075] Step 204: In response to the wake-up signal, after at least one peripheral unit is powered on, at least one first configuration value is read from the memory unit through the direct access unit, and the read at least one first configuration value is written into the corresponding first configuration register to restore at least one peripheral unit.

[0076] In some embodiments, in response to a wake-up signal, power is supplied to at least one peripheral unit; after the at least one peripheral unit is powered on, it begins operation, accesses the power-off non-loss memory (i.e., memory cell) of the integrated circuit through a direct access unit, reads the first configuration value of each peripheral unit from the memory according to the storage address of at least one first configuration value; according to the register address of the first configuration register of each peripheral unit, writes all the read first configuration values ​​sequentially into the first configuration register of the corresponding peripheral unit through the direct access unit. In this way, at least one peripheral unit can be restored to its configuration before power-off, that is, the configuration of at least one peripheral unit before and after power-off remains consistent, thus solving the problem of configuration loss of peripherals due to power-off.

[0077] The technical solution provided in this disclosure, when a peripheral in an integrated circuit is powered on, responds to a received sleep signal and, before the peripheral is powered off, reads the configuration value from the configuration register of each peripheral via DMA and stores it in a memory unit that is not lost upon power-off. Since the valid configuration of the peripheral before power-off is pre-stored in the memory unit, when the peripheral is powered off, responds to a received wake-up signal and reads the configuration value from the configuration register of each peripheral via DMA and writes it back to the configuration register of each peripheral, thereby ensuring that all peripherals are restored to the same configuration before power-off. Thus, this solution eliminates the need for the CPU to participate in the peripheral configuration value reading and writing operations; the configuration recovery of the sleep-wake process can be completed solely through a hardware-level direct access unit, ensuring configuration consistency before and after peripheral power-off.

[0078] like Figure 3 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 204 above may specifically include the following steps:

[0079] Step 2041: Determine the register address of the first configuration register of each peripheral unit.

[0080] To ensure that at least one first configuration value read is written into the corresponding first configuration register, the register address of the first configuration register of each peripheral unit needs to be determined first; wherein, the register address can be an absolute address, that is, including the base address and the address offset.

[0081] In some embodiments, during the chip design process, developers can pre-assign register addresses to the first configuration registers of each peripheral unit and establish a register mapping table based on the first configuration registers and corresponding register addresses of each peripheral unit. This register mapping table is then pre-stored in a pre-allocated storage area of ​​the integrated circuit's memory cell via software. This pre-allocated storage area can then be accessed through a direct access unit to read the register mapping table, and the register address of the first configuration register of each peripheral unit can be determined based on the register mapping table. Alternatively,

[0082] When the direct access unit includes multiple configuration registers, the register address allocated to the first configuration register of each peripheral unit is written into the multiple configuration registers by software, so that the multiple configuration registers can be directly accessed through the direct access unit to read the register address of the first configuration register of each peripheral unit.

[0083] In some embodiments, where the direct access unit includes multiple configuration registers, step 2041 above may include steps A to C as follows:

[0084] Step A: Determine the second configuration value of at least one second configuration register of the directly accessed unit.

[0085] The second configuration value is the register address of the first configuration register.

[0086] In some embodiments, since the second configuration register is used to configure the register address of the first configuration register, the second configuration value is the register address of the first configuration register. That is, there is a mapping relationship between the first configuration register and the second configuration register. Therefore, in order to determine the register address of the first configuration register, at least one second configuration register of the direct access unit can be directly accessed through the direct access unit to obtain at least one second configuration value, and each second configuration value is determined as the register address of the first configuration register corresponding to the second configuration register. The register address may include a base address and an address offset.

[0087] For example, let's take a direct access unit comprising N second configuration registers as an example. Assume the N second configuration registers are Module Register 0 to Module Register (N-1). During integrated circuit initialization configuration, the register addresses of peripheral registers that need to be automatically saved and restored during sleep / wake-up can be pre-written into Module Register 0 to Module Register (N-1) via software. If each peripheral register is 32 bits, and the register addresses of N peripheral registers need to be filled, with each 32-bit peripheral register occupying 4 bytes, the register addresses of N peripheral registers will occupy a total of 4N bytes.

[0088] Step B: Determine the target configuration order of the first configuration registers of each peripheral unit.

[0089] The target configuration order is used to indicate the correspondence between at least one second configuration register and at least one first configuration register.

[0090] In some embodiments, one possible approach is to write the register addresses of the corresponding first configuration registers into at least one second configuration register in ascending order of the indices of the first configuration registers of each peripheral unit. That is, a first configuration register with a smaller index value corresponds to a second configuration register with a smaller index value, and vice versa. In other words, the target configuration order refers to configuring the first configuration registers of each peripheral unit in order of their index values. Another possible approach is to write the register addresses of the corresponding first configuration registers into at least one second configuration register based on preset rules, such as the priority or type of each peripheral unit. In this case, the target configuration order is a non-sequential configuration of the first configuration registers of each peripheral unit.

[0091] In some embodiments, if the target configuration order is to configure the first configuration registers of each peripheral unit in order of index value size, the target configuration order can be determined directly according to the arrangement order of at least one second configuration register in the direct access unit; if the target configuration order is to configure the first configuration registers of each peripheral unit in a non-sequential manner, a mapping table of correspondence between at least one second configuration register and at least one first configuration register is established in advance and stored in a pre-allocated memory area, so that the target configuration order of the first configuration registers of each peripheral unit can be determined by reading the mapping table through software.

[0092] For example, consider at least one first configuration register including Register 0 and Register 1, and at least one second configuration register including Module Register 0 and Module Register 1. If the target configuration order is to configure the first configuration registers of each peripheral unit according to the index value, then Register 0 corresponds to Module Register 0, and Register 1 corresponds to Module Register 1; if the target configuration order is to configure the first configuration registers of each peripheral unit in a non-sequential manner, then Register 0 corresponds to Module Register 1, and Register 1 corresponds to Module Register 0.

[0093] Step C: Based on the target configuration order and the second configuration value of at least one second configuration register, determine the register address of the first configuration register of each peripheral unit.

[0094] In some embodiments, since the first configuration register corresponding to each second configuration register can be determined based on the target configuration order, after reading the second configuration value of the current second configuration register, the second configuration value can be used as the register address of the first configuration register corresponding to the current second configuration register.

[0095] For example, consider the first configuration registers of peripheral units configured in the order of their index values. Assume that at least one first configuration register includes Register 0 and Register 1, and at least one second configuration register includes Module Register 0 and Module Register 1. Based on the order of their index values, it can be determined that Register 0 corresponds to Module Register 0, and Register 1 corresponds to Module Register 1. Therefore, the second configuration value of Module Register 0 can be determined as the register address of Register 0, and the second configuration value of Module Register 1 can be determined as the register address of Register 1.

[0096] Based on the above embodiments, since the second configuration value of at least one second configuration register of the direct access unit can be determined, and the target configuration order of the first configuration registers of each peripheral unit can be determined, the register address of the first configuration register of each peripheral unit can be determined based on the target configuration order and the second configuration value of at least one second configuration register. That is, on the one hand, compared to the traditional solution where the register addresses of peripheral registers need to be stored in memory through a distributed mapping table, this solution reduces memory usage by storing address information through the second configuration register of the direct access unit; on the other hand, the target configuration order allows for flexible configuration of the second configuration registers to dynamically adapt to different scenarios, thereby accurately determining the register address of each peripheral register based on the configuration of the second configuration register.

[0097] Step 2042: Based on at least one register address, the at least one first configuration value read is written into the first configuration register corresponding to each register address through the direct access unit.

[0098] In some embodiments, since a register address is a unique identifier for a register in memory space—that is, a register address is used to precisely locate a register in the system address space—the register corresponding to a register address can only be accessed through the register address. The aforementioned at least one register address is used to identify at least one corresponding first configuration register. Therefore, when at least one first configuration value needs to be written to at least one first configuration register, the at least one first configuration register to be accessed is determined based on at least one register address. Thus, through the direct access unit, the at least one first configuration value read is written to the first configuration register corresponding to each register address.

[0099] In some embodiments, step 2042 may specifically include: determining the arrangement order of at least one second configuration register; determining the first configuration register corresponding to each second configuration register based on the target configuration order; and writing at least one first configuration value read into the first configuration register corresponding to each second configuration register in sequence according to the arrangement order of at least one second configuration register through the direct access unit.

[0100] In some embodiments, the arrangement order of at least one second configuration register can be determined according to the descending index order of at least one second configuration register, that is, the descending index order of at least one second configuration register is determined as the arrangement order of at least one second configuration register.

[0101] In some embodiments, after determining the arrangement order of at least one second configuration register, the first configuration register corresponding to each second configuration register is determined based on the correspondence between the at least one second configuration register and the at least one first configuration register indicated by the target configuration order. This allows the order in which the direct access unit performs write operations on the first configuration registers corresponding to each second configuration register to be determined according to the arrangement order of the at least one second configuration register. Furthermore, the direct access unit writes at least one read first configuration value to the first configuration register corresponding to each second configuration register according to the order of the write operations. That is, the earlier a second configuration register is listed, the earlier the first configuration value is written to its corresponding first configuration register; the later a second configuration register is listed, the later the first configuration value is written to its corresponding first configuration register. In this way, the wake-up and recovery of each peripheral device can be achieved in an orderly manner.

[0102] For example, assume that at least one first configuration register includes register A and register B, and at least one second configuration register of the direct access unit includes register C and register D. Register C corresponds to register A, and register D corresponds to register B, based on the target configuration order. If register C is arranged before register D, it is determined that the write operation to register A (corresponding to register C) is performed first, followed by the write operation to register B (corresponding to register D). Thus, after reading the first configuration values ​​of registers A and B, the first configuration value of register A is written to register A first, and then the first configuration value of register B is written to register B. It should be noted that when performing write operations on registers A and B respectively, the first configuration values ​​are written to registers A and B sequentially according to their respective register addresses.

[0103] The technical solution provided in this disclosure can determine the register address of the first configuration register of each peripheral unit. Therefore, based on at least one register address, at least one first configuration value read can be written into the first configuration register corresponding to each register address through the direct access unit. This can accurately write at least one first configuration value read into the corresponding first configuration register, thus avoiding writing the first configuration value into the wrong register. Therefore, it can ensure that the peripheral is restored to the configuration before the order was placed after being woken up.

[0104] like Figure 4 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 204 may further include the following steps:

[0105] Step 2043: Determine at least one target storage address in the address space of the memory unit that corresponds to at least one first configuration value.

[0106] In some embodiments, the at least one target storage address is a storage address used to store at least one first configuration value. A corresponding storage address can be pre-assigned to each first configuration value, and a mapping relationship between each first configuration value and its corresponding storage address can be stored. This mapping relationship can then be read by software to determine at least one target storage address corresponding to at least one first configuration value. Alternatively, if the direct access unit includes a register for storing a base address, the at least one target storage address corresponding to at least one first configuration value can be calculated in real time by reading the base address stored in the register and combining it with the address offset.

[0107] In some embodiments, where the direct access unit includes a register for storing a base address, step 2043 may specifically include: determining a target base address based on a third configuration value of a third configuration register of the direct access unit; determining an address offset corresponding to a first configuration register of each peripheral unit based on an index of a first configuration register of each peripheral unit; and determining at least one target storage address corresponding to at least one first configuration value based on the target base address and the corresponding address offset.

[0108] In some embodiments, the third configuration register is used to configure the base address of the storage address storing at least one first configuration value. That is, the third configuration value is the target base address of the storage address storing at least one first configuration value. In other words, in order to determine the storage address of at least one first configuration value, the third configuration register of the direct access unit can be directly accessed by the direct access unit to obtain the third configuration value, and at least one target storage address can be determined based on the target base address and the address offset relative to the target base address.

[0109] For example, consider a 32-bit peripheral register. Assume the third configuration register is the Memory AddressBase register, and the third configuration value read from the Memory AddressBase register is Address Base. When the first configuration register includes Register 0 and Register 1, the address offset is determined to be 0 based on the index of Register 0, thus obtaining the target memory address Address Base; the address offset is determined to be 1*(0x4) based on the index of Register 1, thus obtaining the target memory address Address Base+1*(0x4).

[0110] In some embodiments, at least one target storage address is determined based on the target base address and the address offset relative to the target base address. Each target storage address can be determined as the target storage address for storing the first configuration value of the first configuration register of each peripheral unit based on the index size order of the first configuration register of each peripheral unit. That is, the correspondence between the first configuration value of the first register and the corresponding target storage address is configured sequentially according to the index of the first configuration register from small to large. Alternatively, the correspondence between the first configuration value of the first register and the corresponding target storage address can be configured non-sequentially. In this case, a mapping table between the first configuration value of each first register and the corresponding target storage address needs to be established and stored in advance. Then, the mapping table is read by software to determine the target storage address for storing the first configuration value of each first register.

[0111] For example, when the first configuration register includes Register 0 and Register 1, assuming the calculated target memory addresses are Address Base and Address Base+1*(0x4) respectively, if the first configuration value of the first register is configured sequentially from smallest to largest according to the index of the first configuration register, then Register 0 corresponds to Address Base and Register 1 corresponds to Address Base+1*(0x4); if the first configuration value of the first register is configured non-sequentially, then Register 0 corresponds to Address Base+1*(0x4) and Register 1 corresponds to Address Base.

[0112] Based on the above embodiments, since the target base address is determined based on the third configuration value of the third configuration register of the direct access unit, and the address offset corresponding to the first configuration register of each peripheral unit is determined based on the index of the first configuration register of each peripheral unit, at least one target memory address corresponding to at least one first configuration value is determined based on the target base address and the corresponding address offset. Thus, it is only necessary to dynamically calculate at least one target memory address corresponding to at least one first configuration value through the base address register of the direct access unit. Therefore, when each target memory address changes, it is only necessary to modify the base address register of the direct access unit to dynamically adjust the memory location. In this way, dynamic addressing is realized through hardware.

[0113] Step 2044: Read the first configuration value of the first configuration register of each peripheral unit from at least one target memory address through the direct access unit.

[0114] In some embodiments, at least one target memory address in a power-off non-loss memory is accessed via a direct access unit based on an on-chip bus to read the first configuration value of the first configuration register of each peripheral unit stored at each target memory address.

[0115] For example, consider a 32-bit peripheral register. When the first configuration register includes Register0 and Register1, during the sleep-wake process, the first configuration value is moved from the target base address of the non-volatile memory (NVMemory) via the direct access unit. After each peripheral unit wakes up, the first configuration value is read from the NVOMemory at address Address Base via the direct access unit and identified as the first configuration value of Register0. Since each 32-bit register occupies 4 bytes, the first configuration value can be read from the NVOMemory at address Address Base+1*(0x4) via the direct access unit and identified as the first configuration value of Register1.

[0116] In other embodiments, the first configuration value of the first configuration register of each peripheral unit can be read sequentially from at least one target memory address based on the arrangement order of at least one second configuration register of the direct access unit.

[0117] The technical solution provided in this disclosure allows for the determination of at least one target memory address corresponding to at least one first configuration value in the address space of the memory unit. Therefore, by directly accessing the unit, the first configuration value of the first configuration register of each peripheral unit can be read from at least one target memory address. In other words, during the wake-up recovery process, this solution can accurately read the corresponding first configuration value from at least one target memory address corresponding to at least one first configuration value. This avoids subsequently writing incorrect first configuration values ​​to the first configuration registers of each peripheral unit, thereby ensuring the configuration consistency of the first configuration registers of each peripheral unit before and after power-down.

[0118] like Figure 5 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 202 above may include the following steps:

[0119] Step 2021: Determine the target configuration order of the first configuration register of each peripheral unit.

[0120] The target configuration order is used to indicate the correspondence between at least one second configuration register and at least one first configuration register of the directly accessed unit.

[0121] Step 2022: Determine the register address of the first configuration register of each peripheral unit.

[0122] For an explanation of steps 2021 and 2022 above, please refer to the detailed description of steps A and B in the above embodiments. This disclosure will not repeat the details.

[0123] Step 2023: Based on at least one register address, read the first configuration value from the first configuration register corresponding to each register address in the order of the target configuration through the direct access unit.

[0124] In some examples, the first configuration register corresponding to each second configuration register can be determined according to the target configuration order. Therefore, when it is desired to read the first configuration value of the first configuration register corresponding to the current second configuration register, the first configuration register corresponding to the current second configuration register is accessed through the direct access unit based on the second configuration value of the current second configuration register, which is the register address of the first configuration register corresponding to the current second configuration register, in order to read the first configuration value of the first configuration register.

[0125] The technical solution provided in this disclosure can determine the target configuration order of the first configuration registers of each peripheral unit and the register address of the first configuration register of each peripheral unit. Therefore, based on at least one register address, the first configuration value is read from the first configuration register corresponding to each register address according to the target configuration order through the direct access unit. Thus, during system sleep, the direct access unit's ability to directly access the address can be used to accurately locate each first configuration register, avoiding the omission or error of the first configuration value due to address error. This ensures that the currently required first configuration value can be accurately read.

[0126] like Figure 6 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 202 above may specifically include the following steps:

[0127] Step 2024: Determine at least one target storage address in the address space of the memory unit that corresponds to at least one first configuration value.

[0128] For an explanation of step 2024 above, please refer to the detailed description of step 2043 in the above embodiments. This disclosure will not repeat the details.

[0129] Step 2025: By directly accessing the unit, the first configuration values ​​of the first configuration registers of each peripheral unit are stored in the corresponding target memory addresses in at least one target memory address.

[0130] In some embodiments, after determining the target storage address for storing each first configuration value, since the direct access unit has the ability to directly access the address, the target storage address corresponding to each first configuration value is accessed one by one by the direct access unit to write the corresponding first configuration value to the target storage address corresponding to each first configuration value.

[0131] For example, consider a 32-bit peripheral register. When the first configuration register includes Register0 and Register1, assume that the target memory address Address Base corresponding to Register0 and the target memory address Address Base+1*(0x4) corresponding to Register1 are determined from the address space of the non-volatile memory. Before each peripheral unit goes to sleep, the first configuration value is read from Register0 and stored in AddressBase, and the first configuration value is read from Register1 and stored in Address Base+1*(0x4) via direct access.

[0132] The technical solution provided in this disclosure allows for the determination of at least one target storage address corresponding to at least one first configuration value within the address space of the memory unit. Therefore, by directly accessing the unit, the first configuration values ​​of the first configuration registers of each peripheral unit are stored at the corresponding target storage addresses within the at least one target storage address. In other words, this solution can pre-save the configuration values ​​of each peripheral register before power-off in a non-volatile memory before hibernation, and the first configuration value of each peripheral is stored at a unique target storage address, avoiding confusion of the configuration values ​​of each peripheral. This provides a favorable guarantee that each peripheral unit can restore its configuration value before power-off after wake-up.

[0133] Exemplary electronic devices

[0134] Figure 7 A structural diagram of an electronic device provided in an embodiment of this disclosure includes at least one processor 111 and a memory 112.

[0135] The processor 111 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 11 to perform desired functions.

[0136] The memory 112 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 111 may execute one or more computer program instructions to implement the wake-up recovery method for integrated circuits and / or other desired functions of the various embodiments of this disclosure described above.

[0137] In one example, the electronic device 11 may also include an input device 113 and an output device 114, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0138] The input device 113 may include various sensors, including but not limited to: a distance sensor for detecting the distance between a target object and the vehicle; an image sensor for acquiring information about the vehicle's surrounding environment. In some examples, the input device may also include a pressure sensor for detecting seat pressure to determine the presence and location of passengers; a temperature sensor for monitoring the temperature inside the cabin; a humidity sensor for monitoring the humidity inside the cabin to assist in regulating the in-vehicle environment; an air quality sensor for monitoring in-vehicle air quality, such as carbon dioxide and volatile organic compounds (VOCs); a light sensor for detecting the intensity of light inside and outside the vehicle; an acceleration sensor for detecting changes in the vehicle's acceleration; a distance sensor for detecting the distance between the vehicle and other objects; a touchscreen sensor for interaction with the vehicle's infotainment system; biometric sensors, such as fingerprint recognition and facial recognition; a heart rate monitor for monitoring the driver's heart rate; a sound sensor for voice recognition and interaction to enable voice control; a seat sensor for monitoring seat usage, such as whether the seat is occupied and the passenger's body size; and wireless communication sensors, such as Bluetooth and Wi-Fi, for connecting to smart devices to achieve data transmission and remote control. In addition to the examples given above, the input device may include more or fewer sensors, which will not be elaborated here.

[0139] The output device 114 can output various information or signals to other hardware or devices, which may include displays, car audio systems, seats, windows, steering wheels, communication networks, and their connected remote output devices. The displays may include multiple different displays such as a driver's side display, a passenger side display, and a rear-seat display. The car audio system may include multiple speakers located in different positions within the vehicle cabin, and each display or speaker can operate independently.

[0140] Of course, for the sake of simplicity, Figure 7 Only some of the components of the electronic device 11 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 11 may include any other suitable components depending on the specific application.

[0141] Exemplary computer program products and computer-readable storage media

[0142] In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps in the wake-up recovery method for an integrated circuit described in the various embodiments of this disclosure in the "Exemplary Methods" section above.

[0143] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0144] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform steps in the wake-up recovery method for an integrated circuit described in the various embodiments of this disclosure in the "Exemplary Methods" section above.

[0145] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0146] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0147] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A wake-up recovery method for integrated circuits, the method comprising: When at least one peripheral unit in the integrated circuit is powered on, a sleep signal is received through the direct access unit in the integrated circuit. In response to the sleep signal, before the at least one peripheral unit is powered down, the first configuration value is read from the first configuration register of each peripheral unit through the direct access unit, and at least one of the first configuration values ​​is stored in the memory unit of the integrated circuit; wherein, the first configuration value of the first configuration register is the configuration value of the first configuration register before the peripheral unit is powered down; When at least one peripheral unit in the integrated circuit is powered down, a wake-up signal is received through the direct access unit; In response to the wake-up signal, after the at least one peripheral unit is powered on, at least one of the first configuration values ​​is read from the memory unit through the direct access unit, and the at least one of the first configuration values ​​read is written into the corresponding first configuration registers to restore the at least one peripheral unit.

2. The method according to claim 1, wherein, The step of writing at least one of the read first configuration values ​​into the corresponding first configuration registers includes: Determine the register address of the first configuration register of each peripheral unit; Based on at least one of the register addresses, the at least one first configuration value read is written into the first configuration register corresponding to each of the register addresses through the direct access unit.

3. The method according to claim 2, wherein, Determining the register address of the first configuration register of each peripheral unit includes: Determine a second configuration value for at least one second configuration register of the direct access unit; wherein the second configuration value is the register address of the first configuration register; Determine the target configuration order of the first configuration registers of each peripheral unit; wherein the target configuration order is used to indicate the correspondence between at least one second configuration register and at least one first configuration register; Based on the target configuration order and the second configuration value of at least one second configuration register, the register address of the first configuration register of each peripheral unit is determined.

4. The method according to claim 3, wherein, The step of writing at least one of the first configuration values ​​read from at least one of the register addresses into the first configuration registers corresponding to each of the register addresses through the direct access unit includes: Determine the arrangement order of at least one of the second configuration registers; Based on the target configuration order, determine the first configuration register corresponding to each of the second configuration registers; Through the direct access unit, at least one of the first configuration values ​​read are sequentially written into the first configuration register corresponding to each of the second configuration registers, according to the arrangement order of at least one of the second configuration registers.

5. The method according to claim 1, wherein, The step of reading at least one of the first configuration values ​​from the memory unit through the direct access unit includes: In the address space of the memory unit, at least one target storage address corresponding to at least one of the first configuration values ​​is determined; The first configuration value of the first configuration register of each peripheral unit is read from the at least one target memory address through the direct access unit.

6. The method according to claim 5, wherein, Determining at least one target storage address in the address space of the memory unit corresponding to at least one of the first configuration values ​​includes: The target base address is determined based on the third configuration value of the third configuration register of the direct access unit; Based on the index of the first configuration register of each peripheral unit, determine the address offset corresponding to the first configuration register of each peripheral unit; Based on the target base address and the corresponding address offset, determine the at least one target storage address corresponding to at least one of the first configuration values.

7. The method according to claim 1, wherein, The step of reading the first configuration value from the first configuration register of each peripheral unit through the direct access unit includes: Determine the target configuration order of the first configuration registers of each peripheral unit; wherein the target configuration order is used to indicate the correspondence between at least one second configuration register and at least one first configuration register of the direct access unit; Determine the register address of the first configuration register of each peripheral unit; Based on at least one of the register addresses, the first configuration value is read from the first configuration register corresponding to each of the register addresses in the order of the target configuration via the direct access unit.

8. The method according to claim 1, wherein, The step of storing at least one of the first configuration values ​​in the memory cell of the integrated circuit includes: In the address space of the memory unit, at least one target storage address corresponding to at least one of the first configuration values ​​is determined; The first configuration value of the first configuration register of each peripheral unit read is stored in the corresponding target storage address in the at least one target storage address through the direct access unit.

9. An integrated circuit, comprising: At least one peripheral unit, a direct access unit, and a memory unit; wherein, The direct access unit is configured to receive a sleep signal when at least one peripheral unit is powered on; and in response to the sleep signal, before the at least one peripheral unit is powered off, read a first configuration value from the first configuration register of each peripheral unit, and store at least one of the first configuration values ​​in the memory unit; wherein the first configuration value of the first configuration register is the configuration value of the first configuration register before the peripheral unit is powered off. The memory unit is used to store the first configuration value of the first configuration register of each of the peripheral units; The direct access unit is further configured to receive a wake-up signal when the at least one peripheral unit is powered down; and in response to the wake-up signal, read at least one of the first configuration values ​​from the memory unit after the at least one peripheral unit is powered on; and write the at least one of the first configuration values ​​read into the corresponding first configuration registers to restore the at least one peripheral unit.

10. The integrated circuit according to claim 9, wherein, The direct access unit includes at least one second configuration register and a third configuration register; Wherein, at least one of the second configuration registers is used to configure the register address of the corresponding first configuration register, and the third configuration register is used to configure the target base address of at least one of the first configuration values ​​stored in the memory unit.

11. A computer-readable storage medium storing a computer program for performing the wake-up recovery method for an integrated circuit according to any one of claims 1-8.

12. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the wake-up recovery method for integrated circuits according to any one of claims 1-8. Alternatively, the electronic device may include the integrated circuit described in claims 9 and 10.

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