Cooperative parallelization error correction method and device for DRAM (Dynamic Random Access Memory)
A collaborative parallel error correction method, which injects pseudo-random numbers at the DRAM chip level and performs pseudo-random number comparison at the memory controller level, solves the problems of high storage overhead, large performance loss, and error correction interference in DRAM error correction schemes, and achieves correction effects with low redundancy, high reliability, and low latency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-03-13
AI Technical Summary
Existing DRAM error correction schemes suffer from high storage overhead, significant performance loss, and susceptibility to interference from miscorrections. Especially in high error rate scenarios, existing cooperative error correction schemes increase hardware complexity and latency, and fail to effectively address the impact of in-memory error correction miscorrections on the reliability and performance of error correction codes at the memory controller.
Pseudo-random numbers are generated at the DRAM chip level to inject the sub-block where the error is located. At the memory controller level, the error location is identified by comparing pseudo-random numbers. RS erasure codes are used for correction, realizing the cooperation between in-memory error correction codes and memory controller error correction codes, parallelizing the error correction method, avoiding direct error correction, and reducing redundant information transmission.
It achieves low-overhead, high-reliability, and low-latency DRAM error correction, reduces the latency of read-write operations, and improves the error correction capability of the memory controller by identifying error locations through pseudo-random number comparison, thus avoiding silent data corruption.
Smart Images
Figure CN121658280A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of computer storage, and more specifically, relates to a cooperative parallelization error correction method and apparatus for DRAM. Background Technology
[0002] As DRAM (Dynamic Random Access Memory) manufacturing processes continue to shrink, its storage density and capacity have significantly improved, but reliability issues have become increasingly prominent. Existing DDR5 memory employs a two-stage error correction code to ensure storage reliability. Specifically, the first stage is on-die error correction code (also known as On-Die ECC, OD-ECC), which is typically single-bit error correction; the second stage is memory controller-side error correction code (also known as Rank-Level ECC, RL-ECC), which is typically Reed-Solomon code.
[0003] While two-stage error correction schemes can effectively improve memory reliability, existing schemes suffer from the following problems because the in-memory error correction codes are not visible to the memory controller: 1. Excessive storage overhead: Taking DDR5 ×4 DRAM as an example, the superposition of in-memory error correction code and memory controller error correction code results in a total redundancy rate as high as 32.8%, which seriously squeezes the effective memory capacity; 2. Significant performance loss: The memory controller-side error correction code usually needs to be repeatedly triggered during read-modify-write (RMW) operations to serially decode and encode the in-memory error correction code, resulting in a significant increase in latency; 3. Susceptible to error correction interference: Since the error correction code on the memory controller side cannot know the internal operation of OD-ECC, if the error correction code outputs data that has been incorrectly corrected, the error correction code on the memory controller side may not be able to correctly locate the error, resulting in uncorrectable errors or silent data corruption.
[0004] To address the lack of coordination between in-memory error correction codes and memory controller-side error correction codes, several cooperative error correction code schemes have been proposed. XED exposes some information by extending error detection capabilities, but its performance degrades significantly in high error rate scenarios. DUO modifies the memory standard and interface protocol and introduces a double cross-checking mechanism, but requires additional checking steps, increasing latency and power consumption. PAIR also changes the memory standard, including memory timing parameters. These schemes share the following drawbacks: 1. Most systems use blocking cross-checking for errors. When the error rate increases, the number of checks increases dramatically, severely impacting system performance. 2. Failed to adequately address the negative impact of in-memory error correction codes on the reliability and performance of error correction codes at the memory controller level, given the existence of existing in-memory error correction codes; 3. Overhead and benefits are mismatched: Although reliability is improved, it often changes memory standards and protocols, reduces the versatility of the solution, and comes at the cost of significantly increased hardware complexity and latency.
[0005] Overall, current technologies lack a memory error correction method that can achieve low redundancy overhead and low performance loss while avoiding the impact of in-memory error correction codes miscorrection. Summary of the Invention
[0006] In response to the deficiencies and improvement needs of existing technologies, this invention provides a method that is currently lacking in the technology, which can avoid the impact of in-memory error correction codes on error correction while maintaining low redundancy overhead and low performance loss. The purpose is to achieve effective cooperation between in-memory error correction codes and memory controller error correction codes, thereby achieving low-overhead, high-reliability, and low-latency DRAM error correction.
[0007] To achieve the above objectives, according to one aspect of the present invention, a cooperative parallelization error correction method for DRAM is provided, comprising: At the DRAM chip level, for data block D and its parity bits read from the memory bank, a preset in-memory error correction code is used to perform error detection on the codeword composed of data block D and its parity bits. If an error is detected in data block D, a codeword of length [length missing] is generated at the DRAM chip level. A pseudo-random number is generated and injected into the sub-block containing the error at the DRAM chip, resulting in data block D'. Data block D' is then sent to the memory controller. In the DRAM chip, each memory array block is divided into one or more fixed-length sub-blocks. The length of the sub-block; In the memory controller, after receiving multiple data blocks from the DRAM chip, they are combined into RS erasure codewords of a preset length; pseudo-random numbers are identified as known errors by comparing pseudo-random numbers in the RS erasure codewords; RS erasure codes are used to correct the known errors and the remaining unknown errors in the RS erasure codewords, thus completing error correction. In the memory controller, a new pseudo-random number is generated each time a pseudo-random number comparison is successful, and the first pseudo-random number is generated. i The second generated pseudo-random number and the first in the DRAM chip i The generated pseudo-random numbers are the same; i= 1,2…… Furthermore, .
[0008] Furthermore, the cooperative parallel error correction method for DRAM provided by the present invention further includes: while identifying pseudo-random numbers in RS erasure code codewords as known errors through pseudo-random number comparison, recording the positions of the known errors to obtain an error position set. While using RS erasure coding to correct known errors and remaining unknown errors in RS erasure codewords, the location of the errors is recorded, resulting in a set of error locations. ; For the set of error locations and error location set Perform cross-validation, if If so, a warning message is sent to the CPU indicating potential silent data corruption.
[0009] Furthermore, the cooperative parallelization error correction method for DRAM provided by the present invention further includes: performing a read-modify-write operation according to the following steps: Read the data to be updated from the memory library. and its check bits Then, the data The data position to be updated is 0, thus retaining the data. and utilize data And check bits Calculate the parity-check matrix ; Using in-memory error correction codes to correct data and its check bits Error correction is performed on the in-memory error-correcting codewords to obtain the corrected data bits. And record the accompanying expressions generated during the error correction process; Using the check matrix Calculate the retained data separately check bits and new data check bits XORing the two yields the uncorrected check bits. ; Combine the syntactic and the uncorrected check bits. Perform an XOR operation to obtain the corrected check bit. ; Utilizing new data For the corrected data bits After the update, along with the corrected checksum... They are written together into the memory database to complete the read, modify, and write operations.
[0010] According to another aspect of the present invention, a collaborative parallel error correction device for DRAM is provided, comprising: an in-memory error correction module, a first pseudo-random number generator, a pseudo-random number injector, and a first data transmission module deployed on the memory side, and a second data transmission module, a second pseudo-random number generator, a pseudo-random number identifier, and an RS erasure coding module deployed on the memory controller. The first pseudo-random number generator is used to generate pseudo-random numbers at the DRAM chip level, and the second pseudo-random number generator is used to generate pseudo-random numbers in the memory controller; the first pseudo-random number generator and the second pseudo-random number generator... i The generated pseudo-random numbers are the same. i= 1,2……; The in-memory error correction module is used to perform error detection on the data block D read from the memory bank and the codeword composed of its check bits using a preset in-memory error correction code; The memory injector is used to trigger the first pseudo-random number generator to generate a number of lengths at the DRAM chip when the memory error correction module detects an error in data block D. The pseudo-random number is generated by the first pseudo-random number generator and injected into the sub-block where the error occurs, resulting in data block D'; in a DRAM chip, each memory array block is divided into one or more fixed-length sub-blocks. The length of the sub-block; The first data transmission module is used to transmit data from the DRAM chip to the memory controller; The second data transmission module is used to receive data from the DRAM chip, and after receiving multiple data blocks from the DRAM chip, it combines them into RS erasure codewords of a preset length. The pseudo-random number identification module is used to compare the sub-blocks in the RS erasure code codeword with the pseudo-random numbers generated by the second pseudo-random number generator in order to identify the pseudo-random numbers in the RS erasure code codeword and to treat the identified pseudo-random numbers as known errors. Each time the pseudo-random number comparison is successful, the pseudo-random number identification module will trigger the second pseudo-random number generator to generate new pseudo-random numbers. The RS erasure coding module is used to correct known errors and remaining unknown errors in RS erasure codewords using RS erasure coding, thus completing error correction.
[0011] Furthermore, the in-memory error correction module includes: an adjoint generator, an adjoint decoder, and an error correction module; The syntactic generator is used to generate the syntactic needed for decoding; The synic decoder is used to locate errors in the synic detection data generated by the synic generator; The error correction module is used to correct errors in the data; The pseudo-random number injector includes: a first bitwise OR logic unit, a first NAND gate, a first comparator, a second bitwise OR logic unit, an AND gate, a second NAND gate, and a tri-state gate; The first OR logic unit has its input connected to the output of the syndic generator, and is used to perform a bitwise OR operation on the syndic generated by the syndic generator. The first NAND gate has its first input connected to the output of the first bitwise OR logic unit and its second input connected to the output of the syntactic decoder. It is used to perform NAND operations on the input signal. The first comparator has a first input terminal for receiving data read from a memory block, and a second input terminal connected to the output terminal of the first pseudo-random number generator, which is used to compare each sub-block of data with the pseudo-random number generated by the first pseudo-random number generator. The second bitwise OR logic unit has its input connected to the output of the first comparator, and is used to perform a bitwise OR operation on the comparison result of each sub-block and the pseudo-random number. An AND gate, whose input is connected to the output of the second bitwise OR logic unit, is used to perform a bitwise AND operation on the input signal to obtain an indication signal for indicating whether the sub-block is equal to the pseudo-random number; The second NAND gate has its first input terminal connected to the output terminal of the first NAND gate and its second input terminal connected to the output terminal of the AND gate. It is used to perform a NAND operation on the input signal to obtain a control signal for instructing the first pseudo-random number generator to generate a new pseudo-random number. A tri-state gate, whose first input is connected to the output of a first NAND gate, and whose second input is connected to the output of a first pseudo-random number generator, outputting a pseudo-random number for injecting the error into the sub-block.
[0012] Furthermore, the pseudo-random number recognizer includes: a second comparator and a recognition unit; The second comparator has a first input terminal for inputting RS erasure code codewords and a second input terminal connected to the output terminal of the second pseudo-random number generator. It is used to compare each sub-block in the RS erasure code codeword with the pseudo-random number output by the second pseudo-random number generator. The identification unit has its input connected to the output of the second comparator and its output connected to the input of the second pseudo-random number generator. When the second comparator successfully matches the data, it identifies the current sub-block location as a known error location and sends a control signal to the second pseudo-random number generator to trigger the generator to generate a new pseudo-random number.
[0013] Furthermore, the cooperative parallel error correction device for DRAM provided by the present invention further includes: an error location comparator deployed on the memory controller; An error location comparator whose first input is used to receive a set of error locations. Its second input is used to receive the set of error locations. It is used for the set of error locations. and error location set Perform cross-validation, and If this happens, a warning message is sent to the CPU indicating potential silent data corruption. Among them, the set of error locations Let be the set of error locations recorded when correcting known errors and remaining unknown errors in RS erasure code codewords using RS erasure coding. This refers to the set of error locations in RS erasure codewords identified through pseudo-random number comparison. Furthermore, the collaborative parallel error correction device for DRAM provided by the present invention further includes: an in-memory synchronous encoder deployed on the memory chip; the in-memory synchronous encoder includes: a calculation control module, a reserved data parity bit generator, an updated data parity bit generator, a parity bit generator, and a parity bit error correction module; The calculation control module is used to read the data to be updated from the memory bank. The data position to be updated is 0, thus retaining the data. and utilize data and its check bits Calculate the parity-check matrix ; The calculation control module is also used to utilize the in-memory error correction module to process the data. and its check bits Error correction is performed on the in-memory error-correcting codewords to obtain the corrected data bits. And record the accompanying expressions generated during the error correction process; Reserved data parity bit generator, used to utilize the parity matrix Calculate retained data check bits ; Update the data checksum generator to utilize the checksum matrix. Calculate new data check bits ; Check bit generator, used to generate check bits And check bits XORing yields the uncorrected check bits. ; The check bit correction module is used to correct the syntactic error and the uncorrected check bit. Perform an XOR operation to obtain the corrected check bit. ; The calculation control module is also used to utilize new data. For the corrected data bits After the update, along with the corrected checksum... They are written together into the memory database to complete the read, modify, and write operations.
[0014] Furthermore, .
[0015] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects: (1) After detecting an error in a data block during the OD-ECC stage, this invention does not directly correct it, but instead injects a pseudo-random number into the sub-block where the error is located. This avoids uncorrectable errors during the OE-ECC stage and exposes the error location to the memory controller through the pseudo-random number. At the memory controller, the error location in the data block can be identified by comparing the pseudo-random number. These errors can be corrected with less redundant information. In this process, there is no need to block the original verification process or modify the memory standard and interface protocol. This achieves effective cooperation between the in-memory error correction code and the memory controller error correction code, thereby achieving low-overhead, high-reliability and low-latency DRAM error correction.
[0016] (2) The present invention decomposes the update process in the read-modify-write operation process in the DRAM chip into the correction of data error and the correction of error in the check bit, realizing the parallel execution of encoding and decoding operations, and effectively reducing the latency of read-modify-write operation. Attached Figure Description
[0017] Figure 1 This is a flowchart of a cooperative parallelization error correction method for DRAM provided in an embodiment of the present invention.
[0018] Figure 2 This is a schematic diagram of a cooperative parallelization error correction device for DRAM provided in an embodiment of the present invention.
[0019] Figure 3 This is a schematic diagram of the pseudo-random number injector provided in an embodiment of the present invention.
[0020] Figure 4 This is a schematic diagram of the pseudo-random number recognizer provided in an embodiment of the present invention.
[0021] Figure 5 This is a schematic diagram of the structure of an in-memory synchronous encoder provided in an embodiment of the present invention. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.
[0023] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0024] To achieve low-overhead, high-reliability, and low-latency DRAM error correction, this invention provides a cooperative parallel error correction method and device for DRAM. The overall approach is as follows: instead of directly correcting errors during OD-ECC error detection, pseudo-random numbers are injected at the error location and transmitted to the memory controller. This exposes the error location to the memory controller, preventing uncorrectable errors from occurring during the OD-ECC stage and affecting overall reliability. Furthermore, it allows the RL-ECC stage in the memory controller to utilize known error location information, improving error correction capabilities without changing the number of redundant parity bits. This process does not block the original verification process, nor does it require modification of memory standards and interface protocols, thus avoiding any adverse impact on system performance and latency.
[0025] The following is an example.
[0026] Example 1: A cooperative parallelization error correction method for DRAM, such as Figure 1 As shown, it includes: At the DRAM chip level, for data block D and its parity bits read from the memory bank, a preset in-memory error correction code is used to perform error detection on the codeword composed of data block D and its parity bits. If an error is detected in data block D, a codeword of length [length missing] is generated at the DRAM chip level. A pseudo-random number is generated and injected into the sub-block containing the error at the DRAM chip, resulting in data block D'. Data block D' is then sent to the memory controller. In the DRAM chip, each memory array block is divided into one or more fixed-length sub-blocks. The length of the sub-block; In the memory controller, after receiving multiple data blocks from the DRAM chip, they are combined into RS erasure codewords of a preset length; pseudo-random numbers are identified as known errors by comparing pseudo-random numbers in the RS erasure codewords; RS erasure codes are used to correct the known errors and the remaining unknown errors in the RS erasure codewords, thus completing error correction. In the memory controller, a new pseudo-random number is generated each time a pseudo-random number comparison is successful, and the first pseudo-random number is generated. i The second generated pseudo-random number and the first in the DRAM chip i The generated pseudo-random numbers are the same; i= 1,2……
[0027] RS erasure codes can handle both known and unknown errors. Known errors are those whose location is known, while unknown errors are those whose location is unknown. For an RS(n, k) code, where n represents the length of the encoded codeword (data bits + parity bits), k represents the length of the data bits, and m = n – k represents the number of parity bits, the error correction capability of the RS(n, k) code is determined by the following relationship:
[0028] Where e is the number of unknown position errors, s is the number of known position errors, and m is the number of check bits.
[0029] In this embodiment, after detecting errors in a data block during the OD-ECC stage, it does not directly correct them. Instead, it injects pseudo-random numbers into the sub-block containing the error, thereby avoiding uncorrectable errors during the OE-ECC stage. At the memory controller, the location of the error in the data block can be identified through pseudo-random number comparison, and these errors can be corrected with minimal redundant information.
[0030] Each DRAM chip comprises multiple DRAM bankgroups, each bank group contains multiple DRAM banks, and each bank is further divided into multiple memory array tiles (MATs). During actual storage, data is stored within these MATs. This embodiment divides the MATs into sub-blocks and injects pseudo-random numbers on a sub-block basis, ensuring that the sub-block containing the error can be identified at the memory controller level using synchronously generated pseudo-random numbers. It is easy to understand that the length of the sub-block should be set in conjunction with the error correction capability and reliability requirements of the RS code at the actual memory controller level. A longer length results in higher accuracy of pseudo-random number identification at the memory controller level, but also requires correcting more known errors. Conversely, a shorter length results in fewer known errors requiring correction, but lower accuracy of pseudo-random number identification at the memory controller level. Optionally, in this embodiment, the following settings are provided: The length is the same as the length of the memory array block. That is to say, every time an error is detected, a pseudo-random number is injected into the entire memory array block where the error is located, thereby simplifying the process of injecting and identifying pseudo-random numbers.
[0031] In this embodiment, since error detection is performed but error correction is not performed at the memory chip level, the redundant verification information of OE-ECC can be reduced, thereby reducing the in-memory redundancy overhead.
[0032] To further improve reliability, this embodiment also includes: while identifying pseudo-random numbers in RS erasure codewords as known errors through pseudo-random number comparison, recording the positions of the known errors to obtain a set of error positions. While using RS erasure coding to correct known errors and remaining unknown errors in RS erasure codewords, the location of the errors is recorded, resulting in a set of error locations. ; For the set of error locations and error location set Perform cross-validation, if If so, a warning message is sent to the CPU indicating potential silent data corruption.
[0033] This embodiment records the error location, enabling the memory controller to accurately grasp the distribution of error bits. Through cross-validation, it can promptly identify silent data corruption and send corresponding prompts to the CPU, thereby preventing unknown silent data corruption from affecting normal applications.
[0034] To further optimize memory performance, this embodiment optimizes read-modify-write operations.
[0035] OD-ECC in memory chips typically uses linear block codes as in-memory error correction codes. Linear block codes rely on parity-check matrices. To perform multi-level XOR operations to encode or decode data Using the verification matrix By performing an XOR operation with it, the parity bit can be obtained. .
[0036] Data Divided into and , and satisfy ,but:
[0037] in, This indicates the XOR operation. and These represent the use of the parity check matrix. right and The generated check digit.
[0038] Assumption This refers to the parts that do not need to be updated during the update operation. The portion that needs to be overwritten by newly written data should be protected if a single-bit error occurs during storage. Then, during decoding, the error complication is:
[0039] For memory read-modify-write (RMW) operations, the newly written data is represented as... The newly written data and the data to be retained at the access address are then compared using the checksum bit. yes:
[0040] Data errors can be corrected using existing in-memory error-correcting codes. To correct the check bits, only the syndrome and... XOR is sufficient; the relevant expression is:
[0041] Based on the above analysis, in this embodiment, the read-modify-write operation is performed according to the following steps: Read the data to be updated from the memory library. and its check bits Then, the data The data position to be updated is 0, thus retaining the data. and utilize data And check bits Calculate the parity-check matrix ; Using in-memory error correction codes to correct data and its check bits Error correction is performed on the in-memory error-correcting codewords to obtain the corrected data bits. And record the accompanying expressions generated during the error correction process; Using the check matrix Calculate the retained data separately check bits and new data check bits XORing the two yields the uncorrected check bits. ; Combine the syntactic and the uncorrected check bits. Perform an XOR operation to obtain the corrected check bit. ; Utilizing new data For the corrected data bits After the update, along with the corrected checksum... They are written together into the memory database to complete the read, modify, and write operations.
[0042] Through the above optimizations, this embodiment achieves simultaneous encoding and decoding of linear block codes, alleviating the latency problem of RMW.
[0043] Example 2: A cooperative parallel error correction device for DRAM, such as Figure 2As shown, it includes: an in-memory error correction module, a first pseudo-random number generator, a pseudo-random number injector, and a first data transmission module deployed on the memory side; and a second data transmission module, a second pseudo-random number generator, a pseudo-random number recognizer, and an RS erasure coding module deployed on the memory controller. The first pseudo-random number generator is used to generate pseudo-random numbers at the DRAM chip level, and the second pseudo-random number generator is used to generate pseudo-random numbers in the memory controller; the first pseudo-random number generator and the second pseudo-random number generator... i The generated pseudo-random numbers are the same. i= 1,2……; The in-memory error correction module is used to perform error detection on the data block D read from the memory bank and the codeword composed of its check bits using a preset in-memory error correction code; The memory injector is used to trigger the first pseudo-random number generator to generate a number of lengths at the DRAM chip when the memory error correction module detects an error in data block D. The pseudo-random number is generated by the first pseudo-random number generator and injected into the sub-block where the error occurs, resulting in data block D'; in a DRAM chip, each memory array block is divided into one or more fixed-length sub-blocks. The length of the sub-block; each time a pseudo-random number comparison is successful, the pseudo-random number recognition module will trigger the second pseudo-random number generator to generate a new pseudo-random number; The first data transmission module is used to transmit data from the DRAM chip to the memory controller; The second data transmission module is used to receive data from the DRAM chip, and after receiving multiple data blocks from the DRAM chip, it combines them into RS erasure codewords of a preset length. The pseudo-random number identification module is used to compare the sub-blocks in the RS erasure code codeword with the pseudo-random numbers generated by the second pseudo-random number generator in order to identify the pseudo-random numbers in the RS erasure code codeword and to treat the identified pseudo-random numbers as known errors. The RS erasure coding module is used to correct known errors and remaining unknown errors in RS erasure codewords using RS erasure coding, thus completing error correction.
[0044] In this embodiment, a first pseudo-random number generator, a pseudo-random number injector, a second pseudo-random number generator, and a pseudo-random number identifier are additionally introduced, which will be explained in detail below.
[0045] A pseudo-random number generator is a computational tool that generates seemingly random sequences of numbers using deterministic algorithms. While the generated sequences are not truly random, they exhibit statistical uniformity and independence. The core principle of this type of generator is based on mathematical operations using an initial seed value, employing methods such as linear congruence generators and Mason tweening algorithms to generate random number sequences. In this embodiment, existing pseudo-random number generators can be used for both the first and second pseudo-random number generators.
[0046] In this embodiment, the in-memory error correction module includes: an adjoint generator, an adjoint decoder, and an error correction module; The syntactic generator is used to generate the syntactic needed for decoding; The syndrome decoder is used to detect error locations in the syndrome data generated by the syndrome generator; the syndrome decoder contains an address decoder to translate the input address into bit pointers and MAT pointers to select the corresponding memory cell; The error correction module is used to correct errors in the data. Essentially, it is an error comparator used to detect whether there are errors in the selected storage unit.
[0047] Optionally, in this embodiment, the length of the pseudo-random numbers generated by the pseudo-random number injector is the same as the length of the memory array block, which is 16. That is to say, the pseudo-random number injector is a memory array block aligned pseudo-random number injector, and its structure is as follows: Figure 3 As shown, it includes: First bitwise OR logic unit, first NAND gate, first comparator, second bitwise OR logic unit, AND gate, second NAND gate and tri-state gate; The first OR logic unit has its input connected to the output of the syndic generator, and is used to perform a bitwise OR operation on the syndic generated by the syndic generator. The first NAND gate has its first input connected to the output of the first bitwise OR logic unit and its second input connected to the output of the syntactic decoder. It is used to perform NAND operations on the input signal. The first comparator has a first input terminal for receiving data read from a memory block, and a second input terminal connected to the output terminal of a first pseudo-random number generator. It is used to compare each sub-block in the data with the pseudo-random number generated by the first pseudo-random number generator. In a preferred embodiment, in this embodiment, the first comparator reuses the error comparator in the in-memory error correction module. The second bitwise OR logic unit has its input connected to the output of the first comparator, and is used to perform a bitwise OR operation on the comparison result of each sub-block and the pseudo-random number. An AND gate, whose input is connected to the output of the second bitwise OR logic unit, is used to perform a bitwise AND operation on the input signal to obtain an indication signal for indicating whether the sub-block is equal to the pseudo-random number; The second NAND gate has its first input connected to the output of the first NAND gate and its second input connected to the output of the AND gate. It is used to perform a NAND operation on the input signal to obtain a control signal that instructs the first pseudo-random number generator to generate a new pseudo-random number. When the control signal is "0", the pseudo-random number generator will jump to generate the next pseudo-random number generator. When the control signal is "1", the current pseudo-random number remains unchanged. A tri-state gate, whose first input is connected to the output of a first NAND gate, and whose second input is connected to the output of a first pseudo-random number generator, outputting a pseudo-random number for injecting the error into the sub-block.
[0048] The pseudo-random number injector works as follows: when the storage array detects an error, the injector replaces the corresponding data with a pseudo-random number prompt and outputs it through the data pin, enabling the memory controller to identify the location of the error.
[0049] In this embodiment, the structure of the pseudo-random number recognizer on the memory controller side is as follows: Figure 4 As shown, it includes: a second comparator and an identification unit; The second comparator has a first input terminal for inputting RS erasure code codewords and a second input terminal connected to the output terminal of the second pseudo-random number generator. It is used to compare each sub-block in the RS erasure code codeword with the pseudo-random number output by the second pseudo-random number generator. The identification unit has its input connected to the output of the second comparator and its output connected to the input of the second pseudo-random number generator. When the second comparator successfully matches the data, it identifies the current sub-block location as a known error location and sends a control signal to the second pseudo-random number generator to trigger the generator to generate a new pseudo-random number.
[0050] To further improve memory reliability, this embodiment also includes: an error location comparator deployed on the memory controller; An error location comparator whose first input is used to receive a set of error locations. Its second input is used to receive the set of error locations. It is used for the set of error locations. and error location set Perform cross-validation, and If this happens, a warning message is sent to the CPU indicating potential silent data corruption. Among them, the set of error locations Let be the set of error locations recorded when correcting known errors and remaining unknown errors in RS erasure code codewords using RS erasure coding. This is the set of error locations in RS erasure codewords identified through pseudo-random number comparison.
[0051] To further optimize memory read-modify-write (RMW) operations, this embodiment also includes: an in-memory synchronous encoder deployed on the memory chip; the structure of the in-memory synchronous encoder is as follows: Figure 5 As shown, it includes: a calculation control module, a reserved data check bit generator, an updated data check bit generator, a check bit generator, and a check bit error correction module; The calculation control module is used to read the data to be updated from the memory bank. The data position to be updated is 0, thus retaining the data. and utilize data and its check bits Calculate the parity-check matrix ; The calculation control module is also used to utilize the in-memory error correction module to process the data. and its check bits Error correction is performed on the in-memory error-correcting codewords to obtain the corrected data bits. And record the accompanying expressions generated during the error correction process; Reserved data parity bit generator, used to utilize the parity matrix Calculate retained data check bits ; Update the data checksum generator to utilize the checksum matrix. Calculate new data check bits ; Check bit generator, used to generate check bits And check bits XORing yields the uncorrected check bits. ; The check bit correction module is used to correct the syntactic error and the uncorrected check bit. Perform an XOR operation to obtain the corrected check bit. ; The calculation control module is also used to utilize new data. For the corrected data bits After the update, along with the corrected checksum... They are written together into the memory database to complete the read, modify, and write operations.
[0052] Its working principle is as follows: During the RMW process, the old data is decoded and the new data is encoded simultaneously to ensure that the parity bit is updated synchronously, thereby avoiding the accumulation of delays caused by traditional serial operations.
[0053] Through the collaborative work of the above modules, this embodiment adopts a parallel mechanism in the detection and error correction processes, which significantly reduces latency and redundancy overhead.
[0054] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A cooperative parallelization error correction method for DRAM, characterized in that, include: At the DRAM chip level, for data block D and its parity bits read from the memory bank, a preset in-memory error correction code is used to perform error detection on the codeword composed of data block D and its parity bits. If an error is detected in data block D, a codeword of length [length missing] is generated at the DRAM chip level. A pseudo-random number is generated and injected into the sub-block containing the error at the DRAM chip, resulting in data block D'. Data block D' is then sent to the memory controller. In the DRAM chip, each memory array block is divided into one or more fixed-length sub-blocks. The length of the sub-block; In the memory controller, after receiving multiple data blocks from the DRAM chip, they are combined into RS erasure codewords of a preset length; pseudo-random numbers are identified as known errors by comparing pseudo-random numbers in the RS erasure codewords; RS erasure codes are used to correct the known errors and the remaining unknown errors in the RS erasure codewords, thus completing error correction. In the memory controller, a new pseudo-random number is generated each time a pseudo-random number comparison is successful, and the first pseudo-random number is generated. i The second generated pseudo-random number and the first in the DRAM chip i The generated pseudo-random numbers are the same; i= 1,2……。 2. The cooperative parallelization error correction method for DRAM as described in claim 1, characterized in that, 。 3. The cooperative parallelization error correction method for DRAM as described in claim 1 or 2, characterized in that, Also includes: While identifying known errors in RS erasure code codewords through pseudo-random number comparison, the locations of these known errors are recorded, resulting in a set of error locations. While using RS erasure coding to correct known errors and remaining unknown errors in RS erasure codewords, the location of the errors is recorded, resulting in a set of error locations. ; For the set of error locations and the set of error locations Perform cross-validation, if If so, a warning message is sent to the CPU indicating potential silent data corruption.
4. The cooperative parallelization error correction method for DRAM as described in claim 1 or 2, characterized in that, This also includes performing read-modify-write operations according to the following steps: Read the data to be updated from the memory library. and its check bits Then, the data The data position to be updated is 0, thus retaining the data. and utilize data And check bits Calculate the parity-check matrix ; Using in-memory error correction codes to correct data and its check bits Error correction is performed on the in-memory error-correcting codewords to obtain the corrected data bits. And record the accompanying expressions generated during the error correction process; Using the check matrix Calculate the retained data separately check bits and new data check bits XORing the two yields the uncorrected check bits. ; The syndrome is compared with the uncorrected check bit. Perform an XOR operation to obtain the corrected check bit. ; Utilizing new data For the corrected data bits After the update, along with the corrected checksum... They are written together into the memory database to complete the read, modify, and write operations.
5. A cooperative parallel error correction device for DRAM, characterized in that, include: The in-memory error correction module, the first pseudo-random number generator, the pseudo-random number injector, and the first data transmission module are deployed on the memory side, and the second data transmission module, the second pseudo-random number generator, the pseudo-random number recognizer, and the RS erasure coding module are deployed on the memory controller. The first pseudo-random number generator is used to generate pseudo-random numbers at the DRAM chip level, and the second pseudo-random number generator is used to generate pseudo-random numbers in the memory controller. First pseudo-random number generator and second pseudo-random number generator i The generated pseudo-random numbers are the same. i= 1,2……; The in-memory error correction module is used to perform error detection on the data block D read from the memory bank and the codeword composed of its check bits using a preset in-memory error correction code; The memory injector is used to trigger the first pseudo-random number generator to generate a number of length [value missing] at the DRAM chip when the memory error correction module detects an error in data block D. The pseudo-random number generator generates a pseudo-random number, and injects the pseudo-random number generated by the first pseudo-random number generator into the sub-block where the error occurs, thus obtaining data block D'; in the DRAM chip, each memory array block is divided into one or more fixed-length sub-blocks. The length of the sub-block; The first data transmission module is used to transmit data from the DRAM chip to the memory controller; The second data transmission module is used to receive data from the DRAM chip, and after receiving multiple data blocks from the DRAM chip, it combines them into RS erasure codewords of a preset length; The pseudo-random number identification module is used to compare the sub-blocks in the RS erasure code codeword with the pseudo-random numbers generated by the second pseudo-random number generator in order to identify the pseudo-random numbers in the RS erasure code codeword and to treat the identified pseudo-random numbers as known errors. Each time a pseudo-random number comparison is successful, the pseudo-random number identification module will trigger the second pseudo-random number generator to generate a new pseudo-random number; The RS erasure coding module is used to correct known errors and remaining unknown errors in RS erasure codewords using RS erasure coding, thereby completing error correction.
6. The cooperative parallelization error correction device for DRAM as described in claim 5, characterized in that, The in-memory error correction module includes: an adjoint generator, an adjoint decoder, and an error correction module; The accompaniment generator is used to generate the accompaniment required for decoding; The adjoint decoder is used to detect error locations in the adjoint detection data generated by the adjoint generator; The error correction module is used to correct errors in the data; The pseudo-random number injector includes: a first bitwise OR logic unit, a first NAND gate, a first comparator, a second bitwise OR logic unit, an AND gate, a second NAND gate, and a tri-state gate; The first OR logic unit has its input terminal connected to the output terminal of the complication generator, and is used to perform a bitwise OR operation on the complication generated by the complication generator; The first NAND gate has its first input terminal connected to the output terminal of the first bitwise OR logic unit, and its second input terminal connected to the output terminal of the syntactic decoder. It is used to perform NAND operations on the input signal. The first comparator has a first input terminal for receiving data read from a memory block, and a second input terminal connected to the output terminal of the first pseudo-random number generator, which is used to compare each sub-block in the data with the pseudo-random number generated by the first pseudo-random number generator. The second bitwise OR logic unit has its input connected to the output of the first comparator, and is used to perform a bitwise OR operation on the comparison result of each sub-block and the pseudo-random number. The AND gate has its input terminal connected to the output terminal of the second bitwise OR logic unit. It is used to perform a bitwise AND operation on the input signal to obtain an indication signal for indicating whether the sub-block and the pseudo-random number are equal. The second NAND gate has its first input connected to the output of the first NAND gate and its second input connected to the output of the AND gate. It is used to perform a NAND operation on the input signal to obtain a control signal for instructing the first pseudo-random number generator to generate a new pseudo-random number. The tri-state gate has its first input connected to the output of the first NAND gate, its second input connected to the output of the first pseudo-random number generator, and its output is a pseudo-random number used to inject the error into the sub-block.
7. The cooperative parallelization error correction device for DRAM as described in claim 6, characterized in that, The pseudo-random number recognizer includes: a second comparator and a recognition unit; The second comparator has a first input terminal for inputting RS erasure code codewords, and a second input terminal connected to the output terminal of the second pseudo-random number generator, for comparing each sub-block in the RS erasure code codeword with the pseudo-random number output by the second pseudo-random number generator. The identification unit has its input terminal connected to the output terminal of the second comparator and its output terminal connected to the input terminal of the second pseudo-random number generator. When the second comparator successfully compares the data, it identifies the current sub-block location as a known error location and sends a control signal to the second pseudo-random number generator to trigger the second pseudo-random number generator to generate a new pseudo-random number.
8. The cooperative parallelization error correction device for DRAM as described in claim 7, characterized in that, It also includes: an error location comparator deployed on the memory controller; The error location comparator has its first input terminal used to receive a set of error locations. Its second input is used to receive the set of error locations. It is used for the set of error locations. and the set of error locations Perform cross-validation, and If this happens, a warning message is sent to the CPU indicating potential silent data corruption. Among them, the set of error locations Let be the set of error locations recorded when correcting known errors and remaining unknown errors in RS erasure code codewords using RS erasure coding. This is the set of error positions in RS erasure codewords identified through pseudo-random number comparison.
9. The cooperative parallelization error correction device for DRAM as described in any one of claims 5 to 8, characterized in that, Also includes: In-memory synchronous encoder deployed on a memory chip; The in-memory synchronous encoder includes: a calculation control module, a reserved data check bit generator, an updated data check bit generator, a check bit generator, and a check bit error correction module; The computing control module is used to read the data to be updated from the memory library. The data position to be updated is 0, thus retaining the data. and utilize data and its check bits Calculate the parity-check matrix ; The calculation control module is also used to utilize the in-memory error correction module to process the data. and its check bits Error correction is performed on the in-memory error-correcting codewords to obtain the corrected data bits. And record the accompanying expressions generated during the error correction process; The reserved data check bit generator is used to utilize the check matrix. Calculate retained data check bits ; The updated data checksum generator is used to utilize the checksum matrix. Calculate new data check bits ; Check bit generator, used to generate check bits And check bits XORing yields the uncorrected check bits. ; The check bit correction module is used to compare the syndrome with the uncorrected check bit. Perform an XOR operation to obtain the corrected check bit. ; The calculation control module is also used to utilize new data. For the corrected data bits After the update, along with the corrected checksum... They are written together into the memory database to complete the read, modify, and write operations.
10. The cooperative parallelization error correction device for DRAM as described in any one of claims 1 to 3, characterized in that, 。