Integrated circuit bus communication address allocation method

Abstract

A method for allocating an integrated circuit bus address comprises the steps that a master device outputs a notification signal to a plurality of slave devices through a bus, when one slave device of the plurality of slave devices receives the notification signal, the slave device generates a delay time period, detects a signal of a serial data line, and sends the signal to the serial data line; if the serial data line pin is not detected to present the conversion from the high potential to the low potential, the slave device updates the device identification code of the slave device at the end of the delay period, the serial data line pin outputs a low-potential pulse and maintains a low-potential period, and the serial data line pin outputs a low-potential pulse and maintains a low-potential period at the end of the low-potential period. And pulling the signal of the serial data line to a high potential, and detecting the signal of the serial data line.

Description

Technical Field

[0001] This invention relates to a method for allocating communication addresses on an integrated circuit bus of an electronic device, and more particularly to a method for allocating communication addresses when multiple electronic devices share the same integrated circuit bus. Background Technology

[0002] Modern electronic devices can use many different bus systems for communication. Most bus systems and other transmission systems allow multiple electronic devices to transmit data bidirectionally, so different communication addresses must be assigned to the devices. The most well-known of these bus systems or networks is Ethernet. Communication devices in an Ethernet network must have so-called MAC addresses and IP addresses. Communication devices have fixed MAC addresses, while the IP addresses of communication devices are dynamically assigned.

[0003] Another type of bus system is the Inter-Integrated Circuit (I2C) bus, a serial communication bus used to connect motherboards, mobile phones, and embedded systems to low-speed peripheral devices. I2C can be applied to various control architectures, such as the System Management Bus (SMBus), Power Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display Data Channel (DDC), and Advanced Telecom Computing Architecture (ATCA). I2C uses a 7-bit address space but reserves 16 addresses, allowing communication with up to 112 nodes on a single bus. Common I2C buses have different modes depending on the transmission rate: standard mode (100 Kbit / s) and low-speed mode (10 Kbit / s), but the clock frequency can be allowed to drop to zero, representing a pause in communication. The new generation of I2C bus can support more nodes (supporting a 10-bit address space) and faster communication speeds (400 Kbit / s, 3.4 Mbit / s). Traditionally, when there are devices with the same address in an I2C system, the system must add a data multiplexer to increase the number of channels, or use general-purpose input / output (GPIO) hardware to allocate I2C device addresses. When GPIO is insufficient, it will affect I2C address configuration, so a new address configuration method is needed to solve this problem. Summary of the Invention

[0004] This embodiment provides a method for allocating addresses on an Inter-Integrated Circuit (I2C) bus system. The I2C bus system includes a master device, multiple slave devices, and a bus, wherein the master device and the multiple slave devices are coupled to the bus. The method includes the master device outputting a notification signal to the multiple slave devices via the bus. When one of the multiple slave devices receives the notification signal, it sets its serial data line (SDA) pin to receive mode. The slave device generates a delay period during which it detects the pin signal of the SDA pin. If no high-to-low transition is detected on the SDA pin during the delay period, the slave device updates its device identifier at the end of the delay period and switches the SDA pin to output mode, outputting a low-level pulse from the SDA pin and maintaining the low-level period. At the end of the low-level period, the SDA pin is pulled high, switching the SDA pin back to receive mode and detecting the SDA pin.

[0005] The embodiment also provides a method for allocating an integrated circuit bus address for an integrated circuit bus system, the integrated circuit bus system including a master device, multiple slave devices, and a bus, wherein the master device and the multiple slave devices are coupled to the bus. The method includes the master device outputting a notification signal to the multiple slave devices via the bus; when one of the multiple slave devices receives the notification signal, it sets the serial data line pin of the slave device to a receive mode; the slave device generates a delay period, during which it detects the pin signal of the serial data line pin; updates the device identification code of the slave device based on the pin signal detected during the delay period; if the serial data line pin presents a high potential at the end of the delay period, it updates the device identification code of the slave device and switches the serial data line pin of the slave device to an output mode, outputting a low-potential pulse from the serial data line pin and maintaining a low-potential period; at the end of the low-potential period, it pulls the serial data line pin to a high potential, switches the serial data line pin to the receive mode, and detects the serial data line pin.

[0006] The embodiment also provides a method for allocating an integrated circuit bus address for an integrated circuit bus system, the integrated circuit bus system including a master device, multiple slave devices, and a bus, wherein the master device and the multiple slave devices are coupled to the bus. The method includes: the master device outputting a notification signal to the multiple slave devices via the bus; when one of the multiple slave devices receives the notification signal, setting the serial data line pin of the slave device to a receive mode; the slave device generating a delay period during which it detects the pin signal of the serial data line pin; updating the device identification code of the slave device based on the pin signal detected during the delay period; and at the end of the delay period, if the serial data line pin is at a low potential, the slave device generating another delay period during which it detects the pin signal of the serial data line pin. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the integrated circuit bus system architecture in the embodiment.

[0008] Figure 2 yes Figure 1 A schematic diagram of the operating signals of an integrated circuit bus system.

[0009] Figure 3 yes Figure 1 A schematic diagram of the transmission signals and data packets in an integrated circuit bus system.

[0010] Figure 4A and Figure 4B yes Figure 1 A flowchart of the address configuration method for an integrated circuit bus system.

[0011] Figure 5 yes Figure 1 Signal diagram of address configuration method for integrated circuit bus system.

[0012] [Symbol Explanation]

[0013] 100 Integrated Circuit Bus System

[0014] 110 main equipment

[0015] 120, 130 from equipment

[0016] 122, 132 serial data line pins

[0017] 140 and 150 resistors

[0018] SCL serial clock line

[0019] SDA serial data line

[0020] S, P, Todd, Teven, T1 to T4 time periods

[0021] Address bits A0 to A6

[0022] Data bytes from D0 to D7

[0023] ACK confirmation bit

[0024] 400 methods

[0025] Steps S400 to S428

[0026] DLY1, DLY2 Delay Period

[0027] PRD1, PRD2 low-potential pulses

[0028] ID device identification code Detailed Implementation

[0029] Figure 1 This is a schematic diagram of the architecture of the Inter-Integrated Circuit (I2C) system 100 in this embodiment. The I2C system 100 includes a master device 110, slave devices 120 and 130, and resistors 140 and 150. The I2C system 100 uses two bidirectional open-drain lines, including a serial data line SDA and a serial clock line SCL. The serial data line SDA is used to transmit data and address signals, and the serial clock line SCL is used to transmit clock signals. The serial data line SDA and the serial clock line SCL are at a low potential when they are conducting and are floating when they are not conducting, so resistors 140 and 150 are used to pull the potential high. For example, the operating voltage can be 5V, and the resistance values ​​of resistors 140 and 150 can be 1.8kΩ. The bus of the I2C system 100 is wired-AND configured, meaning that when the serial clock line SCL is high, the serial data line SDA has no signal modulation. The master device 110 is used to start signal transmission, generate a clock signal, and terminate signal transmission. Slave devices 120 and 130 are used to receive the clock signal and respond according to the signals transmitted by the master device 110. Each device connected to the bus can be addressed by a unique address and has a master / slave relationship. The master device 110 can act as a master transmitter or a master receiver.

[0030] Figure 2This is a schematic diagram of the operation signals of the integrated circuit bus system 100 in the embodiment. The integrated circuit bus system 100 begins data transmission during the initial period S. At this time, while the serial clock line SCL remains high, the serial data line SDA is pulled low. During period T1, the serial data line SDA sets the first data bit, while the serial clock line SCL remains low. Subsequently, when the potential of the serial clock line SCL rises to a high level (period T2), the data is received by the device. This process repeats continuously, with the data bit of the serial data line SDA switching when the serial clock line SCL is low (periods T1, T3, T4). odd (and so on), and read data when the serial clock line SCL is high (times T2, T4, T... even (And so on). Finally, in the end segment P, when the serial clock line SCL is high, the serial data line SDA is pulled high, representing a stop signal. In other words, the integrated circuit bus system 100 initiates communication by sending a start signal from the master device 110, and the slave devices 120 and 130 enter receive mode after receiving the start signal. Then, the master device 110 sends the address of the target device and read / write information.

[0031] Integrated circuit bus systems typically provide two address modes: 7-bit and 10-bit. Taking the 7-bit mode as an example... Figure 3This is a schematic diagram of the transmission signals and data packets in the 7-bit address mode of the embodiment. The front end of the data packet contains a 7-bit communication target device address (A0 to A6) and a one-bit read / write information. The slave device with this address will send an acknowledgment bit ACK. An acknowledgment bit ACK=0 indicates successful setup (the slave device pulls the serial data line SDA low), and then data transmission begins. When the serial clock line SCL is high, the signal of the serial data line SDA remains unchanged. The serial data line SDA can only be changed when the serial clock line SCL is low. The data transmission process transmits one byte of data at a time. Each byte (D0 to D7) in the data packet is followed by an acknowledgment bit ACK. When transmitting the acknowledgment bit ACK, the master device 110 will release the bus. At this time, the slave device must pull the serial data line SDA low; otherwise, the master device 110 will issue a stop signal or resend a start signal. Between each byte, the slave device can pull the serial clock line SCL low to force a pause in transmission. However, when there are slave devices with the same address on the integrated circuit bus system 100, the integrated circuit bus system 100 must add a data multiplexer to increase the number of channels, or use general-purpose input / output (GPIO) on the hardware to allocate device addresses of the integrated circuit bus system 100. Therefore, the embodiment proposes another address configuration method to solve this problem by assigning a unique device identification code (ID) to each slave device.

[0032] Figure 4A and Figure 4B This is a flowchart of an address configuration method 400 for an integrated circuit bus system 100 in this embodiment. Method 400 includes the following steps:

[0033] S400: The process begins, and the values ​​of the device identification codes of all devices 120 and 130 are reset to zero;

[0034] S402: The master device 110 transmits a notification signal to all slave devices 120 and 130 connected to the bus via the bus;

[0035] S404: Switch serial data line pins 122 and 132 of devices 120 and 130 to receive mode;

[0036] S406: A delay period occurs after receiving signals from devices 120 and 130;

[0037] S408: Taking slave device 120 as an example, slave device 120 detects the serial data line signal during the delay period;

[0038] S410: Does the slave device 120 detect that the serial data line signal has been pulled low? If yes, proceed to step S411; if no, proceed to step S412.

[0039] S411: Increment the value of the device identification code of device 120 by 1, and return to step S408;

[0040] S412: Has the delay period of device 120 ended? If yes, proceed to step S413; otherwise, return to step S408.

[0041] S413: Does the slave device 120 detect a low level serial data line signal? If yes, return to step S406; if no, proceed to step S414.

[0042] S412: Regenerate the delay period from device 120, and return to step S404;

[0043] S414: Increment the value of the device identification code of device 120 by 1 and switch the serial data line pin 122 of device 120 to output mode;

[0044] S416: Outputs a low-potential pulse with a low-potential period;

[0045] S418: At the end of the low-level period, the serial data line signal of device 120 will be pulled back to a high level;

[0046] S420: Switches the serial data line pin 122 of the slave device 120 to receive mode and detects the serial data line signal;

[0047] S422: Does the slave device 120 detect a low level serial data line signal? If yes, return to step S406; if no, proceed to step S424.

[0048] S424: Device identification code update from device 120 is complete;

[0049] S426: Wait for all slave devices to update their device identification codes or for a preset time without any potential change;

[0050] S428: Process Completed

[0051] Steps S408 to S424 are based on slave device 120 as an example. The same steps can be applied to slave device 130 or other slave devices connected to the bus.

[0052] Figure 5This is a signal diagram of the address configuration method of the integrated circuit bus system 100 in this embodiment. When the integrated circuit bus system 100 is allocating an address, the serial clock line SCL remains at a high level. The master device 110 will issue a command requesting address reallocation. The slave device 120 outputs a low-level pulse PRD1 at the end of the delay period DLY1. The slave device 130 outputs another low-level pulse PRD2 at the end of the delay period DLY2. After the slave devices 120 and 130 successfully output low-level pulses, the slave devices 120 and 130 generate device identification codes and complete the update according to the order in which the low-level pulses are emitted. If the delay periods of the slave devices 120 and 130 are similar and the low-level pulses are emitted at the same time, the one that emits the pulse first takes priority. If the serial data line SDA is already at a low level when a slave device is about to emit a low-level pulse, the slave device will delay the low-level pulse output. If devices 120 and 130 simultaneously send low-level pulses, check if the serial data line SDA remains low after the slave device cancels its low-level pulse. If so, it indicates overlap with another slave device, and the slave device will re-execute the low-level pulse output to confirm there is no overlap with other slave devices. The address arrangement is based on the order in which the low-level pulses are sent; the device that sends the pulse first will receive the smallest address number, and the address numbers for other slave devices will be accumulated and not changed. After all slave devices have been renumbered, slave devices 120 and 130 can communicate with the master device 110 using their corresponding device identification codes. The communication method includes the master device 110 sending a data packet. When slave devices 120 and 130 receive this data packet, they determine whether the device identification code in the data packet corresponds to their own device identification code. If the device identification code in the data packet corresponds to the device identification code of slave device 120, slave device 120 responds according to the content of the data packet; if the device identification code in the data packet corresponds to the device identification code of slave device 130, slave device 130 responds according to the content of the data packet. The device identification code differs from the hardware identification code of slave device 120 or 130. The device identification code can be updated by incrementing, decrementing, or sequentially specifying the address table. The delay periods DLY1 and DLY2 can be a random value, a product serial number, an internal lookup table, a register initial value, or other specified methods.

[0053] In summary, this invention proposes a novel address configuration method that resolves address conflicts arising from devices with the same address on an integrated circuit bus system by assigning a unique device identifier to each slave device. The method described in this invention eliminates the need for a data multiplexer to increase the number of channels and also avoids the need for hardware GPIO to allocate device addresses on the integrated circuit bus system, thus reducing the complexity of hardware design and manufacturing costs.

[0054] In this specification and the scope of the claims, the terminology used is for the purpose of describing specific embodiments of the invention only and should not be construed as limiting the scope of the invention. Unless the context clearly indicates otherwise, the singular forms "a," "the," etc., used in this specification and the scope of the claims should be understood to include their plural forms as well.

[0055] As used herein, the term “and / or” should be interpreted as encompassing any single item or any combination of the listed items. Specifically, when expressions such as “A and / or B” are used, they should be understood to include: (1) A only; (2) B only; and (3) both A and B.

[0056] Furthermore, when the terms "comprising," "including," or "having" are used herein, they should be understood as indicating the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. In other words, these terms should be interpreted as introducing an open-ended enumeration, not a closed-ended enumeration.

[0057] In this document, the terms “coupled,” “connected,” and “electrically connected” are used interchangeably and should be broadly understood to indicate the state of electrical and / or electronic connection. These terms should not be interpreted restrictively but should encompass all forms of electrical or electronic connection. Furthermore, the term “communication” as used in this invention should be understood as a broad concept. Specifically, when describing “communication” between a first entity and a second entity, this means that the first entity is sending and / or receiving information signals to and / or from the second entity electrically (via wired or wireless media). These information signals may include, but are not limited to, voice information, image information, control information, or any combination thereof. It is worth noting that the above definition of “communication” is not limited by signal type and can apply to both analog and digital signals. In other words, as long as there is transmission or reception of electrical messages, regardless of their specific form, it should be considered within the scope of “communication” as described in this invention.

[0058] The illustrative elements, logic, logic blocks, modules, circuits, operations, and algorithm steps described in the various embodiments of the present invention can be implemented by electronic hardware, firmware, software, or any combination thereof. The functional interchangeability of hardware, firmware, and software has been generally described in the various illustrative elements, modules, and circuits described above. The choice of a specific implementation will depend on the constraints of the particular application and the overall system design.

[0059] The hardware and data processing apparatus used to implement the various illustrative components, logic, logic blocks, modules, and circuits described herein may include, but are not limited to: general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices (PLDs), discrete gate or transistor logic, discrete hardware components, or any combination thereof. This hardware and apparatus shall be configured to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration. In some embodiments, specific functions may be performed by dedicated circuitry to optimize performance.

[0060] As previously described, certain aspects of the present invention can be implemented in software. For example, the various functions of the components, or the various blocks or steps of the methods, operations, programs, or algorithms, can be implemented as non-transitory processor-executable instructions or computer-executable instructions in one or more computer program modules. These instructions can be encoded on one or more processor-readable or computer-readable storage media for execution by or control of the operation of a data processing apparatus (including the apparatus components described herein). Such storage media may include, but are not limited to: random-access memory (RAM), read-only memory (ROM), electrically-erasable programmable read-only memory (EEPROM), hard disk storage, optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other medium capable of storing program code in the form of instructions or data structures. Any combination of these storage media should also be considered within the scope of protection of the present invention.

[0061] In the description of the embodiments, the various illustrative elements, logic, logic blocks, modules, circuits, operations, and algorithm steps can be implemented using electronic hardware, firmware, software, or a combination thereof. The functional interchangeability of hardware, firmware, and software has been generally illustrated in the various illustrative elements, modules, circuits, and steps described above. Whether such functionality is implemented via hardware, firmware, or software depends on the specific application and the constraints of the overall system design.

[0062] Some embodiments may include additional features not specifically described herein, while other embodiments may not include undisclosed elements. In other words, undisclosed elements may be selectively omitted. It should be emphasized that the omission of undisclosed elements should be considered as one possible implementation of the invention, rather than a limitation. This allows the invention to be adapted to different application scenarios and technical requirements.

[0063] Although the various features described in this invention may be described within the context of a single embodiment, it should be understood that these features can be combined or separated in various ways to constitute different implementations. Features described in a single embodiment may be integrated into a comprehensive embodiment, implemented separately in multiple independent embodiments, or implemented in any suitable sub-combination. Therefore, the scope of the claims of this invention may include combinations of all features, sub-combinations after removing one or more features, and variations or modifications of these sub-combinations. This flexible structure is intended to provide comprehensive protection and allow for technological development, enabling the invention to adapt to different application needs and technical conditions. The scope of protection of this invention should include, but is not limited to, the explicitly described embodiments, but should also cover all variations, modifications, and sub-combinations consistent with the basic principles of this invention.

[0064] The order of operations described in the various embodiments of the present invention, as illustrated in the accompanying drawings, should not be construed as a restrictive order of execution. The order of these operations can be adjusted according to specific implementations to achieve the desired result without performing all illustrated operations. The scope of the invention also includes inserting additional operations (not illustrated) between the illustrated operations. For example, one or more additional operations may be performed before, after, or simultaneously with any illustrated operation.

[0065] In some implementations, multiplexing or parallel processing techniques may be employed to improve efficiency. Furthermore, the separation of the various system components described in this specification should not be construed as requiring such a division in all implementations. Instead, the described program components and systems may be integrated into a single software suite or multiple software suites depending on specific needs.

[0066] It should be specifically noted that the various schematic diagrams (including but not limited to component diagrams) discussed herein are provided for illustrative purposes only and are not drawn to scale. These diagrams are intended to aid in understanding various aspects of the invention and should not be construed as limiting the scope of the invention.

[0067] Those skilled in the art will readily understand various modifications to the embodiments described herein, and the general principles defined herein can also be applied to other embodiments without departing from the spirit or scope of this document. Therefore, the claims are not limited to the embodiments described herein, but should be given the broadest scope consistent with this document, the principles stated herein, and the novel features disclosed herein.

[0068] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A method for allocating addresses on an integrated circuit bus, used in an integrated circuit bus system, the integrated circuit bus system comprising a master device, multiple slave devices, and a bus, wherein the master device and the multiple slave devices are coupled to the bus, the method comprising: The master device outputs a notification signal to the multiple slave devices via the bus; When a slave device receives the notification signal, it sets the serial data line (SDA) pin of the slave device to receive mode. This delay period is generated by the device; During this delay period, detect the pin signal of the serial data line pin; If no high-to-low transition is detected on the serial data line pin during the delay period, the device identification code of the slave device is updated at the end of the delay period, and the serial data line pin of the slave device is switched to output mode. The serial data line pin outputs a low-level pulse and maintains the low-level period; At the end of this low-potential period, pull the serial data line pin to a high potential; Switch the serial data line pin to the receive mode and detect the signal of the serial data line.

2. A method for allocating addresses on an integrated circuit bus, used in an integrated circuit bus system, the integrated circuit bus system comprising a master device, multiple slave devices, and a bus, wherein the master device and the multiple slave devices are coupled to the bus, the method comprising: The master device outputs a notification signal to the multiple slave devices via the bus; When a slave device receives the notification signal, it sets the serial data line (SDA) pin of the slave device to receive mode. This delay period is generated by the device; Detect the signal on the serial data line during this delay period; The device identification (ID) of the slave device is updated based on the signal detected on the serial data line during the delay period; If the signal on the serial data line is at a high level at the end of the delay period, the device identification code of the slave device is updated, and the serial data line pin of the slave device is switched to output mode. The serial data line pin outputs a low-level pulse and maintains the low-level period; At the end of the low-potential period, the signal on the serial data line is pulled to the high-potential. Switch the serial data line pin to the receive mode and detect the signal of the serial data line.

3. The method of claim 1 or 2, further comprising: If the serial data line pin has a low potential, the slave device will generate another delay period.

4. The method of claim 1 or 2, further comprising: If the serial data line pin has a high potential, the slave device will communicate with the master device using the updated device identification code after the other slave devices of the plurality of slave devices have completed updating the device identification code or after a preset period of time during which there is no potential change on the serial data line pin.

5. The method of claim 4, wherein, The slave device communicates with the master device using its device identification code, including: The master device sends a data packet; When the slave device receives the data packet, it determines whether the device identification code in the data packet corresponds to the updated device identification code of the slave device; and If the device identifier in the data packet corresponds to the updated device identifier of the slave device, then the slave device responds according to the content of the data packet.

6. A method for allocating addresses on an integrated circuit bus, used in an integrated circuit bus system, the integrated circuit bus system comprising a master device, multiple slave devices, and a bus, wherein the master device and the multiple slave devices are coupled to the bus, the method comprising: The master device outputs a notification signal to the multiple slave devices via the bus; When a slave device receives the notification signal, it sets the serial data line (SDA) pin of the slave device to receive mode. This delay period is generated by the device; Detect the signal on the serial data line during this delay period; The device identification (ID) of the slave device is updated based on the signal detected on the serial data line during the delay period; If the signal on the serial data line is at a low level at the end of the delay period, the slave device generates another delay period. The signal on the serial data line is detected during this other delay period.

7. The method of claim 1, 2 or 6 further comprises setting the initial value of the device identification code to 0.

8. The method of claim 2 or 6, wherein updating the device identifier of the slave device based on the signal detected during the delay period comprises: Detect the change in the potential pulse signal from high to low on the serial data line pin; and The device identification code of the slave device is updated according to the number of changes in the potential pulse signal; The device identification code is different from the hardware identification code of the slave device.

9. The method as described in claim 1, 2 or 6, further comprising, after the master device outputs the notification signal to the plurality of slave devices via the bus, the master device records the number of slave devices based on the number of voltage changes from high potential to low potential on the bus.

10. The method of claim 1, 2 or 6, wherein the notification signal output by the master device via the bus is a broadcast signal, a special command, a command string or an I2C-defined general call.

11. The method as described in claim 1, 2 or 6, wherein the delay period is a random value, a product production serial number, an internal lookup table, or a register initial value.

12. The method of claim 1, 2 or 6, wherein the device identifier is specified sequentially according to an incrementing, decrementing or built-in address table.

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