Data transmission module and transmission method from SPI bus to AHB bus

Abstract

The invention discloses a bus control module for converting an SPI bus into an AHB. The bus control module comprises an SPI slave instruction data analysis module, a register module, a mode configuration module, a data transmission cache module, a data detection module and a state detection module, wherein the instruction data analysis module is used for instructions, addresses and data, the register module comprises a plurality of registers used for configuring module functions, and the mode configuration module is used for configuring a transmission mode; according to the invention, the read-write control of the register in the module can be realized through the read-write instruction section, the stability of data transmission is ensured through a dual write protection mechanism, and an external SPI host realizes the read-write of the register in the SOC and the reading and loading of firmware through the SPI bus-to-AHB bus control module, so that the stability of data transmission is ensured. Wherein the firmware is stored in an RAM (Random Access Memory) storage area or a plug-in FLASH storage area in the SOC.

Description

Technical Field

[0001] This invention belongs to the field of communication technology and relates to data transmission, specifically to a data transmission module and method for transmitting data from an SPI bus to an AHB bus. Background Technology

[0002] The SPI (Serial Peripheral Interface) bus is a full-duplex synchronous serial bus developed by Motorola, primarily used for communication between microcontrollers and peripheral devices such as EEPROM, Flash, real-time clocks, and digital-to-analog converters. The SPI bus system uses four signal lines for data transmission: the serial clock line SCK, the master input / slave output data line MISO, the master output / slave input data line MOSI, and the slave select line SSEL, allowing direct adaptation to various standard peripheral devices. The AHB (Advanced High Performance Bus) is an on-chip bus introduced by ARM. The AHB bus is mainly used for connections between high-performance modules (such as CPUs, DMA, and DSPs). As the on-chip system bus of a SoC, it features single-clock-edge operation; non-tri-state implementation; support for burst transmission; support for segmented transmission; and support for multiple master controllers.

[0003] Chinese patent CN202010249408.8 discloses a high-speed SPI device, including an SRAM storage module connected to a host via an AHB bus for loading communication data; and an SPI module connected to the SRAM storage module and connected to a slave device via an SPI bus interface. The SPI module is used to retrieve the required data from the SRAM storage module in a time-division multiplexing manner using ping-pong data transmission operation when the host sends data to the slave device, and continuously send the required data to the slave device.

[0004] Chinese patent CN201920406373.7 discloses a serial bus to AHB bus conversion circuit, where the serial bus refers to I2C, SPI, or UART serial communication protocols. The conversion circuit includes a serial-to-parallel / parallel-to-serial conversion circuit, a synchronous bidirectional FIFO, a packet parsing state machine, and an AHB bus conversion circuit. These components are interconnected in sequence, supporting data read / write of definable lengths, with a maximum support of 127 bytes.

[0005] Chinese patent CN202010268498.5 discloses a dynamic debugging method based on the SPI protocol. The steps include: establishing a communication connection with the host using the SPI protocol and receiving instructions from the host; communicating with the system chip via the AHB protocol and writing or reading data from the system chip according to the instructions sent by the host; and sending the internal information of the system chip to the host after the data writing or information reading is completed.

[0006] In the process of transmitting data from the SPI bus to the AHB bus, the existing technology has limited functionality. For example, it cannot achieve continuous address delivery, data transmission parameter configuration, or automatic read / write detection, resulting in limited application scenarios and failing to meet the needs of different application modes. Summary of the Invention

[0007] In view of the technical defects of the prior art, the present invention discloses a data transmission module and method from SPI bus to AHB bus.

[0008] As described in this invention.

[0009] The data transmission module and method from SPI bus to AHB bus described in this invention are applied in the SOC field. They are flexible, secure, and support multiple application scenarios. Register write protection and write register enable control enable secure register writing to avoid writing illegal values. Inter-bus data transmission is always enabled to ensure data write security and data buffer protection, thus achieving multiple protections to ensure data transmission security.

[0010] This invention can also control data transmission length and select modes through register adjustment. Application scenarios include external SPI host controlling the module via SPI bus to AHB bus to configure SOC internal registers, read and write SOC internal RAM storage area, read and write SOC external FLASH storage area, etc. Through specific instruction data structure, it can realize multiple functional modes and is suitable for a variety of application scenarios. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a specific implementation of the SPI bus to AHB bus data transmission module of the present invention; Figure 2 This is a schematic diagram illustrating a specific embodiment of the register module described in this invention; Figure 3 This is a schematic diagram of a specific embodiment of the state transition diagram of the instruction data parsing module state machine of the present invention; Figure 4 These are schematic diagrams illustrating two specific implementations of the transmission method of the present invention, which performs read and write operations via read and write instructions. Figure 5 This is a flowchart illustrating a specific implementation of the single read / write configuration process described in this invention. Figure 6 This is a flowchart illustrating a specific implementation of the continuous read / write configuration process described in this invention. Detailed Implementation

[0012] To more intuitively and clearly describe the specific details of the technical solution of the present invention, a detailed description will be provided below in conjunction with specific embodiments and example drawings.

[0013] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0014] like Figure 1 As shown, a typical application scenario of the SPI bus to AHB bus data transmission module of the present invention is to connect between the external SPI host and the internal AHB bus of the SOC, including an instruction data parsing module, a register module, a mode configuration module, a data transmission buffer module, a data detection module, and a status detection module.

[0015] The external SPI host transmits signals to the data transmission module from the SPI bus to the AHB bus via the SPI bus. First, the instruction data parsing module parses out the instruction, address, and data information contained in the received signal.

[0016] The parsed instructions determine whether a read or write operation is performed on the register. Taking a write operation as an example, when a write operation is detected, the register module first configures the write protection register reg_protect_r and writes a write protection enable instruction. If the write protection enable instruction written into the write protection register reg_protect_r matches the write protection instruction code pre-stored in the module, then the write enable of the target register inside the module is enabled, thereby realizing the write operation on the register inside the module of this invention. By completing the configuration of the register inside the module, read and write operations on the registers connected to the AHB bus are realized when switching from the SPI bus to the AHB bus.

[0017] The data transmission module from SPI bus to AHB bus controls the reading and writing of registers within the module through the read and write instruction segment in the data. When the SPI slave receives data and parses the write register instruction from the read and write instruction segment, the register configuration segment implements the write operation on the target register. When the read register instruction is parsed, the target register data is read directly. By adding the read and write instruction segment, subsequent registers can be started quickly, and it can be applied to various application scenarios such as reading and writing.

[0018] Then, configure the enable register `bus_wen_r` to match the overall enable signal `passwd`, thus enabling overall data transmission between the data transmission module and the AHB bus. Configure the read / write mode by configuring the read / write control register `ctrl_r`, including settings such as 4-byte read / write, continuous multi-group data read / write, and continuous read / write of FLASH or RAM storage areas. In continuous read / write mode, the length of the continuous read / write data is controlled by configuring the read length register `len_r`. The list of possible registers within the register module is as follows: Figure 2 .

[0019] In this invention, the SPI bus to AHB bus control circuit module implements internal register write protection control and overall transmission enable control. The internal register write protection control function requires first configuring the write protection register reg_protect_r by writing a 16-bit write protection enable instruction. The write protection enable instruction in reg_protect_r matches the 16-bit pre-stored fixed write protection instruction code within the module before enabling write protection of the target register. After write protection is enabled, write operations are performed on other control registers. Then, the enable register bus_wen_r is configured, and a 32-bit overall enable instruction is written to match the module's internal overall enable signal passwd, enabling overall data transmission between the SPI bus and AHB bus. This dual write protection mechanism better ensures the stability and security of data transmission.

[0020] After the register module is configured, the control signal enters the mode configuration module, thereby realizing the functions corresponding to different modes.

[0021] During continuous transmission, a data transmission buffer module is used to prevent data overflow. One specific implementation of the data transmission buffer module is to use a synchronous first-in-first-out (FIFO) memory, which achieves secure transmission with the AHB bus within the SOC through a handshake principle.

[0022] After data transmission is complete, the data detection module automatically checks the number of data transmissions. If the requirement is not met, the status detection module outputs an error detection flag. Whether the status is showing an error detection flag or normal bus transmission, the status flag can be obtained through the status detection module.

[0023] The external host transmits address data to the AHB bus within the SOC via the data transmission module from the SPI bus to the AHB bus described in this invention, thereby enabling the configuration of the SOC's internal registers, read and write operations of the RAM storage module, and read and write operations of the external FLASH storage area.

[0024] Figure 3 This is the state transition diagram of the state machine of the instruction data parsing module described in this invention. The state transition diagram is divided into two stages: the register configuration stage and the data transmission stage.

[0025] During the register configuration phase, read / write judgments are performed on the internal registers of the module, including reading and writing instructions, register addresses, and register data. After the register configuration phase is completed, the data transmission phase begins. Through register configuration, the data transmission mode, read / write operations, and data transmission length can be obtained. Thus, during the data transmission phase, data is transmitted to the SOC internal registers, RAM storage modules, and FLASH storage modules via the AHB bus.

[0026] Specifically, in the state transition diagram, the default initial state is the idle state (IDLE). During the register configuration phase, when the external SPI host pulls down the SPI chip select signal (CS), the state begins to transition, entering the instruction configuration state (CMD). The first byte is the internal register read / write instruction of this invention's module. After instruction configuration is completed in the CMD state, it is determined whether the instruction is a read or write operation of the module's internal register. Then, it enters the register address state (REG_ADDR) to receive the subsequent 4 bytes of the module's internal register address. When the instruction is a write operation, after receiving the module's internal register address, it enters the register write state (REG_WR) to write 4 bytes of register address data and mode parameter data to the module's internal register address, configuring the data transmission mode, read / write operation, and data transmission length required for the register write operation. When the instruction is a read operation, after receiving the module's internal register address, it enters the register read state (REG_RD) to send the required internal register data to the external host in 4-byte format. The system then returns to the idle state (IDLE), and the register configuration phase ends.

[0027] During the data transmission phase, when the external SPI host pulls the SPI chip select signal CS low, it detects that the configuration phase of the module's register has completed the configuration of the data transmission mode, read / write operation, and data transmission length between the module and the AHB bus. The state then transitions to the bus address state ADDR, receiving a 4-byte SOC internal AHB bus address. When configured for a write SOC operation during the register configuration phase, after receiving the SOC internal AHB bus address, it enters the SOC write state WDATA, writing data to the SOC internal AHB bus address until the external SPI host pulls the CS signal high. When the module's register is configured for a read SOC operation, after receiving the SOC internal AHB bus address, it enters the SOC read state RDATA, sending the data corresponding to the SOC internal AHB bus address to the external host until the external SPI host pulls the CS signal high, returning to the idle state IDLE.

[0028] For the SPI bus to AHB bus data transmission module described in this invention, internal register configuration and data transmission are implemented through a fixed configuration process. Read / write instructions are used to determine register read / write operations, thereby performing read / write operations on the target address register, such as... Figure 4 The diagram illustrates two specific implementation methods. The first line describes the operation as follows: Upon receiving instruction 1C, it is determined to be a write register operation. The register address is parsed, and register data is written to the register at the corresponding address. The second line describes the operation as follows: Upon receiving instruction 3B, it is determined to be a read register operation. The register address is parsed, and register data is read from the register at the corresponding address.

[0029] The data transmission module from the SPI bus to the AHB bus described in this invention can realize a single read / write configuration process, the specific process of which is as follows: Figure 5 As shown, without continuous read / write mode configured, the default single read / write mode is used. Upon receiving instruction 1C, it is determined to be a register write operation. The register address is parsed, and a 32-bit write operation and a 32-bit read operation are performed on the corresponding register. The 32-bit write operation writes 32 bits of data to the internal register address sent by the external host, thus configuring the internal registers of the module. The 32-bit read operation reads 32 bits of data from the internal register address sent by the external host, thus comparing the data in the internal registers of the module to determine if the data written by the external host to the internal registers of the module is correct.

[0030] The difference between continuous read / write mode and single read / write mode is the use of continuous write operations and continuous read operations, continuously writing and reading data into and from the address. The specific process is as follows: Figure 6 As shown.

[0031] For continuous read / write mode, the SPI bus to AHB bus control circuit module of this invention implements mode configuration and data transmission through a fixed configuration process. First, it completes the configuration of write protection for internal registers and the overall enable for data transmission. Then, it selects the transmission mode and enables write access by configuring the read / write control register ctrl_r, and configures the continuous data transmission length by configuring the read length register len_r. For FLASH mode, which performs read / write operations on FLASH, since the address is fixed, the AHB bus only needs to access the transmit data register TXDATA and receive data register RXDATA in the SPI module. The transmit data register TXDATA is used to send data to the FLASH, and the receive data register RXDATA is used to receive data sent by the FLASH. Therefore, when performing read / write operations on FLASH, it is only necessary to operate on the transmit data register TXDATA and receive data register RXDATA in the SOC's internal registers. For RAM mode, this mode continuously writes 32 bits of data to continuously incrementing addresses.

[0032] For SOC systems, the SPI bus to AHB bus data transmission module of the present invention achieves better secure data transmission of the module through the write protection control function and the all-enable control configured in the register, avoiding the impact of accidental writing on normal data transmission function.

[0033] In the module configuration process of this invention, in addition to reading and writing registers separately through the register read / write instruction segment and the register configuration segment, the SPI bus transmission signal is sequentially connected by the register read / write instruction segment, the register configuration segment, and the data transmission segments of different modes. This implementation method is better suited for data transmission scenarios with multiple mode selection.

[0034] In this invention, the SPI bus to AHB bus control circuit module implements internal register write protection control and overall transmission enable control. The internal register write protection control function requires first configuring the write protection register reg_protect_r by writing a 16-bit write protection enable instruction. The write protection enable instruction in reg_protect_r matches the 16-bit pre-stored fixed write protection instruction code within the module before enabling write protection of the target register. After write protection is enabled, write operations are performed on other control registers. Then, the enable register bus_wen_r is configured, and a 32-bit overall enable instruction is written to match the module's internal overall enable signal passwd, enabling overall data transmission between the SPI bus and AHB bus. This dual write protection mechanism better ensures the stability and security of data transmission.

[0035] The data transmission module from the SPI bus to the AHB bus can read and write the internal RAM storage area and the external FLASH of the SOC by configuring the internal registers of the SOC, so as to realize the configuration of different functions and the switching of different modes.

[0036] This invention implements a fixed, complete, and coherent configuration data stream, which includes: a register read / write instruction segment, a register configuration segment, and data transmission segments in different modes. The data transmission segments determine the data transmission modes implemented according to the functional configuration of the register configuration segment, including a non-contiguous 32-bit data transmission mode, a continuous RAM read / write mode, and a continuous FLASH read / write mode.

[0037] The data transmission module and method from SPI bus to AHB bus described in this invention are applied in the SOC field. They are flexible, secure, and support multiple application scenarios. Register write protection and write register enable control enable secure register writing to avoid writing illegal values. Inter-bus data transmission is always enabled to ensure data write security and data buffer protection, thus achieving multiple protections to ensure data transmission security.

[0038] This invention can also control data transmission length and select modes through register adjustment. Application scenarios include external SPI host controlling the module via SPI bus to AHB bus to configure SOC internal registers, read and write SOC internal RAM storage area, read and write SOC external FLASH storage area, etc. Through specific instruction data structure, it can realize multiple functional modes and is suitable for a variety of application scenarios.

[0039] The foregoing descriptions are preferred embodiments of the present invention. Unless there is a clear contradiction between the preferred embodiments or a prerequisite for a particular preferred embodiment, the preferred embodiments can be arbitrarily combined and used. The embodiments and specific parameters described are only for clearly illustrating the inventor's invention verification process and are not intended to limit the patent protection scope of the present invention. The patent protection scope of the present invention is still determined by its claims. Similarly, any equivalent structural changes made based on the content of the specification of the present invention should also be included within the protection scope of the present invention.

Claims

1. A data transmission module from SPI bus to AHB bus, characterized in that, It includes an instruction data parsing module, a register module, a mode configuration module, a data transfer buffer module, a data detection module, and a status detection module; The instruction data parsing module is used to parse the received signals; the register module is used to configure the parsed instructions; the mode configuration module is used to configure different modes; the data transmission buffer module is used to buffer data in continuous transmission mode; the data detection module is used to detect whether the data transmission is correct; and the status detection module is used to output the current status.

2. The data transmission module from SPI bus to AHB bus as described in claim 1, characterized in that, The register module includes: an enable register for enabling overall data transmission; a read / write control register for configuring read / write modes; a write protection register for determining and initiating write protection enable instructions; and a read length register for configuring the length of continuous read / write data in continuous read / write mode.

3. The data transmission module from SPI bus to AHB bus as described in claim 1, characterized in that, The instruction data parsing module adopts a state machine structure. The state diagram includes an idle state, an instruction configuration state, and a register address state connected in logical order. The register address state is also connected to a register write state and a register read state. The state diagram also includes a bus address state connected to the idle state, and the bus address state is also connected to the SOC write state and the SOC read state; all other states in the state machine except the idle state can directly return to the idle state.

4. A data transmission method from SPI bus to AHB bus, characterized in that, Based on the data transmission module of claim 1, the following steps are included: Step 1. The external SPI host transmits signals to the data transmission module from the SPI bus to the AHB bus via the SPI bus, and the instruction data parsing module parses out the instruction, address and data information contained in the received signal; Step 2. The instruction data parsing module configures the register module based on the parsed information; Step 3. Based on the parsed information, the mode configuration module implements the functions corresponding to different modes; Step 4. Perform data transmission.

5. The data transmission method as described in claim 4, characterized in that, Step 2 specifically includes: Configure the write protection register according to the parsed instructions; Configure the enable register to match the global enable signal to enable the signal; Configure the read / write control register to set the read / write mode; In continuous read / write mode, configure the read length register to set the continuous read / write data length.

6. The data transmission method as described in claim 5, characterized in that, The configuration of the write protection register specifically involves: writing a write protection enable instruction to the write protection register, and checking whether the write protection enable instruction in the write protection register matches the pre-stored fixed write protection instruction code. If they match, the write enable of the target register is enabled, and then write operations are performed on other control registers after the write enable is enabled; if they do not match, the data transmission is terminated.

7. The data transmission method as described in claim 4, characterized in that, In step 1, the SPI bus transmission signal is composed of the register read / write instruction segment, the register configuration segment, and the data transmission segment of different modes connected in sequence.

8. The data transmission method as described in claim 4, characterized in that, In step 4, after data transmission is completed, the data detection module automatically detects the number of data transmissions. If the requirement is not met, the status detection module outputs an error detection flag. Whether the status is showing an error detection flag or normal bus transmission, the status flag can be obtained through the status detection module.

9. The data transmission method as described in claim 4, characterized in that, The specific operating modes of the instruction parsing module in steps 1 and 2 are as follows: When the external SPI master pulls the SPI chip select signal low, the state begins to transition and enters the instruction configuration state. After the instruction configuration is completed in the instruction configuration state, it is determined whether the instruction is a read operation or a write operation of the module's internal register. Then, it enters the register address state and receives the module's internal register address for the subsequent read / write instruction. When the instruction is a write register operation, after the module's internal register address is received, it enters the register write state and writes the register address data to the module's internal register address; when the instruction is a read register operation, after the module's internal register address is received, it enters the register read state and sends the module's internal register data to be read to the external host. The system returns to an idle state, and the register configuration phase ends.

10. The data transmission method as described in claim 4, characterized in that, The data transmission process in step 4 is as follows: When the external SPI host pulls the SPI chip select signal low, the state transitions to the bus address state, and the internal AHB bus address of the SOC is received. When configured for a write SOC operation, the SOC write state is entered, and data is written to the internal AHB bus address of the SOC until the external SPI host pulls the SPI chip select signal high. When the module register of this invention is configured for a read SOC operation, after the internal AHB bus address of the SOC is received, the SOC read state is entered, and the data corresponding to the internal AHB bus address of the SOC is sent to the external host until the external SPI host pulls the SPI chip select signal high, and the system returns to the idle state.

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