An argmax in-memory computing system based on memristors

Abstract

This invention discloses an in-memory argmax calculation system based on memristors, belonging to the field of integrated circuit technology. It includes an n x m 1T1R array, a WTA circuit, and m one-step readout and comparison modules. Each one-step readout and comparison module includes a voltage clamping circuit, an NMOS current mirror, and a PMOS current mirror. Considering hardware limitations, when the binary number in the vector to be compared is less than or equal to a preset number, the vector to be compared is stored column-wise by the 1T1R array. The reference voltage clamp accurately reads the column current, the current mirror scales the column current proportionally, and the WTA circuit compares different column currents in one step, enabling fast, efficient, and low-power one-step readout of the comparison result. This invention integrates current clamping readout, scaling, and comparison within the same readout cycle, avoiding multi-cycle operations and intermediate data buffering, improving computational efficiency, reducing system latency, and eliminating the need for complex external circuits, resulting in low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and more specifically, relates to an argmax in-memory computing system based on memristors. Background Technology

[0002] Traditional computer systems generally employ the von Neumann architecture, where storage and processing units are physically separated. Frequent data transfers between these units during computation significantly increase bus load and power consumption, creating the so-called "von Neumann bottleneck" and "memory wall" problems. With the rapid development of artificial intelligence and big data applications, the demands for high throughput, low latency, and low power consumption in computing systems are constantly increasing, highlighting the shortcomings of traditional architectures in terms of energy efficiency and parallelism. Therefore, in-memory computing technology, which performs computations directly within storage units, reducing data transfer overhead, has become an important research direction in the field of computing architecture.

[0003] Memristors, as a novel type of non-volatile memory device, possess advantages such as simple structure, low power consumption, small size, and good compatibility with CMOS processes, and are widely used in in-memory computing systems. In memristor-based in-memory computing architectures, the weights and intermediate computation results of neural networks are typically stored in a memristor array in the form of resistive states. Vector-matrix operations or vector accumulation operations can be performed through parallel readouts. A column or row in the memristor array can represent a high-dimensional vector, and parallel readouts of multiple columns can simultaneously obtain the computation results of multiple vectors, making it naturally suitable for large-scale parallel computing tasks in neural networks.

[0004] However, in existing technologies, neural network inference processes commonly require comparing multiple result vectors and determining the maximum value (i.e., argmax in-memory computation), in applications such as classification decisions, competition mechanisms, or attention selection. Existing argmax in-memory computation schemes typically require reading each column of results multiple times and using analog-to-digital conversion circuits or multi-stage comparison circuits to perform step-by-step comparisons. This not only increases system latency and power consumption but also introduces complex peripheral circuits, limiting the performance advantages of in-memory computation architectures in neural network applications. Summary of the Invention

[0005] To address the aforementioned deficiencies or improvement needs of existing technologies, this invention provides an in-memory argmax computation system based on memristors, which solves the technical problems of complex peripheral circuits, high system latency, and high power consumption in existing in-memory argmax computation schemes during neural network inference.

[0006] To achieve the above objectives, this invention provides an in-memory argmax calculation system based on memristors, used to determine the maximum value of m vectors to be compared; each vector to be compared includes n binary numbers; m and n are both positive integers; the n x m matrix formed by the m vectors to be compared is denoted as matrix . ;

[0007] The aforementioned argmax in-memory computing system includes: a one-step readout and comparison circuit and a controller; the one-step readout and comparison circuit includes: an n x m 1T1R array, a WTA circuit, and m one-step readout and comparison modules; the WTA circuit includes m sets of one-to-one corresponding input terminals and output terminals; the input terminals of the m one-to-one ...

[0008] The controller is used when n is less than or equal to a preset number. At that time, the 1T1R array is used as a matrix. The corresponding operation array, for the matrix Perform a comparison operation on the corresponding operation array: select each memristor in the operation array, and set the matrix... Each binary number in the array is stored in the corresponding memristor of the corresponding operation array in the form of an analog quantity. A driving voltage is applied to each BL line of the corresponding operation array, so that the memristor in the corresponding operation array generates a current proportional to its stored value. The current is then aggregated on the corresponding column and output to the corresponding one-step readout and comparison module.

[0009] The one-step readout and comparison module includes: voltage clamping circuit, NMOS current mirror, and PMOS current mirror;

[0010] The voltage clamping circuit is used to clamp the voltage at the connected column output terminal to a preset reference voltage. At the same time, it receives current from the corresponding column output terminal and inputs it into the NMOS current mirror;

[0011] The NMOS current mirror is used to scale the current input from the voltage clamping circuit proportionally and then input it to the corresponding input terminal of the WTA circuit via the PMOS current mirror.

[0012] The WTA circuit is used to compare the magnitudes of the currents input to its m input terminals, and outputs a high-level signal at the output terminal corresponding to the maximum current, and outputs a low-level signal at the other output terminals.

[0013] More preferably, the controller is used when n is greater than a preset number. When this happens, perform the following operations:

[0014] Initialization operation: Initializes the current matrix to a matrix. ;

[0015] Intermediate operation: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of submatrices obtained from the current partitioning. Divide the N rows of the 1T1R array into k groups according to the same partitioning method, thus dividing the 1T1R array into k operation arrays corresponding one-to-one with the k submatrices. Perform comparison operations on the corresponding operation array for each submatrix, read the signals output from each output terminal of the WTA circuit, and map them into binary numbers respectively to obtain a binary number vector. A total of k binary number vectors are obtained, forming a matrix of k rows and m columns. High-level signals are mapped to the binary number 1; low-level signals are mapped to the binary number 0.

[0016] Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. If necessary, re-execute the intermediate operations and judgment operations in sequence; otherwise, select a subarray with k rows and m columns from the 1T1R array as the matrix. The corresponding operation array, for the matrix Perform the comparison operation on the corresponding operand array.

[0017] More preferably, the number of the above-mentioned readout and comparison circuits is multiple;

[0018] The controller is used when n is greater than a preset number. When this happens, perform the following operations:

[0019] Initialization operation: Initializes the current matrix to a matrix. ;

[0020] Intermediate operation: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of sub-matrices obtained from the current partitioning; select k one-step readout and comparison circuits, and make them correspond one-to-one with the k sub-matrices; for each sub-matrix, select a sub-array of the same size as the sub-matrix from the 1T1R array in the corresponding one-step readout and comparison circuit as the corresponding operation array; simultaneously select each memristor in the operation array corresponding to each sub-array, store each binary number in the sub-array in the form of analog quantity in the memristor of the corresponding operation array, and simultaneously apply a driving voltage on each BL line of each operation array, so that the memristor in the corresponding operation array generates a current proportional to its stored value, and after being aggregated on the corresponding column, output to the corresponding one-step readout and comparison module; read the signals output from each output terminal of the WTA circuit in the selected k one-step readout and comparison circuits, and map them into binary numbers respectively to obtain k binary number vectors, which form a matrix of k rows and m columns. High-level signals are mapped to the binary number 1; low-level signals are mapped to the binary number 0.

[0021] Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. If necessary, re-execute the intermediate operations and judgment operations in sequence; otherwise, select a one-step readout and comparison circuit, and select a k-row, m-column subarray from the 1T1R array in that one-step readout and comparison circuit as the matrix. The corresponding operation matrix, for the matrix Perform the comparison operation on the corresponding operand array.

[0022] More preferably, the m vectors to be compared are the m vectors output by a preset target layer in a pre-trained target neural network;

[0023] The training objectives of the target neural network include: when n is greater than a preset number At that time, minimize the difference loss obtained by performing direct comparison decision and split comparison decision on the m comparison vectors output by the preset target layer after inputting the training samples into the target neural network;

[0024] Here, the m vectors to be compared, output by the target layer after the training samples are input into the target neural network, are represented as a matrix. The results obtained by directly comparing the decision are obtained by analyzing the matrix. The results were obtained through comparison and judgment.

[0025] The method for comparing and deciding on any matrix M includes: summing the matrix M along the column direction to obtain m sums; comparing the m sums to obtain an m-dimensional vector vec, which serves as the result of the comparison and decision on matrix M; the element in the vector vec corresponding to the position of the maximum sum is 1, and the rest are 0;

[0026] The result obtained after splitting and comparing the decision is obtained in the following way:

[0027] Initialization: Initializes the current matrix to a matrix. ;

[0028] Splitting and intermediate comparison operations: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of submatrices obtained from the current partition; compare and decide on each submatrix to obtain the corresponding intermediate vector; construct a k-row, m-column matrix from the intermediate vectors corresponding to the k submatrices. ;

[0029] Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. Then, re-execute the splitting, intermediate comparison, and discrimination operations sequentially; otherwise, for the matrix... The comparison decision is used to obtain the result after splitting the comparison decision.

[0030] More preferably, the voltage clamping circuit includes: an operational amplifier and an NMOS transistor. The positive input terminal of the operational amplifier is used to connect a preset reference voltage. The negative input terminal is connected to the NMOS transistor. The source of the transistor is connected to the voltage clamping circuit and serves as the input to the corresponding one-step readout and comparison module. The output is connected to the NMOS transistor. The gate of the NMOS transistor is connected to the gate of the NMOS transistor. The drain of the circuit is used as the output terminal of the voltage clamping circuit.

[0031] More preferably, the above-mentioned NMOS current mirror includes: an NMOS transistor. and NMOS transistor NMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, NMOS transistor The gate and NMOS transistor The gate of the NMOS transistor is connected to the NMOS transistor and serves as the input terminal of the NMOS current mirror; the NMOS transistor... and NMOS transistor The source is used to connect to a low flat voltage. The drain serves as the output terminal of the NMOS current mirror; NMOS transistor The size is an NMOS transistor The size is y times the value of the current mirror, used to scale the current at the input of the NMOS current mirror by a factor of y; y is a positive number.

[0032] More preferably, the value of y ranges from 1 to 100.

[0033] More preferably, the PMOS current mirror includes: a PMOS transistor. and PMOS transistor PMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, PMOS transistor The gate and PMOS transistor The gate of the PMOS transistor is connected to the PMOS transistor and serves as the input terminal of the PMOS current mirror. and PMOS transistor The source is used to receive high-level signals. PMOS transistor The drain of the PMOS current mirror and the corresponding one-step readout and comparison module are connected to the corresponding input terminal of the corresponding WTA circuit.

[0034] More preferably, the WTA circuit comprises: m identical WTA units;

[0035] The WTA unit includes: NMOS transistors , , , , , , , and PMOS transistor , , , ;

[0036] NMOS transistor The drain of the transistor serves as the input terminal of the WTA cell, and is connected to the NMOS transistor respectively. , , The deletion of the poles is connected;

[0037] PMOS transistor The gates of the PMOS transistors are respectively connected to the gates of the PMOS transistors. drain, PMOS transistor Gate, NMOS transistor drain, NMOS transistor The drains of the PMOS transistors are connected, and the connection point serves as a common node. The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, NMOS transistor drain, PMOS transistor The gates are connected, and the connection point is denoted as point X;

[0038] PMOS transistor and NMOS transistor The drains of the PMOS transistors are connected to form an inverter. NMOS transistor The gate of the PMOS transistor is connected to point X. and NMOS transistor The connection point of the drain electrode serves as the output terminal of the WTA unit;

[0039] PMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. Gate and drain of NMOS transistor gate, NMOS transistor gate, NMOS transistor The drains are connected;

[0040] PMOS transistor PMOS transistor PMOS transistor NMOS transistor The sources are all used to connect to high-level signals. NMOS transistor , , , , , , , The source electrode is used for grounding;

[0041] NMOS transistor The gate is used to receive control signals; when the control signal is high, the WTA unit is reset and outputs a low-level signal; when the control signal is low, the WTA unit is in the working state.

[0042] In a WTA circuit, the common nodes of all WTA units are connected;

[0043] The m input terminals of the WTA circuit are the input terminals of the m WTA units in the WTA circuit, and the m output terminals of the WTA circuit are the output terminals of the m WTA units in the WTA circuit.

[0044] More preferably, This represents the maximum number of memristors that can be distinguished in a column of memristors in a memristor array during a single comparison operation, after considering non-ideal factors of the memristor array.

[0045] More preferably, the 1T1R array is manufactured using SMIC 55nm process; .

[0046] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0047] 1. This invention provides an in-memory argmax calculation system based on memristors, comprising: an n x m 1T1R array, a WTA circuit, and m one-step readout and comparison modules; each one-step readout and comparison module includes: a voltage clamping circuit, an NMOS current mirror, and a PMOS current mirror; considering hardware limitations, the binary number in the vector to be compared is less than or equal to a preset number. The system stores the comparison vectors column-wise using a 1T1R array, clamps the column current with a reference voltage to accurately read it, scales the column current proportionally using a current mirror, and compares the different column currents in one step using a WTA circuit. This allows for a fast, efficient, and low-power one-step reading of the comparison results. Unlike existing technologies that execute current reading and comparison as separate peripheral modules in a serial manner, this invention integrates current clamping, reading, scaling, and comparison within the same readout cycle. This avoids multi-cycle operations and intermediate data buffering, improves computational efficiency, reduces system latency, and eliminates the need for complex external circuits, resulting in lower power consumption.

[0048] 2. Furthermore, the argmax in-memory calculation system provided by this invention can handle situations where the binary number in the vector to be compared is greater than a preset number. To address this, a recursive hierarchical comparison mechanism driven by an upper limit n0 is introduced to achieve a scalable implementation of the argmax operation. Through step-by-step encoding and compression, the complexity and power consumption of subsequent comparison stages are significantly reduced. Furthermore, within the same comparison level, the comparison operations of each subgroup can be executed in parallel or serially. Parallel execution further improves computational efficiency, while serial execution reuses the same readout and comparison circuit, resulting in a smaller circuit size. Simultaneously, the architecture of this invention is decoupled from the specific WTA circuit implementation, making it suitable for memristor arrays of different sizes; it is also suitable for vector comparison and maximum value determination tasks in large-scale neural network inference.

[0049] 3. Furthermore, in the argmax in-memory computation system provided by the present invention, the m vectors to be compared are the m vectors output by the target layer of the target neural network, and during the training phase of the target neural network, constraints are imposed on the arrangement of the binary data in the m vectors output by the target layer of the target neural network, so that the comparison results of each subgroup can consistently reflect the relative size relationship between the vectors to be compared, thereby further improving the accuracy of argmax in-memory computation. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the structure of the argmax in-memory computing system based on memristors provided in an embodiment of the present invention.

[0051] Figure 2 This is a schematic diagram of the structure of a memristor provided in an embodiment of the present invention.

[0052] Figure 3 This is a schematic diagram of the structure of the one-step readout and comparison module provided in an embodiment of the present invention.

[0053] Figure 4 This is a schematic diagram of the structure of the WTA unit provided in an embodiment of the present invention.

[0054] Figure 5 The data size of the vector to be compared, as provided in the embodiments of the present invention, exceeds A schematic diagram of the in-memory calculation process of argmax. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0056] To achieve the above objectives, this invention provides an in-memory argmax calculation system based on memristors, used to determine the maximum value of m vectors to be compared; each vector to be compared includes n binary numbers; m and n are both positive integers; the n x m matrix formed by the m vectors to be compared is denoted as matrix . ;

[0057] The aforementioned argmax in-memory computing system includes: a one-step readout and comparison circuit and a controller; the one-step readout and comparison circuit includes: an n x m 1T1R array, a WTA circuit (i.e., a winner-take-all circuit), and m one-step readout and comparison modules; the WTA circuit includes m sets of one-to-one corresponding input terminals and output terminals; the input terminals of the m one-to-one ...

[0058] The controller is used when n is less than or equal to a preset number. At that time, the 1T1R array is used as a matrix. The corresponding operation array, for the matrix Perform a comparison operation on the corresponding operation array: select each memristor in the operation array, and set the matrix... Each binary number in the array is stored in the corresponding memristor of the corresponding operation array in the form of an analog quantity. A driving voltage is applied to each BL line of the corresponding operation array, so that the memristor in the corresponding operation array generates a current proportional to its stored value. The current is then aggregated on the corresponding column and output to the corresponding one-step readout and comparison module.

[0059] The one-step readout and comparison module includes: voltage clamping circuit, NMOS current mirror, and PMOS current mirror;

[0060] The voltage clamping circuit is used to clamp the voltage at the connected column output terminal to a preset reference voltage. At the same time, it receives current from the corresponding column output terminal and inputs it into the NMOS current mirror;

[0061] The NMOS current mirror is used to scale the current input from the voltage clamping circuit proportionally and then input it to the corresponding input terminal of the WTA circuit via the PMOS current mirror.

[0062] The WTA circuit is used to compare the magnitudes of the currents input to its m input terminals, and outputs a high-level signal at the output terminal corresponding to the maximum current, and outputs a low-level signal at the other output terminals.

[0063] It should be noted that this invention applies to 1T1R arrays in any arrangement, and is not limited here. Specifically, there are three array arrangements for the 1T1R array: an array arrangement where the word line WL is parallel to the source line SL and perpendicular to the bit line BL; an array arrangement where the word line WL is parallel to the bit line BL and perpendicular to the source line SL; and an array arrangement where the word line WL is perpendicular to both the bit line BL and the source line SL. Regardless of the arrangement, during comparison, a driving voltage is applied to the bit line BL, a gating signal is applied to the word line WL, and a superimposed current is output on the source line SL.

[0064] In one alternative implementation, the controller is configured to handle situations where n is greater than a preset number. When this happens, perform the following operations:

[0065] Initialization operation: Initializes the current matrix to a matrix. ;

[0066] Intermediate operation: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of submatrices obtained from the current partitioning. Divide the N rows of the 1T1R array into k groups according to the same partitioning method, thus dividing the 1T1R array into k operation arrays corresponding one-to-one with the k submatrices. Perform comparison operations on the corresponding operation array for each submatrix, read the signals output from each output terminal of the WTA circuit, and map them into binary numbers respectively to obtain a binary number vector. A total of k binary number vectors are obtained, forming a matrix of k rows and m columns. ;

[0067] Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. If necessary, re-execute the intermediate operations and judgment operations in sequence; otherwise, select a subarray with k rows and m columns from the 1T1R array as the matrix. The corresponding operation array, for the matrix Perform the comparison operation on the corresponding operand array.

[0068] In another alternative implementation, the number of the above-mentioned readout and comparison circuits is multiple;

[0069] The controller is used when n is greater than a preset number. When this happens, perform the following operations:

[0070] Initialization operation: Initializes the current matrix to a matrix. ;

[0071] Intermediate operation: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of sub-matrices obtained from the current partitioning; select k one-step readout and comparison circuits, and make them correspond one-to-one with the k sub-matrices; for each sub-matrix, select a sub-array of the same size as the sub-matrix from the 1T1R array in the corresponding one-step readout and comparison circuit as the corresponding operation array; simultaneously select each memristor in the operation array corresponding to each sub-array, store each binary number in the sub-array in the form of analog quantity in the memristor of the corresponding operation array, and simultaneously apply a driving voltage on each BL line of each operation array, so that the memristor in the corresponding operation array generates a current proportional to its stored value, and after being aggregated on the corresponding column, output to the corresponding one-step readout and comparison module; read the signals output from each output terminal of the WTA circuit in the selected k one-step readout and comparison circuits, and map them into binary numbers respectively to obtain k binary number vectors, which form a matrix of k rows and m columns. ;

[0072] Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. If necessary, re-execute the intermediate operations and judgment operations in sequence; otherwise, select a one-step readout and comparison circuit, and select a k-row, m-column subarray from the 1T1R array in that one-step readout and comparison circuit as the matrix. The corresponding operation matrix, for the matrix Perform the comparison operation on the corresponding operand array.

[0073] It should be noted that in memristor-based argmax in-memory computing systems, the neural network inference process typically requires comparing multiple vectors to be compared and determining the maximum value to complete operations such as classification decisions, competitive selection, or attention filtering. As the size of the memristor array continues to increase, the dimensionality and number of candidate vectors significantly increase. Directly comparing the array output results globally or column-by-column often leads to limitations in the size of the comparison circuit, a significant increase in system latency and power consumption, and insufficient scalability, gradually becoming a major bottleneck restricting the performance of in-memory computing systems. Considering the aforementioned hardware limitations, the dimensionality of the vectors to be compared that can be directly processed by the one-step readout and comparison circuit is limited. Therefore, this invention provides a preset boundary value. Preferably, This refers to the maximum number of memristors that can be distinguished in a single comparison operation, considering non-ideal factors of the memristor array. In one alternative implementation, the 1T1R array is manufactured using an SMIC 55nm process. .

[0074] Through the hierarchical recursive comparison mechanism, this invention achieves scalable maximum value determination for a large number of candidate vectors while ensuring accuracy, reducing system latency and power consumption, and is suitable for in-memory computation and inference applications based on memristors.

[0075] Preferably, in one optional implementation, the m vectors to be compared are the m vectors output by the target layer of the target neural network. To further ensure the correctness of the hierarchical comparison and recursive decision process in neural network inference, constraints are imposed on the arrangement of the binary data in the m vectors output by the target layer of the target neural network during the training phase, so that the comparison results of each subgroup can consistently reflect the relative size relationship between the vectors to be compared, thereby further improving the accuracy of argmax in-memory calculation. Based on this, the training objective of the above-mentioned target neural network includes not only the training objective under its own target task, but also: when n is greater than a preset number At that time, minimize the difference loss obtained by performing direct comparison decision and split comparison decision on the m comparison vectors output by the preset target layer after inputting the training samples into the target neural network;

[0076] The training samples are determined by the target task of the target neuron; for example, when the target task of the target neuron is an image classification task, the training samples are image samples; when the target task of the target neuron is a speech classification task, the training samples are speech samples, and there is no limitation here.

[0077] After inputting the training samples into the target neural network, the m vectors to be compared output by the target layer are represented as a matrix. The results obtained by directly comparing the decision are obtained by analyzing the matrix. The results were obtained through comparison and judgment.

[0078] The method for comparing and deciding on any matrix M includes: summing the matrix M along the column direction to obtain m sums; comparing the m sums to obtain an m-dimensional vector vec, which serves as the result of the comparison and decision on matrix M; the element in the vector vec corresponding to the position of the maximum sum is 1, and the rest are 0;

[0079] The result obtained after splitting and comparing the decision is obtained in the following way:

[0080] Initialization: Initializes the current matrix to a matrix. ;

[0081] Splitting and intermediate comparison operations: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of submatrices obtained from the current partition; compare and decide on each submatrix to obtain the corresponding intermediate vector; construct a k-row, m-column matrix from the intermediate vectors corresponding to the k submatrices. ;

[0082] Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. Then, re-execute the splitting, intermediate comparison, and discrimination operations sequentially; otherwise, for the matrix... The comparison decision is used to obtain the result after splitting the comparison decision.

[0083] In one alternative implementation, the voltage clamping circuit includes: an operational amplifier and an NMOS transistor. The positive input terminal of the operational amplifier is used to connect a preset reference voltage. The negative input terminal is connected to the NMOS transistor. The source of the transistor is connected to the voltage clamping circuit and serves as the input to the corresponding one-step readout and comparison module. The output is connected to the NMOS transistor. The gate of the NMOS transistor is connected to the gate of the NMOS transistor. The drain of the circuit is used as the output terminal of the voltage clamping circuit.

[0084] It should be noted that the voltage clamping circuit described above is only a preferred voltage clamping circuit and is not the only available voltage clamping circuit. Other voltage clamping circuits can also be used, and there are no limitations on them here.

[0085] In one alternative implementation, the above-mentioned NMOS current mirror includes: an NMOS transistor. and NMOS transistor NMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, NMOS transistor The gate and NMOS transistor The gate of the NMOS transistor is connected to the NMOS transistor and serves as the input terminal of the NMOS current mirror; the NMOS transistor... and NMOS transistor The source is used to connect to a low flat voltage. The drain serves as the output terminal of the NMOS current mirror; NMOS transistor The size is an NMOS transistor The size is y times the value of the current mirror, used to scale the current at the input of the NMOS current mirror by a factor of y; y is a positive number.

[0086] Generally, the dimensions of the aforementioned NMOS transistor refer to the aspect ratio. In one optional implementation, the value of y ranges from 1 to 100, preferably 20.

[0087] It should be noted that the above-mentioned NMOS current mirror is only a preferred NMOS current mirror, and is not the only available NMOS current mirror. Other NMOS current mirrors can also be used, and there are no restrictions here.

[0088] In one alternative implementation, the PMOS current mirror includes: a PMOS transistor. and PMOS transistor PMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, PMOS transistor The gate and PMOS transistor The gate of the PMOS transistor is connected to the PMOS transistor and serves as the input terminal of the PMOS current mirror. and PMOS transistor The source is used to receive high-level signals. PMOS transistor The drain of the PMOS current mirror and the corresponding one-step readout and comparison module are connected to the corresponding input terminal of the corresponding WTA circuit.

[0089] It should be noted that the above-mentioned PMOS current mirror is only a preferred PMOS current mirror, and is not the only available PMOS current mirror. Other PMOS current mirrors can also be used, and there are no restrictions here.

[0090] In this invention, the WTA circuit is configured to indicate the channel position corresponding to the maximum input, rather than simply outputting the magnitude of the maximum input. Specifically, the WTA circuit receives current signals from m one-step readout and comparison modules, and completes the competition decision among multiple inputs in a single comparison operation, determining the comparison branch corresponding to the maximum current signal as the winner. The output of the WTA circuit is represented in voltage domain, where the output terminal corresponding to the winner outputs a first level (high-level signal), and the remaining output terminals output a second level (low-level signal), thereby forming a one-hot winner indication signal to clearly identify the position of the maximum column or the maximum candidate vector.

[0091] In one optional implementation, the WTA circuit includes a contention comparator stage and a decision output stage: the contention comparator stage is used to suppress contention among multiple input signals in the analog domain to generate internal node signals reflecting the relative magnitudes of each input; the decision output stage is used to convert the internal node signals into stable voltage output signals. By setting inverters, comparators, or equivalent digitization circuits after the internal nodes of each contention branch, the WTA circuit can directly output the winner indication result in the voltage domain, facilitating direct interface with subsequent control modules, decoding modules, or digital logic circuits. It should be noted that this invention does not limit the specific circuit structure of the WTA circuit; any WTA circuit capable of realizing multi-input contention and outputting a voltage-form winner indication signal can be used as an implementation of the WTA circuit.

[0092] Preferably, in one optional embodiment, the WTA circuit includes m identical WTA units;

[0093] The WTA unit includes: NMOS transistors , , , , , , , and PMOS transistor , , , ;

[0094] NMOS transistor The drain of the transistor serves as the input terminal of the WTA cell, and is connected to the NMOS transistor respectively. , , The deletion of the poles is connected;

[0095] PMOS transistor The gates of the PMOS transistors are respectively connected to the gates of the PMOS transistors. drain, PMOS transistor Gate, NMOS transistor drain, NMOS transistor The drains of the PMOS transistors are connected, and the connection point serves as a common node. The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, NMOS transistor drain, PMOS transistor The gates are connected, and the connection point is denoted as point X;

[0096] PMOS transistor and NMOS transistor The drains of the PMOS transistors are connected to form an inverter. NMOS transistor The gate of the PMOS transistor is connected to point X. and NMOS transistor The connection point of the drain electrode serves as the output terminal of the WTA unit;

[0097] PMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. Gate and drain of NMOS transistor gate, NMOS transistor gate, NMOS transistor The drains are connected;

[0098] PMOS transistor PMOS transistor PMOS transistor NMOS transistor The sources are all used to connect to high-level signals. NMOS transistor , , , , , , , The source electrode is used for grounding;

[0099] NMOS transistor The gate is used to receive control signals; when the control signal is high, the WTA unit is reset and outputs a low-level signal; when the control signal is low, the WTA unit is in the working state.

[0100] In a WTA circuit, the common nodes of all WTA units are connected;

[0101] The m input terminals of the WTA circuit are the input terminals of the m WTA units in the WTA circuit, and the m output terminals of the WTA circuit are the output terminals of the m WTA units in the WTA circuit.

[0102] It should be noted that "one-step readout" in this invention refers to completing the reading and comparison of multiple current columns under the same readout enable condition, rather than reading each column sequentially or multiple times.

[0103] The following describes a specific embodiment of the argmax in-memory computation system provided by this invention, focusing on the argmax operation commonly used in neural network inference. This embodiment is only used to explain the technical solution of this invention and does not constitute a limitation on the scope of protection of this invention.

[0104] In neural network inference, especially in classification networks, competitive neural networks, or attention mechanisms, it is often necessary to compare multiple vectors or the outputs of multiple neurons (i.e., the vectors to be compared) to select the output with the largest response value as the final result, i.e., to complete the argmax operation. In memristor-based in-memory computing systems, the weights or intermediate calculation results of the neural network can be mapped and stored in a memristor array. Each column in the memristor array corresponds to the calculation result of a vector, and the magnitude of the column current represents the cumulative result of the vector or the activation intensity of the neuron.

[0105] The argmax in-memory computing system provided in this embodiment includes: a one-step readout and comparison circuit and a controller; the one-step readout and comparison circuit includes: an n x m 1T1R array, a WTA circuit and m one-step readout and comparison modules; the WTA circuit includes m sets of one-to-one corresponding input terminals and output terminals; the input terminals of the m one-to-one ...

[0106] like Figure 1 As shown, the controller in this embodiment includes: a control module, a WL driver and decoding module, and a BL driver and input control module;

[0107] like Figure 2 As shown, a memristor includes two resistive states: a high-resistance state (HRS) and a low-resistance state (LRS). The memristor can transition between these two resistive states by applying a port voltage of a specific direction and magnitude. Specifically, by applying a voltage greater than... A positive voltage can switch a memristor from a high-resistance state to a low-resistance state; conversely, by applying a voltage less than... With a negative voltage, the memristor can transition from a low-resistance state to a high-resistance state; among which... The threshold value for the memristor to transition from a high-resistance state to a low-resistance state; This is the threshold value for the memristor to transition from a low-resistance state to a high-resistance state. The resistance values ​​for the high and low configurations of the memristor are respectively... and , In this embodiment, , .

[0108] A 1T1R cell consists of a memristor, typically with its lower electrode connected to the source of a MOSFET. There are three array arrangements for 1T1R cells. This embodiment uses an array arrangement where the word line (WL) is parallel to the source line (SL) and perpendicular to the bit line (BL), with the direction of the SL line in the 1T1R array defining the column direction. For an n x m 1T1R array, there are m WL lines, m SL lines, and n BL lines. The WL driver and decoding module is directly connected to the WL lines of the m columns of memristors in the memristor array; the BL driver and input control module is directly connected to the BL lines of the n rows of memristors; and the m one-step readout and comparison modules are directly connected to the SL lines of the m columns of memristors.

[0109] External systems interact directly with the system through the control module. The control module transmits data to the WL driver and decoder modules, and transmits different control signals to the WL driver and decoder modules, the BL driver and input control modules, and the one-step readout and comparison circuit. The read data is finally transmitted back to the control module by the one-step readout and comparison circuit.

[0110] like Figure 3 As shown, the one-step readout and comparison module includes: a voltage clamping circuit, an NMOS current mirror, and a PMOS current mirror; the voltage clamping circuit is used to clamp the voltage of the connected column output terminal at a preset reference voltage. At the same time, it receives current from the corresponding column output terminal and inputs it into the NMOS current mirror; the NMOS current mirror is used to scale the current input from the voltage clamping circuit proportionally and then input it into the corresponding input terminal of the WTA circuit through the PMOS current mirror.

[0111] The argmax in-memory computation system is used to determine the maximum value of m vectors to be compared. Each vector includes n binary numbers, representing the computational response of a certain category, path, or candidate result in the neural network; where m and n are both positive integers. The m vectors to be compared are the m vectors output by the target layer of the target neural network. To further ensure the correctness of the hierarchical comparison and recursive decision process in neural network inference, constraints are imposed on the arrangement of the binary data in the m vectors output by the target layer of the target neural network during the training phase, so that the comparison results of each subgroup can consistently reflect the relative size relationship between the vectors to be compared, thereby further improving the accuracy of the comparison.

[0112] In neural network inference, multiple vectors to be compared are mapped to the column directions of a memristor array. Specifically, for an n x m 1T1R array, each column corresponds to a candidate output (e.g., a class, a candidate vector), denoted as the j-th column (j). Each row corresponds to an input dimension or accumulated term, denoted as the i-th row ( Through the cooperation of the control module, the WL drive and decoding module, and the BL drive and input control module, the 1T1R array forms n column currents in one comparison operation, and the magnitude of each column current represents the response intensity of the corresponding candidate output.

[0113] In the inference scenario, the input vector to be compared is loaded to the bitline terminal by the BL drive and input control module. The memristor conductance (or resistance state) is used to characterize the network weights or equivalent parameters. After the gating WL line interacts with the internal conduction path of the array, each column forms a readout current at the SL terminal. The maximum current corresponds to the maximum response, meaning the result of argmax satisfies:

[0114]

[0115] It should be noted that the above is only used to illustrate the meaning of comparison and does not limit the specific weight encoding method.

[0116] This embodiment coordinates the operation through a control module, enabling the 1T1R array to enter "read and compare" mode. Specifically: the control module sends a read enable signal to the WL driver and decoder module, selecting the WLs to be compared; the control module sends a read configuration command to the BL driver and input control module, applying the voltage required for readout at the BL terminal. Simultaneously, the control module enables the one-step readout and comparison module to enter the working state, allowing each column's SL terminal to connect to the corresponding one-step readout and comparison module.

[0117] For each column, the voltage clamping circuit in the corresponding one-step readout and comparison module includes an operational amplifier and an NMOS transistor. The clamping structure is formed. The positive input terminal of the operational amplifier is used to connect a preset reference voltage. The negative input terminal is connected to the NMOS transistor. The source and the corresponding column output of the 1T1R array are connected. Utilizing the virtual short and virtual open characteristics of the operational amplifier, the voltage at the corresponding column output is clamped to a preset reference voltage. This ensures that the voltage difference across the 1T1R cell remains near the array during readout. This structure enables the voltage difference across the 1T1R unit to remain constant, thus keeping the read current stable.

[0118] This clamping mechanism ensures that the readout voltage conditions for each column are consistent within the same readout cycle, thus obtaining the column current. It has good comparability, reduces comparison errors caused by node voltage drift, and provides a stable input for subsequent WTA competition.

[0119] After the current is read out, each current column is first scaled proportionally by an NMOS current mirror so that the current amplitude falls within the appropriate operating range of the subsequent circuit. Then, the scaled current is input to the corresponding input terminal of the WTA circuit by a PMOS current mirror, forming a competitive relationship between multiple current columns.

[0120] In this embodiment, the NMOS current mirror includes: an NMOS transistor. and NMOS transistor NMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, NMOS transistor The gate and NMOS transistor The gate of the NMOS transistor is connected to the NMOS transistor and serves as the input terminal of the NMOS current mirror; the NMOS transistor... and NMOS transistor The source is used to connect to a low flat voltage. The drain serves as the output terminal of the NMOS current mirror; NMOS transistor The size is an NMOS transistor The dimension is y times the width-to-length ratio, used to proportionally scale the current at the input of the NMOS current mirror by a factor of y; y is a positive number. In this embodiment, the above dimension refers to the width-to-length ratio, and the value of y ranges from 1 to 100, preferably 20. In this embodiment, the above low-level voltage... The value is 0V.

[0121] In this embodiment, the PMOS current mirror includes: a PMOS transistor. and PMOS transistor PMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, PMOS transistor The gate and PMOS transistor The gate of the PMOS transistor is connected to the PMOS transistor and serves as the input terminal of the PMOS current mirror. and PMOS transistor The source is used to receive high-level signals. PMOS transistor The drain of the PMOS current mirror serves as the output terminal of the corresponding one-step readout and comparison module, and is connected to the corresponding input terminal of the corresponding WTA circuit. In this embodiment, the aforementioned high-level signal... The value is 3.3V.

[0122] In this embodiment, the WTA circuit includes m identical WTA units;

[0123] like Figure 4 As shown, the WTA unit includes: an NMOS transistor. , , , , , , , and PMOS transistor , , , .

[0124] Specifically, PMOS transistor , , and NMOS transistor The sources are all connected to a high-level power supply V. DD NMOS transistor , , , , , , , The source is grounded. NMOS transistor The drain of the transistor serves as the input terminal of the WTA cell, receiving the input current I, and is connected to the NMOS transistor. , , The gate of the PMOS transistor is connected to the input circuit, transmitting the input information to subsequent comparison and feedback circuits. gate and PMOS transistor drain, PMOS transistor gate, NMOS transistor drain, NMOS transistor The drains are connected to form a common node (the voltage here is denoted as ). ).

[0125] PMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, NMOS transistor drain, PMOS transistor The gate of the transistor is connected, and the connection point is marked as node X. This node is also connected to the gate of the PMOS transistor. NMOS transistor The gate is connected. PMOS transistor and NMOS transistor The drain of the PMOS transistor is connected to serve as the output terminal of the WTA unit. and NMOS transistor Construct an inverter, with the voltage at node X as the input. , generate output voltage It serves as a signal isolation and digital output device. (PMOS transistor) The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. Gate and drain of NMOS transistor gate, NMOS transistor gate, NMOS transistor The drains are connected. NMOS transistor The gate is used to receive control signals and determine the operating state of the feedback circuit.

[0126] When control signal When the signal is high, the WTA unit is reset and outputs a low-level signal; when the control signal is low... When the signal is low, the WTA unit is in working state and begins to provide feedback;

[0127] In a WTA circuit, the common nodes of all WTA units are connected;

[0128] The m input terminals of the WTA circuit are the input terminals of the m WTA units in the WTA circuit, and the m output terminals of the WTA circuit are the output terminals of the m WTA units in the WTA circuit.

[0129] In the above process, NMOS transistor and To construct an inverter, ensure the voltage signal output at the output terminal is... Purity. PMOS transistor NMOS transistor , , , It forms a feedback regulation, based on the control signal. The change begins to be fed back or reset, and the comparison results are obtained.

[0130] When control signal When the signal is high, the NMOS transistor Turn on, NMOS transistor When the control signal is off, feedback stops, and the WTA unit is reset, all outputs are low-level signals. When the signal is low, the NMOS transistor Turn off NMOS transistor Turn on, and the current I at node X of the WTA cell with a larger input current I. x The voltage V at node X is larger, resulting in a higher voltage V. x The flow rate decreases faster, which in turn increases the flow through the PMOS transistor. and NMOS transistor The current flowing through the PMOS transistor. and NMOS transistor The current increase will increase the NMOS transistor The gate voltage is reduced, thereby lowering the voltage at the common node. ,and The reduction will reduce the I of all units. x This suppresses the V of other units. x Decrease. Ultimately, only the V of the WTA cell where the maximum current is located will decrease. x If the voltage is lower than the inverter's flip voltage, a high level is output at the corresponding output terminal, and the V of other WTA units... x All are higher than the switching voltage, and a low level is output at the corresponding output terminal.

[0131] The WTA cell can accept input current and connect to the corresponding WTA cells in other columns through a common node. The maximum value is determined by comparison. The voltage output of the WTA cell containing the maximum value is then calculated. The voltage output of other WTA units .

[0132] All column-specific WTA cells are interconnected via a common comparison node, creating a multi-column current competition relationship. Each column's WTA cell receives its own comparison current input. Within the same readout cycle, the WTA circuit automatically completes the competition based on the current magnitude: when the input current of a certain column is the maximum across all columns, that column's WTA cell is determined to be the "winner," and its output terminal outputs a high-level signal (e.g., ...). The WTA cells in the remaining columns output a low-level signal (e.g., 0V).

[0133] For a memristor array with m columns, there are m one-step readout and comparison modules in its corresponding one-step readout and comparison circuit. The circuit area overhead is linearly related to the column complexity, and the area overhead is not large. This module can read and compare in one step, improving computational efficiency.

[0134] In this embodiment, considering the upper limit of the WTA cell's operation (i.e., the upper limit at the physical and circuit level) caused by non-ideal factors such as the line resistance of the 1T1R array itself, direct comparison will result in a large error when the data size of the vector to be compared exceeds this upper limit. Therefore, this embodiment determines a threshold. , The maximum number of memristors that can be distinguished by the WTA cell in a row of memristors in a single comparison operation, after considering non-ideal factors such as the line resistance of the memristor array, is determined by the structural characteristics and operating conditions of the WTA cell and is an inherent hardware parameter of the system. In this embodiment, the 1T1R array uses SMIC 55nm process. .

[0135] When the data size (i.e., dimension n) of the vectors to be compared does not exceed In this case, a single comparison operation is performed to complete the argmax decision: the 1T1R array is treated as an n x m matrix composed of m vectors to be compared. The corresponding operation array, for the matrix Perform a comparison operation on the corresponding operation array: select each memristor in the operation array, and set the matrix... Each binary number is stored in the corresponding memristor of the corresponding operation array in the form of an analog quantity. A driving voltage is applied to each BL line of the corresponding operation array, so that the memristor in the corresponding operation array generates a current proportional to its stored value. The current is then aggregated on the corresponding column and output to the corresponding one-step readout and comparison module.

[0136] When the data size (i.e., dimension n) of the vectors to be compared exceeds In this embodiment, a hierarchical argmax in-memory computation system based on memristors is proposed. By introducing a recursive hierarchical comparison mechanism driven by the upper limit of WTA comparison capability, efficient and scalable maximum value determination of a large number of candidate vectors can be achieved while ensuring that a single WTA unit works within a feasible range.

[0137] The overall technical idea of ​​the above recursive hierarchical comparison mechanism is to transform the high-dimensional argmax operation in neural network inference into a hierarchical decision-making process consisting of multiple low-dimensional comparisons and successive compressions.

[0138] Specifically, this embodiment does not directly perform a global comparison of the high-dimensional vectors to be compared. Instead, it fully considers the upper limit n0 of the number of inputs (i.e., the number of memristors generating current on a column) that the comparison hardware (WTA unit) can handle in one operation. The binary numbers in the vectors to be compared are recursively grouped according to this upper limit, and the comparison operation is performed in parallel at each group level. Through multi-level comparison and intermediate result encoding and compression, the comparison scale is gradually reduced, and the maximum value determination is finally completed.

[0139] Therefore, the number of comparison levels is not set arbitrarily, but is determined by the size of the vectors to be compared and the processing power of a single WTA unit, thus forming a scalable hierarchical comparison architecture.

[0140] like Figure 5 As shown, when the data size (i.e., dimension n) of the vectors to be compared exceeds... At that time, the control module will press the input to be compared. Grouping into multiple subgroups (denoted as the number of subgroups in the current comparison level) And such that the number of binary numbers contained in each subgroup is no greater than 100. The WTA circuit is controlled to perform comparisons on each subgroup to obtain intermediate comparison results: a parallel comparison is performed between the first subgroups, a parallel comparison is performed between the second subgroups, and so on, until the first subgroup... Subgroups. Among them, the above The comparisons can be performed in parallel within the same comparison stage, or the WTA circuit can be reused to perform them sequentially in a timing manner, thereby forming the first-level comparison result.

[0141] After completing the first level of comparison, we will get There are several intermediate comparison results, which can be considered as a new representation of the vector to be compared, with dimensions of... .

[0142] when Not greater than In such cases, the intermediate comparison results can be directly fed back into the WTA circuit for comparison to complete the final decision.

[0143] when Still greater than At that time, the control module continues to process the intermediate comparison results according to... Divide the data into groups such that the number of binary numbers in each subgroup is no greater than [a certain value]. ,get Create a new subgroup and perform the next level of comparison. The above grouping and comparison process can be performed recursively until the number of subgroups obtained from a certain level does not exceed [a certain threshold]. Output the index of the maximum value or the one-hot decision result to complete the argmax operation.

[0144] In each comparison level, the comparison results of each vector to be compared on the corresponding subgroup are output in binary form and combined in a predetermined order to form an intermediate encoded representation. Through step-by-step comparison and encoding compression, the representation dimension of the vectors to be compared is continuously reduced.

[0145] In the final comparison layer, the system performs a global comparison operation on the final encoding of all vectors to be compared, and outputs the candidate vector index or one-hot decision result corresponding to the maximum encoding, thereby completing the argmax operation.

[0146] Within the same comparison level, the comparison operations of each subgroup are executed in parallel, or, in the case of reusing the aforementioned WTA comparison unit, the comparison operations of each subgroup are executed sequentially in a timing manner.

[0147] Specifically, when n is greater than the preset number For serial execution mode:

[0148] The control module performs the following operations:

[0149] Initialization operation: Initializes the current matrix to a matrix. ;

[0150] Intermediate operation: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of submatrices obtained from the current partitioning. Divide the N rows of the 1T1R array into k groups according to the same partitioning method, thus dividing the 1T1R array into k operation arrays corresponding one-to-one with the k submatrices. Perform comparison operations on the corresponding operation array for each submatrix, read the signals output from each output terminal of the WTA circuit, and map them into binary numbers respectively to obtain a binary number vector. A total of k binary number vectors are obtained, forming a matrix of k rows and m columns. High-level signals are mapped to the binary number 1; low-level signals are mapped to the binary number 0.

[0151] Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. If necessary, re-execute the intermediate operations and judgment operations in sequence; otherwise, select a subarray with k rows and m columns from the 1T1R array as the matrix. The corresponding operation array, for the matrix Perform the comparison operation on the corresponding operand array.

[0152] In the above method, the comparison of each subgroup is performed serially, and the same one-step readout and comparison circuit can be reused, resulting in a smaller circuit size.

[0153] Specifically, when n is greater than the preset number For parallel execution:

[0154] The number of readout and comparison circuits in the above step is multiple;

[0155] The control module performs the following operations:

[0156] Initialization operation: Initializes the current matrix to a matrix. ;

[0157] Intermediate operation: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of sub-matrices obtained from the current partitioning; select k one-step readout and comparison circuits, and make them correspond one-to-one with the k sub-matrices; for each sub-matrix, select a sub-array of the same size as the sub-matrix from the 1T1R array in the corresponding one-step readout and comparison circuit as the corresponding operation array; simultaneously select each memristor in the operation array corresponding to each sub-array, store each binary number in the sub-array in the form of analog quantity in the memristor of the corresponding operation array, and simultaneously apply a driving voltage on each BL line of each operation array, so that the memristor in the corresponding operation array generates a current proportional to its stored value, and after being aggregated on the corresponding column, output to the corresponding one-step readout and comparison module; read the signals output from each output terminal of the WTA circuit in the selected k one-step readout and comparison circuits, and map them into binary numbers respectively to obtain k binary number vectors, which form a matrix of k rows and m columns. High-level signals are mapped to the binary number 1; low-level signals are mapped to the binary number 0.

[0158] Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. If necessary, re-execute the intermediate operations and judgment operations in sequence; otherwise, select a one-step readout and comparison circuit, and select a k-row, m-column subarray from the 1T1R array in that one-step readout and comparison circuit as the matrix. The corresponding operation matrix, for the matrix Perform the comparison operation on the corresponding operand array.

[0159] In the above approach, the comparisons of each subgroup are performed in parallel, and the system latency does not increase linearly with the dimension of the candidate vector.

[0160] In summary, the one-step readout and comparison circuit proposed in this embodiment includes: an n x m 1T1R array, a WTA circuit, and m one-step readout and comparison modules. Each one-step readout and comparison module includes: a voltage clamping circuit, an NMOS current mirror, and a PMOS current mirror. The current is accurately read out by clamping with a reference voltage, the column current is scaled proportionally by the current mirror, and the WTA circuit compares different column currents in one step, enabling fast, efficient, and low-power one-step readout and comparison results. By rationally constructing the circuit modules and the readout and comparison process, this invention can effectively improve the performance of one-step readout and comparison of memristor array units, significantly reduce hardware resources and system latency, and provide a new technical path for efficiently realizing neural network inference applications based on in-memory computing.

[0161] This embodiment introduces an upper limit... The recursive hierarchical comparison mechanism enables a scalable implementation of the argmax operation; the complexity and power consumption of subsequent comparisons are significantly reduced through step-by-step encoding compression; at the same time, the architecture is decoupled from the specific WTA circuit implementation, making it suitable for memristor arrays of different sizes; it is suitable for vector comparison and maximum value determination tasks in large-scale neural network inference.

[0162] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memristor-based argmax in-memory computing system, characterized in that, The application relates to a method for maximum value determination of m vectors to be compared, each of which comprises n binary numbers, wherein m and n are positive integers, and an n*m matrix formed by the m vectors to be compared is denoted as matrix . The argmax in-memory computing system includes: a one-step readout and comparison circuit and a controller; the one-step readout and comparison circuit includes: an n x m 1T1R array, a WTA circuit, and m one-step readout and comparison modules; the WTA circuit includes m sets of one-to-one corresponding input terminals and output terminals; the input terminals of the m one-to-one ... The controller is used when n is less than or equal to a preset number. When using a 1T1R array as a matrix The corresponding operation array, for the matrix Perform a comparison operation on the corresponding operation array: select each memristor in the operation array, and set the matrix... Each binary number in the array is stored in the corresponding memristor of the corresponding operation array in the form of an analog quantity. A driving voltage is applied to each BL line of the corresponding operation array, so that the memristor in the corresponding operation array generates a current proportional to its stored value. The current is then aggregated on the corresponding column and output to the corresponding one-step readout and comparison module. The step-by-step readout and comparison module includes: a voltage clamping circuit, an NMOS current mirror, and a PMOS current mirror; the voltage clamping circuit is used to clamp the voltage of the connected column output terminal at a preset reference voltage. At the same time, it receives current from the corresponding column output terminal and inputs it into the NMOS current mirror; the NMOS current mirror is used to scale the current input from the voltage clamping circuit proportionally and then input it into the corresponding input terminal of the WTA circuit via the PMOS current mirror. The WTA circuit is used to compare the magnitude of the current input to its m input terminals, and outputs a high-level signal at the output terminal corresponding to the maximum current, and outputs a low-level signal at the other output terminals.

2. The argmax in-memory computing system according to claim 1, characterized in that, The controller is used when n is greater than a preset number. When this happens, perform the following operations: Initialization operation: Initializes the current matrix to a matrix. ; Intermediate operation: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of sub-matrices obtained from the current partitioning. Divide the N rows of the 1T1R array into k groups according to the same partitioning method, thereby dividing the 1T1R array into k operation arrays corresponding one-to-one with the k sub-matrices. Perform the comparison operation on the corresponding operation array for each sub-matrix, read the signals output from each output terminal of the WTA circuit, and map them into binary numbers respectively to obtain a binary number vector. A total of k binary number vectors are obtained, forming a matrix of k rows and m columns. High-level signals are mapped to the binary number 1; low-level signals are mapped to the binary number 0. Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. If necessary, re-execute the intermediate operation and the judgment operation in sequence; otherwise, select a subarray with k rows and m columns from the 1T1R array as the matrix. The corresponding operation array, for the matrix The comparison operation is performed on the corresponding operation array.

3. The argmax in-memory computing system according to claim 1, characterized in that, There are multiple readout and comparison circuits in the first step; The controller is used when n is greater than a preset number. When this happens, perform the following operations: Initialization operation: Initializes the current matrix to a matrix. ; Intermediate operation: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of sub-matrices obtained from the current partitioning; select k one-step readout and comparison circuits, and make them correspond one-to-one with the k sub-matrices; for each sub-matrix, select a sub-array of the same size as the sub-matrix from the 1T1R array in the corresponding one-step readout and comparison circuit as the corresponding operation array; simultaneously select each memristor in the operation array corresponding to each sub-array, store each binary number in the sub-array in the form of analog quantity in the memristor of the corresponding operation array, and simultaneously apply a driving voltage on each BL line of each operation array, so that the memristor in the corresponding operation array generates a current proportional to its stored value, and after being aggregated on the corresponding column, output to the corresponding one-step readout and comparison module; read the signals output from each output terminal of the WTA circuit in the selected k one-step readout and comparison circuits, and map them into binary numbers respectively to obtain k binary number vectors, which form a matrix of k rows and m columns. High-level signals are mapped to the binary number 1; low-level signals are mapped to the binary number 0. Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. If necessary, the intermediate operation and the judgment operation are executed again in sequence; otherwise, a one-step readout and comparison circuit is selected, and a k-row, m-column subarray is selected from the 1T1R array in that one-step readout and comparison circuit as a matrix. The corresponding operation matrix, for the matrix The comparison operation is performed on the corresponding operation array.

4. The in-memory argmax computing system according to any one of claims 2-3, characterized in that, The m vectors to be compared are the m vectors output by the preset target layer in the pre-trained target neural network; The training objective of the target neural network includes: when n is greater than a preset number. When the training samples are input into the target neural network, minimize the difference loss between the results obtained by direct comparison decision and split comparison decision on the m comparison vectors output by the preset target layer after inputting the training samples into the target neural network; The m vectors to be compared, output by the preset target layer after the training samples are input into the target neural network, are represented as a matrix. The results obtained by directly comparing the decision are obtained by analyzing the matrix. The results were obtained through comparison and judgment. The method for comparing and deciding on any matrix M includes: summing the matrix M along the column direction to obtain m sums; comparing the m sums to obtain an m-dimensional vector vec, which serves as the result of the comparison and decision on matrix M; the element in the vector vec corresponding to the position of the maximum sum is 1, and the rest are 0; The result obtained after splitting and comparing the decision is obtained in the following way: Initialization: Initializes the current matrix to a matrix. ; Splitting and intermediate comparison operations: Divide the current matrix into multiple submatrices along the row direction, such that the number of rows in each submatrix is ​​less than or equal to the number of rows in the matrix. Let k be the number of submatrices obtained from the current partition; compare and decide on each submatrix to obtain the corresponding intermediate vector; construct a k x m matrix from the intermediate vectors corresponding to the k submatrices. ; Decision operation: Determine if k is greater than the preset number. If so, then update the current matrix to matrix [matrix name missing]. Then, re-execute the splitting, intermediate comparison, and discrimination operations sequentially; otherwise, for the matrix... The comparison decision is used to obtain the result after splitting the comparison decision.

5. The argmax in-memory computing system according to any one of claims 1-3, characterized in that, The voltage clamping circuit includes: an operational amplifier and an NMOS transistor. The positive input terminal of the operational amplifier is used to connect a preset reference voltage. The negative input terminal is connected to the NMOS transistor. The source terminal is connected to the voltage clamping circuit and serves as the input terminal for the corresponding one-step readout and comparison module. The output terminal is connected to the NMOS transistor. The gate of the NMOS transistor is connected to the gate of the NMOS transistor. The drain of the circuit is used as the output terminal of the voltage clamping circuit.

6. The in-memory argmax computing system according to any one of claims 1-3, characterized in that, The NMOS current mirror includes: an NMOS transistor. and NMOS transistor NMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, NMOS transistor The gate and NMOS transistor The gate of the NMOS transistor is connected to the NMOS transistor and serves as the input terminal of the NMOS current mirror; the NMOS transistor... and NMOS transistor The source is used to connect to a low flat voltage. The drain serves as the output terminal of the NMOS current mirror; the NMOS transistor The size is an NMOS transistor The size is y times the value of the current mirror, used to scale the current at the input of the NMOS current mirror by a factor of y; y is a positive number.

7. The argmax in-memory computing system according to any one of claims 1-3, characterized in that, The PMOS current mirror includes: a PMOS transistor. and PMOS transistor PMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, PMOS transistor The gate and PMOS transistor The gate of the PMOS transistor is connected to the PMOS transistor and serves as the input terminal of the PMOS current mirror. and PMOS transistor The source is used to receive high-level signals. PMOS transistor The drain of the circuit serves as the output terminal of the PMOS current mirror and the corresponding one-step readout and comparison module, and is connected to the corresponding input terminal of the corresponding WTA circuit.

8. The argmax in-memory computing system according to any one of claims 1-3, characterized in that, The WTA circuit comprises: m identical WTA units; The WTA unit includes: an NMOS transistor. , , , , , , , and PMOS transistor , , , ; NMOS transistor The drain of the transistor serves as the input terminal of the WTA unit, and is connected to the NMOS transistor respectively. , , The deletion of the poles is connected; PMOS transistor The gates of the PMOS transistors are respectively connected to the gates of the PMOS transistors. drain, PMOS transistor Gate, NMOS transistor drain, NMOS transistor The drains of the PMOS transistors are connected, and the connection point serves as a common node. The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. drain, NMOS transistor drain, PMOS transistor The gates are connected, and the connection point is denoted as point X; PMOS transistor and NMOS transistor The drains of the PMOS transistors are connected to form an inverter. NMOS transistor The gate of the PMOS transistor is connected to point X. and NMOS transistor The connection point of the drain electrode serves as the output terminal of the WTA unit; PMOS transistor The drains of the NMOS transistors are respectively connected to the drains of the NMOS transistors. Gate and drain of NMOS transistor gate, NMOS transistor gate, NMOS transistor The drains are connected; PMOS transistor PMOS transistor PMOS transistor NMOS transistor The sources are all used to connect to high-level signals. NMOS transistor , , , , , , , The source electrode is used for grounding; NMOS transistor The gate is used to receive control signals; when the control signal is a high-level signal, the WTA unit is reset and outputs a low-level signal; when the control signal is a low-level signal, the WTA unit is in the working state. The common nodes of all WTA units in the WTA circuit are connected; The m input terminals of the WTA circuit are the input terminals of the m WTA units in the WTA circuit, and the m output terminals of the WTA circuit are the output terminals of the m WTA units in the WTA circuit.

9. The argmax in-memory computing system according to any one of claims 1-3, characterized in that, The This represents the maximum number of memristors that can be distinguished in a column of memristors in a memristor array during a single comparison operation, after considering non-ideal factors of the memristor array.

10. The argmax in-memory computing system according to claim 9, characterized in that, The 1T1R array is manufactured using SMIC 55nm process; .

Images