Encryption and decryption circuit, chip, AES circuit system and method

Abstract

The invention relates to an encryption and decryption circuit, a chip, an AES circuit system and a method. The encryption and decryption circuit comprises a first multiplexer, a second multiplexer, a third multiplexer, a forward and reverse row shift module, a forward and reverse byte substitution module, a fourth multiplexer, a forward and reverse column mixing module, a fifth multiplexer, a round key addition module, a sixth multiplexer and a splicing iteration data module. And a seventh multiplexer and a data iteration register. A data path is dynamically selected through a multiplexer, and in combination with a forward and reverse row shifting module, a forward and reverse byte substitution module and a forward and reverse column mixing module, high integration of encryption and decryption operation and reusability of the module can be realized. Therefore, the implementation cost of the circuit can be reduced, and the circuit is particularly suitable for embedded and low-power-consumption application scenes sensitive to the chip area.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to encryption / decryption circuits, chips, AES circuit systems and methods. Background Technology

[0002] Advanced Encryption Standard (AES), a widely adopted symmetric encryption algorithm globally, is a core technology for ensuring data security in fields such as electronic communications, the Internet of Things (IoT), and mobile payments. With the increasing urgency of low power consumption and high performance requirements in these applications, efficiently implementing the AES algorithm at the hardware level has become a key challenge in the field of integrated circuit design.

[0003] In related technologies, AES hardware implementations typically construct separate data paths for encryption and decryption processes. While this architecture, which completely separates the core encryption and decryption modules, can achieve standard algorithm functionality, it inevitably leads to significant circuit resource redundancy. This exacerbates the consumption of chip area and power consumption, making it difficult to meet the needs of applications sensitive to hardware efficiency and power consumption. Summary of the Invention

[0004] This application provides an encryption / decryption circuit, a chip, an AES circuit system, and a method.

[0005] According to a first aspect of the embodiments of this application, an encryption / decryption circuit is provided, comprising: The system comprises a first multiplexer, a second multiplexer, a third multiplexer, a forward and reverse row shifting module, a forward and reverse byte substitution module, a fourth multiplexer, a forward and reverse column mixing module, a fifth multiplexer, a round key addition module, a sixth multiplexer, a concatenated iterative data module, a seventh multiplexer, and a data iteration register; among which, The output of the first multiplexer is connected to the input of the round key addition module, and the output of the round key addition module is connected to the first input of the second multiplexer through the splicing iterative data module. The second multiplexer is connected to the input of the data iteration register through the forward and reverse row shift module; The output of the third multiplexer is connected to the input of the fourth multiplexer through the forward and reverse byte substitution module; The output of the fourth multiplexer is connected to the input of the forward and reverse column mixing module and the first input of the fifth multiplexer. The output of the forward and reverse column mixing module is connected to the second input of the fifth multiplexer. The output of the fifth multiplexer is connected to the input of the round key addition module, the sixth multiplexer, and the splicing iterative data module. The output of the round key addition module is connected to the splicing iterative data module through the sixth multiplexer. The output of the splicing iterative data module is connected to the second input of the second multiplexer through the seventh multiplexer. The output of the sixth multiplexer is connected to the input of the data iteration register.

[0006] In one possible implementation, the encryption / decryption circuit further includes forward and reverse key expansion data paths, which include: a key expansion row shift module, a key expansion byte substitution module, a round constant XOR module, a key XOR module, a ninth multiplexer, a tenth multiplexer, an eleventh multiplexer, a twelfth multiplexer, and a thirteenth multiplexer; wherein... The input of the key extension row shift module is connected to the output of the external iterative key register, and the output of the key extension row shift module is connected to the input of the key extension byte substitution module through the ninth multiplexer. The output of the key extension byte substitution module is connected to the input of the round constant XOR module. The output of the key extension byte substitution module is connected to the first input of the key XOR module through the tenth multiplexer and the eleventh multiplexer. The input of the tenth multiplexer is connected to the output of the iterative key register. The output of the round constant XOR module is connected to the first input of the key XOR module through the eleventh multiplexer. The second input of the key XOR module is connected to the iterative key register through the twelfth multiplexer, and the output of the key XOR module is connected to the iterative key register through the thirteenth multiplexer.

[0007] In one possible implementation, the encryption process of the encryption / decryption circuit includes: First round of key addition: The first multiplexer selects the corresponding master key KEY according to the key length and performs key addition operation with the plaintext data. The master key addition flag is high. The second multiplexer selects the result of 128-bit 4-group round key addition and writes it back to the data iteration register after the forward row shift operation of the forward and reverse row shift module. Round Iteration: The third multiplexer selects 32-bit plaintext according to the data selection signal, and sequentially passes it through the forward and reverse byte substitution module, the fourth multiplexer, the forward and reverse column mixing module, the fifth multiplexer, the round key addition module, the sixth multiplexer, the concatenated iterative data module, the seventh multiplexer, the second multiplexer, and the forward and reverse row shifting module, updating the data iteration register; the forward and reverse byte substitution module performs a forward byte substitution operation, the forward and reverse column mixing module performs a forward column mixing operation, and the forward and reverse row shifting module performs a forward row shifting operation; In the Nrth round of iteration: the third multiplexer selects 32-bit plaintext according to the data selection signal, and passes it sequentially through the forward and reverse byte substitution module, the fourth multiplexer, the fifth multiplexer, the round key addition module, and the sixth multiplexer to update the data iteration register. The forward and reverse byte substitution module performs the forward byte substitution operation.

[0008] In one possible implementation, the decryption process of the encryption / decryption circuit includes: First round of key addition: The first multiplexer selects the corresponding master key KEY according to the key length and performs key addition operation with the plaintext data. The master key addition flag is high. The second multiplexer selects the result of 128-bit 4-group round key addition and performs reverse row shift operation through the forward and reverse row shift module to write back to the data iteration register. Round Iteration: The third multiplexer selects 32-bit plaintext according to the data selection signal, and sequentially passes it through the forward and reverse byte substitution module, the round key addition module, the fourth multiplexer, the forward and reverse column mixing module, the fifth multiplexer, the sixth multiplexer, the concatenated iterative data module, the seventh multiplexer, the second multiplexer, and the forward and reverse row shifting module, updating the data iteration register; the forward and reverse byte substitution module performs the reverse byte substitution operation, the forward and reverse column mixing module performs the reverse column mixing operation, and the forward and reverse row shifting module performs the reverse row shifting operation; In the Nrth round of iteration: the third multiplexer selects 32-bit plaintext according to the data selection signal, and passes it sequentially through the forward and reverse byte substitution module, the fourth multiplexer, the fifth multiplexer, the round key addition module, and the sixth multiplexer to update the data iteration register. The forward and reverse byte substitution module performs the reverse byte substitution operation.

[0009] In one possible implementation, the forward key expansion process for both the encryption and decryption processes includes: W[4N] passes through the key extension row shift module, the ninth multiplexer, the key extension byte substitution module, the round constant XOR module, the key XOR module, the eleventh multiplexer, the key XOR module, and the thirteenth multiplexer in sequence from W[4N-1] to update the corresponding master key KEY; W[4N+1~4N+k] selects the corresponding key through the tenth and twelfth multiplexers and performs an XOR operation, and updates the corresponding master key KEY through the thirteenth multiplexer; After forward key expansion, the master key KEY stores the round key of round Nr, which is used for decryption operations.

[0010] In one possible implementation, the reverse key expansion process of the encryption and decryption processes includes: W[4N+1~4N+k] selects the corresponding key through the tenth and twelfth multiplexers and performs an XOR operation, and updates the corresponding master key KEY through the thirteenth multiplexer; W[4N] is processed sequentially through the key extension row shift module, the ninth multiplexer, the key extension byte substitution module, the round constant XOR module, the eleventh multiplexer, the key XOR module, and the thirteenth multiplexer to update the corresponding master key KEY.

[0011] According to a second aspect of the embodiments of this application, a chip is provided that integrates any of the encryption and decryption circuits described above.

[0012] According to a third aspect of the embodiments of this application, an AES circuit system is provided, comprising: Encryption / decryption circuit, AHB control module, user register module, working mode control module, and GHASH operation circuit; The AHB control module is connected to the working mode control module through the user register module, and the working mode control module is connected to the GHASH operation circuit.

[0013] In one possible implementation, the encryption / decryption circuit includes: a data path module, a control path module, and a data storage module; The data storage module is used to store temporary data and results during the encryption, decryption, and key expansion processes; The control path module is used to generate enable signals and selection signals, control the data selection and data flow direction of the data path, and control the corresponding registers in the data storage module to perform iterative data updates. The data path module is used to process iterative data and keys.

[0014] In one possible implementation, the control path module includes an encryption / decryption control module, a key expansion control module, and a round counter; The data path module includes a round operation data path and a key expansion data path; The data storage module includes a data iteration register, an iteration key register, and an Nr round key register; The encryption / decryption control module is used to control the round operation data path, the data iteration register, and the Nr round key register; The key expansion control module is used to control the key expansion data path and the iterative key register.

[0015] In one possible implementation, the encryption / decryption control module is configured to control the number of round transformation iterations according to the AES-128 / 192 / 256 standard encryption / decryption process, and adopts an encryption / decryption data path multiplexing structure, wherein the encryption data path and decryption data path multiplexing round key addition module, forward and reverse byte substitution module, forward and reverse row shift module, and forward and reverse column hybrid module.

[0016] In one possible implementation, the key expansion control module is configured to control the number of key expansions according to the AES-128 / 192 / 256 standard key expansion process, including a forward and reverse byte substitution module, a cyclic shift module, and a round constant transformation module, wherein the h-transformation and g-transformation reuse the forward and reverse byte substitution module.

[0017] According to a fourth aspect of the embodiments of this application, an AES encryption / decryption method is provided, applied to any of the above-described encryption / decryption circuits, the method comprising: A selection signal is generated through the control path module; Encryption and decryption operations are performed through the round operation data path in the data path module; wherein, the encryption and decryption operations reuse the round key addition module, forward and reverse byte substitution module, forward and reverse row shift module, and forward and reverse column mixing module in the round operation data path; Data from the encryption and decryption process is stored through a data storage module; Specifically, the selection signal controls the multiplexer in the round operation data path to configure different data flow paths in the encryption and decryption processes, so that data can flow through the reused operation module and the intermediate results of the round iteration are stored in the data storage module.

[0018] According to a fifth aspect of the embodiments of this application, an electronic device is provided. The electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and the processor executes the program to implement the method described above.

[0019] According to a sixth aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the methods described above in this application.

[0020] According to a seventh aspect of the embodiments of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the methods described above in this application.

[0021] The encryption / decryption circuit, chip, AES circuit system, and method provided in this application eliminate module redundancy by sharing most of the core circuitry, as encryption and decryption no longer require two separate computing modules. This significantly reduces the number of logic gates, lowering the implementation cost of the circuit, making it particularly suitable for embedded and low-power applications where chip area is critical. Attached Figure Description

[0022] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which: Figure 1 A block diagram of an encryption / decryption circuit provided for an exemplary embodiment of this application; Figure 2 A schematic diagram of the encryption / decryption data flow of an encryption / decryption circuit provided in an exemplary embodiment of this application; Figures 3A-3C An encryption flowchart of an encryption / decryption circuit provided for an exemplary embodiment of this application; Figures 3D to 3F A flowchart illustrating the decryption process of an encryption / decryption circuit provided in an exemplary embodiment of this application; Figure 4A A schematic diagram of the structure of a forward key expansion data path provided in an exemplary embodiment of this application; Figure 4B A schematic diagram of the structure of a reverse key expansion data path provided in an exemplary embodiment of this application; Figure 5 A schematic diagram of AES-128 algorithm key expansion provided for an exemplary embodiment of this application; Figure 6 A schematic diagram of AES-192 algorithm key expansion provided for an exemplary embodiment of this application; Figure 7 A schematic diagram of AES-256 algorithm key expansion provided for an exemplary embodiment of this application; Figure 8 An AES circuit system provided as an exemplary embodiment of this application; Figure 9A An internal architecture diagram of an encryption / decryption circuit provided in an exemplary embodiment of this application; Figure 9B An internal architecture diagram of an encryption / decryption circuit provided in yet another exemplary embodiment of this application; Figure 10 A flowchart of an AES encryption / decryption method provided for an exemplary embodiment of this application. Detailed Implementation

[0023] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0024] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0025] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this application are used only to distinguish different devices, modules, or modules, and are not intended to limit the order of functions performed by these devices, modules, or modules or their interdependencies.

[0026] It should be noted that the terms "a" and "a plurality of" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more". The names of the messages or information exchanged between multiple devices in the embodiments of this application are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0027] like Figure 1 As shown, Figure 1 The block diagram shows an encryption / decryption circuit provided in an embodiment of this application. The encryption / decryption circuit includes: a first multiplexer, a second multiplexer, a third multiplexer, a forward and reverse row shifting module, a forward and reverse byte substitution module, a fourth multiplexer, a forward and reverse column mixing module, a fifth multiplexer, a round key addition module, a sixth multiplexer, a concatenated iterative data module, a seventh multiplexer, and a data iteration register. These modules cooperate through a specific connection method to support forward and reverse (encryption and decryption) data stream processing. The connection relationships of the encryption / decryption circuit are as follows: The output of the first multiplexer is connected to the input of the round key addition module, and the output of the round key addition module is connected to the first input of the second multiplexer through the splicing iterative data module. The second multiplexer is connected to the input of the data iteration register through the forward and reverse row shift modules; The output of the third multiplexer is connected to the input of the fourth multiplexer through a forward and reverse byte substitution module; The output of the fourth multiplexer is connected to the input of the forward and reverse column mixing module and the first input of the fifth multiplexer. The output of the forward and reverse column mixing module is connected to the second input of the fifth multiplexer. The output of the fifth multiplexer is connected to the input of the round key addition module, the sixth multiplexer, and the splicing iterative data module. The output of the round key addition module is connected to the splicing iterative data module through the sixth multiplexer. The output of the splicing iterative data module is connected to the second input of the second multiplexer through the seventh multiplexer. The output of the sixth multiplexer is connected to the input of the data iteration register.

[0028] Specifically, in this embodiment, the output of the first multiplexer is connected to the input of the round key addition module, and is used to send initial data or intermediate data into the round key addition module for key mixing operation.

[0029] The output of the round key addition module is connected to the first input of the second multiplexer through the splicing iterative data module. The splicing iterative data module is used to combine or split data blocks to support iterative processing.

[0030] The output of the second multiplexer is connected to the input of the data iteration register through the forward and reverse row shift module. The forward and reverse row shift module is used to implement the row shift operation of the data, that is, row shift during encryption and reverse row shift during decryption.

[0031] The output of the third multiplexer is connected to the input of the fourth multiplexer through the forward and reverse byte substitution module. The forward and reverse byte substitution module performs byte substitution operations, that is, S-box substitution during encryption and reverse S-box substitution during decryption.

[0032] The output of the fourth multiplexer is connected to the input of the forward and reverse column mixing module and the first input of the fifth multiplexer, respectively. The forward and reverse column mixing module performs column mixing operation, that is, it performs column mixing during encryption and reverse column mixing during decryption.

[0033] The output of the forward and reverse column mixing module is connected to the second input of the fifth multiplexer. The output of the fifth multiplexer is connected to the inputs of the round key addition module, the sixth multiplexer, and the splicing iterative data module, thereby allowing data to be selected between multiple paths.

[0034] The output of the round key addition module is also connected to the splicing iterative data module via a sixth multiplexer to bypass related operations in specific rounds.

[0035] The output of the splicing iterative data module is connected to the second input of the second multiplexer through the seventh multiplexer to realize data feedback or feedforward.

[0036] The output of the sixth multiplexer is directly connected to the input of the data iteration register, which is used to store the final or intermediate data into the data iteration register to support multi-round iterative processing.

[0037] It should be noted that the number of modules such as the wheel encryption module, the splicing iterative data module, the splicing iterative data module, and the register in the embodiment can be set as needed, and the embodiment is not limited to this.

[0038] The encryption / decryption circuit provided in this embodiment dynamically selects the data path through a multiplexer and, combined with forward and reverse row shifting modules, forward and reverse byte substitution modules, and forward and reverse column hybrid modules, achieves a high degree of integration and module reusability for encryption and decryption operations. The data iteration register, by temporarily storing intermediate states, ensures the continuity of the iteration process, thereby efficiently completing the encryption / decryption task.

[0039] like Figure 2 As shown, Figure 2 The diagram illustrates the encryption and decryption data flow of the encryption and decryption circuit provided in the embodiments of this application. The diagram shows how the encryption and decryption processes are implemented by sharing the same set of hardware computing modules.

[0040] In the first round of key addition, the plaintext data and the master key are added by the round key addition module, and the forward row shifting operation is performed by the forward and reverse row shifting module.

[0041] In the first to Nr-1 iterations, the data flows sequentially through: the forward and reverse byte substitution module to perform forward byte substitution, the forward and reverse column mixing module to perform forward column mixing, the round key addition module to perform round key addition, and the forward and reverse row shift module to perform forward row shift.

[0042] In the Nrth iteration, the data flows sequentially through: the forward and reverse byte substitution module to perform forward byte substitution, and the round key addition module to perform round key addition.

[0043] Specifically, during the encrypted data stream phase: (1) First round of key addition.

[0044] The plaintext input and the master key are first XORed by the round key addition module. The result is processed by the forward and reverse row shift modules and then stored in the data iteration register as the input for the first round of iteration.

[0045] (2) Intermediate round iteration (rounds 1 to Nr-1).

[0046] Data flows sequentially through the forward and reverse byte substitution module (performing forward substitution), the forward and reverse column mixing module (performing forward column obfuscation), and the round key addition module, and is then prepared for the next iteration via the forward and reverse row shifting module. This process demonstrates that within the core encryption loop, the four core modules—round key addition, forward and reverse byte substitution, forward and reverse row shifting, and forward and reverse column mixing—are continuously reused. Here, Nr represents the iteration number.

[0047] (3) The last round (round Nr).

[0048] The implementation can determine whether it is an iteration round by the value of Nr. If it is an iteration round, the intermediate round iteration described above is executed; otherwise, the subsequent round is executed. This process is similar to the intermediate round, but according to the requirements of the AES standard algorithm, the column mixing operation is omitted. The data passes through the forward and reverse byte substitution module to perform forward byte substitution and the round key addition module to perform key addition operation, and then the final ciphertext output is generated.

[0049] During the data stream decryption phase: In the first iteration, the key addition operation between the ciphertext data and the master key is performed by the round key addition module, and the reverse row shift operation is performed by the forward and reverse row shift module.

[0050] In the first to Nr-1 iterations, the data flows sequentially through: the forward and reverse byte substitution module to perform reverse byte substitution, the round key addition module to perform round key addition, the forward and reverse column mixing module to perform reverse column mixing, and the forward and reverse row shifting module to perform reverse row shifting.

[0051] In the Nrth iteration, the data flows sequentially through: the forward and reverse byte substitution module to perform reverse byte substitution, and the round key addition module to perform round key addition.

[0052] In the embodiment, Nr > 1 and Nr is a positive integer.

[0053] Specifically: (1) First round of key addition.

[0054] After the ciphertext input and the master key are XORed by the round key addition module, the result is processed by the forward and reverse row shift module and written into the data iteration register.

[0055] (2) Intermediate round iteration (rounds 1 to Nr-1).

[0056] The data flow order differs from that of encryption, sequentially flowing through the forward and reverse byte substitution module, the round key addition module, the forward and reverse column mixing module, and the forward and reverse row shifting module. This path demonstrates the hardware of the encryption process reused in the decryption process; that is, the reverse byte substitution in the decryption process and the forward byte substitution in the encryption process are manifestations of the same S-Box lookup logic under different address mappings; the reverse column mixing and the forward column mixing share the core of the Galois field multiplier; and the reverse row shift and the row shift are the same shift logic changing direction under control signals.

[0057] (3) The last round (round Nr).

[0058] The implementation can determine whether it is an iteration round by the value of Nr. If it is an iteration round, the intermediate round iteration described above is executed; otherwise, the last round is executed. This round also omits column mixing operations. After the data is processed by the forward and reverse byte substitution module to perform reverse byte substitution and the round key addition module to perform key addition, the final plaintext is recovered.

[0059] This embodiment demonstrates the encryption and decryption data streams in parallel, with the encryption and decryption sharing the same computing module. This allows the encryption and decryption functions to converge to the same set of physical hardware through dynamically configured data paths, which fundamentally eliminates the need for parallel dual circuits in traditional designs, thereby reducing chip area and power consumption.

[0060] As a specific implementation of the above embodiments Figures 3A-3C This is a flowchart illustrating the encryption process of the encryption / decryption circuit provided in an embodiment of this application. Figures 3D to 3F This is a flowchart illustrating the decryption process of the encryption / decryption circuit provided in this application embodiment. This embodiment, in conjunction with the above-described encryption / decryption circuit process, describes the specific steps of an encryption / decryption method employing an iterative multiplexing structure. This process is controlled by a selection signal and guided by a multiplexer, enabling efficient multiplexing of the core hardware module for encryption and decryption operations. Figure 3A The red part in the image represents the first round of encryption. Figure 3B The green part in the diagram represents rounds 1 to Nr-1 of the encryption process. Figure 3C The blue part in the image represents the final round (Nrth round) of the encryption process. Figure 3D The red part in the image represents the first round of decryption. Figure 3E The green part in the diagram represents the decryption process from round 1 to Nr-1. Figure 3F The blue part in the diagram represents the final round (round Nr) of the decryption process.

[0061] In this embodiment, the encryption process of the encryption / decryption circuit may include: First round of key addition: The first multiplexer selects the corresponding master key KEY according to the key length and performs key addition operation with the plaintext data. The master key addition flag is high. The second multiplexer selects the result of 128-bit 4-group round key addition and writes it back to the data iteration register after forward row shift operation of the forward and reverse row shift module. Round Iteration: The third multiplexer selects 32-bit plaintext based on the data selection signal, and it passes sequentially through the forward and reverse byte substitution module, the fourth multiplexer, the forward and reverse column mixing module, the fifth multiplexer, the round key addition module, the sixth multiplexer, the iterative data splicing module, the seventh multiplexer, the second multiplexer, and the forward and reverse row shifting module, updating the data iteration register; the forward and reverse byte substitution module performs forward byte substitution operation, the forward and reverse column mixing module performs forward column mixing operation, and the forward and reverse row shifting module performs forward row shift operation; In the Nrth round of iteration: the third multiplexer selects 32-bit plaintext based on the data selection signal, and it passes sequentially through the forward and reverse byte substitution module, the fourth multiplexer, the fifth multiplexer, the round key addition module, and the sixth multiplexer, updating the data iteration register. The forward and reverse byte substitution module performs the forward byte substitution operation.

[0062] In this embodiment, the decryption process of the encryption / decryption circuit includes: First round of key addition: The first multiplexer selects the corresponding master key KEY according to the key length and performs key addition operation with the plaintext data. The master key addition flag is high. The second multiplexer selects the result of 128-bit 4-group round key addition, performs reverse row shift operation through the forward and reverse row shift module, and writes it back to the data iteration register. Round Iteration: The third multiplexer selects 32-bit plaintext based on the data selection signal, and it passes sequentially through the forward and reverse byte substitution module, the round key addition module, the fourth multiplexer, the forward and reverse column mixing module, the fifth multiplexer, the sixth multiplexer, the iterative data splicing module, the seventh multiplexer, the second multiplexer, and the forward and reverse row shifting module, updating the data iteration register; the forward and reverse byte substitution module performs the reverse byte substitution operation, the forward and reverse column mixing module performs the reverse column mixing operation, and the forward and reverse row shifting module performs the reverse row shift operation; In the Nrth round of iteration: the third multiplexer selects 32-bit plaintext based on the data selection signal, and it passes sequentially through the forward and reverse byte substitution module, the fourth multiplexer, the fifth multiplexer, the round key addition module, and the sixth multiplexer, updating the data iteration register. The forward and reverse byte substitution module performs the reverse byte substitution operation.

[0063] Specifically, the first multiplexer may include MUX0 to MUX3, the second multiplexer may include MUX9, the third multiplexer may include MUX4, the fourth multiplexer may include MUX5, the fifth multiplexer may include MUX6, the sixth multiplexer may include MUX7, and the seventh multiplexer may include MUX10.

[0064] Specifically, in the encryption process: (1) Combination Figure 3A As shown, the first round of key encryption may specifically include: Operation: Multiplexers MUX0 to MUX3 select the corresponding master key (KEY) according to the key length and perform key addition operation with the input plaintext data (DATA).

[0065] Path: At this time, the master key addition flag is high, and the multiplexer MUX9 selects the result of the 128-bit (divided into 4 groups) round key addition, and writes it back to the data iteration register after a forward row shift operation.

[0066] Function: To complete the first round of initialization for encryption operations.

[0067] (2) Combination Figure 3B As shown, the encryption in round iterations (rounds 1 to Nr-1) can specifically include: Operation: This encryption process is an iterative encryption step. The multiplexer MUX4 selects 32-bit intermediate data from the data iteration register according to the selection signal and inputs it into the round operation data path.

[0068] Path: In this iterative process, data flows sequentially through the following modules to form a complete encryption transformation chain: ① Forward and reverse byte substitution module; The data first enters this module, where a forward byte substitution operation is performed to achieve a non-linear transformation of the data.

[0069] ② Selected via MUX5; The byte-switched data passes through a fourth multiplexer (MUX5). During the encryption process, the MUX5 is configured to direct the data to the column mixing module.

[0070] ③ Mixed forward and reverse column module; When data enters this module, a forward column mixing operation is performed to diffuse the columns of the state matrix, enhancing the algorithm's obfuscation characteristics.

[0071] ④ Selected via MUX6; The column-mixed data arrives at the fifth multiplexer (MUX6). At this point, since the last round has not been reached (the Nr-th round flag is invalid), MUX6, under the action of the control signal, selects to receive the output data from the forward and reverse column mixing module. At this time, the Nr-th round flag is invalid, and MUX6 selects the output of the forward and reverse column mixing module to ensure that the column mixing operation is executed normally.

[0072] ⑤ Round key addition module; The data stream is fed to the round key addition module, where it is XORed with the round key of the current round.

[0073] ⑥ Selected via MUX7; The data is sent to the splicing iterative data module via the sixth multiplexer (MUX7).

[0074] ⑦ After being concatenated with the remaining data, it is selected by MUX10 and MUX9; In the data concatenation and iteration module, the currently processed 32-bit data is concatenated with the remaining 96-bit data in the data iteration register that was not processed in this round, and recombined into a complete 128-bit state. This combined data passes sequentially through the seventh multiplexer (MUX10) and the second multiplexer (MUX9), where MUX9 selects this path in round iteration mode to send the data to the row shifting module.

[0075] ⑧ Forward and reverse row shifting module.

[0076] The data eventually enters the forward and reverse row shifting module, where a forward row shift operation is performed, completing the final transformation step of this iteration.

[0077] Result: Update the value in the data iteration register to complete one iteration. This process is repeated Nr-1 times.

[0078] In this embodiment, the shifted data is written back to the data iteration register to update its contents, serving as the input state for the next iteration. This process is repeated Nr-1 times until the encryption transformation of all intermediate rounds is completed.

[0079] Reuse is reflected in the fact that the round key addition module, the forward and reverse byte substitution module, the forward and reverse row shifting module, and the forward and reverse column hybrid module are reused in this multi-round iteration.

[0080] (3) Combination Figure 3C As shown, the encryption in the Nrth iteration can specifically include: Operation: The last round of iteration omits column mixing operations, which is based on the requirements of the AES standard algorithm.

[0081] According to the requirements of the AES standard algorithm, the final round of encryption iteration omits column mixing operations. This special process is implemented by dynamically configuring the data path through control signals (such as the Nr-th round flag).

[0082] Path: Data flows sequentially through: ① Forward and reverse byte substitution module; The data first enters this module, where a forward byte substitution operation is performed, completing the final round of non-linear transformation.

[0083] ②After selection by MUX5, the forward and reverse column mixing module is bypassed, and selection is directly performed by MUX6; After the byte-swapping data passes through the fourth multiplexer (MUX5), because the Nr-th round flag is valid, the fifth multiplexer (MUX6) no longer selects to receive data from the forward and reverse column mixing module, but directly selects the pass-through path from MUX5. This bypasses the forward and reverse column mixing module and conforms to the algorithm standard.

[0084] At this point, the data, after forward byte substitution, is output through MUX5. The Nr-th round flag is now valid, and MUX6 selects the direct path, skipping the forward column mixing module and directly sending the data to the round key addition module. This avoids unnecessary column mixing operations, reducing computational latency and power consumption.

[0085] ③ Round key addition module; The data goes directly into the round key addition module and is XORed with the round key of the last round.

[0086] ④ Selected via MUX7; The data is transmitted to the subsequent processing unit via the sixth multiplexer (MUX7).

[0087] Result: Update the data iteration register to obtain the final ciphertext output.

[0088] This process demonstrates how the encryption / decryption circuitry dynamically switches operation sequences through control. In the final round, by enabling the Nr-th round flag to control the selection of MUX6, the forward and reverse column mixing module is automatically skipped in this round. This strictly adheres to the AES algorithm specification while avoiding unnecessary module activation and saving power. Simultaneously, the round key addition module and the forward and reverse byte substitution module are reused in this round, demonstrating the efficient and consistent utilization of hardware resources throughout the entire encryption process (from the first round to the last).

[0089] In the first to Nr-1 iterations of the decryption process, the data stream sequentially undergoes reverse byte substitution via the forward and reverse byte substitution module, round key addition via the round key addition module, reverse column mixing via the forward and reverse column mixing module, and reverse row shift via the forward and reverse row shift module.

[0090] In this embodiment, although the data flow order in the decryption process differs from that in the encryption process, the forward and reverse byte substitution module, round key addition module, forward and reverse column mixing module, and forward and reverse row shifting module used in the decryption process are exactly the same as those in the encryption process. Only the working mode (forward / reverse) and execution order are changed through control signals. This embodiment demonstrates that two operation modes can be implemented by dynamically configuring a single data path, which is a direct manifestation of deep reuse of hardware resources and fundamentally avoids hardware redundancy caused by dual encryption and decryption paths.

[0091] In the decryption process: (1) Combination Figure 3D As shown, the first round of key encryption may specifically include: Operation: Similar to the first round of encryption, MUX0 to MUX3 select the corresponding master key and perform key addition operation with the ciphertext data.

[0092] Path: After the master key is set to high with the flag bit, the result is selected by MUX9 and written back to the data iteration register through the reverse row shift operation of the forward and reverse row shift module.

[0093] Reuse is reflected in this step: the round key addition module and the forward and reverse row shifting module in the encryption process are reused (by configuring it to reverse mode).

[0094] (2) Combination Figure 3E As shown, the decryption process in round iterations (rounds 1 to Nr-1) can specifically include: Operation: The multiplexer MUX4 selects 32-bit intermediate data from the data iteration register according to the selection signal and inputs it into the round operation data path.

[0095] Path: Data flows sequentially through: ① Forward and reverse byte substitution module; The data first enters this module, where a reverse byte substitution operation is performed, and the current round of decryption transformation begins.

[0096] ② Round key addition module; The data that has undergone reverse byte substitution is directly fed into the round key addition module and XORed with the round key of the current round.

[0097] ③ Selected via MUX5; The data after round key addition passes through a fourth multiplexer (MUX5). In the intermediate round of the decryption process, the MUX5 is configured to guide the data to the forward and reverse column mixing module.

[0098] ④ Mixed forward and reverse column module; When data enters this module, a reverse column mixing operation is performed to undo the diffusion effect of column mixing during the encryption process.

[0099] ⑤ Selected via MUX6; The reverse column mixed data arrives at the fifth multiplexer (MUX6). At this time, the Nrth round flag is invalid, and MUX6, under the action of the control signal, selects to receive the output data from the forward and reverse column mixing module.

[0100] ⑥ Selected via MUX7; The data is sent to the splicing iterative data module via the sixth multiplexer (MUX7).

[0101] ⑦ After splicing, it is selected by MUX10 and MUX9; In the data concatenation and iteration module, the currently processed 32-bit data is concatenated with the remaining data in the data iteration register that was not processed in this round, and recombined into a complete 128-bit state. This combined data passes sequentially through the seventh multiplexer (MUX10) and the second multiplexer (MUX9), where MUX9 selects this path in round iteration mode to send the data to the row shifting module.

[0102] ⑧ Forward and reverse row shifting modules; The data eventually enters the forward and reverse row shift module, where the reverse row shift operation is performed, completing the final transformation step of this iteration.

[0103] Result: Update the data iteration register. This process is repeated Nr-1 times.

[0104] The data, after being reverse-shifted, is written back to the data iteration register, updating its contents and serving as the input state for the next iteration. This process is repeated Nr-1 times until all intermediate rounds of decryption transformation are completed.

[0105] Reuse is reflected in the fact that, in the aforementioned multiple iterations, the decryption process reuses the same round key addition module, forward and reverse byte substitution module, forward and reverse column mixing module, and forward and reverse row shifting module as the encryption process. The core difference lies only in changing the gating state of multiplexers such as MUX5 and MUX6 through control signals, thereby reorganizing the order in which the data flows through these multiplexing units (for example, performing round key addition first and then reverse column mixing), realizing flexible switching from encryption to decryption functions, and fundamentally eliminating the hardware redundancy caused by building two independent data paths.

[0106] (3) Combination Figure 3F As shown, the decryption in the Nrth iteration can specifically include: Operation: Similar to the final round of encryption, the final iteration of the decryption process also omits the column mixing operation, according to the requirements of the AES standard algorithm. This is achieved by dynamically configuring the multiplexer through signals such as the Nr-th round flag generated by the control path module.

[0107] Path: In this final round of decryption iteration, the data flows sequentially through: ① Forward and reverse byte substitution module; The data first enters this module, where a reverse byte substitution operation is performed to complete the final round of nonlinear inverse transformation.

[0108] ② By selecting via MUX5 and MUX6, the forward and reverse column hybrid module is bypassed; The data that has completed the reverse byte substitution passes through the fourth multiplexer (MUX5). At this point, since the Nr-th round flag is valid, the fifth multiplexer (MUX6) is configured to directly select the pass-through path from MUX5, thereby bypassing the forward and reverse column mixing module and skipping the reverse column mixing operation.

[0109] ③ Round key addition module; The data goes directly into the round key addition module and is XORed with the round key of the last round.

[0110] ④ Selected via MUX7.

[0111] The data is transmitted to the subsequent processing unit via the sixth multiplexer (MUX7).

[0112] Result: Update the data iteration register to obtain the final plaintext output.

[0113] The above process illustrates the flexibility and efficiency of the encryption / decryption circuit architecture. By uniformly controlling the MUX6 in the final round of encryption and decryption through the Nr-th round flag, the column mixing module can be intelligently bypassed in the final round, ensuring the correctness of the algorithm execution. This not only strictly adheres to the AES standard but also effectively reduces system power consumption by avoiding the activation of relatively complex column mixing logic in the final round. Throughout the decryption process, core units such as the round key addition module and the forward and reverse byte substitution module are continuously reused, fully demonstrating the unified management of hardware resources throughout the entire encryption and decryption process.

[0114] This embodiment demonstrates, through the aforementioned encryption and decryption process, that by utilizing a multiplexer, two different data stream paths are configured for encryption and decryption without adding redundant hardware. This allows the same set of computational modules (round key addition module, forward and reverse byte substitution module, forward and reverse row shifting module, and forward and reverse column hybrid module) to be efficiently reused in both computational modes. This iterative reuse structure significantly reduces circuit resource consumption and power consumption, providing technical support for the integration of the AES algorithm into low-power systems.

[0115] In one embodiment provided in this application, the functionality of the encryption / decryption circuit described above is further specified. This encryption / decryption circuit is designed as an intelligent, configurable control core capable of supporting the complete AES algorithm standard.

[0116] In this embodiment, the encryption / decryption circuit is configured to support AES-128, AES-192, and AES-256 algorithms, and adaptively switches between them by changing the iteration number Nr through a control wheel.

[0117] Specifically, the encryption / decryption circuit is configured to support three algorithm standards: AES-128, AES-192, and AES-256. Its core control mechanism is to adaptively switch and control the number of round transformation iterations Nr in the encryption / decryption process by recognizing the key length configuration information of external input or internal registers.

[0118] When the key length is 128 bits, the encryption / decryption circuit sets the round transformation iteration number Nr to 10.

[0119] When the key length is 192 bits, the encryption / decryption circuit sets the round transformation iteration number Nr to 12.

[0120] When the key length is 256 bits, the encryption / decryption circuit sets the round transformation iteration number Nr to 14.

[0121] The encryption / decryption circuit can integrate a round counter to accurately track the number of rounds executed during the encryption / decryption process. The circuit uses a preset Nr value (10, 12, or 14) as the target, updates the counter after each iteration using comparison logic, and issues a process termination signal when the target number of rounds is reached, thereby controlling the data path to complete the entire encryption / decryption operation.

[0122] This embodiment integrates the aforementioned optimized data paths (such as multiplexing structures and folded key expansion) into a highly efficient, unified, and intelligent whole through a sophisticated Nr control strategy. Ultimately, this achieves the goal of providing multi-standard, high-performance AES computation on a single hardware platform with low power consumption and small area cost.

[0123] In conjunction with the above embodiments, in another embodiment provided in this application, the encryption / decryption circuit further includes forward and reverse key expansion data paths for generating the required round keys for encryption and decryption operations. This key expansion data path also employs a multiplexing design to support forward (for encryption) and reverse (for decryption) key expansion processes. The forward and reverse key expansion data paths include: a key expansion row shift module, a key expansion byte substitution module, a round constant XOR module, a ninth multiplexer, a key XOR module, a tenth multiplexer, an eleventh multiplexer, a twelfth multiplexer, and a thirteenth multiplexer; wherein, The input of the key extension row shift module is connected to the output of the external iterative key register, and the output of the key extension row shift module is connected to the input of the key extension byte substitution module through the ninth multiplexer. The output of the key extension byte substitution module is connected to the input of the round constant XOR module. The output of the key extension byte substitution module is connected to the first input of the key XOR module through the tenth multiplexer and the eleventh multiplexer. The input of the tenth multiplexer is connected to the output of the iterative key register. The output of the round constant XOR module is connected to the first input of the key XOR module through the eleventh multiplexer. The second input of the key XOR module is connected to the iterative key register through the twelfth multiplexer, and the output of the key XOR module is connected to the iterative key register through the thirteenth multiplexer.

[0124] Specifically, in this embodiment, the input of the key extension row shift module is connected to the output of an external iterative key register to receive the intermediate key word to be processed. The output of the key extension row shift module is connected to the input of the key extension byte substitution module via a ninth multiplexer.

[0125] The output of the key expansion byte substitution module is connected to the input of the round constant XOR module on one side, and to the eleventh multiplexer via the tenth multiplexer, ultimately feeding the data to the first input of the key XOR module. The input of the tenth multiplexer is also connected to the output of the iterative key register, used to select different key word sources. The output of the round constant XOR module is also connected to the first input of the key XOR module via the eleventh multiplexer.

[0126] The second input of the key XOR module is connected to the iteration key register via the twelfth multiplexer, used to select another key word to participate in the XOR operation. The output of the key XOR module is then connected back to the iteration key register via the thirteenth multiplexer, used to write the newly generated round key word back to storage.

[0127] This key expansion data path, through the coordinated selection of the aforementioned multiplexer network under different control signals, configures different data paths for forward and reverse key expansion. Since the key expansion byte substitution module and the forward and reverse byte substitution modules in the round operation data path are the same physical hardware unit, during key expansion, the key word to be processed is routed to this shared byte substitution unit to perform the S-box substitution operation. This avoids the need to set up a separate S-box lookup table for key expansion, greatly saving chip area.

[0128] Through this highly integrated and reusable design, the key expansion data path provided in this embodiment can efficiently and flexibly generate all round keys required for encryption and decryption, further enhancing the core competitiveness of the entire AES operation circuit in terms of low power consumption and small area.

[0129] In conjunction with the above embodiments, such as Figure 4A As shown, Figure 4A This is a schematic diagram of the forward key expansion data path provided in an embodiment of this application. The diagram illustrates how an optimized hardware structure efficiently generates the round keys required for AES encryption and demonstrates the key multiplexing design. Specifically, the key expansion row shifting module can be a forward / reverse byte substitution module, and the key expansion byte substitution module can be a forward / reverse byte substitution module. The ninth, tenth, eleventh, twelfth, and thirteenth multiplexers can be MUX0, MUX1, MUX2, MUX3, and MUX4, respectively.

[0130] Therefore, in this embodiment, the key expansion data path includes a forward and reverse byte substitution module, a round constant XOR module, a round constant generation module, and a forward and reverse row shift module. These modules can all be 32-bit. The key expansion data path updates the 32-bit round key every cycle. AES-128 / 192 / 256 is expanded every 4 / 6 / 8 cycles, N is the number of iteration rounds, AES-128 / 192 / 256 iterates 10 / 8 / 7 rounds respectively, and k is the number of iterations per round. Figure 4A As shown, where: Iterative key register: Used to store and iteratively update intermediate key words generated during key expansion.

[0131] 32-bit forward and reverse row shift module: performs cyclic shift operations on the input key word.

[0132] 32-bit forward and reverse byte substitution module: Performs S-Box byte substitution on the shifted key. This is a critical multiplexing point; this module shares the same physical hardware as the forward and reverse byte substitution module in the round operation data path.

[0133] Round constant XOR module: Performs an XOR operation between the result of byte substitution and a predefined round constant, which is part of the AES key extension standard procedure.

[0134] The round constant generation module is used to generate constants for the current round.

[0135] Multiplexer (MUX): Based on the key expansion control logic, selects the correct key path for subsequent XOR and update operations.

[0136] Specifically, the execution flow of the forward key expansion data path may include: Path start point: Retrieve the specific key word (such as W[4N-1]) generated in the previous expansion round from the iterative key register.

[0137] Core Transformation (g Transformation): The key word flows through the following sequentially: 32-bit forward and reverse row shift module; 32-bit forward and reverse byte substitution module (reuses self-rotation operation path); Wheel constant XOR module; Path integration and update: The result after the above g transformation is selected by a multiplexer and XORed with another key word in the iterative key register. Finally, the generated new round key word is written back to the iterative key register to complete the update.

[0138] In the embodiments provided in this application, the forward key expansion process of the encryption and decryption processes includes: W[4N] is processed sequentially through the key extension row shift module, the ninth multiplexer, the key extension byte substitution module, the round constant XOR module, the key XOR module, the eleventh multiplexer, the key XOR module, and the thirteenth multiplexer to update the corresponding master key KEY.

[0139] W[4N+1~4N+k] selects the corresponding key through the tenth and twelfth multiplexers and performs an XOR operation, and updates the corresponding master key KEY through the thirteenth multiplexer.

[0140] After forward key expansion, the master key KEY stores the round key of round Nr, which is used for decryption operations.

[0141] Specifically, in this embodiment, for the generation of the key word W[4N], the data is retrieved from the iterative key register of the data storage module, and then flows sequentially through the forward and reverse row shift module, guided to the forward and reverse byte substitution module, and the round constant XOR module. After XORing with the key word W[4N-4], the iterative key register is updated. For the generation of key words W[4N+1] to W[4N+k], the iterative key register is updated by selecting the corresponding already generated key word and performing an XOR operation.

[0142] In the embodiments, combined with Figure 4A The forward key expansion data path structure shown, taking AES128 as an example, has the following forward key expansion process: Step 1, corresponding to Figure 4A The red path in the middle is used to generate the key word at position W[4N] in the round key array.

[0143] Specifically, the key word W[4N-1] obtained from the previous round of expansion is read from the iterative key register.

[0144] The key is first cyclically shifted by the forward and reverse row shifting module, and then guided by the multiplexer MUX0 to the forward and reverse byte substitution module to perform forward byte substitution (the forward and reverse byte substitution module in the round operation data path is reused here).

[0145] The result of the replacement is XORed with the round constant, then selected by the multiplexer MUX2, and XORed with the key word W[4N-4] in the iterative key register.

[0146] Finally, the result of the operation is written back to the corresponding position of the iteration key register as the new round key word W[4N] through the multiplexer MUX4.

[0147] It should be noted that, taking W[4N-4] as an example, the following explanation is provided: W: Represents a 32-bit (4-byte) key word, which is the basic unit of key expansion.

[0148] [ ]: The numbers inside are indices, indicating the position of the key in the entire extended key sequence.

[0149] 4N: N represents the number of rounds of key expansion, and 4N means that each round of expansion will generate 4 new keywords (for AES-128).

[0150] Therefore, 4N - 4 represents the index of the four positions preceding the current expansion round.

[0151] Step 2, direct XOR path (corresponding to...) Figure 4A The green path in the middle is used to generate the subsequent key words at positions W[4N+1] to W[4N+3].

[0152] This path generates subsequent round key words (taking AES-128 as an example, k=3, i.e. W[4N+1], W[4N+2], W[4N+3]).

[0153] Using multiplexers MUX1 and MUX3, the currently generated key word (such as the previous W[4N+m]) is XORed with the key word W[4N+m-4].

[0154] The XOR result is written back to the iteration key register via the multiplexer MUX4, and updated with the corresponding new round key word.

[0155] Step 3, Process Completion and Output: Repeat the above steps to complete the entire key expansion process. After the forward key expansion process is completed, the last round key stored in the iterative key register (KEY) can be directly used for subsequent decryption operation initialization.

[0156] In this embodiment, the reverse key expansion process of the encryption and decryption processes may include: W[4N+1~4N+k] selects the corresponding key through the tenth and twelfth multiplexers and performs an XOR operation, and updates the corresponding master key KEY through the thirteenth multiplexer.

[0157] W[4N] is processed sequentially through the key extension row shift module, the ninth multiplexer, the key extension byte substitution module, the round constant XOR module, the eleventh multiplexer, the key XOR module, and the thirteenth multiplexer to update the corresponding master key KEY.

[0158] Specifically, such as Figure 4B As shown, Figure 4B This is a schematic diagram of the structure of the reverse key expansion data path provided in the embodiments of this application.

[0159] When the key expansion data path is configured to perform reverse key expansion: For the generation of key words W[4N+1] to W[4N+k], the corresponding generated key word is selected and XORed to update the key register in the iterative data storage module; for the generation of key word W[4N], the data is taken from key word W[4N+k] in the iterative key register, and flows through forward and reverse row shift module, guided to forward and reverse byte substitution module, round constant XOR module, and then XORed with key word W[4N+4] to update iterative key register.

[0160] Specifically, in this embodiment, it can be combined with Figure 4B The reverse key expansion data path structure shown, taking the AES-128 algorithm as an example, involves reversing the key expansion algorithm to derive the previous round keys from the last round key, thus preparing the key sequence required for the decryption process. The reverse key expansion process is as follows: Step 1, direct XOR path (corresponding to...) Figure 4B The red path in the middle is used to reverse derive the key words at positions W[4N+3] to W[4N+1] ( First, the currently recovered key (e.g., W[4N+m]) is selected and reversed XORed with the key W[4N+m-4] using multiplexers MUX1 and MUX3.

[0161] The XOR result is written back to the iteration key register via the multiplexer MUX4 and updated to W[4N+m-1] (taking k=3 as an example, W[4N+3], W[4N+2], W[4N+1] are generated in reverse order).

[0162] Step 2, Core Inverse Transformation Path (corresponding to the blue path in the diagram, used for reverse derivation of the key word at position W[4N]): Read the key word W[4N+1] generated in step 1 from the iterative key register.

[0163] The key word passes through the forward and reverse row shifting module and the multiplexer MUX0 in sequence, and is then guided to the forward and reverse byte substitution module to perform forward byte substitution (the forward and reverse byte substitution module in the round operation data path is reused here as well).

[0164] The result of the replacement is XORed with the round constant, then selected by the multiplexer MUX2, and XORed with the key word W[4N+4] in the iterative key register.

[0165] Finally, the result of the operation is written back to the corresponding position of the iteration key register as the round key word W[4N] derived in reverse through the multiplexer MUX4.

[0166] like Figure 5 As shown, Figure 5 This diagram illustrates the key expansion of the AES-128 algorithm as provided in this application embodiment. The diagram visually demonstrates, through a topological structure, how all round keys required for the encryption process are generated from the original key (initial round key) through multiple rounds of iteration.

[0167] The key expansion process is as follows: (1) Initialization: The leftmost W[0], W[1], W[2], and W[3] in the diagram constitute the initial 128-bit master key, which is divided into four 32-bit words.

[0168] (2) Iterative expansion process: The entire expansion process is an iterative process performed in rounds. Each round of expansion generates a new round key of 128 bits (4 new words).

[0169] Taking the first round of expansion as an example, new W[4], W[5], W[6], and W[7] are generated by performing specific transformations on W[0], W[1], W[2], and W[3]. The key step in this process involves the g transformation.

[0170] This iterative process continues until all the required round keys are generated. For AES-128, a total of 10 rounds of encryption are required, so key expansion requires the generation of 11 sets of 128-bit round keys (including the first round using the master key). The diagram shows the complete generation path from the initial key to the final round key (W

[40] to W

[43] ).

[0171] (3) The core function of g transformation: The 'g' labeled in the diagram represents the core nonlinear transformation function in key expansion. As described in the previous embodiment, this 'g' transformation specifically includes: row shifting, byte substitution (multiplexing the forward and reverse byte substitution modules in the self-round operation data path), and round constant XOR.

[0172] Figure 5 This embodiment clearly reveals the holistic and iterative nature of AES-128 key expansion at the system level. In conjunction with the aforementioned embodiments, the key expansion data path in this embodiment achieves hardware optimization of this iterative process by multiplexing the forward and reverse byte substitution modules and folding multiple operations in the g-transform into an efficient path. This enables the circuit structure provided in this application embodiment to fully and correctly implement the key expansion algorithm specified by the AES-128 standard with low power consumption and small hardware cost, providing reliable key support for encryption and decryption operations.

[0173] like Figure 6 As shown, this is a schematic diagram of the AES-192 algorithm key expansion provided in an embodiment of this application. The diagram illustrates the round key expansion process and data organization method when using a 192-bit key, demonstrating the complete support of the AES-192 standard by the aforementioned encryption / decryption circuit.

[0174] Combination Figure 6 As shown, the AES-192 key expansion process is as follows: (1) Initialization: The leftmost W[0], W[1], W[2], W[3], W[4], and W[5] in the diagram constitute the initial 192-bit master key, which is divided into six 32-bit words.

[0175] (2) Iterative expansion process: The expansion process is iterated in rounds. Due to the different key lengths, its expansion pattern differs from that of AES-128.

[0176] Each round of expansion generates 6 new key words based on the 6 key words from the previous round. For example, the first round of expansion takes the previous 6 words (W[0]~W[5]) as input and generates 6 new words (W[6]~W

[11] ) through operations including g transformation.

[0177] This process continues iteratively until all the required round keys are generated. For AES-192, a total of 12 rounds of encryption are required, and key expansion requires 7 rounds of iteration (since each round generates 6 words, a total of 8×6=48 words are generated, which satisfies the 12 rounds of encryption and the 13 sets of 128-bit round keys required for the first round).

[0178] It should be noted that in the final round of expansion, as shown in the figure, generating W

[48] ~W

[51] from W

[42] ~W

[47] only produces 4 new words. This is because the total number of generated key words has already met all the requirements of AES-192 encryption and decryption.

[0179] (3) Multiplexing of the g transform: Similar to AES-128, the g transform marked in the figure also includes row shifting, byte substitution (reusing the forward and reverse byte substitution modules in the round operation data path), and round constant XOR operation. This demonstrates that the key extension data path of this invention can adapt to different key lengths through a unified hardware design.

[0180] Figure 6 As demonstrated by the foregoing embodiments, the encryption / decryption circuit provided in this application, through configurable control logic, can flexibly handle the specific rule of generating 6 key words per round in AES-192 key expansion. This verifies the versatility and efficiency of the circuit architecture provided in this application. That is, through the same highly optimized hardware data path that reuses the forward and reverse byte substitution modules, coupled with corresponding control signals, it can seamlessly support multiple standards such as AES-128 and AES-192 without requiring independent circuits for different key lengths. This ensures performance while maximizing the optimization of chip area and power consumption.

[0181] like Figure 7 As shown, this is a schematic diagram of AES-256 algorithm key expansion provided in an embodiment of this application. The diagram fully illustrates the expansion process and organization of the round key when using a 256-bit key, clearly demonstrating the comprehensive compatibility and efficient support of the encryption / decryption circuit provided in this embodiment for the highest security level, AES-256.

[0182] Combination Figure 7 As shown, the AES-256 key expansion process is as follows: (1) Initialization: The leftmost W[0] to W[7] in the diagram constitute the initial 256-bit master key, which is divided into eight 32-bit words.

[0183] (2) Iterative expansion process: The expansion process exhibits a unique iterative pattern, reflecting the special characteristics of the AES-256 algorithm.

[0184] Each round of expansion generates eight new keys based on the eight keys from the previous round. For example, the first round of expansion takes W[0]~W[7] as input and generates W[8]~W

[15] .

[0185] For AES-256, its extended algorithm alternates between g-transform and h-transform in each round of 8 output words. Specifically, g-transform (including row shift, byte substitution and round constant XOR) is applied when generating positions such as W[8] and W

[16] ; while h-transform (mainly including byte substitution) is applied when generating positions such as W

[12] and W

[20] .

[0186] This process is iterative. For AES-256, a total of 14 rounds of encryption are required, and key expansion requires 7 rounds of iteration. Similar to AES-192, the last round of expansion (generating W

[56] ~W

[59] from W

[48] ~W

[55] ) only produces 4 new words, because it has already satisfied all the requirements of the algorithm.

[0187] (3) High-level reuse of transformation modules: Figure 7 Both the g-transform and h-transform shown involve byte substitution operations. Whether it's the g-transform or the h-transform, the same forward and reverse byte substitution modules in the same round operation data path are reused to complete the S-Box lookup. This avoids configuring two different sets of byte substitution logic separately for key expansion, achieving optimal utilization of hardware resources.

[0188] This embodiment extends the data path architecture with a unified key and, through sophisticated control logic, can flexibly adapt to the complex extension rules in the AES-256 standard that alternate between g-transform and h-transform. This ultimately verifies that the iterative multiplexing structure proposed in this embodiment possesses excellent versatility and configurability. The same hardware, through signal configuration, can seamlessly support algorithms with three different security levels: AES-128, AES-192, and AES-256, fundamentally eliminating the need to design multiple independent circuits for different standards, thus achieving the optimal balance between chip area, power consumption, and performance at the highest level.

[0189] Based on the encryption / decryption circuit provided in the above embodiments, this embodiment further optimizes the timing efficiency of the key expansion data path. Therefore, the key expansion data path can be configured to fold the cyclic shift, byte substitution, round constant XOR, and key XOR operations into a single clock cycle.

[0190] Specifically, in the embodiment, the key expansion data path is configured to fold the core operation sequence in key expansion, namely RotWord, SubWord, Round Constant XOR, and Key XOR, into a single clock cycle.

[0191] In traditional designs, these operations are typically performed in a multi-stage pipeline or time-division multiplexing manner, requiring multiple clock cycles to complete a core transformation (such as the g-transform). This embodiment integrates these originally serial operations into a highly parallel data path through optimized combinational logic design. Specifically, the circuit is designed to receive the original key input and, within one clock cycle, sequentially pass through shift logic, a byte substitution lookup table (to reuse the aforementioned arithmetic modules), round constant XOR logic, and finally a key XOR network, directly outputting the transformed result.

[0192] Furthermore, through the coordinated control and data routing of the multiplexer network, the folded combinational logic path can be time-division multiplexed to compute multiple key words required in a round of expansion, such as W[4N], W[4N+1], W[4N+2], and W[4N+3] in AES-128.

[0193] In this embodiment, the key expansion core operation, which originally required four clock cycles, can be compressed into one cycle, greatly improving the timing efficiency and throughput of key expansion, helping to reduce overall system latency and meet the needs of high-speed data processing scenarios. By folding multiple operations into the same set of combinational logic and utilizing a time-division multiplexing strategy, it avoids setting up independent registers and controllers for each operation or each key generation path, significantly reducing the number of timing components (such as flip-flops) and control logic, thereby effectively saving chip area. Since the reduction in the operation cycle of this embodiment directly reduces the dynamic switching activity factor of the circuit, it reduces the load on the clock network and the power consumption caused by register toggling. At the same time, the simplification of hardware resources also reduces static power consumption.

[0194] In conjunction with the above embodiments, in a specific embodiment provided in this application, the operation timing of the aforementioned key expansion data path is further defined and optimized. The aforementioned key expansion data path can use 32 bits as the basic operation unit and, based on the key length configuration, complete one round of AES-128, AES-192, or AES-256 key expansion every 4, 6, or 8 clock cycles.

[0195] The key expansion data path uses 32 bits as the basic unit of operation for data processing. This design is fully consistent with the AES algorithm standard, which divides the key into multiple 32-bit units, ensuring seamless integration between hardware implementation and algorithm requirements.

[0196] In this embodiment, the key expansion data path and control path module work together to adaptively adjust the number of clock cycles required to complete one round of key expansion according to different key length configurations. When configured in AES-128 mode (key length is 128 bits), a key expansion round is completed every 4 clock cycles.

[0197] When configured in AES-192 mode (key length is 192 bits), a round of key expansion is completed every 6 clock cycles.

[0198] When configured in AES-256 mode (key length is 256 bits), a round of key expansion is completed every 8 clock cycles.

[0199] This cycle configuration strategy directly corresponds to the number of 32-bit words contained in different key lengths (4, 6, and 8 words respectively). Within each clock cycle, the key expansion data path efficiently processes the corresponding 32-bit data block using the folding processing method described in the previous embodiments, ultimately generating all the new key words required for this round of expansion within the specified number of cycles.

[0200] This embodiment defines the circuit's full support for the three standard key lengths of AES. Through a configurable periodic control mechanism, it flexibly adapts to different algorithm specifications with a unified hardware architecture, demonstrating good versatility.

[0201] Based on the above embodiments, in another embodiment provided in this application, a chip is also provided, which integrates the encryption and decryption circuits corresponding to any of the above embodiments.

[0202] In this embodiment, the chip integrates the aforementioned encryption and decryption circuit based on the iterative multiplexing structure as a key functional module onto a single semiconductor substrate, forming a physical product with high-performance data encryption and decryption capabilities.

[0203] This chip utilizes semiconductor manufacturing processes to fabricate the encryption / decryption circuitry, including its data path module, control path module, data storage module, and all necessary components such as related multiplexer networks and arithmetic modules, together with other possible system modules, on the same silicon wafer. This encryption / decryption circuitry is the one described in detail in any of the foregoing embodiments, employing an iterative multiplexing structure to reduce power consumption and chip area.

[0204] Therefore, the chip in the embodiments can refer to an integrated circuit product formed by integrating electronic components onto a single substrate through semiconductor manufacturing processes. For example, the chip can be a function-specific control module, such as a microcontroller, a dedicated cryptographic coprocessor, a digital signal processor (DSP), a microprocessor unit (MPU), or a micro central processing unit (CPU). This chip can process digital signals, analog signals, or perform functions such as signal control, instruction processing, and data computation. For example, when the chip integrates the encryption / decryption circuit of any of the foregoing embodiments of this application, the chip possesses the ability to perform efficient, low-power AES encryption / decryption operations.

[0205] For example, the chip can take on various specific product forms, such as, but not limited to: Microcontrollers: can be used as built-in security accelerators in devices such as IoT nodes and smart cards.

[0206] System-on-a-Chip (SoC): It can be integrated as a security subsystem core in a SoC (System on a Chip), along with a central processing unit, memory controller, peripheral interfaces, etc., and applied in complex systems such as smartphones, network processors, and memory controllers.

[0207] Dedicated security chips or cryptographic coprocessors: focused on providing cryptographic computing services.

[0208] In this embodiment, because the integrated encryption / decryption circuit itself has the characteristics of resource reuse and structural simplicity, the dynamic and static power consumption of the entire chip is significantly lower than that of chips using traditional discrete circuit designs when performing frequent encryption / decryption tasks. At the same time, the smaller circuit area directly reduces the chip's manufacturing cost and facilitates product miniaturization. Furthermore, hardware-accelerated AES operations are far more efficient than software implementations; integrating this circuit can greatly reduce the computational burden on the main processor and improve the system's throughput for data stream processing. Additionally, hardware-implemented algorithms are generally more difficult to attack and steal than software-implemented algorithms, thereby enhancing the overall security of the chip.

[0209] Based on the above embodiments, in another embodiment provided in this application, such as Figure 8As shown, an AES circuit system is also provided, which includes encryption / decryption circuits corresponding to any of the above embodiments, an AHB (Advanced High-performance Bus) control module, a user register module, a working mode control module, and a GHASH operation circuit. The AHB control module is connected to the working mode control module through the user register module, and the working mode control module is connected to the GHASH operation circuit.

[0210] The AHB control module serves as a standardized interface between the system and external processors (such as the CPU), implementing the standard AMBA AHB bus slave protocol. This module is responsible for receiving and parsing read / write transactions from the system bus, forwarding control commands and data to the user register module, and returning the operation status and results to the host.

[0211] The AHB control module is responsible for communicating with external main processors (such as CPUs and DSPs). It receives and parses control signals on the AHB bus (such as clock hclk, reset hrst_n, address haddr, write data hwdata, etc.), and passes the processed instructions and data to the internal user register module.

[0212] The user register module, serving as the system's configuration and status center, contains a set of software-programmable registers. These registers store all runtime parameters, including but not limited to encryption / decryption keys, initialization vectors, data input / output, operating mode selection, start / stop control bits, and status flags.

[0213] The operating mode control module, as the system's scheduling core, reads configuration information from the user register module and generates corresponding micro-operation control sequences based on the selected operating mode. This module precisely coordinates the collaborative work of the encryption / decryption circuit and the GHASH operation circuit, controlling the data flow and feedback mechanism to correctly implement the encryption / decryption and authentication process required by the target mode.

[0214] The encryption / decryption circuit, serving as the core computing engine of this system, is the encryption / decryption operation circuit based on an iterative multiplexing structure in the aforementioned embodiments. Under the command of the working mode control module, the encryption / decryption circuit can perform low-level AES encryption / decryption operations.

[0215] The GHASH operation circuit, a dedicated coprocessor, is used to perform Galois field multiplication operations in authenticated encryption modes such as GCM, calculate Message Authentication Codes (MACs), and provide integrity and authenticity guarantees for data.

[0216] It should be noted that the working mode control module is used to configure the encryption and decryption circuit to operate in at least one of the following modes: ECB (Electronic Codebook), CBC (Cipher Block Chaining), CFB (Cipher Feedback), OFB (Output Feedback), CTR (Counter), or GCM (Galois / Counter Mode).

[0217] ECB mode is the simplest mode, encrypting plaintext blocks independently. Identical plaintext blocks will generate identical ciphertext blocks, resulting in lower security and generally not recommended for encrypting large amounts of data.

[0218] CBC mode involves XORing each plaintext block with the previous ciphertext block before encryption, and requires an initialization vector. It is one of the most widely used modes.

[0219] CFB mode converts a block cipher into a self-synchronizing stream cipher. The previous ciphertext block is fed back to the cryptographic algorithm to encrypt the next plaintext block.

[0220] OFB mode converts a block cipher into a synchronous stream cipher. The output of the cryptographic algorithm is fed back to itself to generate a key stream, which is then XORed with the plaintext to prevent error propagation.

[0221] CTR mode converts a block cipher into a stream cipher. It generates a keystream by encrypting an incrementing counter value, which is then XORed with the plaintext. This mode supports parallel computation and is highly efficient.

[0222] GCM mode is an extension of CTR mode, providing both encryption and authentication (identity verification). Building upon CTR encryption, it adds Galois field multiplication to calculate authentication tags, making it a very popular and recommended mode in high-performance network communication.

[0223] In the embodiments, the encryption and decryption circuit with an iterative multiplexing structure provided in the above embodiments serves as the computing engine of the AES circuit system, responsible for performing the lowest-level AES round transformation and key expansion operations, and has the characteristics of low power consumption and small area.

[0224] The operating mode control module, acting as the scheduling center of the AES circuit system, does not directly execute the AES core calculations. Instead, it controls the encryption and decryption circuits to operate in specific modes based on configuration commands from the user or upper-layer software. The operating mode control module is configured to generate corresponding control sequences and signals, organizing the single AES basic encryption and decryption core to achieve multiple operating modes.

[0225] For different modes, the working mode control module controls the data feedback path, the loading of the initialization vector, the generation and updating of the counter, and the collaborative workflow of the AES core and the GHASH core (if applicable). For example, in CBC mode, the working mode control module ensures that the previous ciphertext block is correctly fed back and XORed with the next plaintext block; in CTR mode, it manages the incrementing of the counter and controls the AES core to encrypt the counter value.

[0226] The AES circuit system provided in this application embodiment can be seamlessly integrated into the SoC via the AHB standard bus interface, allowing for efficient access and control by the processor and providing excellent system integration convenience. Through intelligent scheduling of the operating mode control module, the highly optimized single computing core at the underlying level is flexibly organized to support the aforementioned operating modes, achieving a leap from a single-function circuit to a multi-functional, highly flexible system.

[0227] like Figure 9A As shown, Figure 9A This is a block diagram of the encryption / decryption circuit provided in an embodiment of this application. The encryption / decryption circuit includes: a control path module 10, a data path module 20, and a data storage module 30. These modules cooperate with each other to achieve efficient and low-power AES encryption / decryption operations. The control path module 10 is used to generate enable and selection signals, control the data selection and data flow direction of the data path, and control the corresponding registers in the data storage module to perform iterative data updates.

[0228] In this embodiment, the control path module 10 serves as the control center of the circuit, generating and outputting a global selection signal. This selection signal is used to control the direction of data flow in the data path and the operating mode of the arithmetic module.

[0229] Data path module 20 is used to process iterative data and keys.

[0230] The data storage module 30 is used to store temporary data and results during the encryption, decryption, and key expansion processes.

[0231] The data storage module 30 is connected to the data path module 20 and is used to store various types of data generated during the encryption and decryption process, including initial data, intermediate results of round iterations, and final calculation results.

[0232] The control path module 10 selects the multiplexer 205 in the data path 21 of the round operation by selecting the signal to configure different data flow paths in the encryption and decryption processes, so that the data can flow through the multiplexed operation module and store the intermediate results of the round iteration in the data storage module 30.

[0233] In one embodiment provided in this application, the data path module 20 may specifically include a round operation data path 21. The round operation data path 21 includes a round key addition module 201, a forward and reverse byte substitution module 202, a forward and reverse row shifting module 203, and a forward and reverse column mixing module 204. When the round operation data path 21 is configured to perform encryption and decryption operations, the round key addition module 201, the forward and reverse byte substitution module 202, the forward and reverse row shifting module 203, and the forward and reverse column mixing module 204 in the round operation data path are reused.

[0234] In this embodiment, the data path module 20 is the core for performing encryption and decryption calculations, and it contains a round operation data path 21. This round operation data path 21 can be composed of multiple operation modules (including: a round key addition module 201, a forward and reverse byte substitution module 202, a forward and reverse row shifting module 203, and a forward and reverse column mixing module 204). The round operation data path 21 is configured to reuse at least a portion of its operation modules during encryption and decryption operations. In other words, the same set of physical hardware computing modules serves the encryption and decryption processes respectively by being configured with different functions at different times.

[0235] The encryption / decryption circuit provided in this embodiment controls the multiplexer 205 in the round operation data path 21 via a selection signal generated by the control path module 10. The multiplexer 205 dynamically switches the input and output connections of the data source according to the received selection signal, thereby configuring different data flow paths in the encryption and decryption processes. In this way, the data to be processed can be guided through the multiplexed operation modules and the encryption or decryption operations required are performed in the correct order. The intermediate results generated in each iteration are written back to the data storage module 30 as input for the next iteration, until all rounds of encryption / decryption operations are completed.

[0236] This embodiment integrates encryption and decryption functions into the same hardware circuit through the modular design and reuse mechanism described above, significantly reducing circuit resource redundancy caused by setting up independent data paths in traditional solutions. It can reduce chip area and system power consumption while maintaining complete algorithm performance, making it suitable for integrated chips and application systems that are sensitive to power consumption and cost.

[0237] In this embodiment, the aforementioned round operation data path 21 includes modules for performing basic transformations of the AES algorithm, such as a round key addition module 201, a forward and reverse byte substitution module 202, a forward and reverse row shift module 203, and a forward and reverse column mixing module 204. The round key addition module 201 is used to implement the XOR operation between the round key and the state data.

[0238] The forward and reverse byte substitution module 202 is used to implement non-linear byte substitution based on the S-Box (Substitution-Box). The S-Box is a predefined, non-linear lookup table, which is the obfuscation component in the AES algorithm. During byte substitution (SubBytes), the input byte can be uniquely mapped to another completely new output byte by looking up the S-Box table.

[0239] The forward and reverse row shifting module 203 is used to implement the cyclic shifting operation of the status data rows.

[0240] In this embodiment, the core hardware resources, shared by the round key addition module 201, the forward and reverse byte substitution module 202, and the forward and reverse row shift module 203, constitute the core hardware resources used for both encryption and decryption operations. The control path module 10 precisely controls the multiplexer 205, ensuring that data flows through these identical physical modules during encryption or decryption, although the input source, output destination, and order in the data stream may differ depending on the selection signal.

[0241] It should be noted that in traditional AES hardware circuits, encryption and decryption are usually designed as two separate hardware modules, one for forward column mixing and the other for reverse column mixing, which leads to significant waste of resources.

[0242] The embodiments provided in this application, by designing a configurable forward and reverse column hybrid module 204, allow the core computational structures (such as Galois domain multipliers and XOR networks) to be reused in encryption and decryption processes.

[0243] Specifically, the control path module 10 generates a selection signal, which controls the multiplexer 205 to select whether to use the constant matrix of the forward transformation or the constant matrix of the inverse transformation of the forward and inverse column mixing module 204 for calculation.

[0244] In this way, the same physical forward and reverse column mixing module 204 can perform forward column mixing calculations during encryption using a constant matrix of forward transformation, and perform reverse column mixing calculations during decryption using a constant matrix of reverse transformation.

[0245] In this embodiment, by identifying and utilizing the similarity of the operational structures of the forward and reverse column mixing module 204, the forward and reverse column mixing module 204 is designed as a configurable module, making it one of the reusable operational modules. This minimizes hardware resource overhead while ensuring the integrity and security of the algorithm, thereby reducing chip area and power consumption.

[0246] This application embodiment, through the aforementioned reused computation modules, enables the encryption and decryption functions to be consolidated into a single, streamlined hardware circuit. By reusing the three most fundamental transformation modules in the AES algorithm—key addition, byte substitution, and row shifting—redundant circuitry in traditional dual-path designs can be eliminated to the greatest extent possible, laying a solid foundation for a significant reduction in chip area and power consumption.

[0247] Based on the above embodiments, in another embodiment provided in this application, such as Figure 9B As shown, Figure 9B This diagram illustrates the detailed internal architecture of the encryption / decryption circuit provided in this embodiment. It shows the specific composition and collaborative working principle of the three main modules (control path module 10, data path module 20, and data storage module 30) within the operational circuit. Specifically, in the encryption / decryption circuit, the control path module 10 may further include an encryption / decryption control module 11, a key expansion control module 12, and a round counter 13; the data path module 20 may further include a round operation data path 21 and a key expansion data path 22; and the data storage module 30 includes a data iteration register 31, an iteration key register 32, and an Nr round key register 33.

[0248] In this embodiment, the encryption / decryption circuit interacts with the external system through an interface module (AES_IF), receiving control signals such as start enable, encryption / decryption flag, and key length, as well as input data such as raw data and key, and outputting the final data, derived key, and completion flag. Specifically, the internal structure and function of each module are as follows: Control path module 10 is the command and control center of the circuit, used to coordinate the entire encryption / decryption and key expansion process. Internally, it includes: The encryption / decryption control module 11 is a state machine that generates control signals according to the AES standard algorithm to precisely manage the data flow direction of the round operation data path 21, the number of round transformation iterations Nr, and the write enable of the data iteration register 31 in the data storage module 30.

[0249] The encryption / decryption control module is configured to control the number of iterations of the encryption / decryption process according to the AES-128 / 192 / 256 standard, and adopts an encryption / decryption data path multiplexing structure, which includes a multiplexing module for encryption and decryption data paths, a forward and reverse byte substitution module, a forward and reverse row shifting module, and a forward and reverse column hybrid module.

[0250] The key expansion control module 12 is another state machine that is dedicated to controlling the execution flow and key expansion times of the key expansion data path 22 according to the AES standard, and managing the updates of the iterative key register 32 in the data storage module 30.

[0251] Round counter 13 works in conjunction with encryption / decryption control module 11 to track and record the current round in real time, ensuring that the number of iterations corresponds to the key length (AES-128 / 192 / 256).

[0252] Data path module 20 is the hardware engine that executes all core computing tasks, and includes two main paths: The round operation data path 21 includes operation modules such as a round key addition module, a forward and reverse byte substitution module, a forward and reverse row shifting module, and a forward and reverse column mixing module. This path is controlled by the encryption / decryption control module 11, which dynamically configures the data path through a multiplexer to reuse the same set of physical modules to perform encryption or decryption operations respectively.

[0253] Key expansion data path 22 is used to generate the round key required for each round from the original key. This path is controlled by key expansion control module 12 and configured to multiplex the forward and reverse byte substitution modules in round operation data path 21 to maximize the utilization of hardware resources.

[0254] In this embodiment, the key expansion data path 22 is a dedicated path for generating the round keys required for each round of encryption or decryption.

[0255] Specifically, the key expansion algorithm in the AES standard has two core transformations: g-transformations include byte substitution (SubWord), circular shift (RotWord), and round constant XOR (Rcon).

[0256] h-transformation: In certain key length extensions (such as AES-256), byte substitution operations are also performed on the intermediate key word.

[0257] In traditional designs, the key expansion module has its own independent forward and reverse byte substitution module. However, in this embodiment, during key expansion, the key expansion data path 22 can route the key to be processed to the forward and reverse byte substitution module shared by the round operation data path 21. The control path module 10 generates corresponding selection signals to ensure that there is no timing conflict with encryption / decryption operations, or to achieve time-division multiplexing of resources through a multiplexer in the circuit design.

[0258] The data storage module 30 stores all temporary states and results during the computation process, ensuring the correct execution of the iteration flow. Specifically, it includes: Data Iteration Register 31: Used to store state data generated during round operations.

[0259] Iterative key register 32: Used to store key data generated during the key expansion process.

[0260] Nr Round Key Register 33: Used to temporarily store the round key required for the current encryption / decryption round.

[0261] This embodiment achieves fine-grained management of computational tasks and parallel processing potential by subdividing the control path into two independent state machines: encryption / decryption control and key expansion control. The division of the two paths in the data path module and the cross-multiplexing of key computation modules (such as the key expansion multiplexing byte replacement module) are key circuit structures for achieving low power consumption and small area. The register partitioning of the data storage module ensures the correctness and efficiency of the data flow during the iterative process.

[0262] Based on the above embodiments, this application also provides an AES encryption / decryption method, which can be applied to the encryption / decryption circuits provided in any of the above embodiments, such as... Figure 10 As shown, the method may include the following steps: In step S110, a selection signal is generated by the control path module.

[0263] The control path module can dynamically generate a series of selection signals based on external configurations (such as encryption / decryption mode and key length) and internal operation status. These signals provide the basis for configuring the data flow path in subsequent steps.

[0264] In step S120, encryption and decryption operations are performed through the round operation data path in the data path module. Specifically, the encryption and decryption operations reuse the round key addition module, forward and reverse byte substitution module, forward and reverse row shifting module, and forward and reverse column mixing module in the round operation data path.

[0265] In this embodiment, the encryption and decryption operations do not use two separate sets of hardware. Instead, they reuse the same round key addition module, forward and reverse byte substitution module, forward and reverse row shifting module, and forward and reverse column hybrid module in the same round operation data path. In this way, resource sharing can be achieved at the hardware level.

[0266] In step S130, the data from the encryption and decryption process is stored through the data storage module.

[0267] In this process, by selecting a multiplexer in the signal control wheel operation data path, different data flow paths are configured in the encryption and decryption processes, so that data can flow through the multiplexed operation module and the intermediate results of the wheel iteration are stored in the data storage module.

[0268] In this embodiment, the data storage module is responsible for storing the intermediate results, iteration keys, and final data generated during the method execution process, providing necessary data storage and transmission support for multiple rounds of iterative operations.

[0269] The selection signal generated in step S110 controls the multiplexer network in the round operation data path. This allows the method to dynamically configure two different data flow paths in the encryption and decryption processes. Data is guided through the multiplexed hardware modules according to the current process (encryption or decryption), and the corresponding forward or reverse transformations are performed in the correct order. Intermediate results generated in each iteration are stored in the data storage module in step S130 for use in the next iteration, until all operations are completed.

[0270] The AES encryption / decryption method provided in this application uses signal control to converge the encryption and decryption operations onto the same physical computing module. This eliminates the hardware resource redundancy problem in traditional solutions, thereby reducing circuit power consumption and area.

[0271] Based on the above embodiments, in another embodiment provided in this application, the configuration of the above-mentioned round operation data path includes: In encryption operations: In the first iteration, the plaintext data and the master key are added by the round key addition module, and the forward row shift operation is performed by the forward and reverse row shift module.

[0272] In the first to Nr-1 iterations, the data flows sequentially through: the byte substitution module to perform forward byte substitution, the forward and reverse column mixing module to perform forward column mixing, the round key addition module to perform round key addition, and the forward and reverse row shift module to perform forward row shift.

[0273] In the Nrth iteration, the data flows sequentially through: the byte substitution module to perform forward byte substitution, and the round key addition module to perform round key addition.

[0274] For details, please refer to the description of the above embodiments, which will not be repeated here. This embodiment clearly demonstrates the working mechanism of the reuse architecture in encryption mode by explicitly defining the mapping relationship between the data flow path of each round in the encryption operation and the corresponding hardware module. This stable and standardized operation sequence ensures the correctness of the algorithm function, and at the same time confirms the efficient reuse of key addition, byte substitution, row shifting and forward and reverse column hybrid modules in the entire encryption process. It is the specific execution logic to achieve the goal of simplifying circuit resources and reducing power consumption.

[0275] In the decryption operation: In the first iteration, the key addition operation between the ciphertext data and the master key is performed by the round key addition module, and the reverse row shift operation is performed by the forward and reverse row shift module.

[0276] In the first to Nr-1 iterations, the data flows sequentially through: the byte substitution module to perform reverse byte substitution, the round key addition module to perform round key addition, the forward and reverse column mixing module to perform reverse column mixing, and the forward and reverse row shift module to perform reverse row shift.

[0277] In the Nrth iteration, the data flows sequentially through: the byte substitution module to perform reverse byte substitution, and the round key addition module to perform round key addition.

[0278] For details, please refer to the description of the above embodiments, which will not be repeated here. This embodiment clarifies the detailed data path of the decryption operation. The key point is that although the four operations of byte substitution, key addition, column mixing, and row shifting are all involved in the decryption process, their execution order differs from the encryption process. The round-robin data path reconfigures the data flow through control signals, reusing the same set of physical hardware modules, successfully realizing this differentiated decryption logic. This demonstrates that the reuse architecture provided by the embodiment is not only suitable for encryption but also efficiently and correctly supports decryption functions, satisfying complete encryption and decryption requirements with the same set of hardware resources, directly reflecting resource reuse.

[0279] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0280] The modules, components, or modules described in the embodiments of this application can be implemented in software or hardware. The names of these modules, components, or modules do not necessarily constitute a limitation on the module, component, or module itself.

[0281] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary hardware logic components that can be used include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0282] The above description is merely an embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0283] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. An encryption / decryption circuit, characterized in that, The encryption / decryption circuit includes: a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a seventh multiplexer, a forward and reverse byte substitution module, a forward and reverse column mixing module, a forward and reverse row shifting module, a round key addition module, a concatenated iterative data module, and a data iteration register; wherein, The output of the first multiplexer is connected to the input of the round key addition module, and the output of the round key addition module is connected to the first input of the second multiplexer through the splicing iterative data module. The second multiplexer is connected to the input of the data iteration register through the forward and reverse row shift module; The output of the third multiplexer is connected to the input of the fourth multiplexer through the forward and reverse byte substitution module; The output of the fourth multiplexer is connected to the input of the forward and reverse column mixing module and the first input of the fifth multiplexer. The output of the forward and reverse column mixing module is connected to the second input of the fifth multiplexer. The output of the fifth multiplexer is connected to the input of the round key addition module, the sixth multiplexer, and the splicing iterative data module. The output of the round key addition module is connected to the splicing iterative data module through the sixth multiplexer. The output of the splicing iterative data module is connected to the second input of the second multiplexer through the seventh multiplexer. The output of the sixth multiplexer is connected to the input of the data iteration register.

2. The encryption / decryption circuit according to claim 1, characterized in that, The encryption / decryption circuit further includes forward and reverse key expansion data paths, which include: a key expansion row shift module, a key expansion byte substitution module, a round constant XOR module, a key XOR module, a ninth multiplexer, a tenth multiplexer, an eleventh multiplexer, a twelfth multiplexer, and a thirteenth multiplexer; wherein... The input of the key extension row shift module is connected to the output of the external iterative key register, and the output of the key extension row shift module is connected to the input of the key extension byte substitution module through the ninth multiplexer. The output of the key extension byte substitution module is connected to the input of the round constant XOR module. The output of the key extension byte substitution module is connected to the first input of the key XOR module through the tenth multiplexer and the eleventh multiplexer. The input of the tenth multiplexer is connected to the output of the key register. The output of the round constant XOR module is connected to the first input of the key XOR module through the eleventh multiplexer. The second input of the key XOR module is connected to the key register through the twelfth multiplexer, and the output of the key XOR module is connected to the key register through the thirteenth multiplexer.

3. The encryption / decryption circuit according to claim 1 or 2, characterized in that, The encryption process of the encryption / decryption circuit includes: First round of key addition: The first multiplexer selects the corresponding master key KEY according to the key length and performs key addition operation with the plaintext data. The master key addition flag is high. The second multiplexer selects the result of 128-bit 4-group round key addition and writes it back to the data iteration register after the forward row shift operation of the forward and reverse row shift module. Round Iteration: The third multiplexer selects 32-bit plaintext according to the data selection signal, and sequentially passes it through the forward and reverse byte substitution module, the fourth multiplexer, the forward and reverse column mixing module, the fifth multiplexer, the round key addition module, the sixth multiplexer, the concatenated iterative data module, the seventh multiplexer, the second multiplexer, and the forward and reverse row shifting module, updating the data iteration register; the forward and reverse byte substitution module performs a forward byte substitution operation, the forward and reverse column mixing module performs a forward column mixing operation, and the forward and reverse row shifting module performs a forward row shifting operation; In the Nrth round of iteration: the third multiplexer selects 32-bit plaintext according to the data selection signal, and passes it sequentially through the forward and reverse byte substitution module, the fourth multiplexer, the fifth multiplexer, the round key addition module, and the sixth multiplexer to update the data iteration register. The forward and reverse byte substitution module performs the forward byte substitution operation.

4. The encryption / decryption circuit according to claim 1 or 2, characterized in that, The decryption process of the encryption / decryption circuit includes: First round of key addition: The first multiplexer selects the corresponding master key KEY according to the key length and performs key addition operation with the plaintext data. The master key addition flag is high. The second multiplexer selects the result of 128-bit 4-group round key addition and performs reverse row shift operation through the forward and reverse row shift module to write back to the data iteration register. Round Iteration: The third multiplexer selects 32-bit plaintext according to the data selection signal, and sequentially passes it through the forward and reverse byte substitution module, the round key addition module, the fourth multiplexer, the forward and reverse column mixing module, the fifth multiplexer, the sixth multiplexer, the concatenated iterative data module, the seventh multiplexer, the second multiplexer, and the forward and reverse row shifting module, updating the data iteration register; the forward and reverse byte substitution module performs the reverse byte substitution operation, the forward and reverse column mixing module performs the reverse column mixing operation, and the forward and reverse row shifting module performs the reverse row shifting operation; In the Nrth round of iteration: the third multiplexer selects 32-bit plaintext according to the data selection signal, and passes it sequentially through the forward and reverse byte substitution module, the fourth multiplexer, the fifth multiplexer, the round key addition module, and the sixth multiplexer to update the data iteration register. The forward and reverse byte substitution module performs the reverse byte substitution operation.

5. The encryption / decryption circuit according to claim 2, characterized in that, The forward key expansion process for both encryption and decryption includes: W[4N] passes through the key extension row shift module, the ninth multiplexer, the key extension byte substitution module, the round constant XOR module, the key XOR module, the eleventh multiplexer, the key XOR module, and the thirteenth multiplexer in sequence from W[4N-1] to update the corresponding master key KEY; W[4N+1~4N+k] selects the corresponding key through the tenth and twelfth multiplexers and performs an XOR operation, and updates the corresponding master key KEY through the thirteenth multiplexer; After forward key expansion, the master key KEY stores the round key of round Nr, which is used for decryption operations.

6. The encryption / decryption circuit according to claim 2, characterized in that, The reverse key expansion process for encryption and decryption includes: W[4N+1~4N+k] selects the corresponding key through the tenth and twelfth multiplexers and performs an XOR operation, and updates the corresponding master key KEY through the thirteenth multiplexer; W[4N] is processed sequentially through the key extension row shift module, the ninth multiplexer, the key extension byte substitution module, the round constant XOR module, the eleventh multiplexer, the key XOR module, and the thirteenth multiplexer to update the corresponding master key KEY.

7. A chip, characterized in that, Includes the encryption / decryption circuit as described in any one of claims 1-6.

8. An AES circuit system, characterized in that, include: Encryption / decryption circuit, AHB control module, user register module, working mode control module, and GHASH operation circuit; The AHB control module is connected to the working mode control module through the user register module, and the working mode control module is connected to the GHASH operation circuit.

9. The AES circuit system according to claim 8, characterized in that, The encryption / decryption circuit includes: a data path module, a control path module, and a data storage module; The data storage module is used to store temporary data and results during the encryption, decryption, and key expansion processes; The control path module is used to generate enable signals and selection signals, control the data selection and data flow direction of the data path, and control the corresponding registers in the data storage module to perform iterative data updates. The data path module is used to process iterative data and keys.

10. The AES circuit system according to claim 9, characterized in that, The control path module includes an encryption / decryption control module, a key expansion control module, and a round counter; The data path module includes a round operation data path and a key expansion data path; The data storage module includes a data iteration register, an iteration key register, and an Nr round key register; The encryption / decryption control module is used to control the round operation data path, the data iteration register, and the Nr round key register; The key expansion control module is used to control the key expansion data path and the iterative key register.

11. The AES circuit system according to claim 10, characterized in that, The encryption / decryption control module is configured to control the number of round transformation iterations according to the AES-128 / 192 / 256 standard encryption / decryption process, and adopts an encryption / decryption data path multiplexing structure, which includes a multiplexing round key addition module, a forward and reverse byte substitution module, a forward and reverse row shifting module, and a forward and reverse column hybrid module for encryption and decryption data paths.

12. The AES circuit system according to claim 10, characterized in that, The key expansion control module is configured to control the number of key expansions according to the AES-128 / 192 / 256 standard key expansion process, including a forward and reverse byte substitution module, a cyclic shift module, and a round constant transformation module, wherein the h transformation and g transformation reuse the forward and reverse byte substitution module.

13. An AES encryption / decryption method, characterized in that, The method includes: A selection signal is generated through the control path module; Encryption and decryption operations are performed through the round operation data path in the data path module; wherein, the encryption and decryption operations reuse the round key addition module, forward and reverse byte substitution module, forward and reverse row shift module, and forward and reverse column mixing module in the round operation data path; Data from the encryption and decryption process is stored through a data storage module; Specifically, the selection signal controls the multiplexer in the round operation data path to configure different data flow paths in the encryption and decryption processes, so that data can flow through the reused operation module and the intermediate results of the round iteration are stored in the data storage module.

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