Digital circuit dependency analysis method

Abstract

The invention discloses a digital circuit dependency analysis method, which comprises the following steps of: by analyzing the equality of a Boolean differential circuit, converting a dependency judgment problem of D on S into a problem of judging whether the Boolean differential circuit is constantly 0 or not; when whether the Boolean differential circuit is constantly 0 cannot be judged through X value simulation, logic negation is performed on the Boolean differential circuit, so that a dependency judgment problem is formally converted into a satisfiability problem, SAT solving is performed on the problem, whether D depends on S or not is judged according to a solving result, and if not, the Boolean differential circuit is judged to be zero. If the Boolean differential circuit is constrained, the satisfiability problem of the Boolean differential circuit is reconstructed, and the constrained Boolean differential circuit is subjected to SAT solution to further determine the dependency. According to the method, the digital circuit dependency analysis efficiency and accuracy are remarkably improved, the method is suitable for combinational logic circuit scenes of any scale and any complexity, the application range and efficiency of engineering application are greatly improved, and the method has remarkable industrial application value and popularization prospects.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, specifically relating to a method for digital circuit dependency analysis. Background Technology

[0002] With the rapid development of integrated circuits and digital systems, combinational logic circuits, as the fundamental unit in digital circuit design, play a crucial role in signal processing, information transmission, and control. Combinational logic circuits typically consist of multiple input signals and multiple output signals; their outputs depend only on the current combinational state of the input signals and do not involve the circuit's historical inputs or timing information.

[0003] In practical engineering applications, verifying the functional correctness and conducting sensitivity analysis of complex combinational logic circuits are crucial steps in ensuring system reliability and security. Especially in the design of large-scale integrated circuits and very large-scale integrated circuits, engineers often need to analyze whether a set of output signals in a circuit is sensitive to the assignment results of a specific set of input signals, or to determine whether there exists an input assignment that makes the output completely independent of another set of input signals. These issues not only involve the correct implementation of the circuit's function but also relate to the circuit's testability, controllability, and protection against potential security risks.

[0004] Currently, the analysis of dependencies between inputs and outputs of combinational logic circuits mainly relies on traditional methods such as functional simulation, symbolic analysis, and Boolean algebra simplification. These methods perform well for smaller circuits, but their analysis efficiency is low for circuits with large input / output scales and complex logic structures, and they are difficult to systematically determine the independence of outputs from specific input groups. Especially in scenarios requiring automated and formal verification of circuit security attributes and functional isolation, existing techniques often fall short of the requirements for efficiency, accuracy, and scalability.

[0005] Therefore, there is an urgent need for a new method that can determine whether there is a certain input assignment that makes the output function independent of a specific set of input signals for combinational logic circuits of any input-output scale, so as to improve the efficiency and reliability of circuit design verification. Summary of the Invention

[0006] The technical problem to be solved by this invention is to provide a digital circuit dependency analysis method that addresses the shortcomings of existing technologies. This method can efficiently analyze circuit inputs divided into three sets. L , S and X The output signal of the circuit is defined as D In the case of a set, does it exist? L The assignment of values ​​to each variable in the circuit makes the output signal of the circuit... D Completely independentS This method combines multiple techniques, including AIG-based circuit structure optimization, simulation, and Boolean satisfiability (SAT) solving, significantly improving the efficiency and accuracy of digital circuit dependency analysis. It is applicable to combinational logic circuits of any size and complexity, greatly enhancing the applicability and efficiency of engineering applications, and has significant industrial application value and promotion prospects.

[0007] The technical solution adopted by this invention to solve the above-mentioned technical problems is: a digital circuit dependency analysis method, comprising the following steps: S1. Read the Verilog file of the digital circuit to be analyzed, convert it to AIG (And-Inverter Graph) form, perform logic optimization, and divide the circuit input into three sets. L , S and X Define the output signal of the circuit as D For each output signal of the optimized AIG network, extract the corresponding logic cone from the AIG network, which is a combinational logic sub-circuit composed of all input signals and intermediate nodes on which each output signal depends. S2. If the logic cone is a constant function, then randomly assign... L The method ends when each variable is assigned a value; otherwise, it continues constructing the code sequentially. D Each variable in the middle is about S Boolean difference circuits for each variable; S3. Perform X-value simulation on the Boolean differential circuit: L Each variable is randomly assigned a value of 0 or 1. S and X Each variable is assigned an undefined value "X", and a logic simulation is performed. S3.1 If the simulation result is logic 0, then the current... L The method ends when each variable is assigned the solution result. S3.2 If the simulation result is not logic 0, then invert the logic of the Boolean differential circuit and call the SAT solver to solve it; if the solution result does not meet the requirements, then determine... D Depends on S The method ends; if the solution result is satisfactory, then obtain a set of pairs output by the SAT solver. L , S , X Assigning values ​​to each variable in the code; S4. The result obtained in step S3.2 L The values ​​of each variable are input into the Boolean differential circuit, and the SAT solver is called again to solve the problem. If the solution result does not meet the requirements, then the problem is confirmed. LIf the assignment of each variable is valid, it is taken as the solution result, and the method ends; if the solution result is unsatisfactory, return to step S3.2, and use this solution as a new constraint for the SAT solver to continue iteratively solving until a valid solution is obtained. L The method ends when each variable is assigned a value or the time limit for solving is reached.

[0008] The method of this invention analyzes the identity of Boolean differential circuits to... D right S The dependency determination problem is transformed into determining whether the Boolean differential circuit is always zero; that is, when the Boolean differential circuit is always zero, it is considered that... D Not dependent on S When the Boolean differential circuit is not always zero, it is considered that... D right S There is a dependency. When simulation using the X value still cannot determine whether the Boolean differential circuit is always 0, the logic of the Boolean differential circuit is inverted, thereby... D right S The dependency determination problem is formally transformed into a satisfiability problem, and the SAT solver is called to solve it. If the solution result is not satisfied, it means that there is no combination of input signals that makes the Boolean difference circuit take a value of 1, i.e., the dependency determination is not satisfied. D Depends on S If the solution result satisfies the condition and a set of pairs is obtained... L , S , X The assigned values ​​for each variable are then used as constraints in subsequent solution step S4 to reconstruct the satisfiability problem of the Boolean difference circuit. The SAT solver is then invoked to solve the constrained Boolean difference circuit for further evaluation. D right S The actual dependence. If the result of this solution is not satisfied, it indicates that there is no input signal combination that makes the Boolean differential circuit take the value 1 under this constraint, confirming the result obtained in step S3.2. L Each variable's assigned value is valid, and the assigned value is output as the final analysis result. If the current solution is satisfied, it indicates that a feasible solution still exists under the current constraints. In this case, return to step S3.2, use the solution obtained in the previous round as the new constraint input, and execute the incremental SAT solution process until a valid solution that satisfies the judgment condition is found. L The process continues until each variable is assigned a value or the preset solution time limit is reached.

[0009] Specifically, in step S2, the following steps are constructed sequentially. D Each variable in the middle is about S Boolean difference of each variable And through the formula Construct Boolean differential circuit ,in For the AND operator, This is the NOT operator.

[0010] Compared with the prior art, the present invention has the following advantages: The digital circuit dependency analysis method of the present invention: (1) The method of the present invention combines multiple techniques such as circuit structure optimization based on AIG, simulation and Boolean satisfiability (SAT) solution. It prioritizes the rapid elimination of most invalid search space through simulation and only calls the SAT algorithm for complex boundary cases, which significantly reduces the consumption of computing resources and solution time, and significantly improves the efficiency and accuracy of digital circuit dependency analysis.

[0011] (2) The method of the present invention uses Boolean differential circuit and SAT enumeration to ensure the formal rigor of the results. No matter how large the input circuit is, accurate conclusions can be obtained through a complete enumeration and pruning mechanism, avoiding the drawbacks of traditional methods being easily affected by human subjective factors.

[0012] (3) The method of this invention requires no manual intervention and can automatically complete the entire process from circuit structure extraction and logic optimization to dependency determination. It can be widely applied in fields such as integrated circuit design verification, circuit security analysis, sensitivity testing, information flow isolation, and hardware security, providing a brand-new technical means for automated and formalized circuit function determination and security verification. The method of this invention can be combined with mainstream logic synthesis software to provide an efficient, automated, and scalable new technical solution for input-output dependency determination of combinational logic circuits. It is applicable to combinational logic circuit scenarios of any scale and complexity, greatly improving the applicability and efficiency of engineering applications, and has significant industrial application value and promotion prospects. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the combinational logic circuit targeted by the method of the present invention; Figure 2 This is a flowchart of the method of the present invention; Figure 3 For the optimized AIG network in case01.v; Figure 3 middle, S 1. S 2. L 1. L 2 and X 1 represents the circuit input, numbers 7-12 represent nodes, dashed lines with arrows represent logical NOT, and solid lines with arrows represent the connection relationship between nodes. Figure 4 This is a schematic diagram illustrating the construction process of the Boolean differential circuit for case01.v; Figure 4middle, L 1. L 2, 0, S 1. S 2 and X f1 represents the input of the circuit, solid lines with arrows indicate the connection relationship of nodes, AND represents the AND gate, XOR represents the XOR gate, and f1 and f2 represent the output of the Boolean differential circuit. F This represents the output of the connection structure formed by inverting f1 and f2; Figure 5 For case01.v S 1. About D AIG schematic diagram of a Boolean differential circuit of type 1; Figure 5 middle, S 2. L 1. L 2. X 1 and S 1 represents the circuit input, numbers 7-21 represent nodes, dashed lines with arrows represent logical NOT, and solid lines with arrows represent the connection relationship between nodes. Figure 6 Example diagram of simulated propagation of the X value used in the Boolean differential circuit of case01.v; Figure 6 middle, S 2. L 1. L 2. X 1 and S 1 represents the circuit input, numbers 7-21 represent nodes, dashed lines with arrows represent logical NOT, solid lines with arrows represent the connection relationship between nodes, 0, 1, and X represent the input state value during simulation, and 0 and X next to the elliptical wireframe represent the output state value. Detailed Implementation

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0015] The method of this invention is used to analyze the input of a circuit divided into three sets. L , S and X The output signal of the circuit is defined as D In the case of a set, does it exist? L The assignment of values ​​to each variable in the circuit makes the output signal of the circuit... D Completely independent S .like Figure 1 As shown, the combinational logic circuit targeted by the method of the present invention includes: a set , , ,gather .

[0016] Example: Taking the combinational logic circuit shown in case01.v in Table 1 as an example, we perform dependency analysis on it using the method of this invention. This combinational logic circuit includes: a set , , ,gather .

[0017] The flowchart of the method of this invention is shown below. Figure 2 The dependency analysis process of the combinational logic circuits in the embodiments of the present invention specifically includes the following steps: S1. Use an open-source logic synthesis tool (such as Yosys) to read the Verilog file of the digital circuit to be analyzed, convert it to AIG format, and perform logic optimization. The optimized AIG network of case01.v is as follows: Figure 3 As shown. The output signal of the optimized AIG network. D 1. Extract the corresponding logic cone from the AIG network. A logic cone refers to the set of all intermediate nodes and input signals in the network that can be transmitted to the output signal. In this case, there is only one output signal. D 1, therefore Figure 3 That is, its logic cone.

[0018] S2, for the output signal D 1. Perform a constant check. If the logic cone output is always 0 or 1, meaning the logic cone is a constant function, then randomly assign... L Medium variables L 1. L 2. Assign a value and output the assigned value directly; otherwise, construct the output signal sequentially. D 1. About S Medium variables S 1. S Boolean difference of 2 And through the formula Construct Boolean differential circuit ,in For the AND operator, The negation operator. The essence of a Boolean differential circuit is to determine when... S When the value of a certain input signal changes, the output signal D Will 1 change accordingly? If the Boolean differential circuit is always 0, then it indicates... D 1. It does not depend on the input signal.

[0019] by S Taking 1 as an example, the construction process of its Boolean differential circuit is as follows: Figure 4 As shown: In the original circuit S By fixing 1 to both 0 and 1, two new circuits are obtained, and their outputs are compared using an XOR gate. The output of this XOR gate is...S 1 pair D Boolean difference of 1. Similarly, it is necessary to... S 1. Construct the corresponding Boolean differential circuit.

[0020] Finally, we connect a circuit with the inverted outputs f1 and f2 of the Boolean differential circuit constructed by the gatekeeper. The output of this connection structure is: F , constructed as We through F Determine if a set exists L The assignment of values ​​to each variable in the code ensures that all variables targeting the same variable will be affected. S The Boolean difference output of each variable is simultaneously 0. This can be formally expressed as a conjunction problem and transformed into a propositional logic formula that can be processed by the SAT solver. The AIG form, see Figure 5 The case01.v shown S 1. About D A schematic diagram of a Boolean differential circuit of type 1 (AIG).

[0021] S3, To quickly find effective L By assigning values ​​to each variable, we perform X-value simulations on the Boolean differential circuit: L Medium variables L 1. L 2. Randomly assign a value of 0 or 1 (e.g.) L 1=0, L 2=1), for variables S 1. S 2 and X 1. Assign an undefined value “X” (which could be state 0, state 1, or a high-impedance state) and perform a logic simulation.

[0022] See the simulation propagation example diagram of the X value used in the Boolean differential circuit of case01.v. Figure 6 As we can see, the simulation result is X, therefore L 1=0, L 2=1 is not a solution. Only when the simulation results determine the Boolean differential circuit... If the output is 0, it proves that the current... L The random assignment of each variable in the process is successful, making D 1. Not dependent on S This assignment can be directly output as a valid solution result, and the method ends. This step can efficiently filter out a large number of simple cases, avoiding the need to start complex SAT solvers. The number of simulations can be dynamically adjusted for circuits of different sizes.

[0023] because Figure 6The simulation result shown is X. Therefore, the simulation cannot determine the output value of X, so the complete SAT solution process in step S3.2 is initiated: for the Boolean differential circuit... Take the logical negation (i.e., require) F = 1), convert to CNF format, and call the SAT solver to solve: if the solution result is unsatisfactory (unsat), then determine D Depends on S The method ends; if the solution result satisfies (sat), then obtain a set of pairs of outputs from the SAT solver. L , S , X Assigning values ​​to each variable. Because the solution returned by the SAT solver may depend on specific values ​​of X, rather than being entirely determined by... L This is due to the assignment of values ​​to each variable in the solution; therefore, proceed to step S4 to verify the validity of the solution.

[0024] S4. The result obtained in step S3.2 L The values ​​of each variable are input into a Boolean differential circuit, and the SAT solver is called again to solve the problem and determine the result. F Is 0 true? If the solution result is unsatisfactory (unsat), then the condition is confirmed. L If the assignment of each variable is valid, it is taken as the solution result, and the method ends; if the solution result is satisfied (sat), it means there is no valid solution, so return to step S3.2, use this solution as a new constraint for the SAT solver to continue iteratively solving, and finally obtain the solution. L 1=1, L 2=1 is a valid solution, and the method ends.

[0025] The test cases and test results of the method of this invention provided by Innoda are shown in Table 1.

[0026] Table 1

[0027] In Table 1, the input signal L / S / X / D The number represents the type and quantity of input signals in each test case. Input signals with solutions. D The number of input signals D The number of signals for which a valid solution can be successfully obtained using the method of this invention. Input signals for which no solution is found. D The number of signals for which no valid result can be obtained is listed. The time taken to convert the test cases to AIG records the time required to convert them to AIG. The total runtime refers to the total time consumed from reading the test cases to outputting the final judgment result. As shown in Table 1, this invention can perform efficient and automated solving while ensuring correct solutions.

Claims

1. A method for analyzing digital circuit dependencies, characterized in that, Includes the following steps: S1. Read the Verilog file of the digital circuit to be analyzed, convert it to AIG format, perform logic optimization, and divide the circuit input into three sets. L , S and X Define the output signal of the circuit as D Set; for each output signal of the optimized AIG network, extract the corresponding logic cone from the AIG network; S2. If the logic cone is a constant function, then randomly assign... L The method ends when each variable is assigned a value; otherwise, it continues constructing the code sequentially. D Each variable in the middle is about S Boolean difference circuits for each variable; S3. Perform X-value simulation on the Boolean differential circuit: L Each variable is randomly assigned a value of 0 or 1. S and X Each variable is assigned an undefined value "X", and a logic simulation is performed. S3.1 If the simulation result is logic 0, then the current... L The method ends when each variable is assigned the solution result. S3.2 If the simulation result is not logic 0, then invert the logic of the Boolean differential circuit and call the SAT solver to solve it; if the solution result does not meet the requirements, then determine... D Depends on S The method ends; if the solution result is satisfactory, then obtain a set of pairs output by the SAT solver. L , S , X Assigning values ​​to each variable in the code; S4. The result obtained in step S3.2 L The values ​​of each variable are input into the Boolean differential circuit, and the SAT solver is called again to solve the problem. If the solution result does not meet the requirements, then the problem is confirmed. L If the assignment of each variable is valid, it is taken as the solution result, and the method ends; if the solution result is unsatisfactory, return to step S3.2, and use this solution as a new constraint for the SAT solver to continue iteratively solving until a valid solution is obtained. L The method ends when each variable is assigned a value or the time limit for solving is reached.

2. The digital circuit dependency analysis method according to claim 1, characterized in that, In step S2, construct sequentially D Each variable in the middle is about S Boolean difference of each variable And through the formula Construct Boolean differential circuit ,in For the AND operator, This is the NOT operator.

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