CMOS neuron-synaptic unit circuit system suitable for spiking neural network

Abstract

The CMOS neuron-synaptic unit circuit system suitable for the spiking neural network is realized, so that network parameters of the spiking neural network are effectively initialized, and the weight is dynamically adjusted to promote information propagation and learning. The CMOS neuron-synaptic unit circuit system comprises a front LIF neuron circuit module which receives an input pulse signal and generates an output pulse through integration; the synapse circuit receives the output pulse and adjusts the transmission intensity of the signal by adjusting the real-time weight; the STDP circuit adjusts the synaptic weight according to the time difference between the pulse output by the front LIF neuron circuit module and the pulse output by the rear LIF neuron circuit module; the ATML circuit receives the output pulse of the front LIF neuron circuit module and the output pulse of the rear LIF neuron circuit module, and adjusts the weight of the STDP to update the length of a time window by changing the size of a time window length signal Vleak; and the LIF neuron circuit receives the signal from the synaptic circuit module, and simulates the neuron signal integration and pulse generation process again.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to a CMOS neuron-synaptic unit circuit system design suitable for spiking neural networks. It is particularly suitable for processing time-series data and simulating the propagation and learning behavior of biological neural networks, and can meet the needs of most intelligent applications with wide pulse time intervals. Background Technology

[0002] With the continuous advancement of neuromorphic computing technology, the advantages of spiking neural networks (SNNs) in handling temporal information and energy efficiency have led to a gradual increase in demand across multiple fields. SNNs mimic the brain's pulse-based information processing mechanism, providing asynchronous, sparse, and event-driven computation. This makes them excellent in terms of energy efficiency and adept at handling temporal information, thus becoming a strong candidate for neuromorphic computing. Among SNNs, leaky integral-fire (LIF) neuronal circuits are widely used in hardware implementations due to their simplicity and ability to approximate the dynamics of biological neurons. Synaptic circuits, as connections between neuronal circuits, need to handle weighted spike transmission and online learning. Pulse temporal dependent plasticity (STDP), as a biologically plausible mechanism, is key to the adaptive learning of SNNs.

[0003] However, current hardware implementations of SNNs based on CMOS neurons and synaptic circuits still have limitations. Most STDP mechanisms use fixed time windows, making them unable to respond to changes in input frequency and difficult to handle wide-spectrum signals. While some designs provide time window adjustment interfaces, they rely on manual tuning and lack adaptability. Furthermore, point-to-point connection models limit network scalability and parallel computing capabilities. To address these issues, this invention implements a novel CMOS neuron and synaptic unit circuit system that can effectively initialize spiking neural network parameters and dynamically adjust weights for information propagation and learning, meeting the needs of most intelligent applications with wide pulse time intervals. Summary of the Invention

[0004] This invention provides a CMOS neuron-synapse unit circuit system, which is designed specifically for spiking neural networks. It is mainly used to process time series data and can simulate the signal propagation process and learning behavior in spiking neural networks. It can effectively meet the needs of most intelligent applications with a wide range of pulse time interval requirements.

[0005] The objective of this invention is achieved through the following measures:

[0006] Figure 1This is a block diagram of a CMOS neuron-synaptic unit circuit system. The pre-LIF neuron circuit module (100) receives the input pulse signal Spike_in(pre), integrates it, and generates the output pulse Spike_out(pre). The synaptic circuit module (101) receives this output pulse and controls the signal transmission strength by adjusting V_weight. The STDP circuit module (102) adjusts the synaptic weights based on the pulse time difference between the pre-synaptic and post-synaptic signals. The ATML circuit module (103) receives Spike_out(pre) and Spike_out(post), and changes the Vleak value to adjust the STDP time window length. The post-LIF neuron circuit module (104) receives the synaptic signal and again simulates the neuron signal integration and pulse generation process.

[0007] Figure 2 This is a schematic diagram of the initialization of the designed six-neuron network. The network consists of a two-layer neuron structure, with each layer containing three LIF neuron circuit modules. In the first layer, there are LIF1 (200), LIF2 (201), and LIF3 (202) neurons; in the second layer, there are 2LIF1 (208), 2LIF2 (209), and 2LIF3 (210) neurons. During network initialization, the first-layer LIF neuron circuit receives external input current pulse signals Iin1, Iin2, and Iin3, and enables some STDP circuit modules to initialize the real-time weights between the first-layer neurons, including STDP1-12 (203) and STDP1-13 (204). The second layer of neurons receives pulse signals from the first layer of neurons through synaptic circuit modules. The activated synaptic circuit modules include synaptic circuit modules 2-21 (205), synaptic circuit modules 2-22 (206), and synaptic circuit modules 2-23 (207). In addition, some STDP circuit modules are activated to initialize the real-time weights between the second layer of neurons, including STDP2-12 (211) and STDP2-13 (212).

[0008] Figure 3This diagram illustrates the information propagation and learning process of the designed six-neuron network. The network comprises a two-layer neuron structure, with each layer containing three LIF neuron circuit modules. In the first layer, there are LIF1 (300), LIF2 (301), and LIF3 (302) neurons; in the second layer, there are 2LIF1 (307), 2LIF2 (308), and 2LIF3 (309) neurons. During the network information propagation and learning process, the LIF1 neuron circuit in the first layer receives the external input current pulse signal Iin1 and sends pulse signals to the subsequent neurons LIF2 (301) and LIF3 (302) through adjacent synaptic circuit modules according to the initialized real-time weights. The activated synaptic circuit modules include synaptic circuit modules 1-12 (303) and synaptic circuit modules 1-13 (304). The STDP1-23 (305) circuit modules between LIF2 (301) and LIF3 (302) neurons are activated to update the weights between neurons in real time.

[0009] The second-layer 2LIF1 (307) neuron receives pulse signals from the first-layer LIF2 (301) neuron through synaptic circuit module 12-21 (306). It then sends pulse signals to subsequent neurons 2LIF2 (308) and 2LIF3 (309) through adjacent synaptic circuit modules according to initialized real-time weights. The activated synaptic circuit modules include synaptic circuit modules 2-12 (310) and synaptic circuit module 2-23 (311). The STDP2-23 (312) circuit module between neurons 2LIF2 (308) and 2LIF3 (309) is activated to update the weights between neurons in real time.

[0010] The CMOS neuron-synaptic unit circuit designed in this invention improves its adaptability to wide-frequency signals by introducing an adaptive time window module. This allows it to automatically adjust the STDP time window according to the input pulse frequency, offering advantages over the traditional fixed-time-window STDP mechanism when processing dynamic environmental signals. Simultaneously, the designed multi-neuron synaptic propagation structure not only successfully achieves efficient network initialization but also accurately simulates the signal propagation process of a spiking neural network. Furthermore, theoretically, it can achieve high parallelism between network initialization and information propagation learning behavior, improving signal processing efficiency. Attached Figure Description

[0011] Figure 1 This is a block diagram of a CMOS neuron-synapse unit circuit system.

[0012] Figure 2 A schematic diagram of the initialization of a six-neuron network;

[0013] Figure 3This is a schematic diagram of information propagation and learning in a six-neuron network.

[0014] Wherein: 100 is the pre-LIF neuron circuit module; 101 is the synaptic circuit module including: absolute difference calculator (105), flash analog-to-digital converter (106), digital-to-analog converter (107); 102 is the STDP circuit module; 103 is the ATML circuit module; 104 is the post-LIF neuron circuit module. 200 is the LIF1 neuron; 201 is the LIF2 neuron; 202 is the LIF3 neuron; 203 is the STDP1-12 circuit module; 203 is the STDP1-13 circuit module; 205 is the synaptic circuit module 2-21; 206 is the synaptic circuit module 2-22; 207 is the synaptic circuit module 2-23; 208 is the 2LIF1 neuron; 209 is the 2LIF2 neuron; 210 is the 2LIF3 neuron; 211 is the STDP2-12 circuit module; 212 is the STDP2-13 circuit module. 300 is LIF1 neuron; 301 is LIF2 neuron; 302 is LIF3 neuron; 303 is synaptic circuit module 1-12; 304 is synaptic circuit module 1-13; 305 is STDP1-23 circuit module; 306 is synaptic circuit module 12-21; 307 is 2LIF1 neuron; 308 is 2LIF2 neuron; 309 is 2LIF3 neuron; 310 is synaptic circuit module 2-12; 311 is synaptic circuit module 2-23; 312 is STDP2-23 circuit module. Detailed Implementation

[0015] According to the foregoing description of the invention, the circuit structure was designed in the Cadence platform using the 0.18-micron CMOS process provided by Semiconductor Manufacturing International Corporation (SMIC), and simulation verification was performed. Simulation results show that the circuit system can achieve efficient network initialization and network information propagation learning.

[0016] Figure 1 The diagram shows a block diagram of a CMOS neuron-synaptic unit circuit system for spiking neural networks according to the present invention, including a preneuron LIF circuit module (100), a synaptic circuit module (101), an STDP circuit module (102), an ATML circuit module (103), and a postneuron LIF circuit module (104). Each synaptic circuit module (101) includes an absolute difference calculator (105), a flash analog-to-digital converter (106), and a digital-to-analog converter (107).

[0017] The preneuron LIF circuit module (100) receives the external pulse input Spike_in(pre) and generates the output pulse Spike_out(pre) through integration, which is input to the digital-to-analog converter (107) to control the timing of the synapse outputting the pulse signal. The absolute difference calculator (105) receives the initial reference weight Vref and the real-time synaptic weight V_Weight, calculates the absolute value Vin of the difference between the two, and connects it to the flash memory analog-to-digital converter (106). The flash memory analog-to-digital converter (106) receives the absolute value Vin of the difference and the analog-to-digital converter reference voltage Vref_ADC, generates a 64-bit thermometer code, inputs it to the internal decoder to generate 6-bit binary control signals Open1-6, and inputs them to the digital-to-analog converter (107). The digital-to-analog converter (107) determines the timing of the output current pulse according to the input pulse signal Spike_out(pre), controls the magnitude of the output current pulse according to the input 6-bit binary control signals Open1-6, and outputs the pulse signal Spike_in(post), which is input to the postneuron LIF circuit module (104). The post-neuron LIF circuit module (104) receives the external pulse input Spike_Iin(post) and generates an output pulse Spike_out(post) through integration, which is then input to the STDP circuit module (102). The STDP circuit module (102) receives the pre-neuron pulse input Spike_out(pre) and the post-neuron pulse input Spike_out(post) within the time window determined by the time window length signal Vleak, and adjusts the synaptic real-time weight V_Weight output size according to their relative time difference. The ATML circuit module (103) receives the pre-neuron pulse input Spike_out(pre) and the post-neuron pulse input Spike_out(post), and adjusts the weights to update the time window length signal Vleak according to their relative time difference, thus achieving adaptive time window length.

[0018] Figure 2 This is a schematic diagram of the initialization of the designed six-neuron network. The initialization process of the six-neuron network designed in this invention is as follows: First, a neural network architecture with two layers is constructed. The first layer consists of three LIF neuron circuit modules LIF1 (200), LIF2 (201), and LIF3 (202), which are used to receive external input signals and perform preliminary processing and transmission of neural impulses. The second layer consists of three LIF neuron circuit modules 2LIF1 (208), 2LIF2 (209), and 2LIF3 (210), which are responsible for receiving pulse signals transmitted from the neurons in the first layer and further processing them to achieve more complex information encoding and feature extraction functions. According to the preset network connection strategy, a connection path is established between the neurons in the first layer and the second layer through synaptic circuit modules.

[0019] During the initialization phase of the first layer of neurons, independent external input current pulse signal channels are set for LIF1(200), LIF2(201), and LIF3(202), namely input current pulse signals Iin1, Iin2, and Iin3. The parameters of these input signal sources can be flexibly adjusted and configured according to the actual application scenario requirements to accurately drive the activation and pulse firing process of the first layer of neurons. At the same time, some STDP (Pulse Timing Dependent Plasticity) circuit modules between the first layer of neurons are selectively enabled to initialize the synaptic weights between neurons. Specifically, STDP1-12(203) and STDP1-13(204) modules are enabled, corresponding to the synaptic connections between LIF1(200) and LIF2(201) and between LIF1(200) and LIF3(202), respectively.

[0020] For the initialization of the second layer of neurons, the corresponding synaptic circuit modules are enabled to realize the pulse signal transmission and weight adjustment functions between the second layer neurons and the first layer neurons. Specifically, the enabled synaptic circuit modules include synaptic circuit modules 2-21 (205), 2-22 (206), and 2-23 (207), which correspond to the connections between the second layer neurons 2LIF1 (208), 2LIF2 (209), and 2LIF3 (210) and the first layer neurons, respectively. In addition, some STDP circuit modules are enabled within or between the second layer neurons to initialize the synaptic weights between the second layer neurons. Specifically, STDP2-12 (211) and STDP2-13 (212) modules are enabled, which correspond to the synaptic connections between 2LIF1 (208) and 2LIF2 (209) and between 2LIF1 (208) and 2LIF3 (210), respectively.

[0021] Figure 3 This is a schematic diagram of the information propagation and learning process of the designed six-neuron network. The information propagation and learning process of the six-neuron network designed in this invention is as follows: The initial two-layer neural network architecture is used, with each layer containing three LIF neuron circuit modules. The LIF1 (300), LIF2 (301), and LIF3 (302) of the first layer are responsible for receiving and transmitting external input signals, while the 2LIF1 (307), 2LIF2 (308), and 2LIF3 (309) of the second layer further transmit signals from the first layer.

[0022] During the information propagation process of the first layer of neurons, the LIF1 (300) neuron is activated after receiving the external input current pulse signal Iin1. The parameters of this signal can be configured as needed. Upon activation, it triggers the injection of a current pulse, causing the neuron's membrane potential to accumulate. When the threshold is reached, a pulse signal is emitted. This signal is transmitted to LIF2 (301) and LIF3 (302) via synaptic circuit modules 1-12 (303) and 1-13 (304), and the pulse signal intensity is adjusted according to the initialized weight parameters. At the same time, the STDP1-23 (305) circuit module between LIF2 (301) and LIF3 (302) is activated to adjust the synaptic weights based on the pulse timing difference.

[0023] The second layer 2LIF1(307) neuron receives the pulse signal output by LIF2(301) through the synaptic circuit module 12-21(306), and passes it to 2LIF2(308) and 2LIF3(309) according to the initial weight. Similarly, the STDP2-23(312) circuit module in between updates the weight, realizing the synchronous propagation and learning of information in the two-layer network.

[0024] During network operation, the modules work collaboratively. First-layer neurons receive signals and transmit them to the second layer via synapses, while neurons within the same layer update their weights through the STDP mechanism. Second-layer neurons receive signals, integrate and process them, and then transmit them again, similarly utilizing STDP to optimize connections. This hierarchical architecture progressively extracts signal features and maintains high parallelism between network layers while deepening the network layer by layer. Theoretically, it possesses the ability to efficiently initialize and learn information propagation in the face of more complex network structures. The signal transmission, weight updates, and neuron activation of each module work in concert to form a dynamic, brain-like neural network system, providing hardware support for efficient temporal information processing and intelligent computing.

Claims

1. A CMOS neuron-synapse unit circuit system suitable for spiking neural networks, characterized in that: The preneuron LIF circuit module (100) receives the external pulse input Spike_in(pre) and generates the output pulse Spike_out(pre) through integration, which is input to the digital-to-analog converter (107) to control the timing of the synapse outputting the pulse signal. The absolute difference calculator (105) receives the initial reference weight Vref and the real-time synaptic weight V_Weight and calculates the absolute difference Vin between them, which is connected to the flash memory analog-to-digital converter (106). The flash memory analog-to-digital converter (106) receives the absolute difference Vin and the analog-to-digital converter reference voltage Vref_ADC, generates a 64-bit thermometer code, inputs it to the internal decoder to generate a 6-bit binary control signal Open1-6, and inputs it to the digital-to-analog converter (107). The digital-to-analog converter (107) determines the timing of the output current pulse according to the input pulse signal Spike_out(pre), and controls the magnitude of the output current pulse according to the input 6-bit binary control signal Open1-6. The Spike_Iin(post) is input to the post-neuron LIF circuit module (104); the post-neuron LIF circuit module (104) receives the external pulse input Spike_Iin(post) and generates the output pulse Spike_out(post) through integration, which is then input to the STDP circuit module (102); the STDP circuit module (102) receives the pre-neuron pulse input Spike_out(pre) and the post-neuron pulse input Spike_out(post) within the time window determined by the time window length signal Vleak, and adjusts the synaptic real-time weight V_Weight output size according to the relative time difference between the two; the ATML circuit module (103) receives the pre-neuron pulse input Spike_out(pre) and the post-neuron pulse input Spike_out(post), and adjusts the weight to update the time window length signal Vleak according to the relative time difference between the two, thereby achieving adaptive time window length.

2. The system according to claim 1, characterized in that: The initialization process of the six-neuron network is as follows: First, a neural network architecture with two layers is constructed. The first layer consists of three LIF neuron circuit modules LIF1 (200), LIF2 (201) and LIF3 (202), which are used to receive external input signals and perform preliminary processing and transmission of neural impulses. The second layer consists of three LIF neuron circuit modules 2LIF1 (208), 2LIF2 (209) and 2LIF3 (210), which are responsible for receiving pulse signals transmitted from the neurons in the first layer and processing them further. A connection pathway is established between the neurons in the first layer and the neurons in the second layer through the synaptic circuit module. During the initialization phase of the first layer of neurons, independent external input current pulse signal channels are set up for LIF1(200), LIF2(201), and LIF3(202), namely, input current pulse signals Iin1, Iin2, and Iin3. At the same time, some STDP (pulse timing-dependent plasticity) circuit modules between neurons in the first layer are selectively enabled to initialize the synaptic weights between neurons. Specifically, STDP1-12 (203) and STDP1-13 (204) modules are enabled, which correspond to the synaptic connections between LIF1 (200) and LIF2 (201) and LIF1 (200) and LIF3 (202), respectively. For the initialization of the second layer of neurons, the corresponding synaptic circuit modules are enabled to realize the pulse signal transmission and weight adjustment functions between the second layer neurons and the first layer neurons. Specifically, the enabled synaptic circuit modules include synaptic circuit modules 2-21 (205), synaptic circuit modules 2-22 (206) and synaptic circuit modules 2-23 (207), which correspond to the connection between the second layer neurons 2LIF1 (208), 2LIF2 (209), and 2LIF3 (210) and the first layer neurons, respectively. In addition, some STDP circuit modules are enabled inside or between the second layer neurons to initialize the synaptic weights between the second layer neurons. STDP2-12 (211) and STDP2-13 (212) modules are enabled, which correspond to the synaptic connections between 2LIF1 (208) and 2LIF2 (209) and between 2LIF1 (208) and 2LIF3 (210), respectively.

3. The system according to claim 1, characterized in that: The network consists of a two-layer neuron structure, with each layer containing three LIF neuron circuit modules. In the first layer, there are LIF1 (300), LIF2 (301), and LIF3 (302) neurons. In the second layer, there are 2LIF1 (307), 2LIF2 (308), and 2LIF3 (309) neurons. During the network information propagation and learning process, the LIF1 neuron circuit in the first layer receives the external input current pulse signal Iin1 and sends pulse signals to the subsequent neurons LIF2 (301) and LIF3 (302) through the adjacent synaptic circuit modules according to the initialized real-time weights. The activated synaptic circuit modules include synaptic circuit modules 1-12 (303) and synaptic circuit modules 1-13 (304). The STDP1-23 (305) circuit modules between the LIF2 (301) and LIF3 (302) neurons are activated to update the weights between neurons in real time. The second-layer 2LIF1 (307) neuron receives the pulse signal output from the first-layer LIF2 (301) neuron through the synaptic circuit module 12-21 (306). It sends pulse signals to the subsequent neurons 2LIF2 (308) and 2LIF3 (309) through the adjacent synaptic circuit module according to the initialized real-time weights. The activated synaptic circuit modules include synaptic circuit module 2-12 (310) and synaptic circuit module 2-23 (311). The STDP2-23 (312) circuit module between the 2LIF2 (308) and 2LIF3 (309) neurons is activated to realize the real-time update of the weight between neurons.

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