Driving circuit, display panel and display device

Abstract

The invention discloses a driving circuit, a display panel and a display device. The driving circuit comprises a multi-stage driving unit, and the driving unit comprises an input module which outputs a control signal of a first node according to voltage signals of clock signals, pre-stage driving signals and post-stage driving signals accessed by a plurality of signal input ends; the driving signal output module is used for outputting a current-stage driving signal according to a control signal of the first node and a first clock signal; the clamping output module is used for stabilizing the current-stage driving signal; the noise coupling module is electrically connected with the first node and accesses a second clock signal and a pre-stage driving signal; wherein the phases of the second clock signal and the first clock signal are opposite. Periodic noise of the first clock signal to the first node is offset or reduced through coupling of the second clock signal, the pull-down speed of a driving signal output waveform is improved, closing of a transistor grid electrode in an in-plane pixel unit is accelerated, generation of inter-line crosstalk is reduced, and the reliability of a display product is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a driving circuit, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the reliability of display products. This necessitates that the circuitry in display products possess low-noise characteristics to withstand more stringent reliability tests. Specifically, display products include multiple gate lines and multiple data lines. The gate lines and data lines intersect to form a pixel unit, and each pixel unit includes at least one thin-film transistor (TFT). The gate lines are electrically connected to the gates of the TFTs in the pixel unit to drive the TFTs to conduct line by line. The gate drive signal on the gate line is generated by a drive circuit. The output signal of the drive circuit, i.e., the gate drive signal, is susceptible to interference from the periodic high and low levels of the clock signal, thus generating parasitic noise and affecting the reliability of the display product. Summary of the Invention

[0003] The present invention provides a driving circuit, a display panel, and a display device to reduce or eliminate parasitic noise, while increasing the pull-down speed of the driving signal output waveform, accelerating the gate shutdown of transistors in in-plane pixel units, reducing the generation of inter-line crosstalk, and improving the reliability of display products.

[0004] According to one aspect of the present invention, a driving circuit is provided, the driving circuit comprising multiple driving units, each driving unit being used to drive a corresponding gate line on a display panel; the driving unit comprising: The input module includes multiple signal input terminals, and outputs a control signal for the first node based on the voltage signals of the clock signal, the pre-stage drive signal, and the post-stage drive signal connected to the multiple signal input terminals. A drive signal output module is electrically connected to the first node and receives a first clock signal. The drive signal output module outputs a drive signal of this stage according to the control signal of the first node and the first clock signal. A clamping output module is connected between the first node and the drive signal output module. The output signal of the clamping output module is clamped according to the control signal of the first node to stabilize the drive signal of this stage. A noise coupling module is electrically connected to the first node and is connected to a second clock signal and the pre-stage drive signal; wherein the second clock signal and the first clock signal are out of phase, and the second clock signal is used to couple and cancel or reduce the periodic noise of the first clock signal to the first node.

[0005] Optionally, the noise coupling module includes: A coupling unit, wherein the coupling unit is connected between the first node and the second node; A periodic unit, which is electrically connected to the second node and receives the second clock signal and a first level signal, and inputs the second clock signal to the second node under the control of the first level signal; A pull-down unit is electrically connected to the second node and receives the pre-stage drive signal and the second level signal. The second level signal is input to the second node under the control of the pre-stage drive signal.

[0006] Optionally, the coupling unit includes a first capacitor connected between the first node and the second node; Optionally, the periodic unit includes a first switching element, the control terminal of the first switching element is connected to the first level signal, the first terminal of the first switching element is connected to the second clock signal, and the second terminal of the first switching element is electrically connected to the second node; Optionally, the pull-down unit includes a second switching element, the control terminal of the second switching element is connected to the pre-stage drive signal, the first terminal of the second switching element is connected to the second level signal, and the second terminal of the second switching element is electrically connected to the second node.

[0007] Optionally, in the drive signal output module, the number of switching elements electrically connected to the first clock signal is at least one; The capacitance value of the first capacitor is equal to the sum of the parasitic capacitances of each switching element electrically connected to the first clock signal.

[0008] Optionally, the pre-stage driving signal is the first N-stage driving signal, and the post-stage driving signal is the last N-stage driving signal, where N≥2; The number of clock signals is positively correlated with the value of N, and the pulse width of the clock signals is positively correlated with the value of N; the clock signals include the clock signal connected to the input module, the first clock signal, and the second clock signal.

[0009] Optionally, the duty cycle of each clock signal is 50%.

[0010] Optionally, the drive signal output module includes: a third switching element and a second capacitor, wherein the control terminal of the third switching element is electrically connected to the first node, the first terminal of the third switching element is connected to the first clock signal, and the second terminal of the third switching element outputs the drive signal of this stage; the first terminal of the second capacitor is electrically connected to the control terminal of the third switching element, and the second terminal of the second capacitor is electrically connected to the second terminal of the third switching element. Optionally, the input module includes: a fourth switching element and a fifth switching element, wherein the control terminal and the first terminal of the fourth switching element are both connected to the pre-stage drive signal, or the control terminal of the fourth switching element is connected to the pre-stage drive signal, the first terminal is connected to the fourth clock signal, and the second terminal of the fourth switching element is electrically connected to the first node; the control terminal of the fifth switching element is connected to the post-stage drive signal, the first terminal of the fifth switching element is connected to the third clock signal, and the second terminal of the fifth switching element is electrically connected to the first node; Optionally, the clamping output module includes: a sixth switching element, a seventh switching element, an eighth switching element, a ninth switching element, a tenth switching element, an eleventh switching element, a twelfth switching element, a thirteenth switching element, a fourteenth switching element, and a fifteenth switching element; The control terminal and the first terminal of the sixth switching element are both connected to a third-level signal; the control terminal and the first terminal of the seventh switching element are both connected to a fourth-level signal. The control terminal of the eighth switching element is connected to the third level signal, the first terminal of the eighth switching element is connected to the fifth level signal, and the second terminal of the eighth switching element is electrically connected to the second terminal of the seventh switching element; the control terminal of the ninth switching element is connected to the fourth level signal, the first terminal of the ninth switching element is connected to the fifth level signal, and the second terminal of the ninth switching element is electrically connected to the second terminal of the sixth switching element. The control terminals of the tenth and eleventh switching elements are both electrically connected to the first node. The first terminals of the tenth and eleventh switching elements are both electrically connected to the second terminal of the eighth switching element. The second terminal of the tenth switching element is electrically connected to the second terminal of the sixth switching element. The second terminal of the eleventh switching element is electrically connected to the second terminal of the seventh switching element. The control terminals of the twelfth and thirteenth switching elements are both electrically connected to the second terminal of the sixth switching element. The second terminal of the twelfth switching element and the first terminal of the thirteenth switching element are electrically connected and connected to the fifth level signal. The second terminals of the twelfth and thirteenth switching elements are both electrically connected to the first node. The control terminals of the fourteenth and fifteenth switching elements are both electrically connected to the second terminal of the seventh switching element. The second terminal of the fourteenth switching element and the first terminal of the fifteenth switching element are electrically connected and connected to the second level signal. The second terminals of the fourteenth and fifteenth switching elements are both electrically connected to the driving signal of this stage. The third level signal and the fourth level signal are opposite in phase and change periodically, with a period of at least one full-screen scan time.

[0011] Optionally, the drive signal output module further includes a sixteenth switching element; the clamping output module further includes a seventeenth switching element and an eighteenth switching element. The control terminal of the sixteenth switching element is electrically connected to the first node, the first terminal of the sixteenth switching element is electrically connected to the first clock signal, and the second terminal of the sixteenth switching element outputs the signal transmitted at this stage. The control terminal of the seventeenth switching element is electrically connected to the second terminal of the sixth switching element, and the control terminal of the eighteenth switching element is electrically connected to the second terminal of the seventh switching element. The first terminals of the seventeenth and eighteenth switching elements are both connected to the second level signal, and the second terminals of the seventeenth and eighteenth switching elements are both electrically connected to the signal transmitted at this level. The control terminal of the fourth switching element is connected to the pre-stage transmission signal, the first terminal of the fourth switching element is connected to the pre-stage drive signal, and the second terminal of the fourth switching element is electrically connected to the first node.

[0012] Optionally, the clamping output module includes: a nineteenth switching element, a twentieth switching element, a twenty-first switching element, a twenty-second switching element, and a twenty-third switching element; The first terminal of the nineteenth switching element, the first terminal of the twentieth switching element, the first terminal of the twentieth switching element, and the first terminal of the twentieth switching element are all connected to the second level signal. Both the control terminal and the first terminal of the 23rd switching element are connected to a sixth-level signal; the control terminal of the 21st switching element is electrically connected to the first node, and the second terminal of the 21st switching element is electrically connected to the second terminal of the 23rd switching element. The control terminals of the twentieth and twentieth switching elements are both electrically connected to the second terminal of the twentieth switching element, and the second terminal of the twentieth switching element is electrically connected to the first node; the second terminal of the twentieth switching element is electrically connected to the driving signal of this stage. The control terminal of the nineteenth switching element is connected to the fifth clock signal, and the second terminal of the nineteenth switching element is electrically connected to the driving signal of this stage.

[0013] According to another aspect of the present invention, a display panel is provided, including the driving circuit described in any embodiment of the present invention.

[0014] According to another aspect of the present invention, a display device is provided, comprising a display panel as described above.

[0015] This invention incorporates a noise coupling module into the driving circuit. The noise coupling module operates as follows: during the non-output sustain phase (including at least the pre-charge and bootstrap charging phases), the preceding driving signal controls the second clock signal to prevent coupling to the first node, ensuring the first node can stably receive the control signals output by the input module. During the output sustain phase, the driving signal needs to maintain a fixed level for an extended period. The periodically changing high and low levels of the first clock signal are coupled to the first node, and simultaneously, the periodically changing high and low levels of the second clock signal are coupled to the first node. The second clock signal and the first clock signal are out of phase; that is, when the first clock signal is high, the second clock signal is low; and when the first clock signal is low, the second clock signal is high. Therefore, while the first node is raised by the voltage coupling of the first clock signal, it is lowered by the voltage coupling of the second clock signal; while the first node is lowered by the voltage coupling of the first clock signal, it is raised by the voltage coupling of the second clock signal. This allows the periodic noise of the first clock signal to the first node to be canceled or reduced by the coupling of the second clock signal, while increasing the pull-down speed of the drive signal output waveform, accelerating the gate shutdown of transistors in the in-plane pixel unit, reducing the generation of inter-line crosstalk, and improving the reliability of the display product.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A circuit diagram of a driving unit provided in an embodiment of the present invention; Figure 2 A waveform diagram of a driving circuit during the output sustaining phase, provided in an embodiment of the present invention; Figure 3 A circuit diagram of another driving unit provided in an embodiment of the present invention; Figure 4 A circuit diagram of another driving unit provided in an embodiment of the present invention; Figure 5 A circuit diagram of another driving unit provided in an embodiment of the present invention; Figure 6A circuit diagram of another driving unit provided in an embodiment of the present invention; Figure 7 This is a circuit diagram of another driving unit provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] This invention provides a driving circuit comprising multiple driving units, each driving unit driving a corresponding gate line on a display panel, the gate line driving the gate of a transistor in an in-plane pixel unit. The signal output by the driving unit can be referred to as a driving signal or a gate signal.

[0022] Figure 1 This is a circuit diagram of a driving unit provided in an embodiment of the present invention. See also... Figure 1 The drive unit includes: The input module 100 includes multiple signal input terminals and outputs a control signal for the first node Q based on the voltage signals of the clock signal (e.g., the third clock signal CLK3), the pre-stage drive signal (e.g., the first two-stage drive signal Gn-2), and the post-stage drive signal (e.g., the post-two-stage drive signal Gn+2) connected to the multiple signal input terminals. The drive signal output module 200 is electrically connected to the first node Q and receives the first clock signal CLK2. It outputs the drive signal Gn of this stage according to the control signal of the first node Q and the first clock signal CLK2. The clamping output module 300 is connected between the first node Q and the drive signal output module 200. The output signal of the clamping output module 300 is clamped according to the control signal of the first node Q to stabilize the drive signal Gn of this stage. The noise coupling module 400 is electrically connected to the first node Q and is connected to the second clock signal CLK4 and the preceding stage drive signal (e.g., the first two stage drive signal Gn-2). The second clock signal CLK4 and the first clock signal CLK2 are out of phase, and the periodic noise of the first clock signal CLK2 on the first node Q is canceled by the coupling of the second clock signal CLK4.

[0023] The operation of the drive unit includes a pre-charge phase, a bootstrap charging phase, a pull-down phase, and an output sustain phase. After the pre-charge, bootstrap charging, and pull-down phases, the drive signal Gn of this stage achieves shifted output. During the output sustain phase, the drive signal Gn needs to maintain a fixed level (e.g., low level) for a long time. However, the output of the drive signal Gn during the output sustain phase is susceptible to interference from the periodic high and low levels of the first clock signal CLK2, resulting in periodic noise. This periodic noise originates from the parasitic capacitance of the switching elements in the drive signal output module 200, which couples the voltage of the first clock signal CLK2 to the first node Q. Figure 2 This is a waveform diagram of a driving circuit during the output sustaining phase, provided as an embodiment of the present invention. Figure 2 As shown in the comparative example, when the first clock signal CLK2 switches from low level to high level, the voltage coupling of the first node Q increases, resulting in an upward noise spike; when the first clock signal CLK2 switches from high level to low level, the voltage coupling of the first node Q decreases, resulting in a downward noise spike.

[0024] This embodiment of the invention adds a noise coupling module 400 to the driving circuit. The noise coupling module 400 operates as follows: during the non-output sustaining phase (including at least the pre-charge phase and the bootstrap charging phase), the preceding driving signal (e.g., the first two driving signals Gn-2) controls the second clock signal CLK4 to prevent coupling to the first node Q, ensuring that the first node Q can stably receive the control signal output by the input module 100. During the output sustaining phase, the current driving signal Gn needs to maintain a fixed level (e.g., low level) for a long time. The periodic high and low levels of the first clock signal CLK2 are coupled to the first node Q, and simultaneously, the periodic high and low levels of the second clock signal CLK4 are coupled to the first node Q. The second clock signal CLK4 and the first clock signal CLK2 are out of phase; that is, when the first clock signal CLK2 is high, the second clock signal CLK4 is low; and when the first clock signal CLK2 is low, the second clock signal CLK4 is high. Therefore, while the first node Q is boosted by the voltage coupling of the first clock signal CLK2, it is simultaneously boosted by the voltage coupling of the second clock signal CLK4. This allows the periodic noise from the first clock signal CLK2 on the first node Q to be canceled or reduced through coupling with the second clock signal CLK4. Simultaneously, the noise coupling module 400 ensures that when the drive signal at this stage ends its bootstrap charging phase, the second clock signal CLK4 transitions from low to high. This coupling through the noise coupling module 400 boosts the voltage of the first node Q, accelerating the opening of the drive signal output module 200. This facilitates the rapid writing of the low level of the first clock signal CLK1 to the gate of the transistor in the in-plane pixel unit, while also increasing the pull-down speed of the drive signal output waveform, accelerating the closing of the transistor gate in the in-plane pixel unit, reducing inter-line crosstalk, and improving the reliability of the display product.

[0025] Based on the above embodiments, there are alternative ways to configure the noise coupling module 400, which will be described in detail below, but this is not intended to limit the present invention.

[0026] Figure 3 A circuit diagram of another driving unit provided in an embodiment of the present invention. See also Figure 3 In one embodiment, optionally, the noise coupling module 400 includes: The coupling unit 410 is connected between the first node Q and the second node A; Periodic unit 420 is electrically connected to the second node A and receives the second clock signal CLK4 and the first level signal DCH. The second clock signal CLK4 is input to the second node A under the control of the first level signal DCH. The pull-down unit 430 is electrically connected to the second node A and receives the preceding drive signal (e.g., the first two drive signals Gn-2) and the second level signal VGL. The second level signal VGL is input to the second node A under the control of the preceding drive signal (e.g., the first two drive signals Gn-2).

[0027] For example, the noise coupling module 400 operates as follows: during the non-output sustaining phase (including at least the pre-charge phase and the bootstrap charging phase), the pull-down unit 430 is turned on by the preceding drive signal (e.g., the first two drive signals Gn-2), and the second level signal VGL is input to the second node A; at the same time, under the control of the first level signal DCH, the periodic unit 420 is turned on, the second clock signal CLK4 is input to the second node A, and is pulled down by the second level signal VGL. The second node A maintains the second level signal VGL to ensure that the first node Q can stably receive the control signal output by the input module 100 without being affected by the noise coupling module 400. During the output sustain phase, the pull-down unit 430 is disconnected by the preceding drive signal (e.g., the first two drive signals Gn-2). Under the control of the first level signal DCH, the periodic unit 420 remains in the conducting state. The second clock signal CLK4 is input to the second node A, and the periodic high and low levels of the second clock signal CLK4 are further coupled to the first node Q through the coupling unit 410 to cancel or reduce the periodic noise of the first clock signal CLK2 to the first node Q.

[0028] Figure 4 A circuit diagram of another driving unit provided in an embodiment of the present invention. See also Figure 4 In one embodiment, optionally, the coupling unit 410 includes a first capacitor C2, which is connected between the first node Q and the second node A. The first capacitor C2 is capable of coupling the periodically changing high and low levels of the second clock signal CLK4 to the first node Q. This embodiment of the invention includes the first capacitor C2 in the coupling unit 410, resulting in a simple circuit structure that is easy to implement.

[0029] See also Figure 4In one embodiment, the periodic unit 420 optionally includes a first switching element T17. The control terminal of the first switching element T17 is connected to a first level signal DCH, the first terminal of the first switching element T17 is connected to a second clock signal CLK4, and the second terminal of the first switching element T17 is electrically connected to the second node A. The first switching element T17 is an N-type thin-film transistor, which is always in a conducting state under the control of the first level signal DCH. When the second node A is pulled down by the second level signal VGL, the first switching element T17 acts as a large resistor, preventing a short circuit between the second level signal VGL and the second clock signal CLK4. This embodiment of the invention includes a first switching element T17 in the periodic unit 420, resulting in a simple circuit structure that is easy to implement.

[0030] See also Figure 4 In one embodiment, optionally, the pull-down unit T18 includes a second switching element T18. The control terminal of the second switching element T18 is connected to the preceding stage drive signal (e.g., the first two stage drive signals Gn-2), the first terminal of the second switching element T18 is connected to the second level signal VGL, and the second terminal of the second switching element T18 is electrically connected to the second node A. The second switching element T18 is an N-type thin-film transistor, which conducts when the preceding stage drive signal (e.g., the first two stage drive signals Gn-2) is high, pulling down the voltage of the second node A. Since the second switching element T18 acts as a large resistor, it prevents a short circuit between the second level signal VGL and the second clock signal CLK4. This embodiment of the invention provides a pull-down unit T18 including the second switching element T18, resulting in a simple circuit structure that is easy to implement.

[0031] It should be noted that in the above embodiments, the first level signal is described as high level (represented by the reference numeral DCH) as an example, which is not intended to limit the present invention. In other embodiments, the first level signal can also be set to low level. In practical applications, it can be determined according to the type of the first switching element T17.

[0032] It should also be noted that, in Figure 3 and Figure 4 The example described herein illustrates that the periodic unit 420 is always on under the control of the first level signal DCH, and is not intended to limit the invention. In other embodiments, the periodic unit 420 may be controlled by other signals and only turned on during the output sustain phase, inputting the second clock signal CLK4 to the second node A. In this case, in some embodiments, the pull-down unit 430 may be omitted to simplify the circuit structure.

[0033] Based on the above embodiments, optionally, the pre-stage drive signal is the first N-stage drive signal, and the post-stage drive signal is the last N-stage drive signal, where N≥2; wherein, the number of clock signals is positively correlated with the value of N, and the pulse width of the clock signal is positively correlated with the value of N; the clock signals include the clock signal connected to the input module 100, the first clock signal CLK2, and the second clock signal CLK4.

[0034] See also Figure 4 For example, N=2, the pulse width of the clock signal is the width of two line scan times, and the number of clock signals is 4. Specifically, when the current stage drive signal outputs an effective level pulse (e.g., a high-level pulse), the current stage drive signal Gn is still in an ineffective level (e.g., a low-level stage). The high-level pulses of the previous two stage drive signals Gn-2 are two line scan times earlier than the high-level pulse of the current stage drive signal Gn, and the width of the high-level pulses of the previous two stage drive signals Gn-2 is the width of two line scan times.

[0035] Based on this, for this stage of the drive unit, the working principle of the noise coupling module 400 is as follows: the first level signal DCH controls the first switching element T17 to always be in the on state, transmitting the second clock signal CLK4 to the second node A. During the pre-charging phase, the second clock signal CLK4 is at a high level, and the high level of the first two stage drive signals Gn-2 controls the second switching element T18 to be turned on, pulling the second node A to the second level signal VGL; at the same time, the high level of the first two stage drive signals Gn-2 is transmitted to the first node Q, the first node Q is pre-charged, and the first node Q controls the drive signal output module 200 to be turned on, outputting the low level of the first clock signal CLK2, that is, the current stage drive signal Gn is still at a low level. During the bootstrap charging phase, the two-stage drive signal Gn-2 transitions from high to low, and the second clock signal CLK4 transitions from high to low. The second node A remains unaffected and remains low. Simultaneously, since the first node Q is pre-charged and is at a high level, when the first clock signal CLK2 transitions from low to high, the drive signal output module 200, due to its bootstrap action, further pulls the first node Q high, and the level of the current stage drive signal Gn also rises, outputting a high level. During the pull-down phase, the first clock signal CLK2 transitions to low, meaning the current stage drive signal Gn transitions to low. However, during the transition of the first clock signal CLK2 to low, the voltage coupling of the first node Q decreases. Simultaneously, the second clock signal CLK4 transitions to high, charging the second node A to the high voltage of the first level signal DCH, which is coupled to the first node Q via the first capacitor C2, increasing the voltage of the first node Q. This increases or reduces the voltage drop of the first node Q, thus ensuring the pull-down speed of the current stage drive signal Gn. During the output sustaining phase, the first switching element T17 is always in the on state under the control of the first level signal DCH. The voltage of the first clock signal CLK2 and the voltage of the second clock signal CLK4 change periodically, which cancels out the coupling voltage of the first node Q, reduces the voltage change of the first node Q, and improves the circuit stability.

[0036] Based on the above embodiments, optionally, the duty cycle of each clock signal is 50%. This setting helps to ensure that when the first clock signal CLK2 goes high, the second clock signal CLK4 goes low, so that the coupling voltage of the second clock signal CLK4 to the first node Q can cancel the coupling voltage of the first clock signal CLK2 to the first node Q; and when the first clock signal CLK2 goes low, the second clock signal CLK4 goes high, so that the coupling voltage of the second clock signal CLK4 to the first node Q can cancel the coupling voltage of the first clock signal CLK2 to the first node Q.

[0037] Figure 5 A circuit diagram of another driving unit provided in an embodiment of the present invention. See also Figure 5 Based on the above embodiments, optionally, the drive signal output module 200 includes: a third switching element T2 and a second capacitor C1. The control terminal of the third switching element T2 is electrically connected to the first node Q. The first terminal of the third switching element T2 is connected to the first clock signal CLK2, and the second terminal of the third switching element T2 outputs the current stage drive signal Gn. The first terminal of the second capacitor C1 is electrically connected to the control terminal of the third switching element T2, and the second terminal of the second capacitor C1 is electrically connected to the second terminal of the third switching element T2. The third switching element T2 is controlled by the first node Q to output the first clock signal CLK2; the second capacitor C1 serves to stabilize the output and perform bootstrapping.

[0038] For example, the third switching element T2 is an N-type thin-film transistor, which conducts when the first node Q is high. Specifically, during the pre-charge phase, the high level of the two-stage drive signal Gn-2 is transmitted to the first node Q, the first node Q is pre-charged, and the first node Q controls the third switching element T2 to conduct, outputting the low level of the first clock signal CLK2, that is, the current stage drive signal Gn is still low. During the bootstrap charging phase, since the first node Q is pre-charged and is in a high-level state, when the first clock signal CLK2 changes from low to high, the second capacitor C1, due to the bootstrap effect, further pulls the first node Q high, and the level of the current stage drive signal Gn also rises accordingly, outputting a high level. During the pull-down phase, the first clock signal CLK2 goes low, meaning the current stage drive signal Gn goes low. However, during the process of the first clock signal CLK2 going low, the parasitic capacitance of the third switching element T2 reduces the voltage coupling of the first node Q. Simultaneously, the second clock signal CLK4 goes high, charging the second node A to the high voltage of the first level signal DCH, which is coupled to the first node Q via the first capacitor C2, increasing the voltage of the first node Q. This increases or reduces the voltage drop of the first node Q, thus ensuring the pull-down speed of the current stage drive signal Gn. During the output sustain phase, the first switching element T17 remains in the on state under the control of the first level signal DCH. The voltages of the first clock signal CLK2 and the second clock signal CLK4 change periodically, canceling out the coupling voltage of the first node Q, reducing the voltage variation of the first node Q, and improving circuit stability.

[0039] In summary, the noise coupling module 400 not only couples the periodically changing high and low levels of the second clock signal CLK4 to the first node Q via the first capacitor C2, thus canceling or reducing the periodic noise of the first clock signal CLK2 on the first node Q, but also, due to the first capacitor C2, when the current stage drive signal Gn ends the bootstrap charging phase, the second clock signal CLK4 changes from low to high. This coupling through the first capacitor C2 causes a voltage boost at the first node Q. This effect accelerates the opening of the third switching element T2 in the drive signal output module 200, which facilitates the rapid writing of the low level of the first clock signal CLK1 to the gate of the transistor in the in-plane pixel unit. Simultaneously, it increases the pull-down speed of the drive signal output waveform, accelerates the gate shutdown of the transistor in the in-plane pixel unit, and reduces inter-row crosstalk.

[0040] See also Figure 5 Based on the above embodiments, optionally, the input module 100 includes: a fourth switching element T1 and a fifth switching element T3. The control terminal and first terminal of the fourth switching element T1 are both connected to a preceding stage drive signal (e.g., the first two stage drive signals Gn-2), and the second terminal of the fourth switching element T1 is electrically connected to the first node Q. The control terminal of the fifth switching element T3 is connected to a subsequent stage drive signal (e.g., the last two stage drive signals Gn+2), the first terminal of the fifth switching element T3 is connected to a third clock signal CLK3, and the second terminal of the fifth switching element T3 is electrically connected to the first node Q. The fourth switching element T1 is controlled by the preceding stage drive signal, and the fifth switching element T3 is controlled by the subsequent stage drive signal.

[0041] For example, both the fourth switching element T1 and the fifth switching element T3 are N-type thin-film transistors, which are turned on when their control terminals are high. Specifically, during the pre-charge phase, the first two-stage drive signals Gn-2 control the fourth switching element T1 to turn on, and simultaneously transmit the high level of the first two-stage drive signals Gn-2 to the first node Q, thus pre-charging the first node Q. During the bootstrap charging phase, the two-stage drive signals Gn-2 turn low, controlling the fourth switching element T1 to turn off. During the pull-down phase, the last two-stage drive signals Gn+2 control the fifth switching element T3 to turn on, and simultaneously transmit the third clock signal CLK3 to the first node Q. During the output sustain phase, the last two-stage drive signals Gn+2 control the fifth switching element T3 to turn off.

[0042] See also Figure 5 Based on the above embodiments, optionally, the clamping output module 300 includes: a sixth switching element T8, a seventh switching element T9, an eighth switching element T10, a ninth switching element T11, a tenth switching element T12, an eleventh switching element T13, a twelfth switching element T4, a thirteenth switching element T5, a fourteenth switching element T6, and a fifteenth switching element T7. The control terminal and the first terminal of the sixth switching element T8 are both connected to the third-level signal V1; the control terminal and the first terminal of the seventh switching element T9 are both connected to the fourth-level signal V2. The control terminal of the eighth switching element T10 is connected to the third-level signal V1, the first terminal of the eighth switching element T10 is connected to the fifth-level signal VSQ, and the second terminal of the eighth switching element T10 is electrically connected to the second terminal of the seventh switching element T9; the control terminal of the ninth switching element T11 is connected to the fourth-level signal V2, the first terminal of the ninth switching element T11 is connected to the fifth-level signal VSQ, and the second terminal of the ninth switching element T11 is electrically connected to the second terminal of the sixth switching element T8. The control terminals of the tenth switching element T12 and the eleventh switching element T13 are both electrically connected to the first node Q. The first terminals of the tenth switching element T12 and the eleventh switching element T13 are both electrically connected to the second terminal of the eighth switching element T10. The second terminal of the tenth switching element T12 is electrically connected to the second terminal of the sixth switching element T8. The second terminal of the eleventh switching element T13 is electrically connected to the second terminal of the seventh switching element T9. The control terminals of the twelfth switch element T4 and the thirteenth switch element T5 are both electrically connected to the second terminal of the sixth switch element T8. The second terminal of the twelfth switch element T4 and the first terminal of the thirteenth switch element T5 are electrically connected and connected to the fifth level signal VSQ. The second terminals of the twelfth switch element T4 and the thirteenth switch element T5 are both electrically connected to the first node Q. The control terminals of the fourteenth switch element T6 and the fifteenth switch element T7 are both electrically connected to the second terminal of the seventh switch element T9. The second terminal of the fourteenth switch element T6 and the first terminal of the fifteenth switch element T7 are electrically connected and connected to the second level signal VGL. The second terminals of the fourteenth switch element T6 and the fifteenth switch element T7 are both electrically connected to the driving signal Gn of this stage. Among them, the third level signal V1 and the fourth level signal V2 are out of phase and change periodically, with a period of at least one full-screen scan time.

[0043] For example, each switching element is an N-type thin-film transistor, which is turned on when its control terminal is high. When the third level signal V1 is high and the fourth level signal V2 is low, the sixth switching element T8 and the eighth switching element T10 are turned on. The eighth switching element T10 transmits the high level to the control terminals of the twelfth switching element T4 and the fourteenth switching element T6, turning on the twelfth switching element T4 and the fourteenth switching element T6. During the pre-charge phase and the bootstrap charging phase, the first node Q is high, controlling the tenth switching element T12 and the eleventh switching element T13 to turn on. The tenth switching element T12 transmits the fifth level signal VSQ to the control terminals of the twelfth switching element T4 and the fourteenth switching element T6, pulling them down to control the twelfth switching element T4 and the fourteenth switching element T6 to turn off; the eleventh switching element T13 transmits the fifth level signal VSQ to the control terminals of the thirteenth switching element T5 and the fifteenth switching element T7, controlling them to turn off. Therefore, during the pre-charge and bootstrap charging phases, the current stage drive signal Gn is unaffected by the second-level signal VGL. During the pull-down and output sustain phases, the first node Q is low, controlling the tenth and eleventh switching elements T12 and T13 to disconnect; the eighth switching element T10 transmits the fifth-level signal VSQ to the control terminals of the thirteenth and fifteenth switching elements T5, controlling them to disconnect; the twelfth and fourteenth switching elements T4 and T6 receive the high-level signal transmitted by the sixth switching element T8 and are turned on; the twelfth switching element T4 transmits the fifth-level signal VSQ to the first node Q, maintaining the low-level state of the first node Q; the fourteenth switching element T6 outputs the second-level signal VGL as the current stage drive signal Gn, maintaining the low level of the current stage drive signal Gn. The operating principle is similar when the third-level signal V1 is low and the fourth-level signal V2 is high, and will not be elaborated further.

[0044] Optionally, both the fifth level signal VSQ and the second level signal VGL are at low levels. Preferably, the voltage of the fifth level signal VSQ is lower than the voltage of the second level signal VGL. The fifth level signal VSQ is used to control the control terminals of the twelfth switching element T4, the thirteenth switching element T5, the fourteenth switching element T6, and the fifteenth switching element T7. Setting the voltage of the fifth level signal VSQ lower than the voltage of the second level signal VGL helps ensure that the twelfth switching element T4, the thirteenth switching element T5, the fourteenth switching element T6, and the fifteenth switching element T7 can be reliably disconnected.

[0045] Figure 6 A circuit diagram of another driving unit provided in an embodiment of the present invention. See also Figure 6Based on the above embodiments, optionally, the drive signal output module 200 further includes: a sixteenth switching element T14; the clamping output module 300 further includes: a seventeenth switching element T15 and an eighteenth switching element T16; Among them, the control terminal of the sixteenth switching element T14 is electrically connected to the first node Q, the first terminal of the sixteenth switching element T14 is electrically connected to the first clock signal CLK, and the second terminal of the sixteenth switching element T14 outputs the transmission signal Zn of this stage. The control terminal of the seventeenth switching element T15 is electrically connected to the second terminal of the sixth switching element T8, the control terminal of the eighteenth switching element T16 is electrically connected to the second terminal of the seventh switching element T9, the first terminal of the seventeenth switching element T15 and the first terminal of the eighteenth switching element T16 are both connected to the second level signal VGL, and the second terminal of the seventeenth switching element T15 and the second terminal of the eighteenth switching element T16 are both electrically connected to the transmission signal Zn of this stage. The control terminal of the fourth switching element T1 is connected to the preceding stage transmission signal (e.g., the preceding two stage transmission signal Zn-2), the first terminal of the fourth switching element T1 is connected to the preceding stage drive signal (e.g., the preceding two stage drive signal Gn-2), and the second terminal of the fourth switching element T1 is electrically connected to the first node Q.

[0046] Unlike the previous embodiments, this embodiment adds a signal transmission module. The waveforms of the current-stage transmission signal Zn and the current-stage drive signal Gn are identical, used to control the fourth switching element T1. The advantage of this arrangement is that the current-stage drive signal Gn requires a load for driving, thus its waveform has a delay; the current-stage drive signal Gn does not require a load and has a more standard waveform. Optionally, the size of the sixteenth switching element T14 is smaller than the size of the third switching element T2, which allows for a reduction in the size of the drive unit while ensuring the sixteenth switching element T14 has strong driving capability.

[0047] See also Figure 6 For a drive circuit using this drive unit, four clock signals CLK1, CLK2, CLK3, and CLK4, which are sequentially delayed by one row scan time, are required. The clock signals used by this stage of the drive unit are CLK2, CLK3, and CLK4, and the clock signals used by the next stage of the drive unit are CLK3, CLK4, and CLK1, and so on.

[0048] In other embodiments, the driving circuit may also use six clock signals, with the front-stage driving signal in the driving unit being the first three-stage driving signal Gn-3 and the rear-stage driving signal being the last three-stage driving signal Gn+3; the driving circuit may also use eight clock signals, with the front-stage driving signal in the driving unit being the first four-stage driving signal Gn-4 and the rear-stage driving signal being the last four-stage driving signal Gn+4; the driving circuit may also use ten clock signals, with the front-stage driving signal in the driving unit being the first five-stage driving signal Gn-5 and the rear-stage driving signal being the last five-stage driving signal Gn+5, etc.

[0049] Figure 7 A circuit diagram of another driving unit provided in an embodiment of the present invention. See also Figure 7 Based on the above embodiments, optionally, for the driving circuit using this driving unit, eight clock signals CLK1-CLK8, which are sequentially delayed by one row scan time, are required. The preceding stage driving signal used in the driving unit is the first four stage driving signal Gn-4, and the following stage driving signal is the last four stage driving signal Gn+4. The clock signals used by this stage driving unit are the fourth clock signal CLK1, the first clock signal CLK3, and the second clock signal CLK7.

[0050] In other embodiments, the driving circuit may also use four clock signals, with the front-stage driving signal in the driving unit being the front-stage second-level driving signal Gn-2 and the rear-stage driving signal being the rear-stage second-level driving signal Gn+2; the driving circuit may also use six clock signals, with the front-stage driving signal in the driving unit being the front-stage third-level driving signal Gn-3 and the rear-stage driving signal being the rear-stage third-level driving signal Gn+3; the driving circuit may also use ten clock signals, with the front-stage driving signal in the driving unit being the front-stage fifth-level driving signal Gn-5 and the rear-stage driving signal being the rear-stage fifth-level driving signal Gn+5, etc.

[0051] See also Figure 7 Optionally, the clamping output module 300 includes: a nineteenth switching element T19, a twentieth switching element T20, a twenty-first switching element T21, a twenty-second switching element T22, and a twenty-third switching element T23; Among them, the first terminal of the nineteenth switching element T19, the first terminal of the twentieth switching element T20, the first terminal of the twenty-first switching element T21, and the first terminal of the twenty-second switching element T22 are all connected to the second level signal VGL; Both the control terminal and the first terminal of the 23rd switching element T23 are connected to the sixth-level signal DC; the control terminal of the 21st switching element T21 is electrically connected to the first node Q, and the second terminal of the 21st switching element T21 is electrically connected to the second terminal of the 23rd switching element T23. The control terminals of the twentieth switching element T20 and the twenty-second switching element T22 are both electrically connected to the second terminal of the twenty-third switching element T23. The second terminal of the twentieth switching element T20 is electrically connected to the first node. The second terminal of the twenty-second switching element T22 is electrically connected to the drive signal Gn of this stage. The control terminal of the nineteenth switching element T19 is connected to the fifth clock signal CLK7, and the second terminal of the nineteenth switching element T19 is electrically connected to the driving signal Gn of this stage.

[0052] For example, each switching element is an N-type thin-film transistor, which conducts when its control terminal is high, and the sixth-level signal DC is high. The twenty-third switching element T23 transmits the high-level sixth-level signal DC to the control terminals of the twentieth switching element T20 and the twenty-second switching element T22. During the pre-charge and bootstrap charging phases, the first node Q is high, controlling the twenty-first switching element T21 to conduct. The twenty-first switching element T21 transmits the second-level signal VGL to the control terminals of the twentieth switching element T20 and the twenty-second switching element T22, pulling them down to control the twentieth switching element T20 and the twenty-second switching element T22 to de-energize. Specifically, during the pre-charge phase, the second clock signal CLK7 is high, controlling the nineteenth switching element CLK7 to conduct and outputting the second-level signal VGL, meaning the current stage drive signal Gn remains low; during the bootstrap charging phase, the second clock signal CLK7 is low, controlling the nineteenth switching element CLK7 to de-energize, without affecting the current stage drive signal Gn.

[0053] During the pull-down and output sustain phases, the first node Q is at a low level, controlling the twenty-first switch element T21 to disconnect; the control terminals of the twentieth switch element T20 and the twenty-second switch element T22 are turned on because they are kept at a high level. Specifically, the twentieth switch element T20 transmits the second-level signal VGL to the first node Q, maintaining the low level of the first node Q; the twenty-second switch element T22 transmits the second-level signal VGL to the current stage drive signal Gn, ensuring that the current stage drive signal Gn is at a low level.

[0054] Based on the above embodiments, optionally, in the drive signal output module 200, the number of switching elements electrically connected to the first clock signal CLK2 is at least one; the capacitance value of the first capacitor C2 is equal to the sum of the parasitic capacitances of each switching element electrically connected to the first clock signal CLK2. For example... Figure 6 As shown, the capacitance of the first capacitor C2 is equal to the sum of the parasitic capacitances of the third switching element T2 and the sixteenth switching element T14; Figure 5 and Figure 7 As shown, the capacitance of the first capacitor C2 is equal to the parasitic capacitance of the third switching element T2.

[0055] In this embodiment, the voltage of the first clock signal CLK2 is coupled to the first node Q through the parasitic capacitances of the switching elements electrically connected to it; the voltage of the second clock signal CLK4 is coupled to the first node Q through the first capacitor C2. Furthermore, the high-level voltages of the first clock signal CLK2 and the second clock signal CLK4 are equal, and the low-level voltages of the first clock signal CLK2 and the second clock signal CLK4 are equal. In this embodiment, the capacitance value of the first capacitor C2 is set to be equal to the sum of the parasitic capacitances of the switching elements electrically connected to the first clock signal CLK2, so that the amount of high-level charge coupled to the first node Q is equal to the amount of low-level charge, which is more conducive to maintaining the voltage stability of the first node Q.

[0056] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0057] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A driving circuit, characterized in that, It includes a multi-stage driving unit, each stage driving a corresponding gate line on the display panel; the driving unit includes: The input module includes multiple signal input terminals, and outputs a control signal for the first node based on the voltage signals of the clock signal, the pre-stage drive signal, and the post-stage drive signal connected to the multiple signal input terminals. A drive signal output module is electrically connected to the first node and receives a first clock signal. The drive signal output module outputs a drive signal of this stage according to the control signal of the first node and the first clock signal. A clamping output module is connected between the first node and the drive signal output module. The output signal of the clamping output module is clamped according to the control signal of the first node to stabilize the drive signal of this stage. A noise coupling module is electrically connected to the first node and is connected to a second clock signal and the pre-stage drive signal; wherein the second clock signal and the first clock signal are out of phase, and the second clock signal is used to couple and cancel or reduce the periodic noise of the first clock signal to the first node.

2. The driving circuit according to claim 1, characterized in that, The noise coupling module includes: A coupling unit, wherein the coupling unit is connected between the first node and the second node; A periodic unit, which is electrically connected to the second node and receives the second clock signal and a first level signal, and inputs the second clock signal to the second node under the control of the first level signal; A pull-down unit is electrically connected to the second node and receives the pre-stage drive signal and the second level signal. The second level signal is input to the second node under the control of the pre-stage drive signal.

3. The driving circuit according to claim 2, characterized in that, The coupling unit includes a first capacitor, which is connected between the first node and the second node; And / or, the periodic unit includes a first switching element, the control terminal of the first switching element is connected to the first level signal, the first terminal of the first switching element is connected to the second clock signal, and the second terminal of the first switching element is electrically connected to the second node; And / or, the pull-down unit includes a second switching element, the control terminal of the second switching element is connected to the pre-stage drive signal, the first terminal of the second switching element is connected to the second level signal, and the second terminal of the second switching element is electrically connected to the second node.

4. The driving circuit according to claim 3, characterized in that, In the drive signal output module, the number of switching elements electrically connected to the first clock signal is at least one; The capacitance value of the first capacitor is equal to the sum of the parasitic capacitances of each switching element electrically connected to the first clock signal.

5. The driving circuit according to any one of claims 1-4, characterized in that, The preceding stage drive signal is the preceding N stage drive signal, and the following stage drive signal is the following N stage drive signal, where N≥2; The number of clock signals is positively correlated with the value of N, and the pulse width of the clock signals is positively correlated with the value of N; the clock signals include the clock signal connected to the input module, the first clock signal, and the second clock signal; And / or, the duty cycle of each clock signal is 50%.

6. The driving circuit according to claim 1, characterized in that, The drive signal output module includes: a third switching element and a second capacitor. The control terminal of the third switching element is electrically connected to the first node. The first terminal of the third switching element is connected to the first clock signal, and the second terminal of the third switching element outputs the drive signal of this stage. The first terminal of the second capacitor is electrically connected to the control terminal of the third switching element, and the second terminal of the second capacitor is electrically connected to the second terminal of the third switching element. And / or, the input module includes: a fourth switching element and a fifth switching element, wherein the control terminal and the first terminal of the fourth switching element are both connected to the pre-stage drive signal; or, the control terminal of the fourth switching element is connected to the pre-stage drive signal, the first terminal is connected to a fourth clock signal, and the second terminal of the fourth switching element is electrically connected to the first node; the control terminal of the fifth switching element is connected to the post-stage drive signal, the first terminal of the fifth switching element is connected to a third clock signal, and the second terminal of the fifth switching element is electrically connected to the first node; And / or, the clamping output module includes: a sixth switching element, a seventh switching element, an eighth switching element, a ninth switching element, a tenth switching element, an eleventh switching element, a twelfth switching element, a thirteenth switching element, a fourteenth switching element, and a fifteenth switching element; The control terminal and the first terminal of the sixth switching element are both connected to a third-level signal; the control terminal and the first terminal of the seventh switching element are both connected to a fourth-level signal. The control terminal of the eighth switching element is connected to the third level signal, the first terminal of the eighth switching element is connected to the fifth level signal, and the second terminal of the eighth switching element is electrically connected to the second terminal of the seventh switching element; the control terminal of the ninth switching element is connected to the fourth level signal, the first terminal of the ninth switching element is connected to the fifth level signal, and the second terminal of the ninth switching element is electrically connected to the second terminal of the sixth switching element. The control terminals of the tenth and eleventh switching elements are both electrically connected to the first node. The first terminals of the tenth and eleventh switching elements are both electrically connected to the second terminal of the eighth switching element. The second terminal of the tenth switching element is electrically connected to the second terminal of the sixth switching element. The second terminal of the eleventh switching element is electrically connected to the second terminal of the seventh switching element. The control terminals of the twelfth and thirteenth switching elements are both electrically connected to the second terminal of the sixth switching element. The second terminal of the twelfth switching element and the first terminal of the thirteenth switching element are electrically connected and connected to the fifth level signal. The second terminals of the twelfth and thirteenth switching elements are both electrically connected to the first node. The control terminals of the fourteenth and fifteenth switching elements are both electrically connected to the second terminal of the seventh switching element. The second terminal of the fourteenth switching element and the first terminal of the fifteenth switching element are electrically connected and connected to a second level signal. The second terminals of the fourteenth and fifteenth switching elements are both electrically connected to the driving signal of this stage. The third-level signal and the fourth-level signal are opposite in phase and change periodically, with a period of at least one full-screen scan time.

7. The driving circuit according to claim 6, characterized in that, The drive signal output module further includes a sixteenth switching element; the clamping output module further includes a seventeenth switching element and an eighteenth switching element. The control terminal of the sixteenth switching element is electrically connected to the first node, the first terminal of the sixteenth switching element is electrically connected to the first clock signal, and the second terminal of the sixteenth switching element outputs the signal transmitted at this stage. The control terminal of the seventeenth switching element is electrically connected to the second terminal of the sixth switching element, and the control terminal of the eighteenth switching element is electrically connected to the second terminal of the seventh switching element. The first terminals of the seventeenth and eighteenth switching elements are both connected to the second level signal, and the second terminals of the seventeenth and eighteenth switching elements are both electrically connected to the signal transmitted at this level. The control terminal of the fourth switching element is connected to the pre-stage transmission signal, the first terminal of the fourth switching element is connected to the pre-stage drive signal, and the second terminal of the fourth switching element is electrically connected to the first node.

8. The driving circuit according to claim 1, characterized in that, The clamping output module includes: a nineteenth switching element, a twentieth switching element, a twenty-first switching element, a twenty-second switching element, and a twenty-third switching element; The first terminal of the nineteenth switching element, the first terminal of the twentieth switching element, the first terminal of the twentieth switching element, and the first terminal of the twentieth switching element are all connected to a second level signal. Both the control terminal and the first terminal of the 23rd switching element are connected to a sixth-level signal; the control terminal of the 21st switching element is electrically connected to the first node, and the second terminal of the 21st switching element is electrically connected to the second terminal of the 23rd switching element. The control terminals of the twentieth and twentieth switching elements are both electrically connected to the second terminal of the twentieth switching element, and the second terminal of the twentieth switching element is electrically connected to the first node; the second terminal of the twentieth switching element is electrically connected to the driving signal of this stage. The control terminal of the nineteenth switching element is connected to the fifth clock signal, and the second terminal of the nineteenth switching element is electrically connected to the driving signal of this stage.

9. A display panel, characterized in that, Includes the driving circuit as described in any one of claims 1-8.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

Images