Electronic device

Abstract

The electronic device includes: a display panel including pixels; a panel driver configured to drive the display panel in response to the energization signal; and a power manager configured to apply a power voltage to the panel driver in response to a power voltage start signal, in which the panel driver includes a voltage generator configured to output a first power voltage to the display panel based on the power voltage, in which the voltage generator and the power manager are connected through a voltage line, wherein the voltage generator is configured to output a droop voltage to the voltage line in response to the voltage droop start signal, and wherein the voltage generator is configured to output the droop voltage to the voltage line based on the power voltage output to the voltage line.

Description

Technical Field

[0001] Some aspects of embodiments of this disclosure relate to electronic devices. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, and a drive controller that controls the gate driver and the data driver.

[0003] To reduce power consumption, display devices may not include a power supply circuit for generating the power supply voltage, and an external power supply circuit can generate the power supply voltage. In this case, multiple pixels can directly receive the power supply voltage generated by the external power supply circuit. However, although the external power supply circuit can be relatively efficient, the power supply voltage generated by the external power supply circuit may have ripples.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0005] Some aspects of embodiments of this disclosure relate to electronic devices. For example, some aspects of embodiments of this disclosure relate to electronic devices including display devices.

[0006] Some embodiments include electronic devices that selectively use internal or external power supply voltages.

[0007] According to some embodiments, the electronic device may include: a display panel including pixels; a panel driver configured to drive the display panel in response to an energizing signal; and a power manager configured to apply a power voltage to the panel driver in response to a power voltage initiation signal. According to some embodiments, the panel driver may include a voltage generator configured to output a first power voltage to the display panel based on the power voltage. According to some embodiments, the voltage generator and the power manager may be connected via a voltage line. According to some embodiments, the voltage generator may output a decreasing voltage to the voltage line in response to a voltage decrease initiation signal. According to some embodiments, after outputting the power voltage to the voltage line, the decreasing voltage may be output to the voltage line.

[0008] According to some embodiments, the operation periods of the voltage generator and the power manager may include a first period, a second period, a third period, and a fourth period. According to some embodiments, in the first period, the energizing signal may have an active level, the power voltage initiation signal may have a disabled level, and the voltage drop initiation signal may have a disabled level.

[0009] According to some embodiments, during the second time period, the power voltage initiation signal may have an active level, and the voltage drop initiation signal may have a disabled level.

[0010] According to some embodiments, during the second time period, the power manager can output the power voltage to the voltage line in response to the power voltage start signal.

[0011] According to some embodiments, the panel driver may further include: a gate driver configured to output a scan gate signal and a sense gate signal to the display panel; a data driver configured to apply a data voltage to the display panel; and a drive controller configured to control the gate driver, the data driver, and the voltage generator. During the second time period, the drive controller may perform a first drive operation.

[0012] According to some embodiments, during the third time period, the power voltage initiation signal may have a disabled level, and the voltage drop initiation signal may have an active level.

[0013] According to some embodiments, during the third time period, the voltage generator may output the decreasing voltage to the voltage line in response to the voltage decrease initiation signal.

[0014] According to some embodiments, during the third time period, the power manager may stop outputting the power voltage in response to the power voltage start signal.

[0015] According to some embodiments, the voltage generator may include: a voltage drop circuit configured to output the dropped voltage in response to the voltage drop initiation signal; and a voltage output circuit connected to the voltage line and configured to output the first power voltage.

[0016] According to some embodiments, the panel driver may further include: a gate driver configured to output a scan gate signal and a sense gate signal to the display panel; a data driver configured to apply a data voltage to the display panel; a sense driver configured to perform a sensing operation on the display panel; and a drive controller configured to control the gate driver, the data driver, the sense driver, and the voltage generator. According to some embodiments, the pixel may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode receiving the first electrical voltage; a second transistor configured to apply the data voltage to the first node in response to the scan gate signal; a third transistor configured to connect the second node and a sense line in response to the sense gate signal; and a light-emitting element including a first electrode connected to the second node and a second electrode configured to receive a second electrical voltage.

[0017] According to some embodiments, the electronic device may include: a display panel including pixels; a panel driver configured to drive the display panel in response to an energizing signal; and a power manager configured to apply a power voltage to the panel driver in response to a power voltage initiation signal. According to some embodiments, the panel driver may include a voltage generator configured to output a first power voltage to the display panel based on the power voltage. According to some embodiments, the voltage generator and the power manager may be connected via a voltage line. According to some embodiments, the voltage generator may output a decreasing voltage to the voltage line in response to a voltage decrease initiation signal. According to some embodiments, the voltage generator may output a driving voltage different from the first power voltage and the decreasing voltage based on a blocking signal. According to some embodiments, the decreasing voltage is output to the voltage line after the driving voltage can be output to the voltage line.

[0018] According to some embodiments, the operation periods of the voltage generator and the power manager may include a first period, a second period, a third period, and a fourth period. According to some embodiments, in the first period, the energizing signal may have an active level, the power voltage initiation signal may have a disabled level, the voltage drop initiation signal may have a disabled level, and the blocking signal may have a disabled level.

[0019] According to some embodiments, during the second time period, the power voltage initiation signal may have a disabled level, the voltage drop initiation signal may have a disabled level, and the blocking signal may have an active level.

[0020] According to some embodiments, during the second time period, the driving voltage can be output to the voltage line in response to the blocking signal.

[0021] According to some embodiments, a panel driver may include: a gate driver configured to output a gate signal to the display panel; a data driver configured to apply a data voltage to the display panel; and a drive controller configured to control the gate driver, the data driver, and the voltage generator. According to some embodiments, the gate signal and the data voltage can be generated based on the drive voltage. According to some embodiments, during the second time period, the drive voltage can be applied to the gate driver and the data driver in response to a drive voltage start signal.

[0022] According to some embodiments, during the third time period, the power voltage initiation signal may have a disabled level, the voltage drop initiation signal may have an active level, and the blocking signal may have a disabled level.

[0023] According to some embodiments, during the third time period, the decreasing voltage can be output to the voltage line in response to the voltage decrease initiation signal. During the third time period, the output of the driving voltage can be stopped.

[0024] According to some embodiments, in the fourth time period, the power voltage initiation signal may have an active level, the voltage drop initiation signal may have a disabled level, and the blocking signal may have a disabled level.

[0025] According to some embodiments, during the fourth time period, the power voltage can be output to the voltage line in response to the power voltage initiation signal. During the fourth time period, the output of the voltage drop voltage can be stopped.

[0026] According to some embodiments, the voltage generator may include: a voltage drop circuit configured to output the drop voltage in response to the voltage drop initiation signal; a drive voltage generation circuit configured to output the drive voltage to a voltage blocking circuit in response to the blocking signal; the voltage blocking circuit configured to output the drive voltage to the voltage line in response to the blocking signal; and a voltage output circuit connected to the voltage line and configured to output the first power voltage.

[0027] As described above, the operation period of the voltage generator and power manager may include a pre-charging period. According to some embodiments, during the pre-charging period, the capacitor connected to the voltage line can be charged. Therefore, after the output voltage drops, when the power manager outputs the power voltage to the voltage line, the current applied to the voltage line can be gradually increased. This can relatively improve the display quality of the display panel.

[0028] Furthermore, the operation period of the voltage generator and power manager can include a pre-charging period, allowing the capacitor connected to the voltage line to be in a charging state during the detection period. Therefore, the electronic device may not require circuitry for blocking the connection between the power manager and the voltage generator. This allows for relatively improved integration of the electronic device. Additionally, it allows for relatively reduced power consumption. Attached Figure Description

[0029] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 This is a block diagram illustrating an electronic device according to some embodiments of the present disclosure.

[0031] Figure 2 It is shown Figure 1 A block diagram of an example display device.

[0032] Figure 3 This is a block diagram illustrating an example of a voltage generator and a power manager.

[0033] Figure 4 It shows that it is applied to Figure 3 Timing diagrams of the signals from the voltage generator and power manager.

[0034] Figure 5 It is shown Figure 3 A block diagram illustrating the operation of the voltage generator and power manager during the second time period.

[0035] Figure 6 It is shown Figure 3 A block diagram showing the operation of the voltage generator and power manager in the third time period.

[0036] Figure 7 It is shown Figure 3 A block diagram showing the operation of the voltage generator and power manager in the fourth time period.

[0037] Figure 8 It shows that it is applied to Figure 3 Timing diagrams of the signals for the voltage generator and power manager.

[0038] Figure 9This is a block diagram illustrating an example of a voltage generator and a power manager.

[0039] Figure 10 It shows that it is applied to Figure 9 Timing diagrams of the signals from the voltage generator and power manager.

[0040] Figure 11 It is shown Figure 9 A block diagram illustrating the operation of the voltage generator and power manager during the second time period.

[0041] Figure 12 It is shown Figure 9 A block diagram showing the operation of the voltage generator and power manager in the third time period.

[0042] Figure 13 It is shown Figure 9 A block diagram showing the operation of the voltage generator and power manager in the fourth time period.

[0043] Figure 14 It is shown Figure 9 A circuit diagram of an example voltage blocking circuit.

[0044] Figure 15 It shows that it is applied to Figure 9 Timing diagrams of the signals for the voltage generator and power manager.

[0045] Figure 16 It is shown Figure 2 A circuit diagram of an example pixel.

[0046] Figure 17 This is a block diagram illustrating an electronic device according to some embodiments. Detailed Implementation

[0047] In the following description, aspects of some embodiments of this disclosure will be described in more detail with reference to the accompanying drawings.

[0048] Figure 1 This is a block diagram illustrating an electronic device 1 according to some embodiments of the present disclosure.

[0049] The electronic device 1 may include a display device 10, a power manager 20, and a controller 30.

[0050] Display device 10 may include panel driver 110 and display panel 100. Panel driver 110 may receive input image data IMG and input control signal CONT from controller 30. Panel driver 110 may receive power voltage VO from power manager 20. Panel driver 110 may generate drive signal DS, data voltage VDATA, and first power supply voltage ELVDD based on input image data IMG, input control signal CONT, and power voltage VO. Display panel 100 may display an image based on drive signal DS, data voltage VDATA, and first power supply voltage ELVDD.

[0051] The power manager 20 can receive a power voltage start signal VEN from the controller 30. The power manager 20 can output a power voltage VO in response to the power voltage start signal VEN.

[0052] The controller 30 can control the display device 10 and the power manager 20. The controller 30 can be turned on in response to a power-on signal PO. For example, the controller 30 can perform various computing functions or various tasks. According to some embodiments, the controller 30 can be a microprocessor, a central processing unit (CPU), and an application processor (AP), etc. However, this disclosure is not limited to the type of controller 30. The controller 30 can be coupled to other components via an address bus, a control bus, a data bus, etc. According to some embodiments, the controller 30 can be coupled to an expansion bus (such as a peripheral component interconnect (PCI) bus).

[0053] Figure 2 It is shown Figure 1 A block diagram of an example of a display device 10.

[0054] refer to Figure 1 and Figure 2 The display device 10 may include a display panel 100 and a panel driver 110. The panel driver 110 may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, a sensing driver 600, and a voltage generator 700.

[0055] The display panel 100 may have a display area in which an image is displayed and a peripheral area adjacent to the display area (e.g., outside the display area or outside the coverage area of ​​the display area).

[0056] The display panel 100 may include multiple gate lines GL, multiple data lines DL, multiple sensing lines SL, and multiple pixels PX electrically connected to the gate lines GL, data lines DL, and sensing lines SL. The gate lines GL may extend in a first direction D1. The data lines DL may extend in a second direction D2 intersecting the first direction D1. The sensing lines SL may extend in the second direction D2.

[0057] The drive controller 200 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0058] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, a fifth control signal CONT5, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0059] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0060] The drive controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0061] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0062] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0063] The drive controller 200 can generate a fourth control signal CONT4 for controlling the operation of the sensor driver 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the sensor driver 600.

[0064] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL. For example, the gate signal may include... Figure 16 The scanning gate signal SC and the sensing gate signal SS.

[0065] According to some embodiments, the gate driver 300 may be located in the peripheral region. According to some embodiments, the gate driver 300 may be integrated in the peripheral region.

[0066] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0067] According to some embodiments, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0068] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage VDATA of analog type. The data driver 500 outputs the data voltage VDATA to the data line DL.

[0069] According to some embodiments, the data drive 500 may be located in a peripheral area. According to some embodiments, the data drive 500 may be integrated into the peripheral area.

[0070] The sense driver 600 can receive a fourth control signal CONT4 from the drive controller 200. The sense driver 600 can generate sense data SD by sensing pixel PX via sense line SL. For example, the sense driver 600 can sense the drive characteristics (e.g., mobility and / or threshold voltage) of the drive transistor of pixel PX by measuring the sense current (or sense voltage) of the drive transistor of pixel PX via sense line SL. For example, the operation of sensing the drive characteristics (e.g., mobility and / or threshold voltage) of the drive transistor can be referred to as a sensing operation.

[0071] According to some embodiments, the sense driver 600 may be implemented as an integrated circuit separate from the integrated circuit of the data driver 500. According to some embodiments, the sense driver 600 may be included in the data driver 500 or may be included in the drive controller 200.

[0072] Voltage generator 700 can generate a power supply voltage in response to a fifth control signal CONT5 received from drive controller 200. Voltage generator 700 can generate a power supply voltage based on the power voltage VO. For example, the power supply voltage may include... Figure 16 The first power supply voltage ELVDD, the second power supply voltage ELVSS and Figure 9 The driving voltage DV. For example, it can be based on... Figure 9 The driving voltage DV is used to generate the voltage for driving the display panel 100 (e.g., the data voltage VDATA and the activation and deactivation levels of the gate signal, etc.). The fifth control signal CONT5 may include... Figure 15 The voltage drop start signal LEN and the blocking signal BEN.

[0073] Figure 3 This is a block diagram illustrating an example of a voltage generator 700 and a power manager 20. Figure 4 It shows that it is applied to Figure 3 Timing diagram of the signals of voltage generator 700 and power manager 20. Figure 5 It is shown Figure 3 A block diagram of the operation of the voltage generator 700 and the power manager 20 in the second time period TP2A. Figure 6 It is shown Figure 3 A block diagram of the operation of the voltage generator 700 and the power manager 20 in the third time period TP3A. Figure 7 It is shown Figure 3 A block diagram of the operation of the voltage generator 700 and the power manager 20 in the fourth period TP4A.

[0074] refer to Figures 1 to 7 The voltage generator 700 may include a voltage reduction circuit 710 and a voltage output circuit 730. The voltage generator 700 and the power manager 20 can be connected via a voltage line VOL.

[0075] The voltage drop circuit 710 can generate a dropped voltage LV in response to the voltage drop start signal LEN. The voltage drop circuit 710 can output the dropped voltage LV to the voltage line VOL in response to the voltage drop start signal LEN.

[0076] For example, the voltage drop circuit 710 may include a reference voltage generator that generates a reference voltage and a voltage drop regulator that performs a voltage drop regulation operation on the reference voltage to generate a dropped voltage LV. However, this disclosure is not limited to the structure of the voltage drop circuit 710. Additionally, the voltage drop circuit 710 can provide the dropped voltage LV to multiple pixels PX via a voltage line VOL. According to some embodiments, the voltage drop circuit 710 may also include an overcurrent protection (“OCP”) circuit 711 that performs an overcurrent detection operation to determine whether the current flowing through the voltage line VOL is greater than or equal to a reference current. Compared to the power manager 20, the voltage drop circuit 710 performing the voltage drop regulation operation may have a relatively low power conversion efficiency, but the dropped voltage LV generated by the voltage drop circuit 710 may have a relatively small ripple compared to the power voltage VO generated by the power manager 20.

[0077] The voltage output circuit 730 can output the voltage received from the voltage line VOL as a first power supply voltage ELVDD. For example, the voltage output circuit 730 may include a line for outputting the first power supply voltage ELVDD. For example, the voltage output circuit 730 may be configured as the voltage line VOL.

[0078] Power manager 20 can output power voltage VO to voltage line VOL in response to power voltage start signal VEN. According to some embodiments, power manager 20 can be implemented as a switch-mode power supply (“SMPS”) circuit with relatively high power conversion efficiency compared to voltage drop circuit 710. The power voltage VO generated by power manager 20 may have relatively large ripple compared to the drop voltage LV generated by voltage drop circuit 710.

[0079] The operating periods of the voltage generator 700 and the power manager 20 may include a first period TP1A, a second period TP2A, a third period TP3A, and a fourth period TP4A.

[0080] In the first time period TP1A, the energizing signal PO can have an active level, the voltage drop initiation signal LEN can have a disabled level, and the power voltage initiation signal VEN can have a disabled level. For example, the first time period TP1A can be referred to as the energizing period.

[0081] In the second period TP2A following the first period TP1A, the energizing signal PO can have an active level, the voltage drop initiation signal LEN can have a disabled level, and the power voltage initiation signal VEN can have an active level. For example, the second period TP2A can be referred to as the pre-charging period.

[0082] In the second time period TP2A, the power voltage initiation signal VEN can have an active level. The power manager 20 can output the power voltage VO to the voltage line VOL in response to the power voltage initiation signal VEN. Therefore, the capacitor connected to the voltage line VOL can be charged.

[0083] In the third period TP3A following the second period TP2A, the energizing signal PO can have an active level, the voltage drop initiation signal LEN can have an active level, and the power voltage initiation signal VEN can have a disabled level. For example, the third period TP3A can be referred to as the detection period.

[0084] In the third time period TP3A, the voltage drop circuit 710 can output the dropped voltage LV to the voltage line VOL in response to the voltage drop start signal LEN. Additionally, the OCP circuit 711 can perform an overcurrent detection operation to determine whether the current flowing through the voltage line VOL is greater than or equal to a reference current. The power voltage VO may not be supplied to the voltage line VOL, and abnormal events of the display panel 100 (such as overcurrent in the display panel 100) can be detected. In the third time period TP3A, the power manager 20 can stop outputting the power voltage VO in response to the power voltage start signal VEN.

[0085] During the third time period TP3A, the capacitor on the voltage line VOL can be in a charging state. Therefore, the accuracy of overcurrent detection operation can be relatively improved.

[0086] In the fourth period TP4A following the third period TP3A, the energizing signal PO can have an active level, the voltage drop initiation signal LEN can have a disabled level, and the power voltage initiation signal VEN can have an active level. For example, the fourth period TP4A can be referred to as the voltage application period.

[0087] In the fourth period TP4A, the power manager 20 can output the power voltage VO to the voltage line VOL. In the fourth period TP4A, the voltage drop circuit 710 can stop outputting the drop voltage LV. In the fourth period TP4A, the capacitor of the voltage line VOL can be in a charging state. Therefore, the current applied to the voltage line VOL can gradually increase. For example, the inrush current can be reduced. Therefore, the display quality of the display panel 100 can be relatively improved.

[0088] Compared to the power manager 20, the voltage drop circuit 710 may have relatively low power conversion efficiency. When the power voltage VO is applied to the voltage line VOL without a pre-charging period, the charging efficiency of the capacitor connected to the voltage line VOL may decrease. Therefore, when the power manager 20 outputs the power voltage VO, the current applied to the voltage line VOL may suddenly increase. Consequently, the display quality of the display panel 100 may deteriorate.

[0089] According to some embodiments, the operation period of the voltage generator 700 and the power manager 20 may include a pre-charging period. During the pre-charging period, the capacitor connected to the voltage line VOL can be charged. Therefore, when the power manager 20 outputs the power voltage VO to the voltage line VOL after the output voltage drop LV, the current applied to the voltage line VOL can gradually increase. Therefore, the display quality of the display panel 100 can be relatively improved.

[0090] Furthermore, according to some embodiments, the operation period of the voltage generator 700 and the power manager 20 may include a pre-charging period, allowing the capacitor connected to the voltage line VOL to be in a charging state during the detection period. Therefore, the electronic device 1 may not include circuitry for blocking the connection between the power manager 20 and the voltage generator 700. This can relatively improve the integration of the electronic device 1. Additionally, the power consumption of the electronic device 1 can be reduced.

[0091] Figure 8 It shows that it is applied to Figure 3 Timing diagrams of the signals of voltage generator 700 and power manager 20.

[0092] refer to Figures 1 to 8 During the second time period TP2A, the drive controller 200 can execute the first drive operation OP1. For example, the memory circuit MEM included in the drive controller 200 can execute the first drive operation OP1. For example, the first drive operation OP1 can be an operation to load a lookup table. However, this disclosure is not limited to the type of the first drive operation OP1. For example, the time period in which the first drive operation OP1 is executed and the pre-charge time period can be synchronized. For example, the pre-charge time period can begin during the time period in which the first drive operation OP1 is executed.

[0093] In the third time period TP3A, the drive controller 200 may execute the second drive operation OP2. For example, the memory circuit MEM included in the drive controller 200 may execute the second drive operation OP2. For example, the second drive operation OP2 may be an operation to load compensation data. However, this disclosure is not limited to the type of the second drive operation OP2. For example, the precharge period may end during the time period in which the second drive operation OP2 is executed.

[0094] Figure 9 This is a block diagram illustrating an example of a voltage generator 700 and a power manager 20. Figure 10 It shows that it is applied to Figure 9 Timing diagram of the signals of voltage generator 700 and power manager 20. Figure 11 It is shown Figure 9 A block diagram of the operation of the voltage generator 700 and the power manager 20 in the second time period TP2B. Figure 12 It is shown Figure 9 A block diagram of the operation of the voltage generator 700 and the power manager 20 in the third time period TP3B. Figure 13 It is shown Figure 9 A block diagram of the operation of the voltage generator 700 and the power manager 20 in the fourth time period TP4B.

[0095] refer to Figure 1 , Figure 2 as well as Figures 9 to 13 The voltage generator 700 may include a voltage reduction circuit 710, a drive voltage generation circuit 720, a voltage output circuit 730, and a voltage blocking circuit 750. The voltage generator 700 and the power manager 20 can be connected via a voltage line VOL.

[0096] Apart from Figure 9 In addition to the voltage generator 700, the voltage generator 700 also includes a drive voltage generation circuit 720 and a voltage blocking circuit 750. Figure 9 Voltage generator 700 and Figure 3 The voltage generator 700 is the same (or substantially the same) as the voltage generator, and therefore the same reference numerals will be used, and some repeated descriptions of the above-mentioned components may be omitted.

[0097] The drive voltage generation circuit 720 can generate a drive voltage DV. The drive voltage generation circuit 720 can output the drive voltage DV to the voltage line VOL in response to the blocking signal BEN (e.g., output the drive voltage DV to the voltage blocking circuit 750).

[0098] The voltage blocking circuit 750 can apply a drive voltage DV to the voltage line VOL in response to the blocking signal BEN. For example, the voltage blocking circuit 750 can selectively apply the drive voltage DV to the voltage line VOL in response to the blocking signal BEN.

[0099] The operating periods of the voltage generator 700 and the power manager 20 may include a first period TP1B, a second period TP2B, a third period TP3B, and a fourth period TP4B.

[0100] In the first time period TP1B, the energizing signal PO can have an active level, the voltage drop initiation signal LEN can have an inactive level, the power voltage initiation signal VEN can have an inactive level, and the blocking signal BEN can have an inactive level. For example, the first time period TP1B can be referred to as the energizing period.

[0101] In the second period TP2B following the first period TP1B, the energizing signal PO can have an active level, the voltage drop initiation signal LEN can have a disabled level, the power voltage initiation signal VEN can have an active level, and the blocking signal BEN can have an active level. For example, the second period TP2B can be referred to as the pre-charging period.

[0102] In the second time period TP2B, the blocking signal BEN can have an active level. The drive voltage generation circuit 720 can output a drive voltage DV in response to the blocking signal BEN. The voltage blocking circuit 750 can output the drive voltage DV to the voltage line VOL in response to the blocking signal BEN. Therefore, the capacitor connected to the voltage line VOL can be charged.

[0103] In the third time period TP3B following the second time period TP2B, the energizing signal PO can have an active level, the voltage drop initiation signal LEN can have an active level, the power voltage initiation signal VEN can have a disabled level, and the blocking signal BEN can have a disabled level. For example, the third time period TP3B can be referred to as the detection period.

[0104] In the third time period TP3B, the voltage drop circuit 710 can output the dropped voltage LV to the voltage line VOL in response to the voltage drop start signal LEN. Additionally, the OCP circuit 711 can perform an overcurrent detection operation to determine whether the current flowing through the voltage line VOL is greater than or equal to a reference current. The power voltage VO may not be supplied to the voltage line VOL, and abnormal events of the display panel 100 (such as overcurrent in the display panel 100) can be detected. In the third time period TP3B, the power manager 20 can stop outputting the power voltage VO in response to the power voltage start signal VEN.

[0105] In the third time period TP3B, the capacitor on the voltage line VOL can be charged by the drive voltage DV. Therefore, the accuracy of overcurrent detection operation can be improved relatively.

[0106] In the fourth period TP4B following the third period TP3B, the energizing signal PO can have an active level, the voltage drop initiation signal LEN can have a disabled level, the power voltage initiation signal VEN can have an active level, and the blocking signal BEN can have a disabled level. For example, the fourth period TP4B can be referred to as the voltage application period. In the fourth period TP4B, the output voltage drop LV can be stopped. In the fourth period TP4B, the power voltage VO can be output to the voltage line VOL.

[0107] In the fourth time period TP4B, the capacitor of voltage line VOL can be in a charging state. Therefore, the current applied to voltage line VOL can gradually increase. For example, the inrush current can be reduced. Therefore, the display quality of display panel 100 can be relatively improved.

[0108] Compared to the power manager 20, the voltage drop circuit 710 may have relatively low power conversion efficiency. When the power voltage VO is applied to the voltage line VOL without a pre-charging period, the charging efficiency of the capacitor connected to the voltage line VOL may decrease. Therefore, when the power manager 20 outputs the power voltage VO, the current applied to the voltage line VOL may suddenly increase. Consequently, the display quality of the display panel 100 may deteriorate.

[0109] According to some embodiments, the operation period of the voltage generator 700 and the power manager 20 may include a pre-charging period. During the pre-charging period, the capacitor connected to the voltage line VOL can be charged. Therefore, when the power manager 20 outputs the power voltage VO to the voltage line VOL after the output voltage drop LV, the current applied to the voltage line VOL can gradually increase. Therefore, the display quality of the display panel 100 can be relatively improved.

[0110] Figure 14 It is shown Figure 9 A circuit diagram of an example of a voltage blocking circuit 750.

[0111] refer to Figure 1 , Figure 2 as well as Figures 9 to 14 The voltage blocking circuit 750 may include a first transistor BT1, a second transistor BT2, a capacitor C, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0112] A first transistor BT1 can be connected between the voltage line VOL and the drive voltage generation circuit 720. When the first transistor BT1 is turned on, it applies the drive voltage DV generated by the drive voltage generation circuit 720 to the voltage line VOL. When the first transistor BT1 is turned off, it blocks the application of the drive voltage DV to the voltage line VOL. According to some embodiments, the first transistor BT1 may include a control electrode (e.g., gate) connected to the second resistor R2, a first electrode (e.g., source) connected to the drive voltage generation circuit 720, and a second electrode (e.g., drain) connected to the voltage line VOL.

[0113] Capacitor C can be connected between the second electrode of the first transistor BT1 and the second resistor R2, and a third resistor R3 can be connected in parallel with capacitor C between the second electrode of the first transistor BT1 and the second resistor R2. For example, capacitor C and the third resistor R3 can be connected in parallel between the gate and drain of the first transistor BT1.

[0114] The second transistor BT2 can selectively turn on the first transistor BT1 in response to the blocking signal BEN. According to some embodiments, the second transistor BT2 may include a control electrode (e.g., base) that receives the blocking signal BEN through a first resistor R1, a first electrode (e.g., collector) connected to a second resistor R2, and a second electrode (e.g., emitter) that receives a ground voltage through a fourth resistor R4.

[0115] The first resistor R1 may include a first terminal for receiving the blocking signal BEN and a second terminal connected to the control electrode of the second transistor BT2. Therefore, the current corresponding to the blocking signal BEN can be supplied to the control electrode of the second transistor BT2 through the first resistor R1. Furthermore, the second resistor R2 may be connected between the first electrode of the second transistor BT2 and the control electrode of the first transistor BT1, and the fourth resistor R4 may be connected between the second electrode of the second transistor BT2 and the ground voltage.

[0116] According to some embodiments, the first transistor BT1 may be a P-type metal-oxide-semiconductor (“PMOS”) transistor and the second transistor BT2 may be an N-type bipolar junction transistor (“BJT”), but is not limited thereto.

[0117] Figure 15 It shows that it is applied to Figure 9 Timing diagrams of the signals of voltage generator 700 and power manager 20.

[0118] refer to Figure 1 , Figure 2 , Figures 9 to 13 as well as Figure 15During the first period TP1B, the drive controller 200 can output a drive voltage start signal DVS. The voltage generator 700 can output a drive voltage DV in response to the drive voltage start signal DVS. For example, the voltage generator 700 can output the drive voltage DV to the gate driver 300 and the data driver 500. During the pre-charge period, the drive voltage start signal DVS can remain at an active level. Therefore, during the pre-charge period, the voltage generator 700 can output the drive voltage DV in response to the drive voltage start signal DVS.

[0119] Figure 16 It is shown Figure 2 A circuit diagram of an example pixel PX.

[0120] refer to Figure 1 , Figure 2 and Figure 16 A pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor CST, and a light-emitting element EE. For example, a pixel PX may have a 3T-1C structure. However, this disclosure is not limited to the structure of the pixel PX.

[0121] The first transistor T1 may include a control electrode connected to the first node N1, a first electrode receiving a first power supply voltage ELVDD, and a second electrode connected to the second node N2. The first transistor T1 may generate a drive current based on the voltage of the first node N1. For example, the first transistor T1 may be referred to as a drive transistor.

[0122] The second transistor T2 may include a control electrode that receives a scan gate signal SC, a first electrode that receives a data voltage VDATA, and a second electrode connected to the first node N1. The second transistor T2 may apply the data voltage VDATA to the first node N1 in response to the scan gate signal SC. For example, the second transistor T2 may be referred to as a write transistor.

[0123] The third transistor T3 may include a control electrode that receives a sensing gate signal SS, a first electrode connected to a sensing line SL, and a second electrode connected to a second node N2. The third transistor T3 may connect the sensing line SL and the second node N2 in response to the sensing gate signal SS. For example, the third transistor T3 may be referred to as a sensing transistor.

[0124] The storage capacitor CST may include a first electrode connected to a first node N1 and a second electrode connected to a second node N2.

[0125] The light-emitting element EE may include a first electrode connected to the second node N2 and a second electrode receiving a second power supply voltage ELVSS. The light-emitting element EE may emit light based on a drive current.

[0126] Figure 17 This is a block diagram illustrating an electronic device 2101 according to some embodiments.

[0127] refer to Figures 1 to 17 The electronic device 2101 can output various information via the display module 2140 in the operating system. When the processor 2110 executes the application stored in the memory 2120, the display module 2140 can provide application information to the user via the display panel 2141.

[0128] Processor 2110 can obtain external input via input module 2130 or sensor module 2161, and can execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 2141, processor 2110 can obtain user input via input sensor 2161-2 and activate camera module 2171. Processor 2110 can transmit image data corresponding to the image captured by camera module 2171 to display module 2140. Display module 2140 can display the image corresponding to the captured image via display panel 2141.

[0129] As another example, when personal information authentication is performed in display module 2140, fingerprint sensor 2161-1 can obtain input fingerprint information as input data. Processor 2110 can compare the input data obtained by fingerprint sensor 2161-1 with authentication data stored in memory 2120, and can execute the application based on the comparison result. Display module 2140 can display the information executed according to the application logic via display panel 2141.

[0130] As another example, when a music stream icon is selected to be displayed in display module 2140, processor 2110 obtains user input via input sensor 2161-2 and can activate the music stream application stored in memory 2120. When a music execution command is entered in the music stream application, processor 2110 can activate sound output module 2163 to provide the user with sound information corresponding to the music execution command.

[0131] The operation of electronic device 2101 has been briefly described above. The configuration of electronic device 2101 will be described in detail below. Some components of electronic device 2101 described later may be integrated and configured as a single component, or a single component may be separately configured as two or more components.

[0132] Electronic device 2101 can communicate with external electronic device 2102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to some embodiments, electronic device 2101 may include a processor 2110, a memory 2120, an input module 2130, a display module 2140, a power management module 2150, an internal module 2160, and an external module 2170. According to some embodiments, at least one component may be omitted from electronic device 2101, or one or more other components may be added to electronic device 2101. According to some embodiments, some components (e.g., sensor module 2161, antenna module 2162, or voice output module 2163) may be implemented as a single component (e.g., display module 2140).

[0133] Processor 2110 can execute software to control at least one other component (e.g., hardware or software component) of electronic device 2101 coupled to processor 2110, and can perform various data processing or calculations. According to some embodiments, as at least part of data processing or calculation, processor 2110 can store commands or data received from another component (e.g., input module 2130, sensor module 2161, or communication module 2173) in volatile memory 2121, can process commands or data stored in volatile memory 2121, and can store result data in non-volatile memory 2122.

[0134] Processor 2110 may include a main processor 2111 and an auxiliary processor 2112. Main processor 2111 may include one or more of a central processing unit (CPU) 2111-1 and an application processor (AP). Main processor 2111 may also include one or more of a graphics processing unit (GPU) 2111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 2111 may also include a neural processing unit (NPU) 2111-3. NPU 2111-3 may be a processor specifically designed to process artificial intelligence models, and these models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks (artificial neural networks). The artificial neural networks may be, but are not limited to, deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), deep Q-networks, or combinations of two or more of these. Additionally or optionally, the artificial intelligence model may include software structures in addition to hardware structures. At least two of the aforementioned processing units and processors can be implemented as integrated components (e.g., a single chip), or the corresponding processing units and processors can be implemented as independent components (e.g., multiple chips).

[0135] The auxiliary processor 2112 may include a controller. The controller may include interface conversion circuitry and timing control circuitry. The controller can receive image signals from the main processor 2111, convert the data format of the image signals to meet the interface specifications with the display module 2140, and output image data. The controller can output various control signals required to drive the display module 2140.

[0136] The auxiliary processor 2112 may also include a data conversion circuit 2112-2, a gamma correction circuit 2112-3, or a rendering circuit 2112-4, etc. The data conversion circuit 2112-2 can receive image data from the controller. The data conversion circuit 2112-2 can compensate the image data to display an image at a desired brightness according to the characteristics of the electronic device 2101 or user settings, or it can convert the image data to reduce power consumption or eliminate afterimages. The gamma correction circuit 2112-3 can convert the image data or gamma reference voltage so that the image displayed in the electronic device 2101 has desired gamma characteristics. The rendering circuit 2112-4 can receive image data from the controller and can render the image data taking into account the pixel arrangement of the display panel 2141 in the electronic device 2101. At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 can be integrated into another component (e.g., the main processor 2111 or the controller). At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 can be integrated into the data driver 2143 described later.

[0137] Memory 2120 may store various data used by at least one component of electronic device 2101 (e.g., processor 2110 or sensor module 2161). The various data may include, for example, input or output data for commands associated with it. Memory 2120 may include at least one of volatile memory 2121 and non-volatile memory 2122.

[0138] The input module 2130 can receive commands or data from outside the electronic device 2101 (e.g., a user or external electronic device 2102) that will be used by components of the electronic device 2101 (e.g., processor 2110, sensor module 2161, or sound output module 2163).

[0139] Input module 2130 may include a first input module 2131 for receiving commands or data from a user and a second input module 2132 for receiving commands or data from an external electronic device 2102. The first input module 2131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 2132 may support a specified protocol that enables the electronic device 2101 to be connected to the external electronic device 2102 via wired or wireless means. According to some embodiments, the second input module 2132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 2132 may include a connector that allows the electronic device 2101 to be physically connected to the external electronic device 2102. For example, the second input module 2132 may include an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0140] Display module 2140 can visually provide information to the user. Display module 2140 may include display panel 2141, scan driver 2142, and data driver 2143. Display module 2140 may also include a window, base, and bracket for protecting display panel 2141.

[0141] Display panel 2141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, but the type of display panel 2141 is not limited to these. Display panel 2141 may be a rigid type of display panel or a flexible type of display panel that can be rolled or folded. Display module 2140 may also include a support member, bracket, or heat dissipation member that supports display panel 2141.

[0142] The scan driver 2142 can be mounted as a driver chip in the display panel 2141. Optionally, the scan driver 2142 can be integrated into the display panel 2141. For example, the scan driver 2142 may include an amorphous silicon thin-film transistor (TFT) gate driver (ASG) circuit, a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver (OSG) circuit embedded in the display panel 2141. The scan driver 2142 can receive control signals from the controller and can output scan signals to the display panel 2141 in response to the control signals.

[0143] The display panel 2141 may also include a transmitter driver. The transmitter driver can output a transmitter control signal to the display panel 2141 in response to a control signal received from the controller. The transmitter driver may be formed independently of the scan driver 2142, or it may be integrated into the scan driver 2142.

[0144] The data driver 2143 can receive control signals from the controller, can convert image data into analog voltages (e.g., data voltages) in response to the control signals, and can then output the data voltages to the display panel 2141.

[0145] The data driver 2143 can be incorporated into other components (e.g., a controller). Furthermore, the functions of the interface conversion circuitry and timing control circuitry of the aforementioned controller can be integrated into the data driver 2143.

[0146] The display module 2140 may also include a voltage generator circuit, etc. The voltage generator circuit can output various voltages for driving the display panel 2141.

[0147] Power management module 2150 can supply power to components of electronic device 2101. Power management module 2150 may include a battery charged with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power management module 2150 may include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the modules described above and later. Power management module 2150 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0148] The electronic device 2101 may also include an internal module 2160 and an external module 2170. The internal module 2160 may include a sensor module 2161, an antenna module 2162, and a sound output module 2163. The external module 2170 may include a camera module 2171, an optical module 2172, and a communication module 2173.

[0149] Sensor module 2161 can detect input through the user's body or through the pen of the first input module 2131, and can generate an electrical signal or data value corresponding to the input. Sensor module 2161 may include at least one of fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3.

[0150] The fingerprint sensor 2161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 2161-1 can include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0151] Input sensor 2161-2 can generate data values ​​corresponding to the coordinate information of user body input or pen input. Input sensor 2161-2 can convert capacitance changes caused by input into data values. Input sensor 2161-2 can detect input through a passive pen, or can send data to / receive data from an active pen.

[0152] Input sensor 2161-2 can measure biosignals (such as blood pressure, water content, or body fat). For example, when a part of a user's body touches the sensor layer or sensing panel and remains stationary for a specific period of time, input sensor 2161-2 can detect the biosignal based on changes in the electric field caused by the part of the body and output the user's desired information to display module 2140.

[0153] The digitizer 2161-3 can generate data values ​​corresponding to coordinate information input via a pen. The digitizer 2161-3 can convert electromagnetic changes caused by the input into data values. The digitizer 2161-3 can detect input via a passive pen, or can send data to / receive data from an active pen.

[0154] At least one of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be implemented as a sensor layer formed on the display panel 2141 by a continuous process. The fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be located above the display panel 2141, or at least one of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be located below the display panel 2141.

[0155] Two or more of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be integrated into a single sensing panel using the same process. When integrated into a single sensing panel, the sensing panel can be located between the display panel 2141 and a window located above the display panel 2141. According to some embodiments, the sensing panel can be located on the window, but the location of the sensing panel is not limited thereto.

[0156] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be embedded in the display panel 2141. In other words, at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 2141.

[0157] Furthermore, sensor module 2161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 2101. Sensor module 2161 may also include, for example, gesture sensors, gyroscope sensors, atmospheric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0158] Antenna module 2162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. According to some embodiments, communication module 2173 may transmit or receive signals to or from external electronic device 2102 via an antenna suitable for a communication method. The antenna pattern of antenna module 2162 may be integrated into a component of display module 2140 (e.g., display panel 2141) or into input sensors 2161-2.

[0159] The sound output module 2163 can output sound signals to the outside of the electronic device 2101. The sound output module 2163 may include, for example, a speaker or a receiver. The speaker can be used for general purposes (such as playing multimedia or playing recordings). The receiver can be used to receive incoming calls. According to some embodiments, the receiver can be implemented separately from the speaker or as part of the speaker. The sound output pattern of the sound output module 2163 can be integrated into the display module 2140.

[0160] Camera module 2171 can capture still images and moving images. According to some embodiments, camera module 2171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 2171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0161] The optical module 2172 can provide light. The optical module 2172 may include a light-emitting diode or a xenon lamp. The optical module 2172 can operate in conjunction with the camera module 2171, or it can operate independently of the camera module 2171.

[0162] Communication module 2173 can support the establishment of a wired or wireless communication channel between electronic device 2101 and external electronic device 2102, and perform communication via the established communication channel. Communication module 2173 may include a wireless communication module (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). Communication module 2173 can communicate via a short-range communication network (e.g., The external electronic device 2102 communicates with a Wi-Fi Direct or Infrared Data Association (IrDA) or long-range communication network (e.g., cellular network, Internet, or computer network (e.g., LAN or WAN)). These various types of communication modules 2173 can be implemented as a single chip or as multiple chips that are separate from each other.

[0163] Input module 2130, sensor module 2161 and camera module 2171, etc., can be used in conjunction with processor 2110 to control the operation of display module 2140.

[0164] The processor 2110 can output commands or data to the display module 2140, the sound output module 2163, the camera module 2171, or the optical module 2172 based on the input data received from the input module 2130. For example, the processor 2110 can generate image data corresponding to the input data applied by a mouse or an active pen, and can output the image data to the display module 2140. Optionally, the processor 2110 can generate command data corresponding to the input data, and can output the command data to the camera module 2171 or the optical module 2172. When no input data is received from the input module 2130 for a certain period of time, the processor 2110 can switch the operating mode of the electronic device 2101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 2101.

[0165] Processor 2110 can output commands or data to display module 2140, sound output module 2163, camera module 2171, or optical module 2172 based on sensing data received from sensor module 2161. For example, processor 2110 can compare authentication data applied by fingerprint sensor 2161-1 with authentication data stored in memory 2120, and then execute an application based on the comparison result. Processor 2110 can execute commands or output corresponding image data to display module 2140 based on sensing data sensed by input sensor 2161-2 or digitizer 2161-3. If sensor module 2161 includes a temperature sensor, processor 2110 can receive temperature data from sensor module 2161 and can also perform brightness correction on image data based on the temperature data.

[0166] Processor 2110 can receive measurement data from camera module 2171 regarding the presence or absence of a user, the user's position, and the user's gaze. Processor 2110 can also perform brightness correction on image data based on the measurement data. For example, after processor 2110 determines the presence or absence of a user based on input from camera module 2171, data conversion circuit 2112-2 or gamma correction circuit 2112-3 can perform brightness correction on the image data, and processor 2110 can provide the brightness-corrected image data to display module 2140.

[0167] At least some of the aforementioned components can be coupled to each other and transmit signals (e.g., commands or data) between them via inter-peripheral communication schemes (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or ultrapath interconnect (UPI)). Processor 2110 can communicate with display module 2140 via a pre-defined interface. Furthermore, any of the aforementioned communication methods can be used between processor 2110 and display module 2140, but the communication methods between processor 2110 and display module 2140 are not limited to those described above.

[0168] The electronic device 2101 according to the various embodiments described above can be of various types. For example, the electronic device 2101 may include at least one of portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. However, the electronic device 2101 according to some embodiments is not limited to the devices described above.

[0169] The display device according to the embodiments can be applied to display devices including computers (e.g., laptop computers), mobile phones, smartphones, smart tablets, portable multimedia players (PMPs), personal digital assistants (PDAs), or Motion Picture Experts Compression Standard Audio Layer 3 (MP3) players.

[0170] The foregoing is a description of some embodiments of this disclosure and should not be construed as limiting it. Although aspects of some embodiments of this disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the embodiments without substantially departing from the novel teachings and characteristics of the embodiments according to this disclosure. Therefore, all such modifications are intended to be included within the scope of the embodiments according to this disclosure as defined in the appended claims and their equivalents. In the claims, the means plus function clause is intended to cover the structures described herein that perform the functions, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is a description of some embodiments of this disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims and their equivalents. Embodiments according to this disclosure are defined by the appended claims and their equivalents included therein.

Claims

1. An electronic device, wherein, The electronic device includes: Display panel, including pixels; A panel driver is configured to drive the display panel in response to an energizing signal; and The power manager is configured to apply a power voltage to the panel driver in response to a power voltage initiation signal. The panel driver includes a voltage generator configured to output a first power voltage to the display panel based on the power voltage. The voltage generator and the power manager are connected via voltage lines. The voltage generator is configured to output a decreasing voltage to the voltage line in response to a voltage decrease initiation signal, and Wherein, based on the power voltage being output to the voltage line, the voltage generator is configured to output the dropped voltage to the voltage line.

2. The electronic device according to claim 1, wherein, The voltage generator and the power manager operate during four time periods: a first time period, a second time period, a third time period, and a fourth time period. During the first time period, the energizing signal has an active level, the power voltage initiation signal has a disabled level, and the voltage drop initiation signal has a disabled level.

3. The electronic device according to claim 2, wherein, During the second time period, the power voltage initiation signal has an active level, and the voltage drop initiation signal has a disabled level.

4. The electronic device according to claim 3, wherein, During the second time period, the power manager is configured to output the power voltage to the voltage line in response to the power voltage initiation signal.

5. The electronic device according to claim 3, wherein, The panel driver also includes: A gate driver is configured to output a scan gate signal and a sense gate signal to the display panel; A data driver is configured to apply a data voltage to the display panel; and A drive controller is configured to control the gate driver, the data driver, and the voltage generator, and During the second time period, the drive controller performs the first drive operation.

6. The electronic device according to claim 3, wherein, During the third time period, the power voltage initiation signal has a disabled level, and the voltage drop initiation signal has an active level.

7. The electronic device according to claim 5, wherein, During the third time period, the voltage generator is configured to output the dropped voltage to the voltage line in response to the voltage drop initiation signal.

8. The electronic device according to claim 7, wherein, During the third time period, the power manager is configured to stop outputting the power voltage in response to the power voltage start signal.

9. The electronic device according to claim 1, wherein, The voltage generator includes: A voltage drop circuit is configured to output the dropped voltage in response to the voltage drop initiation signal; and A voltage output circuit is connected to the voltage line, and the voltage output circuit is configured to output the first power voltage.

10. The electronic device according to claim 1, wherein, The panel driver also includes: A gate driver is configured to output a scan gate signal and a sense gate signal to the display panel; A data driver is configured to apply a data voltage to the display panel; A sensor driver is configured to perform a sensing operation on the display panel; and A drive controller is configured to control the gate driver, the data driver, the sense driver, and the voltage generator, and The pixels include: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode that receives the first power voltage. The second transistor is configured to apply the data voltage to the first node in response to the scan gate signal; A third transistor is configured to connect the second node and the sensing line in response to the sensing gate signal; and The light-emitting element includes a first electrode connected to the second node and a second electrode configured to receive a second electrical voltage.

11. An electronic device, wherein, The electronic device includes: Display panel, including pixels; A panel driver is configured to drive the display panel in response to an energizing signal; and The power manager is configured to apply a power voltage to the panel driver in response to a power voltage initiation signal. The panel driver includes a voltage generator configured to output a first power voltage to the display panel based on the power voltage. The voltage generator and the power manager are connected via voltage lines. The voltage generator is configured to output a decreasing voltage to the voltage line in response to a voltage decrease initiation signal. The voltage generator is configured to output a drive voltage different from the first power voltage and the falling voltage based on a blocking signal, and Wherein, based on the driving voltage being output to the voltage line, the voltage generator is configured to output the falling voltage to the voltage line.

12. The electronic device according to claim 11, wherein, The voltage generator and the power manager operate during four time periods: a first time period, a second time period, a third time period, and a fourth time period. During the first time period, the energizing signal has an active level, the power voltage initiation signal has a disabled level, the voltage drop initiation signal has a disabled level, and the blocking signal has a disabled level.

13. The electronic device according to claim 12, wherein, During the second time period, the power voltage initiation signal has a disabled level, the voltage drop initiation signal has a disabled level, and the blocking signal has an active level.

14. The electronic device according to claim 13, wherein, During the second time period, the driving voltage is output to the voltage line in response to the blocking signal.

15. The electronic device according to claim 13, wherein, The panel driver also includes: A gate driver is configured to output a gate signal to the display panel; A data driver is configured to apply a data voltage to the display panel; and The drive controller is configured to control the gate driver, the data driver, and the voltage generator. The gate signal and the data voltage are generated based on the driving voltage, and During the second time period, the drive voltage is applied to the gate driver and the data driver in response to the drive voltage start signal.

16. The electronic device according to claim 13, wherein, During the third time period, the power voltage initiation signal has a disabled level, the voltage drop initiation signal has an active level, and the blocking signal has a disabled level.

17. The electronic device according to claim 16, wherein, During the third time period, in response to the voltage drop initiation signal, the dropped voltage is output to the voltage line, and During the third time period, the output of the driving voltage is stopped.

18. The electronic device according to claim 16, wherein, During the fourth time period, the power voltage initiation signal has an active level, the voltage drop initiation signal has a disabled level, and the blocking signal has a disabled level.

19. The electronic device according to claim 18, wherein, During the fourth time period, in response to the power voltage initiation signal, the power voltage is output to the voltage line, and In the fourth time period, the output of the decreasing voltage is stopped.

20. The electronic device according to claim 11, wherein, The voltage generator includes: A voltage drop circuit is configured to output the dropped voltage in response to the voltage drop initiation signal; A drive voltage generation circuit is configured to output the drive voltage to a voltage blocking circuit in response to the blocking signal; The voltage blocking circuit is configured to output the driving voltage to the voltage line in response to the blocking signal; and A voltage output circuit is connected to the voltage line, and the voltage output circuit is configured to output the first power voltage.

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