Display method and display device for parallel light-emitting control signals

Abstract

The invention provides a light-emitting control signal parallel display method and device, and the method comprises the steps: enabling a memory module to store a plurality of bit planes to a plurality of block caches of a frame cache of the memory module, and enabling each block cache to be used for storing a plurality of lines of data in each bit plane; transmitting the multi-row data of the plurality of block caches to a row cache of a sequencing module; the scanning control module controls a row selection line of the sequencing module, and loads the multiple rows of data of the row cache to the display unit; a plurality of row selection signals generated by the sequencing module are transmitted to the display unit through row selection lines, the scanning control module generates a plurality of parallel light-emitting control signals to control the light-emitting time of a plurality of pixels of the display unit, and each light-emitting control signal is configured to refer to the loading timing of the row selection lines loading the same row of pixels.

Description

Technical Field

[0001] The embodiments of this application relate to the field of display technology, and more specifically, to a display method and display device that uses parallel light emission control signals. Background Technology

[0002] In existing display panel driving technologies, parallel scanning is commonly used to meet the demands of high resolution and high refresh rates, thereby improving scanning efficiency and reducing clock frequency. However, parallel scanning technology still has several limitations in practical applications. For example, when scanning multiple lines simultaneously, interference and noise can easily occur between driving signals, leading to uneven screen brightness or grayscale control errors. Furthermore, as display panel size and resolution increase, the load on the driving control module also increases, posing challenges to the system in terms of power consumption, stability, and reliability.

[0003] To address these issues, the industry has proposed various improved solutions based on parallel scanning algorithms, attempting to enhance screen brightness consistency and control precision through mechanisms such as segmentation or dual feedback. However, these technologies still suffer from insufficient precision and excessive brightness loss in the implementation of stepless dimming. In other words, existing parallel scanning frameworks struggle to balance high-precision brightness control with maximum brightness output efficiency, resulting in less smooth transitions in low-brightness areas and failing to fully realize the display's luminous potential. Summary of the Invention

[0004] In view of this, this application provides a display method and display device for parallel emission control signals.

[0005] One aspect of this application provides a display method for parallel light emission control signals, applied to a display device with parallel light emission control signals. The display device includes a main control chip and a display unit. The main control chip includes a memory module, a sequencing module, and a scanning control module. The display method includes: Multiple bit planes are stored separately into multiple block buffers of the frame buffer, where each block buffer is used to store multiple rows of data from each bit plane; The multiple rows of data from the multiple block caches are transferred to the row cache; Load the multiple rows of data from the row cache into the display unit; and Multiple parallel light-emitting control signals are generated to control the light-emitting time of multiple pixels of the display unit, wherein each light-emitting control signal is configured to reference the loading timing of the row selection line loading the same row of pixels.

[0006] This application controls the light emission time of multiple pixels in each row of the display unit in the corresponding subfield by generating each light emission control signal. The light emission time control is accurate to the clock cycle, which enables fine adjustment of the light emission time, thereby achieving a stepless dimming display control effect that combines high precision, low loss, low noise and high reliability.

[0007] Optionally, the display method is applied to a display device with parallel light emission control signals. The display device includes a main control chip and the display unit. The main control chip includes a memory module, a sequencing module, and a scanning control module, wherein: The memory module stores multiple bit planes into multiple block caches of the frame buffer of the memory module. The multiple rows of data from the multiple block caches are transmitted to the multiple row caches of the sequencing module; The scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit; and The scanning control module generates multiple parallel light emission control signals to control the light emission time of multiple pixels in the display unit. Optionally, the scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit: Each light emission control signal generated by the scanning control module controls the light emission time of multiple pixels in each row of the display unit in the corresponding subfield, wherein multiple subfields constitute a frame, and multiple row selection signals generated by the sequencing module are transmitted to the display unit through the row selection line, and the multiple row selection signals and the corresponding multiple light emission control signals are generated sequentially.

[0008] Optionally, the scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit: The scanning control module is configured to combine the time slice sequence and the emission ratio of the corresponding subfield in the time slice sequence memory of the memory module to calculate the lighting clock cycle of the multiple subfields.

[0009] Optionally, the scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit: The starting point of the light control signal on the same row as the row selection line is delayed by one clock cycle from the starting point of the corresponding row selection signal.

[0010] Optionally, the scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit: The end point of the light control signal on the same row as the row selection line is before the next start point of the same row selection signal.

[0011] Optionally, the scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit: The starting points of the operation of the light emission control signal are arranged according to an arithmetic sequence (Equation 1): (Equation 1) in It is the starting point of the light emission control signal; It is the starting point of the light emission control signal mentioned in the first line; The time interval represents the starting point of the light emission control signal described in the next line.

[0012] Optionally, the scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit: The counter of the scanning control module is configured to control the duration of each light emission control signal.

[0013] Optionally, the scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit: The scanning control module is configured to control the duration of the plurality of light emission control signals using a first counter and a second counter, wherein the control of the first counter corresponds to the odd-numbered time slices in the time slice sequence memory of the memory module, and the control of the second counter corresponds to the even-numbered time slices in the time slice sequence memory of the memory module.

[0014] Another aspect of this application provides a display device with parallel light emission control signals, the display device comprising: The main control chip includes: The memory module is configured to store multiple bit planes into multiple block caches of a frame cache of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; A sequencing module, coupled to the memory module, wherein the multiple rows of data in the plurality of block caches are configured to be transferred to the row cache of the sequencing module; and A scanning control module, coupled to the sequencing module, is configured to control the row selection line of the sequencing module to load the multi-row data cached in the row buffer into the display unit; and The display unit is coupled to the sequencing module. Multiple row selection signals generated by the sequencing module are transmitted to the display unit through the row selection lines. The scanning control module generates multiple parallel light emission control signals to control the light emission time of multiple pixels of the display unit. Each light emission control signal is configured to reference the loading timing of the row selection lines that load the same row of pixels.

[0015] Optionally, each light emission control signal generated by the scanning control module controls the light emission time of multiple pixels in each row of the display unit in the corresponding subfield, wherein multiple subfields constitute a frame, and the multiple row selection signals and the corresponding multiple light emission control signals are generated sequentially.

[0016] Optionally, the scanning control module is configured to latch the corresponding dimming factor at the start of each frame and provide the dimming factor to multiple subfields of the frame.

[0017] Optionally, the memory module includes a time-slice sequence memory, which is configured to store the time-slice sequence and the emission ratio of the corresponding subfield. The scanning control module is configured to combine the emission ratio of each subfield to calculate the lighting clock cycle of the multiple subfields.

[0018] Optionally, the scanning control module is configured to operate a starting point of the light emission control signal on the same row as the row selection line with a delay of one clock cycle from the starting point of the corresponding row selection signal.

[0019] Optionally, the scanning control module is configured to operate an end point of the light emission control signal on the same row as the row selection line before the next start point of the same row selection signal.

[0020] Optionally, the scanning control module is configured such that the starting points for operating the light emission control signal are arranged according to an arithmetic sequence:

[0021] in It is the starting point of the light emission control signal; It is the starting point of the light emission control signal mentioned in the first line; The time interval represents the starting point of the light emission control signal described in the next line.

[0022] Optionally, the scanning control module includes a counter configured to control the duration of each light emission control signal.

[0023] Optionally, the scanning control module includes a first counter and a second counter, the first counter and the second counter being configured to control the duration of the plurality of light emission control signals, wherein the control of the first counter corresponds to the odd time slice in the time slice sequence memory of the memory module, and the control of the second counter corresponds to the even time slice in the time slice sequence memory of the memory module. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this application and are not intended to limit this application, wherein: Figure 1 A schematic diagram of a display device with parallel light emission control signals according to an embodiment of this application is shown.

[0025] Figure 2 This diagram illustrates a row buffer, row selection line, and display unit in a display device with parallel light emission control signals according to an embodiment of this application.

[0026] Figure 3 This diagram illustrates a light emission control signal and a corresponding row selection signal in a display device with parallel light emission control signals according to an embodiment of this application.

[0027] Figure 4 This diagram illustrates two light-emitting control signals and corresponding row selection signals in a display device with parallel light-emitting control signals according to an embodiment of this application.

[0028] Figure 5 A flowchart illustrating a method for displaying parallel light emission control signals according to an embodiment of this application is shown. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Firstly, in this application, to achieve precise control of each pixel in the micro LED display device, subsequent embodiments will specifically employ digital quantities (i.e., binary data) as the control method. Specifically, by precisely controlling the illumination duration of each pixel, different grayscale levels are achieved for each pixel in the micro LED display device, thereby realizing a delicate image display effect. For example, the scanning frequency of the micro LED display device is 60Hz, meaning that one scanning cycle is completed every 16.6ms, and the grayscale value range of each pixel in the micro LED display device is... 255 corresponds to 8 bits in binary. Therefore, to precisely control the different grayscale levels of each pixel in a micro LED display, 8 bits are needed for individual control. More specifically, this is achieved by controlling the 8-bit binary number input to each pixel (i.e., ... This allows for fine-tuning of its grayscale levels.

[0033] It should be noted that a bit plane refers to the binary data used for each pixel, and each bit of binary data can be considered as a bit plane. Referring to the previous example, It can be considered as the first bit plane. This can be considered a second bit plane, and so on. When the display device sequentially reads the data from each bit plane, it can generate the image of the current frame. Based on the foregoing, the control data of the micro-LED display device is divided into multiple bit plane data. In some embodiments, the micro-LED display device sequentially reads the data from each bit plane to complete image scanning. Specifically, it will... Divide into 255 equal parts and read... The scan can be completed by analyzing the data of each bit plane.

[0034] like Figure 1 The diagram shown is a schematic of a display device with parallel light emission control signals according to an embodiment of this application. The display device includes a main control chip 2 and a display unit 3. The main control chip 2 (such as an FPGA chip, including a CPU, GPU and MCU) includes a memory module, a sequencing module and a scanning control module.

[0035] The memory module is configured to store multiple bit planes into multiple block buffers within a frame buffer of the memory module, where each block buffer stores multiple rows of data from each bit plane. Specifically, in the microdisplay driving system, the memory module is used to store and manage the multi-stage processing flow of display data. The memory module stores the data after bit plane separation. During the grayscale image input process, bit plane separation processing is performed, where the original multi-bit wide grayscale data (8 bits) is separated into multiple parallel unit-width (1 bit) bit plane data. For example, after passing through the image signal processing unit, the multiple rows of data are divided into multiple bit planes and stored in eight block buffers 0-7 according to a preset block configuration, ultimately forming a complete frame buffer.

[0036] The sequencing module is coupled to the memory module, wherein the multiple rows of data in the plurality of block caches are configured to be transmitted to the first row cache and the second row cache of the sequencing module. The scan control module is coupled to the sequencing module, and the scan control module is configured to control the row selection line of the sequencing module to load the multiple rows of data in the first row cache and the second row cache into the display unit 3.

[0037] Specifically, the sequencing module is the core of timing and data control for the entire driver architecture, and its overall operation is as follows: When the scanning control module starts the display operation, it initiates a request for bit plane data transmission, reads the separated bit plane data from the frame buffer according to block buffers 0-7, and transmits it to the first row buffer and the second row buffer. The first row buffer and the second row buffer are responsible for transmitting the received bit plane data to the display unit 3 according to a predetermined timing at a low clock frequency, in order to wait for the row selection signals of the first row selection line and the second row selection line to be triggered.

[0038] Cooperate Figure 2The diagram illustrates a row buffer, row selection line, and display unit in a display device with parallel light emission control signals according to an embodiment of this application. The display unit 3 is coupled to the sequencing module. Multiple row selection signals generated by the sequencing module are transmitted to the display unit 3 via the first row selection line and the second row selection line. Furthermore, the scan control module generates multiple parallel light emission control signals to control the light emission time of multiple pixels in the display unit. Each light emission control signal is configured to reference the loading timing of the row selection line loading the same row of pixels. In this embodiment, the scan control module controls the first row selection line to activate the row to be loaded in the first pixel array corresponding to the first row buffer; simultaneously, it controls the second row selection line to activate the row to be loaded in the second pixel array corresponding to the second row buffer.

[0039] Furthermore, the first row cache and the second row cache each contain multiple sets of row caches. The first sequence of the first row cache (top portion) corresponds to row caches A0-A3 (the first half of the row) and B0-B3 (the second half of the row), and the second sequence of the second row cache (bottom portion) corresponds to row caches A4-A7 (the first half of the row) and B4-B7 (the second half of the row). When loading the first row of the first pixel array (top portion), row cache A0 loads the first half of the first row, and row cache B0 loads the second half of the first row, with the loading time interval between row cache A0 and row cache B0 being at least one clock cycle. Simultaneously, when loading the first row of the second pixel array (bottom portion), row cache A4 loads the first half of the first row, and row cache B4 loads the second half of the first row, with the loading time interval between row cache A4 and row cache B4 being at least one clock cycle, and the loading time interval between row cache B0 and row cache A4 being at least one clock cycle, and so on.

[0040] Cooperate Figure 3 The diagram shown illustrates a light emission control signal and its corresponding row selection signal in a parallel light emission control signal display device according to an embodiment of this application. Specifically, each light emission control signal generated by the scanning control module is in its corresponding subfield ( The system controls the light emission time of multiple pixels in each row of the display unit 3, wherein multiple subfields form a frame, and the multiple row selection signals and the corresponding multiple light emission control signals are generated sequentially.

[0041] Furthermore, the scanning control module is configured to latch the corresponding dimming factor at the start point of each frame and provide the dimming factor to multiple subfields of the frame. Since a frame is divided into multiple subfields, in order to prevent the dimming factor from changing during scanning in a frame and causing different subfields to use different dimming factors, the corresponding dimming factor is latched at the start point of each frame to ensure that all subfields in the same frame use the same dimming factor.

[0042] In this embodiment, the scanning control module is configured to operate on a starting point of the light emission control signal on the same row as the row selection line. The scan control module is configured to operate on the end point of the light emission control signal of the same row as the row selection line, with a delay of one clock cycle between the start point and the start point of the corresponding row selection signal. Before the next start point of the same row selection signal (e.g., with a time interval), to avoid the end point of the light control signal ( The starting point of the next row selection signal is aligned with the starting point of the next row selection signal, so that the multiple light emission control signals are very close to a complete subfield cycle, thereby reducing brightness loss.

[0043] Furthermore, in controlling the length of the light-emitting control signal that generates a line, a counter can be used to calculate the clock cycle for lighting up; once the expected value is reached, the light-emitting control signal is stopped. For example, in this embodiment... Figure 1 In this embodiment, the scanning control module includes a first counter and a second counter, which are configured to control the duration of the plurality of light emission control signals. The first counter controls odd-numbered time slices in the time slice sequence memory of the memory module, and the second counter controls even-numbered time slices in the time slice sequence memory of the memory module. However, in other embodiments, the scanning control module may also be configured with multiple counters (two or more), each controlling the duration of the plurality of light emission control signals, and is not limited to this embodiment.

[0044] It should be noted that, for subsequent light emission control signals, to avoid overlap between the same counter and other light emission control signals in the next subfield (causing confusion due to simultaneous activation of light emission control signals from different subfields), the subfield is divided into even-numbered and odd-numbered subfields, each configured with a different counter (i.e., the first counter and the second counter). The signals of the first counter and the second counter are interleaved, allowing for precise control of the light emission control signals in all subfields of a frame. The last subfield needs to be a blank subfield to reset the light emission control signals of each row to zero.

[0045] Cooperate Figure 4The diagram illustrates two light-emitting control signals and corresponding row selection signals in a display device with parallel light-emitting control signals according to an embodiment of this application. Specifically, each row is controlled using a separate light-emitting control signal, based on the light-emitting time length of multiple pixels in each row. For example, the first row... Multiple pixels in a row are selected by the row selection signal. With light control signal To control; the Multiple pixels in a row are selected by the row selection signal. With light control signal To control this. In addition, depending on the pixel loading method, if the pixels in a row are segmented and different segments are loaded at different times, then the light emission control signal in the same row as the row selection line also needs to be segmented for control, that is, the same row becomes multiple light emission control signals.

[0046] The light emission control signal uses a sub-field scanning method. Each sub-field scans a different sub-field. The light emission time length of each sub-field is calculated based on the dimming factor (dim_factor) of the entire frame, such as the light emission time ratio. During control, each row is loaded according to its row selection signal, delayed by an appropriate clock cycle (e.g., one clock cycle, to prevent accidental activation of the previous sub-field's data in the actual circuit). The end point of the light emission control signal ( (It also cannot completely coincide with the starting point of the row selection signal of the next subfield, to prevent the image data of the next row from being accidentally lit up in a short period of time.) For example, if a subfield has 3000 clock cycles, the value of the light emission control signal can reach, for example, 2999, which is very close to the cycle of a complete subfield. The brightness loss is very small, and the lighting time of the subfield corresponding to the bit plane can be achieved in stages according to one clock cycle, which has a high precision effect.

[0047] In this embodiment, the scanning control module is configured such that the starting points for operating the light emission control signal are arranged according to an arithmetic sequence:

[0048] in It is the starting point of the light emission control signal; It is the starting point of the light emission control signal mentioned in the first line; The time interval represents the starting point of the light emission control signal described in the next line. It should be noted that the next line refers to the next line of operation, not the next line in the physical sense, such as line0, line60, line120, line180, etc.

[0049] Since the light emission control signals of all rows in the image are equal within a subfield, and the delay difference between the next light emission control signal and the previous light emission control signal forms an arithmetic sequence, the subsequent light emission control signals can be implemented by delaying the first light emission control signal by a fixed time.

[0050] Additionally, the memory module includes a time-slice sequence memory, configured to store time-slice sequences and the emission ratios of corresponding subfields. Specifically, the time-slice sequence memory stores time-slice sequences (subfield indices or subfield sequences) and the emission ratios of corresponding subfields, i.e., bit plane indices and the required emission time ratio for that bit plane. The scan control module is configured to combine the emission ratios of each subfield to calculate the lighting clock cycle for the multiple subfields. Specifically, since the scan control module needs to support out-of-order scanning, it needs to store the emission ratios corresponding to the subfields from the data in the time-slice sequence memory, and combine this with the actual dimming factor of the frame to calculate the actual lighting clock cycle required for each subfield.

[0051] Based on the above structure, the goal of this application's parallel light emission control signal display device is to combine existing parallel scanning frameworks to achieve high-precision, low-loss stepless dimming control. It proposes a dimming control architecture based on sub-field scanning, achieving precise dimming at both the row and segment levels through independent light emission control of each row of pixels. Specifically, the light emission control signal for each row of pixels can be subdivided according to a segmented scanning strategy to support multi-segment light emission control. Regarding time control, this application calculates the illumination duration of each sub-field based on the dimming factor of the entire frame, and adopts a method such as first finding the shortest sub-field and then working backwards to deduce other sub-fields to avoid time errors. This allows the illumination time of the sub-field corresponding to the lowest bit plane (b0) to be precisely controlled in steps down to a single clock cycle, resulting in minimal brightness loss and extremely high display accuracy.

[0052] Furthermore, to prevent accidental activation or signal overlap during subfield switching, this application employs a start-up delay and cutoff protection mechanism for the light emission control signal. It also uses dual counters corresponding to odd and even subfields, operating alternately to ensure timing independence and stability during multi-line parallel scanning. Additionally, the dimming factor is latched at the beginning of each frame to prevent changes during scanning, and a blank subfield is inserted at the last subfield to ensure the screen is completely off at the end. This application also supports out-of-order scanning, capable of reading the light emission ratio of each subfield from the time-slice sequence memory and dynamically calculating the light emission cycle based on the actual dimming factor, further enhancing display flexibility and consistency.

[0053] Compared to related technologies, the display device of this application is based on subfield scanning and achieves high-precision stepless dimming through precise emission timing control down to the clock cycle. Furthermore, the duration of the emission control signal can be extremely close to a complete subfield cycle, resulting in minimal maximum brightness loss. In addition, by finely adjusting the emission timing, the dimming range is significantly widened, and timing conflicts in the emission control signal are eliminated, with dimming factors latched within the frame to ensure stable image display and consistent brightness. In summary, this application achieves a high-performance display output while simultaneously providing stepless dimming display control with high precision, low loss, low noise, and high reliability.

[0054] like Figure 5 The diagram shown is a flowchart of a parallel display method for light emission control signals according to an embodiment of this application, applied to... Figures 1 to 2 The display device includes a main control chip 2 and a display unit 3, wherein the main control chip 2 includes a memory module, a sequencing module and a scanning control module.

[0055] The memory module is configured to store multiple bit planes into multiple block caches of a frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane. The sequencing module is coupled to the memory module, wherein the multiple rows of data in the multiple block caches are configured to be transmitted to the row cache of the sequencing module. The scan control module is coupled to the sequencing module, and the scan control module is configured to control the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit 3. The display method includes the following steps S101, S102 and S103: Step S101: The memory module stores multiple bit planes into multiple block buffers of a frame buffer, where each block buffer stores multiple lines of data from each bit plane. Specifically, after passing through the image signal processing unit, the multiple lines of data are divided into multiple bit planes and stored in eight block buffers 0-7 according to a preset block configuration, ultimately forming a complete frame buffer.

[0056] Step S102: Transmit the multiple rows of data from the multiple block caches to the row cache of the sequencing module.

[0057] Step S103: The scanning control module controls the row selection line of the sequencing module to load the multi-row data in the row cache into the display unit 3.

[0058] Step S104: The scanning control module generates multiple parallel light emission control signals to control the light emission time of multiple pixels of the display unit, wherein each light emission control signal is configured to reference the loading timing of the row selection line loading the same row of pixels.

[0059] In one embodiment, each light emission control signal generated by the scanning control module is in the corresponding subfield ( The scanning control module controls the emission time of multiple pixels in each row of the display unit 3, where multiple subfields constitute a frame. Multiple row selection signals generated by the sequencing module are transmitted to the display unit 3 via the row selection line. These multiple row selection signals and corresponding multiple emission control signals are generated sequentially. Furthermore, the scanning control module is configured to latch the corresponding dimming factor at the start point of each frame and provide the dimming factor to multiple subfields of the frame. Since a frame is divided into multiple subfields, to prevent changes in the dimming factor during scanning within a frame, which could cause different subfields to use different dimming factors, the corresponding dimming factor is latched at the start point of each frame to ensure that all subfields in the same frame use the same dimming factor.

[0060] In one embodiment, the scanning control module is configured to operate a starting point of the light emission control signal on the same row as the row selection line. The scan control module is configured to operate on the end point of the light emission control signal of the same row as the row selection line, with a delay of one clock cycle between the start point and the start point of the corresponding row selection signal. (Before the next starting point of the same row selection signal)

[0061] To control the length of the light-emitting control signal for a given line, a counter can be used to calculate the clock cycle for illumination. Once the expected value is reached, the light-emitting control signal is stopped. For example, in this embodiment, the scan control module includes a first counter and a second counter, which are configured to control the duration of the plurality of light-emitting control signals. The control of the first counter corresponds to the odd-numbered time slices in the time slice sequence memory of the memory module, and the control of the second counter corresponds to the even-numbered time slices in the time slice sequence memory of the memory module.

[0062] In one embodiment, the scanning control module is configured to operate the starting points of the emission control signals according to an arithmetic sequence. Since the emission control signals of all rows in the image are equal within a subfield, and the delay difference between the next emission control signal and the previous emission control signal forms an arithmetic sequence, subsequent emission control signals can be implemented by delaying the first emission control signal by a fixed time.

[0063] In one embodiment, the time-slice sequence memory of the memory module is configured to store time-slice sequences and the emission ratios of corresponding subfields. The scan control module is configured to combine the emission ratios of each subfield to calculate the lighting clock cycle for the multiple subfields. Specifically, since the scan control module needs to support out-of-order scanning, it needs to store the emission ratios corresponding to the subfields from the data in the time-slice sequence memory, and combine this with the actual dimming factor of the frame to calculate the actual lighting clock cycle required for each subfield.

[0064] Compared with related technologies, the display method of this application is based on subfield scanning. Through precise emission timing control down to the clock cycle, it achieves high-precision stepless dimming. Furthermore, the duration of the emission control signal can be extremely close to the complete subfield cycle, resulting in minimal maximum brightness loss. In addition, by finely adjusting the emission time, the dimming range is significantly widened, and timing conflicts in the emission control signal are eliminated, with dimming factors latched within the frame to ensure stable image display and consistent brightness. In summary, this application can maintain high-performance display output while achieving a stepless dimming display control effect that combines high precision, low loss, low noise, and high reliability.

[0065] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0066] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A display method with parallel light emission control signals, characterized in that, The display method includes: Multiple bit planes are stored separately into multiple block buffers of the frame buffer, where each block buffer is used to store multiple rows of data from each bit plane; The multiple rows of data from the multiple block caches are transferred to the row cache; Load the multiple rows of data from the row cache into the display unit; and Multiple parallel light-emitting control signals are generated to control the light-emitting time of multiple pixels of the display unit, wherein each light-emitting control signal is configured to reference the loading timing of the row selection line loading the same row of pixels.

2. The display method for parallel light emission control signals according to claim 1, characterized in that, The display method is applied to a display device with parallel light emission control signals. The display device includes a main control chip and the display unit. The main control chip includes a memory module, a sequencing module, and a scanning control module, wherein: The memory module stores multiple bit planes into multiple block caches of the frame buffer of the memory module. The multiple rows of data from the multiple block caches are transmitted to the multiple row caches of the sequencing module; The scanning control module controls the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit; and The scanning control module generates multiple parallel light emission control signals to control the light emission time of multiple pixels in the display unit.

3. The display method for parallel light emission control signals according to claim 2, characterized in that, Loading the multiple rows of data from the row cache into the display unit, controlled by the scan control module via the row selection line of the sequencing module, includes: Each light emission control signal generated by the scanning control module controls the light emission time of multiple pixels in each row of the display unit in the corresponding subfield, wherein multiple subfields constitute a frame, and multiple row selection signals generated by the sequencing module are transmitted to the display unit through the row selection line, and the multiple row selection signals and the corresponding multiple light emission control signals are generated sequentially.

4. The display method for parallel light emission control signals according to claim 3, characterized in that, The process of using the scanning control module to control the row selection line of the sequencing module and loading the multiple rows of data from the row cache into the display unit includes: The scanning control module is configured to combine the time slice sequence and the emission ratio of the corresponding subfield in the time slice sequence memory of the memory module to calculate the lighting clock cycle of the multiple subfields.

5. The display method for parallel light emission control signals according to claim 3, characterized in that, The process of using the scanning control module to control the row selection line of the sequencing module and loading the multiple rows of data from the row cache into the display unit includes: The starting point of the light control signal on the same row as the row selection line is delayed by one clock cycle from the starting point of the corresponding row selection signal.

6. The display method for parallel light emission control signals according to claim 3, characterized in that, The process of using the scanning control module to control the row selection line of the sequencing module and loading the multiple rows of data from the row cache into the display unit includes: The end point of the light control signal on the same row as the row selection line is before the next start point of the same row selection signal.

7. The display method for parallel light emission control signals according to claim 3, characterized in that, The process of using the scanning control module to control the row selection line of the sequencing module and loading the multiple rows of data from the row cache into the display unit includes: The starting points of the light emission control signals are arranged according to an arithmetic sequence: in It is the starting point of the light emission control signal; It is the starting point of the light emission control signal mentioned in the first line; The time interval represents the starting point of the light emission control signal described in the next line.

8. The display method for parallel light emission control signals according to claim 3, characterized in that, The process of using the scanning control module to control the row selection line of the sequencing module and loading the multiple rows of data from the row cache into the display unit includes: The counter of the scanning control module is configured to control the duration of each light emission control signal.

9. The display method for parallel light emission control signals according to claim 8, characterized in that, By using the scanning control module to control the row selection line of the sequencing module, the multiple rows of data in the row cache are loaded into the display unit: The scanning control module is configured to control the duration of the plurality of light emission control signals using a first counter and a second counter, wherein the control of the first counter corresponds to the odd-numbered time slices in the time slice sequence memory of the memory module, and the control of the second counter corresponds to the even-numbered time slices in the time slice sequence memory of the memory module.

10. A display device with parallel light emission control signals, characterized in that, The display device includes: The main control chip includes: The memory module is configured to store multiple bit planes into multiple block caches of a frame cache of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; A sequencing module, coupled to the memory module, wherein the multiple rows of data in the plurality of block caches are configured to be transmitted to the row cache of the sequencing module; and A scanning control module is coupled to the sequencing module, and the scanning control module is configured to control the row selection line of the sequencing module to load the multi-row data in the row cache into the display unit; and The display unit is coupled to the sequencing module. Multiple row selection signals generated by the sequencing module are transmitted to the display unit through the row selection lines. The scanning control module generates multiple parallel light emission control signals to control the light emission time of multiple pixels of the display unit. Each light emission control signal is configured to reference the loading timing of the row selection lines that load the same row of pixels.

11. The display device with parallel light emission control signals according to claim 10, characterized in that, Each light emission control signal generated by the scanning control module controls the light emission time of multiple pixels in each row of the display unit in the corresponding subfield, wherein multiple subfields constitute a frame, and the multiple row selection signals and the corresponding multiple light emission control signals are generated sequentially.

12. The display device with parallel light emission control signals according to claim 11, characterized in that, The scanning control module is configured to latch the corresponding dimming factor at the start of each frame and provide the dimming factor to multiple subfields of the frame.

13. The display device with parallel light emission control signals according to claim 11, characterized in that, The memory module includes a time-slice sequence memory, which is configured to store the time-slice sequence and the emission ratio of the corresponding subfield. The scanning control module is configured to combine the emission ratio of each subfield to calculate the lighting clock cycle of the multiple subfields.

14. The display device with parallel light emission control signals according to claim 11, characterized in that, The scanning control module is configured such that the starting point of the light emission control signal operating on the same row as the row selection line is delayed by one clock cycle from the starting point of the corresponding row selection signal.

15. The display device with parallel light emission control signals according to claim 11, characterized in that, The scanning control module is configured to operate the light emission control signal on the same row as the row selection line, with the end point preceding the next start point of the same row selection signal.

16. The display device with parallel light emission control signals according to claim 10, characterized in that, The scanning control module is configured such that the starting points for operating the light emission control signal are arranged according to an arithmetic sequence: in It is the starting point of the light emission control signal; It is the starting point of the light emission control signal mentioned in the first line; The time interval represents the starting point of the light emission control signal described in the next line.

17. The display device with parallel light emission control signals according to claim 11, characterized in that, The scanning control module includes a counter configured to control the duration of each light emission control signal.

18. The display device with parallel light emission control signals according to claim 11, characterized in that, The scanning control module includes a first counter and a second counter, which are configured to control the duration of the plurality of light emission control signals. The control of the first counter corresponds to the odd time slices in the time slice sequence memory of the memory module, and the control of the second counter corresponds to the even time slices in the time slice sequence memory of the memory module.

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