Display driving method and display device

Abstract

The invention provides a display driving method and a display device. The display driving method comprises the following steps: respectively storing image data of a plurality of image sub-blocks; storing a plurality of bit plane scanning information corresponding to the plurality of image sub-blocks; carrying the image data of the plurality of image sub-blocks to a plurality of line caches in parallel according to the plurality of pieces of bit plane scanning information; and loading the image data of the line cache to a plurality of image display sub-blocks.

Description

Technical Field

[0001] The embodiments of this application relate to the field of display technology, and more specifically, to display driving methods and display devices. Background Technology

[0002] In current display panel driving technologies, parallel scanning is a common image update method. For example, parallel or out-of-order scanning is performed at the in-place plane level to improve some display quality issues and effectively improve the efficiency of sub-field driving. However, these technologies still operate on the entire image as the unit, and their scanning order is relatively fixed. When the panel needs to process complex or low grayscale images, a fixed scanning mode can easily cause concentrated brightness changes in certain areas, resulting in unnatural tonal jumps in the image during the update process.

[0003] Furthermore, brightness jumps in existing image display technologies often result in a perceptible false contour phenomenon, especially noticeable in low-brightness, gradient, or moving images. Parallel scanning may also lead to concentrated memory read / write pressure during data transfer, making the system more susceptible to problems such as data channel contention and high local power consumption in extreme scenarios. Summary of the Invention

[0004] In view of this, the main objective of this application is to provide a display driving method and display device that can divide an image into multiple image sub-blocks and give each image sub-block an independent storage in a time slice sequence memory and a programmable out-of-order scanning capability, so that the overall scanning order is broken up to a highly irregular state, thereby more effectively suppressing the false contour phenomenon in specific scenes and improving the overall display quality.

[0005] To achieve the above objectives, one aspect of this application provides a display driving method, the display driving method comprising: The image data of multiple image sub-blocks are stored separately, wherein the multiple image sub-blocks are obtained by dividing an image; Store multiple bit-plane scan information corresponding to the multiple image sub-blocks; Based on the multiple bit-plane scanning information, the image data of the multiple image sub-blocks are transferred in parallel to multiple line buffers; and The image data cached in the row is loaded into multiple image display sub-blocks.

[0006] Optionally, storing the bit-plane scan information corresponding to the plurality of image sub-blocks includes: The scanning order of the bit plane scanning information of one image sub-block is different from the scanning order of the bit plane scanning information of another image sub-block.

[0007] Optionally, storing the bit-plane scan information corresponding to the plurality of image sub-blocks includes: Each bit plane scan information includes a bit plane index and a time ratio. The bit plane index is configured as the bit plane corresponding to the plurality of image sub-blocks, and the time ratio is configured as the time ratio for displaying the bit planes corresponding to the plurality of image sub-blocks.

[0008] Optionally, the parallel transfer of image data of the multiple image sub-blocks to multiple line buffers based on the multiple bit-plane scan information includes: Based on the multiple sub-time slices divided by the time slice, the multiple image sub-blocks are constrained to perform image data transfer in the corresponding sub-time slices.

[0009] Optionally, the parallel transfer of image data of the multiple image sub-blocks to multiple line buffers based on the multiple bit-plane scan information includes: Within the same image sub-block, the determination is made based on the bit-plane index of the bit-plane scan information of the image sub-block, including: In response to the current bit plane index being the same as the previous bit plane index, the image data transfer is stopped; and In response to the fact that the current bit plane index and the previous bit plane index are different bit plane indices, the image data is transferred.

[0010] Optionally, the display driving method is applied to a display device, the display device comprising a main control chip and a display unit, the main control chip comprising an image processing module, a memory module, a sequencing module and a scanning control module, wherein: The image processing module divides the image into multiple image sub-blocks. The image data of the multiple image sub-blocks are stored in multiple block caches of the frame buffer of the memory module; The bit plane scanning information corresponding to the multiple image sub-blocks is stored in the time slice sequence memory of the memory module; The scanning control module, based on the multiple bit-plane scanning information, parallelly transfers the image data of the multiple image sub-blocks to the multiple line buffers of the sequencing module; and The sequencing module loads the image data from the row cache into the plurality of image display sub-blocks divided by the display unit.

[0011] Another aspect of this application provides a display device, the display device comprising: The main control chip includes: The image processing module is configured to divide the image into multiple image sub-blocks; A memory module, coupled to the image processing module, is configured to store image data of the plurality of image sub-blocks respectively; A sequencing module, coupled to the memory module, wherein the line buffer of the sequencing module is configured to receive image data of the plurality of image sub-blocks transmitted from the memory module; and A scanning control module, coupled to the sequencing module, is configured to: parallelly transfer image data of the multiple image sub-blocks to multiple line buffers of the sequencing module based on the multiple bit-plane scanning information; and The display unit is coupled to the sequencing module, and the sequencing module loads the image data of the row cache into the plurality of image display sub-blocks divided by the display unit.

[0012] Optionally, the sequencing module includes a first row cache and a second row cache. The first row cache has two first half-row cache areas. The first row cache is configured to load the first row cache when the data in one of the first half-row cache areas is filled. The second row cache has two second half-row cache areas. The second row cache is configured to load the second row cache when the data in one of the second half-row cache areas is filled.

[0013] Optionally, the scanning order of the bit plane scanning information of one image sub-block is different from the scanning order of the bit plane scanning information of another image sub-block.

[0014] Optionally, each bit plane scan information includes a bit plane index and a time ratio, wherein the bit plane index is configured as the bit plane corresponding to the plurality of image sub-blocks, and the time ratio is configured as the time ratio for displaying the bit plane corresponding to the plurality of image sub-blocks.

[0015] Optionally, within the same image sub-block, the determination is made based on the bit plane index of the bit plane scan information of the image sub-block, including: In response to the current bit plane index being the same as the previous bit plane index, the image data transfer is stopped; and In response to the fact that the current bit plane index and the previous bit plane index are different bit plane indices, the image data is transferred. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this application and are not intended to limit this application, wherein: Figure 1 A schematic diagram of a display device according to an embodiment of this application is shown.

[0017] Figure 2 This diagram illustrates a row buffer, row selection line, and display unit in a display device according to an embodiment of this application.

[0018] Figure 3 A flowchart illustrating a display driving method according to an embodiment of this application is shown. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] Firstly, in this application, to achieve precise control of each pixel in the micro LED display device, subsequent embodiments will specifically employ digital quantities (i.e., binary data) as the control method. Specifically, by precisely controlling the illumination duration of each pixel, different grayscale levels are achieved for each pixel in the micro LED display device, thereby realizing a delicate image display effect. For example, the scanning frequency of the micro LED display device is 60Hz, meaning that one scanning cycle is completed every 16.6ms, and the grayscale value range of each pixel in the micro LED display device is... 255 corresponds to 8 bits in binary. Therefore, to precisely control the different grayscale levels of each pixel in a micro LED display, 8 bits are needed for individual control. More specifically, this is achieved by controlling the 8-bit binary number input to each pixel (i.e., ... This allows for fine-tuning of its grayscale levels.

[0023] It should be noted that a bit plane refers to the binary data used for each pixel, and each bit of binary data can be considered as a bit plane. Referring to the previous example, It can be considered as the first bit plane. This can be considered a second bit plane, and so on. When the display device sequentially reads the data from each bit plane, it can generate the image of the current frame. Based on the foregoing, the control data of the micro-LED display device is divided into multiple bit plane data. In some embodiments, the micro-LED display device sequentially reads the data from each bit plane to complete image scanning. Specifically, it will... Divide into 255 equal parts and read... The scan can be completed by analyzing the data of each bit plane.

[0024] like Figure 1 The diagram shown is a schematic of a display device according to an embodiment of this application. The display device includes a main control chip 2 and a display unit 3. The main control chip 2 (such as an FPGA chip, including a CPU, GPU and MCU) includes an image processing module, a memory module, a sequencing module and a scanning control module.

[0025] The image processing module preprocesses and transforms the raw image data to meet the specific needs of the subsequent scanning control module and display unit. Before storage in the frame buffer of the memory module, the image processing module is configured to divide the image into multiple image sub-blocks, and then send the processed image sub-blocks into the memory module for storage. Furthermore, the image processing module can non-linearly adjust the overall brightness of the image to address the problem of excessively short luminous control signals (em signals) in extremely low brightness scenes; it also performs grayscale scaling and multiplication operations on the pixel values ​​of the image to achieve the equivalent brightening operation required in low-grayscale anti-flicker schemes.

[0026] In this embodiment, the memory module is coupled to the image processing module. The memory module is configured to store the image data of the plurality of image sub-blocks respectively, so as to store the image data of the plurality of image sub-blocks in the multiple block buffers of the frame buffer of the memory module. For example, after passing through the image processing module, the image will be divided into multiple image sub-blocks and stored in eight block buffers 0-7 according to a preset block configuration, ultimately forming a complete frame buffer.

[0027] A sequencing module is coupled to the memory module, wherein the row buffer of the sequencing module is configured to receive image data of the plurality of image sub-blocks transmitted from the memory module. A scan control module is coupled to the sequencing module, and the scan control module is configured to transport the image data of the plurality of image sub-blocks in parallel to the plurality of row buffers of the sequencing module according to multiple bit-plane scan information. For example, the image data of the plurality of block buffers is configured to be transmitted to the first row buffer and the second row buffer of the sequencing module. A display unit 3 is coupled to the sequencing module, and the sequencing module loads the image data from the row buffers into the plurality of image display sub-blocks divided by the display unit.

[0028] In this embodiment, multiple bit plane scanning information corresponding to the multiple image sub-blocks is stored in the time slice sequence memory of the memory module. The number of the multiple image sub-blocks corresponds to the number of the multiple image display sub-blocks. Moreover, each bit plane scanning information includes a bit plane index and a time ratio. The bit plane index is configured as the bit plane corresponding to the multiple image sub-blocks, and the time ratio is configured as the time ratio for displaying the bit plane corresponding to the multiple image sub-blocks.

[0029] Furthermore, the scanning order of the bit-plane scanning information of one image sub-block differs from that of another image sub-block. In this case, each image sub-block can be programmed according to its own scanning order, resulting in a disordered arrangement of multiple image sub-blocks in the entire image, which effectively solves the false contour phenomenon.

[0030] Specifically, the sequencing module is the core of timing and data control in the entire driver architecture. Its overall operation is as follows: When the scanning control module starts display operation, it initiates a request for bit-plane data transmission, reads the separated bit-plane data from the frame buffer according to block buffers 0-7, and transmits it to the first row buffer and the second row buffer. The first row buffer and the second row buffer are responsible for transmitting the received bit-plane data to the display unit 3 according to a predetermined timing sequence at a low clock frequency, awaiting the triggering of the row selection signals of the first and second row selection lines.

[0031] Cooperate Figure 2 The diagram shown is a schematic representation of a row buffer, row selection line, and display unit in a display device according to an embodiment of this application. Multiple row selection signals generated by the sequencing module are transmitted to the display unit 3 via the first row selection line and the second row selection line. Furthermore, the scanning control module generates multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels in the display unit.

[0032] In this embodiment, the scanning control module controls the first row selection line to activate the row to be loaded from the first pixel array corresponding to the first row cache, and simultaneously controls the second row selection line to activate the row to be loaded from the second pixel array corresponding to the second row cache. Furthermore, the first row cache and the second row cache each contain multiple half-row cache areas. For example, the first row cache has two first half-row cache areas (e.g., A0 and B0), and the first row cache is configured to load data in response to one of the first half-row cache areas being full. The second row cache has two second half-row cache areas (e.g., A1 and B1), and the second row cache is configured to load data in response to one of the second half-row cache areas being full.

[0033] This application divides the entire image into multiple image sub-blocks using an image processing module. Each image sub-block is configured with independent memory (RAM, such as block cache) in the memory module to provide its own image data storage. Furthermore, a time-slice sequence memory (ts-RAM) is set up to store multiple bit-plane scan information corresponding to the multiple image sub-blocks. During scanning, each image sub-block is driven according to the time-slice sequence (ts) of the bit-plane scan information. If the current bit-plane index of the same image sub-block is the same as the previous bit-plane index, the image data transfer can be directly stopped (skipped) to reduce unnecessary operations. It should be noted that, in addition to the original mechanism of programmable out-of-order time-slice sequences for multiple image sub-blocks of the entire screen image, this application further allows the time-slice sequence of each image sub-block to be independently programmed, forming an architecture where each image sub-block can customize its out-of-order sequence.

[0034] Taking 4 bits as an example, field scanning will generate 16 time-slice sequences (including the final blanking sub-time-slice sequence). If the image is further divided into 4 image sub-blocks, each time-slice sequence will be subdivided into 4 sub-time-slice sequences (sub-ts), which are pre-assigned to different image sub-blocks. Each image sub-block can only complete data transfer within its own sub-time-slice sequence; if the scanning order of all image sub-blocks is completely consistent, it is no different from the traditional scanning method. However, this application allows each image sub-block to arrange the scanning order of its time-slice sequence, resulting in a highly disordered overall image scan, which can significantly improve the false contour phenomenon.

[0035] Furthermore, since each image sub-block only moves data on its corresponding sub-time slice sequence, contention caused by multiple image sub-blocks vying for the channel can be avoided. Simultaneously, by arranging the time slice sequences of different image sub-blocks, the data movement can be distributed across different time slice sequences, achieving smooth power consumption. For the external image interface, each image sub-block has independent memory, and at most one sub-time slice sequence in each time slice sequence is used for reading, while the other three sub-time slice sequences can be scheduled for writing. Therefore, only a small line buffer is needed to meet the requirements of memory read / write contention.

[0036] Unlike related technologies that only perform parallel and out-of-order scanning at the whole-screen bit-plane level, this application further evolves on the existing parallel subfield scanning architecture by introducing image sub-blocks and a design that stores them independently in time-slice sequence memory (TS-RAM). This allows each image sub-block to independently program its time-slice sequence (TS). By dividing the image into blocks and establishing an independently programmable out-of-order scanning order for each image sub-block, the overall scanning presents a higher degree of out-of-order state. Therefore, it can more effectively suppress false contour phenomena in specific scenarios, resulting in a more significant improvement in image quality.

[0037] In terms of resource and data transfer management, this application pre-assigns each image sub-block to a different sub-time slice sequence (sub-ts) and restricts each image sub-block to only perform image data transfer within its own sub-time slice sequence. This fundamentally avoids channel contention caused by simultaneous transfer of multiple image sub-blocks and also avoids read / write conflicts. Since each image sub-block is independently stored in memory, and at most one sub-time slice sequence is read in each time slice sequence while the remaining sub-time slice sequences can be scheduled for writing, a small-capacity line buffer can meet the memory read / write coordination requirements.

[0038] Regarding power consumption, this application can distribute memory read and move operations across different time slice sequences by adjusting the scanning order of each image sub-block. This avoids power spikes caused by concentrated large-scale memory reads within a short period and allows for more even distribution of moving operations, resulting in smoother overall power consumption. In other words, compared to related technologies that only scramble the bit plane, this application can first divide the entire image into multiple image sub-blocks, and then allow each sub-block to be scanned independently, thus comprehensively improving the degree of scrambling while solving the problems of resource contention and concentrated instantaneous power consumption.

[0039] Based on the above design, this application divides the image into multiple image sub-blocks and assigns each sub-block independent storage in time-slice sequence memory (TS-RAM) and programmable out-of-order scanning capability. This disrupts the overall scanning order to a highly irregular state, thereby more effectively suppressing false contour phenomena in specific scenes and improving image quality. Furthermore, each image sub-block is pre-defined to perform data transfer only within its corresponding sub-time-slice sequence, avoiding channel contention caused by simultaneous read / write operations from multiple sub-blocks. Each image sub-block also has independent memory, making read / write allocation within a single time-slice sequence easier to coordinate, and with row caching, read / write conflicts can be avoided. Moreover, by adjusting the scanning and data transfer timing of each sub-block, memory reads and data transfers can be distributed across different time-slice sequences, avoiding concentrated instantaneous power consumption and resulting in a smoother overall power distribution.

[0040] like Figure 3 The diagram shown is a flowchart of a display driving method according to an embodiment of this application, applied to... Figures 1 to 2 The display device includes a main control chip 2 and a display unit 3, wherein the main control chip 2 includes an image processing module, a memory module, a sequencing module and a scanning control module.

[0041] The memory module is configured to store multiple image sub-blocks, divided by the image, into multiple block caches of the frame buffer of the memory module, wherein each block cache is used to store image data in each image sub-block. The sequencing module is coupled to the memory module, wherein the image data in the multiple block caches is configured to be transmitted to the line cache of the sequencing module. The scan control module is coupled to the sequencing module, and the scan control module is configured to control the line selection line of the sequencing module to load the image data in the line cache into the display unit 3. The display driving method includes the following steps S101, S102, S103, S104 and S105: Step S101: Divide the image into multiple image sub-blocks. Specifically, the image is divided into multiple image sub-blocks by the image processing module.

[0042] Step S102: Store the image data of the plurality of image sub-blocks respectively. Specifically, the image data of the plurality of image sub-blocks are stored in the frame buffer of the memory module in multiple block buffers.

[0043] Step S103: Store multiple bit-plane scan information corresponding to the multiple image sub-blocks. Specifically, the multiple bit-plane scan information corresponding to the multiple image sub-blocks is stored in the time-slice sequence memory of the memory module. Each bit-plane scan information includes a bit-plane index and a time ratio. The bit-plane index is configured as the bit-plane corresponding to the multiple image sub-blocks, and the time ratio is configured as the time ratio for displaying the bit-plane corresponding to the multiple image sub-blocks. The scanning order of the bit-plane scan information of one image sub-block is different from the scanning order of the bit-plane scan information of another image sub-block.

[0044] Step S104: The scanning control module moves the image data of the multiple image sub-blocks to multiple line buffers in parallel according to the multiple bit-plane scanning information. In this embodiment, multiple sub-time slices are used to divide the time slice, constraining the multiple image sub-blocks to perform image data moving in the corresponding sub-time slices. Within the same image sub-block, a judgment is made based on the bit-plane index of the bit-plane scanning information of the image sub-block, including: stopping the image data moving in response to the current bit-plane index being the same as the previous bit-plane index; and performing the image data moving in response to the current bit-plane index being different from the previous bit-plane index.

[0045] Step S105: Load the image data from the row cache into multiple image display sub-blocks divided by the display unit 3. In this embodiment, the number of the multiple image sub-blocks corresponds to the number of the multiple image display sub-blocks. The multiple image sub-blocks are configured with independent storage and programmable out-of-order scanning to be displayed in the corresponding multiple image display sub-blocks, which helps to avoid false outlines, improve image quality, and reduce data channel contention during data transfer.

[0046] Based on the above design, this application divides the image into multiple image sub-blocks and assigns each sub-block independent storage in time-slice sequence memory (TS-RAM) and programmable out-of-order scanning capability. This disrupts the overall scanning order to a highly irregular state, thereby more effectively suppressing false contour phenomena in specific scenes and improving image quality. Furthermore, each image sub-block is pre-defined to perform data transfer only within its corresponding sub-time-slice sequence, avoiding channel contention caused by simultaneous read / write operations from multiple sub-blocks. Each image sub-block also has independent memory, making read / write allocation within a single time-slice sequence easier to coordinate, and with row caching, read / write conflicts can be avoided. Moreover, by adjusting the scanning and data transfer timing of each sub-block, memory reads and data transfers can be distributed across different time-slice sequences, avoiding concentrated instantaneous power consumption and resulting in a smoother overall power distribution.

[0047] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0048] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A display driving method, characterized in that, The display driving method includes: Store image data for multiple image sub-blocks separately; Store multiple bit-plane scan information corresponding to the multiple image sub-blocks; Based on the multiple bit-plane scanning information, the image data of the multiple image sub-blocks are moved in parallel to multiple line buffers; and The image data cached in the row is loaded into multiple image display sub-blocks.

2. The display driving method according to claim 1, characterized in that, Before storing the image data of the plurality of image sub-blocks respectively, the display driving method further includes: An image is divided into the plurality of image sub-blocks.

3. The display driving method according to claim 2, characterized in that, The image data for storing the plurality of image sub-blocks respectively includes: The image data of the multiple image sub-blocks are respectively stored in multiple block caches of the frame buffer.

4. The display driving method according to claim 1, characterized in that, The storage of multiple bit-plane scan information corresponding to the multiple image sub-blocks includes: The scanning order of the bit plane scanning information of one image sub-block is different from the scanning order of the bit plane scanning information of another image sub-block.

5. The display driving method according to claim 4, characterized in that, The storage of multiple bit-plane scan information corresponding to the multiple image sub-blocks includes: Each bit plane scan information includes a bit plane index and a time ratio. The bit plane index is configured to index the bit planes corresponding to the plurality of image sub-blocks, and the time ratio is configured to display the time ratio of the bit planes corresponding to the plurality of image sub-blocks.

6. The display driving method according to claim 1, characterized in that, Based on the multiple bit-plane scan information, the image data of the multiple image sub-blocks are transferred in parallel to multiple line buffers, including: Based on the multiple sub-time slices divided by the time slice, the multiple image sub-blocks are constrained to perform image data transfer in the corresponding sub-time slices.

7. The display driving method according to claim 6, characterized in that, Based on the multiple bit-plane scan information, the image data of the multiple image sub-blocks are transferred in parallel to multiple line buffers, including: Within the same image sub-block, the determination is made based on the bit-plane index of the bit-plane scan information of the image sub-block, including: In response to the current bit plane index being the same as the previous bit plane index, the image data transfer is stopped; and In response to the fact that the current bit plane index and the previous bit plane index are different bit plane indices, the image data is transferred.

8. A display device, characterized in that, The display device includes: The main control chip includes: The image processing module is configured to divide an image into multiple image sub-blocks. A memory module, coupled to the image processing module, is configured to store image data of the plurality of image sub-blocks respectively; A sequencing module, coupled to the memory module, wherein the line cache of the sequencing module is configured to receive image data of the plurality of image sub-blocks transmitted from the memory module; and A scanning control module, coupled to the sequencing module, is configured to: transfer the image data of the multiple image sub-blocks in parallel to multiple row buffers of the sequencing module according to the multiple bit plane scanning information; and The display unit is coupled to the sequencing module, and the sequencing module loads the image data of the row cache into the plurality of image display sub-blocks divided by the display unit.

9. The display device according to claim 8, characterized in that, The sequencing module includes a first row cache and a second row cache. The first row cache has two first half-row cache areas. The first row cache is configured to load the first row cache when the data in one of the first half-row cache areas is filled. The second row cache has two second half-row cache areas. The second row cache is configured to load the second row cache when the data in one of the second half-row cache areas is filled.

10. The display device according to claim 8, characterized in that, The scanning order of the bit plane scanning information of one image sub-block is different from the scanning order of the bit plane scanning information of another image sub-block.

11. The display device according to claim 8, characterized in that, Each bit plane scan information includes a bit plane index and a time ratio. The bit plane index is configured as the bit plane corresponding to the plurality of image sub-blocks, and the time ratio is configured as the time ratio for displaying the bit planes corresponding to the plurality of image sub-blocks.

12. The display device according to claim 8, characterized in that, Within the same image sub-block, the determination is made based on the bit-plane index of the bit-plane scan information of the image sub-block, including: In response to the current bit plane index being the same as the previous bit plane index, the image data transfer is stopped; and In response to the fact that the current bit plane index and the previous bit plane index are different bit plane indices, the image data is transferred.

Images