Waveform phase shift detection circuit and detection method thereof

Abstract

The invention relates to a waveform phase shift detection circuit and a detection method thereof, the detection circuit is applied to a phase shift frequency conversion control system, and the detection circuit comprises an edge detection module which is configured to be connected with a PWM output circuit of the phase shift frequency conversion control system and is used for extracting a target edge signal from the PWM output circuit; the asynchronous counting module is connected to the edge detection module and is used for counting the target edge signal to obtain a period count value of the PWM signal; and the window analysis module is connected to the asynchronous counting module and is used for outputting an abnormal detection signal according to a comparison result of the period counting value and a preset threshold value. According to the invention, the problem of wave loss can be rapidly and accurately identified, and resources of a digital signal processor are not occupied.

Description

Technical Field

[0001] This application relates to the field of phase shift control technology, and in particular to a waveform phase shift detection circuit and its detection method. Background Technology

[0002] In phase-shift frequency conversion control systems (such as dual active bridge DC-DC converters and full-bridge inverters), the digital signal processor (DSP) generates multiple PWM signals with precise phase differences through its enhanced pulse width modulation (ePWM) module, controlling energy transfer by adjusting the phase shift angle. For example, the ePWM module can trigger a counter to load a phase shift value (PHS) via a synchronization signal (SYNCI), achieving dynamic phase adjustment of the PWM waveform. However, in actual operation, when the phase shift value (PHS) and the duty cycle comparison value (CMP) cross a certain position (e.g., PHS suddenly changes from less than CMP to greater than CMP, or vice versa), the counter is forced to load a new PHS value when the synchronization signal arrives. This may cause it to directly skip the CMP matching point, thus failing to trigger the output flipping action within one PWM cycle, resulting in a "wave drop" problem.

[0003] To address the phase shift and waveform loss problem, related technologies typically employ hardware-based back-end detection and protection schemes: for example, triggering protection actions by detecting whether the transformer winding current or bus current is overcurrent.

[0004] However, current detection control requires waiting for the current to rise to the threshold, resulting in a large response delay. It cannot intervene immediately when waveform loss occurs. Furthermore, it cannot accurately identify the root cause of the fault, making it difficult to distinguish whether the overcurrent is caused by "wave loss," "load change," or "short circuit," which can easily lead to misjudgment or missed judgment. Summary of the Invention

[0005] This application provides a waveform phase shift detection circuit and its detection method, aiming to solve the problem that traditional current detection control methods cannot quickly and accurately detect and identify waveform phase shifts.

[0006] In a first aspect, embodiments of this application provide a waveform phase shift detection circuit, applied to a phase-shift frequency conversion control system, the detection circuit comprising:

[0007] An edge detection module is configured in the PWM output circuit connected to the phase-shift frequency conversion control system to extract the target edge signal from the PWM output circuit.

[0008] An asynchronous counting module, connected to the edge detection module, is used to count the target edge signal to obtain the period count value of the PWM signal;

[0009] A window analysis module, connected to the asynchronous counting module, is used to output an anomaly detection signal based on the comparison result between the periodic count value and a preset threshold.

[0010] In some embodiments, the detection circuit further includes a level converter, which is disposed between the PWM output circuit and the edge detection module, and is used to perform level conversion on the PWM signal output by the digital signal processor.

[0011] In some embodiments, the asynchronous counting module includes a ring oscillator and an asynchronous counter connected together, the ring oscillator providing an independent counting clock for the asynchronous counter; the asynchronous counter is also connected to the edge detection module, used to count the target edge signal according to the clock generated by the ring oscillator, to obtain the period count value of the PWM signal.

[0012] In some embodiments, the detection circuit includes a latch connected to the window analysis module, which is set when the abnormal detection signal is received and outputs a blocking signal.

[0013] In some embodiments, the level converter has an enable control terminal connected to the output terminal of the latch, used to control the on / off state of the PWM signal according to the signal output by the latch.

[0014] In some embodiments, the window analysis module and / or the level converter are provided with a filtering unit.

[0015] Secondly, this application provides a method for detecting waveform phase shift, applied to a waveform phase shift detection system, the waveform phase shift detection system comprising the detection circuit described above, and the method comprising:

[0016] Obtain the PWM signal;

[0017] Edge detection is performed on the PWM signal to obtain the target edge signal;

[0018] The target edge signal is counted to obtain the period count value of the PWM signal;

[0019] The period count value is compared with a preset threshold to determine the result.

[0020] When the cycle count value is greater than the preset threshold, the PWM signal is determined to be abnormal, and an abnormality detection signal is output.

[0021] In some embodiments, after outputting the anomaly detection signal, the method further includes:

[0022] In response to the anomaly detection signal, the latch is set, generating a blocking signal.

[0023] In some embodiments, the step of performing edge detection on the PWM signal to obtain the target edge signal includes:

[0024] The PWM signal is level-converted to obtain the converted PWM output signal;

[0025] The converted PWM output signal is subjected to edge detection to obtain the target edge signal.

[0026] In some embodiments, after generating the sealing signal, the method further includes:

[0027] Based on the blocked signal, hardware blocking and / or software blocking processing are performed.

[0028] This application provides a waveform phase shift detection circuit and method. The detection circuit includes an edge detection module configured to connect to the PWM output circuit of the phase-shift frequency converter control system, used to extract a target edge signal from the PWM output circuit; an asynchronous counting module connected to the edge detection module, used to count the target edge signal to obtain a period count value of the PWM signal; and a window analysis module connected to the asynchronous counting module, used to output an anomaly detection signal based on a comparison between the period count value and a preset threshold.

[0029] This application embodiment directly detects the periodic changes of the PWM signal through an edge detection module and an asynchronous counting module. When wave loss occurs, the PWM period becomes significantly longer, and the corresponding period count value will exceed the preset maximum threshold. Based on this, wave loss can be determined by the PWM period, enabling rapid and accurate fault identification. Secondly, the window analysis module can immediately output an abnormal detection signal within the first abnormal period when wave loss occurs, with a response time of nanoseconds. This allows for rapid triggering of the protection mechanism in the early stages of a fault, effectively preventing core saturation and power device damage caused by continuous unidirectional excitation in the main circuit.

[0030] Furthermore, the detection circuit provided in this application is a hardware circuit completely independent of the digital signal processor (DSP). It does not rely on the DSP's internal ePWM resources or additional relay modules (such as ePWM2), fundamentally avoiding the occupation of DSP hardware resources by existing software solutions and solving the system bottleneck problem caused by resource constraints in complex control topologies. Simultaneously, this circuit does not depend on the DSP's software operating state; even if the DSP crashes or the program malfunctions, it can still independently complete anomaly detection and protection actions, significantly improving the system's safety and reliability. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0034] Figure 1 A schematic diagram of an embodiment of a waveform phase shift detection circuit provided in this application;

[0035] Figure 2 This is a schematic diagram illustrating the extraction of an embodiment of the edge signal provided in this application;

[0036] Figure 3 A schematic flowchart of the first embodiment of the waveform phase shift detection method provided in this application;

[0037] Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application.

[0038] Explanation of icon numbers:

[0039] Waveform phase shift detection circuit 10, edge detection module 11, asynchronous counting module 12, ring oscillator 121, asynchronous counter 122, window analysis module 13, level converter 14, latch 15, phase shift frequency conversion control system 20, PWM output circuit 21, drive circuit 22, main circuit 23. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0042] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0043] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0045] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0046] In phase-shift frequency conversion control systems (such as dual active bridge DC-DC converters and full-bridge inverters), the digital signal processor (DSP) generates multiple PWM signals with precise phase differences through its enhanced pulse width modulation (ePWM) module, controlling energy transfer by adjusting the phase shift angle. For example, the ePWM module can trigger a counter to load a phase shift value (PHS) via a synchronization signal (SYNCI), achieving dynamic phase adjustment of the PWM waveform. However, in actual operation, when the phase shift value (PHS) and the duty cycle comparison value (CMP) cross a certain position (e.g., PHS suddenly changes from less than CMP to greater than CMP, or vice versa), the counter is forced to load a new PHS value when the synchronization signal arrives. This may cause it to directly skip the CMP matching point, thus failing to trigger the output flipping action within one PWM cycle, resulting in a "wave drop" problem.

[0047] To solve the phase-shifting and wave-dropping problem, related technologies typically employ the following two approaches:

[0048] (1) Software optimization scheme: For example, the "relay module method" introduces an additional ePWM module (such as ePWM2) to fix the phase shift by 90°, and limits the phase shift range of the target module (such as ePWM3) to 0°–180° (total phase shift angle is 90°–270°), thereby avoiding the crossing of PHS and CMP.

[0049] However, this method requires additional hardware PWM resources, which can easily lead to resource shortages in digital signal processors in complex topologies (such as multi-parallel dual active bridge DC-DC power supply systems), and may even affect the implementation of other control functions.

[0050] (2) Hardware back-end detection and protection scheme: For example, triggering protection action by detecting whether the transformer winding current or bus current is overcurrent.

[0051] However, current detection control requires waiting for the current to rise to the threshold, resulting in a large response delay. It cannot intervene immediately when waveform loss occurs. Furthermore, it cannot accurately identify the root cause of the fault, making it difficult to distinguish whether the overcurrent is caused by "wave loss," "load change," or "short circuit," which can easily lead to misjudgment or missed judgment.

[0052] To address the aforementioned issues, this application provides a waveform phase shift detection circuit and its detection method, which can quickly and accurately identify waveform loss problems without consuming digital signal processor resources.

[0053] See Figure 1 , Figure 1This is a schematic diagram of the structure of a waveform phase shift detection circuit 10 provided in this application. The waveform phase shift detection circuit 10 is applied to a phase-shift frequency conversion control system 20. The detection circuit includes an edge detection module 11, an asynchronous counting module 12, and a window analysis module 13.

[0054] The edge detection module 11 is configured in the PWM output circuit 21 connected to the phase-shift frequency conversion control system 20, and is used to extract the target edge signal from the PWM output circuit 21.

[0055] The target edge signal can be a rising edge signal and / or a falling edge signal. For example, the target edge signal can be extracted by the edge detection module 11. Figure 2 t0, t1, and t2 in the example.

[0056] Preferably, only the rising edge signal can be selected to determine whether there is a loss of wave or a continuous wave, which can reduce costs and detection difficulty.

[0057] The asynchronous counting module 12 is connected to the edge detection module 11 and is used to count the target edge signal to obtain the period count value of the PWM signal.

[0058] The window analysis module 13 is connected to the asynchronous counting module 12 and is used to output an anomaly detection signal based on the comparison result of the periodic count value and the preset threshold.

[0059] The phase-shift frequency conversion control system 20 may include a PWM output circuit 21, a drive circuit 22, and a main circuit 23. The main circuit 23 may be a phase-shift full-bridge, dual active, or triple phase-shift control system. The drive circuit 22 may include an optocoupler. Since the operating time of the optocoupler MOSFET is 50ns, high-speed drive shutdown can be achieved.

[0060] In some embodiments, the phase-shifting frequency conversion control system 20 includes a PWM output circuit 21, a drive circuit 22, and a main circuit 23.

[0061] The PWM output circuit 21 can use a digital signal processor (DSP) to generate a PWM signal with phase-shift control logic; the drive circuit 22 receives the PWM signal and converts it into a level and current signal suitable for driving power devices; the main circuit 23 performs energy conversion according to the drive signal to realize power regulation under phase-shift control.

[0062] In some embodiments, the main circuit 23 adopts one of the following topologies:

[0063] Phase-Shifted Full-Bridge Converter;

[0064] Dual Active Bridge (DAB) converter;

[0065] Triple Phase-Shift Converter; or other high-frequency isolated DC-DC or DC-AC topologies suitable for phase-shift control.

[0066] The drive circuit 22 includes an optocoupler isolation drive unit and a power drive stage. The optocoupler is used to achieve electrical isolation between the control side and the power side, while also transmitting the PWM drive signal. Because the optocoupler and its matching MOSFET drive circuit 22 have extremely fast response speeds, their turn-off time can be as low as 50ns, enabling high-speed driving and rapid turn-off of power devices (such as MOSFETs or IGBTs).

[0067] This embodiment directly detects the periodic changes of the PWM signal through the edge detection module 11 and the asynchronous counting module 12. When wave loss occurs, the PWM period becomes significantly longer, and the corresponding period count value will exceed the preset maximum threshold. Based on this, the PWM period is used to determine whether wave loss has occurred, which can achieve rapid and accurate fault identification. Secondly, the window analysis module 13 can immediately output an abnormal detection signal within the first abnormal period when wave loss occurs, with a response time of nanosecond level. It can quickly trigger the protection mechanism in the early stage of the fault, effectively avoiding core saturation and power device damage caused by continuous unidirectional excitation of the main circuit 23.

[0068] Furthermore, the detection circuit provided in this application is a hardware circuit completely independent of the digital signal processor (DSP). It does not rely on the DSP's internal ePWM resources or additional relay modules (such as ePWM2), fundamentally avoiding the occupation of DSP hardware resources by existing software solutions and solving the system bottleneck problem caused by resource constraints in complex control topologies. Simultaneously, this circuit does not depend on the DSP's software operating state; even if the DSP crashes or the program malfunctions, it can still independently complete anomaly detection and protection actions, significantly improving the system's safety and reliability.

[0069] In some embodiments, the detection circuit further includes a level converter 14, which is disposed between the PWM output circuit 21 and the edge detection module 11, and is used to perform level conversion on the PWM signal output by the digital signal processor.

[0070] Specifically, the level converter 14 can convert the PWM signal output by the 3.3V digital signal processor into a 5V CMOS level PWM signal for use in subsequent edge detection.

[0071] For example, taking a standard CMOS device as an example, the parameters of a standard CMOS device are shown in Table 1 below:

[0072] Table 1

[0073]

[0074]

[0075] For example, suppose there is a 3.3V PWM signal that is affected by a 1V transient noise (such as a ground bounce), and the original "low level" of 0.3V is raised to 1.3V.

[0076] In a 3.3V system, 1.3V > 0.8V (VIL) may be misinterpreted as "high level" → generating false edges → counter mis-triggered → misinterpreted as "wave drop" or "period abnormality".

[0077] In a 5V system, 1.3V < 1.5V (VIL) is still recognized as "low level" and there is no misjudgment.

[0078] Because 5V PWM signals have large amplitude, high signal-to-noise ratio, are not easily interfered with, can tolerate greater ground bounce, and have greater noise margin to absorb electromagnetic interference, by increasing the signal level from 3.3V to 5V and converting the PWM signal output by the digital signal processor into a steep square wave signal, the signal's "noise margin" can be increased, significantly improving the tolerance of subsequent circuits to interference. This can improve signal quality and effectively prevent false triggering caused by external interference.

[0079] In some embodiments, the asynchronous counting module 12 includes a ring oscillator 121 and an asynchronous counter 122 connected together. The ring oscillator 121 provides an independent counting clock for the asynchronous counter 122. The asynchronous counter 122 is also connected to the edge detection module 11 and is used to count the target edge signal according to the clock generated by the ring oscillator 121 to obtain the period count value of the PWM signal.

[0080] The ring oscillator 121 is used to generate an independent clock signal with a frequency of 100MHz, which is independent of the master clock (such as the digital signal processor system clock) in the phase-shift frequency conversion control system 20.

[0081] The asynchronous counter 122 increments on each rising edge of the 100MHz clock signal; simultaneously, the counter is reset to zero when a rising edge of the PWM signal is detected. Through this mechanism, the counter accumulates the number of 100MHz clock pulses starting from zero in each PWM cycle, and the resulting count value reflects the actual cycle length of the current PWM signal.

[0082] For example, if the PWM period is 20μs, then the count value is:

[0083] 20μs × 100MHz = 2000;

[0084] The cycle count value is then sent to the window analysis module 13 to determine whether a wave loss or cycle anomaly has occurred.

[0085] Thus, by using a "high-frequency independent clock + rising edge clearing count" method, high-precision, real-time monitoring of the PWM cycle can be achieved. Furthermore, by utilizing a ring oscillator 121 located in external hardware, a clock signal completely independent of the digital signal processor is provided to the detection circuit. The asynchronous counter 122 does not need to rely on the master control clock of the digital signal processor, which makes the protection function an autonomous system. Even if the digital signal processor fails completely for any reason (crash, reset, clock stop), the detection circuit can still rely on its own "heartbeat" to continuously monitor the PWM signal. When abnormalities such as waveform loss, waveform continuity, high / low signal jamming are detected, the drive output is blocked within nanoseconds to ensure system safety.

[0086] In some embodiments, the detection circuit includes a latch 15 connected to the window analysis module 13, which is set when the abnormal detection signal is received and outputs a blocking signal.

[0087] For example, when latch 15 is set, it outputs a high level, which then serves as a blocking signal.

[0088] In some embodiments, the level converter 14 has an enable control terminal connected to the output terminal of the latch 15, used to control the on / off state of the PWM signal according to the signal output by the latch 15.

[0089] For example, when the latch 15 outputs a low level, the level converter 14 is in a first enabled state, allowing the PWM signal to pass through;

[0090] When the latch 15 outputs a high level, the level converter 14 is in the second enabled state and stops outputting the PWM signal.

[0091] Thus, when the window analysis module 13 detects an abnormal PWM cycle (such as waveform loss), it immediately outputs an abnormality detection signal. Upon receiving this signal, the latch 15 immediately sets and outputs a high-level blocking signal. Since this blocking signal directly acts on the enable control terminal of the level converter 14, the control logic is clear. Therefore, when the latch 15 outputs a low level, the level converter 14 transmits the PWM signal normally; when the latch 15 outputs a high level, the level converter 14 immediately enters a disabled state, forcibly stopping the PWM output (output is low or high impedance), thus preventing malfunction of the drive circuit 22 and enabling... Within nanoseconds, the PWM signal transmission path is cut off, and rapid blocking is achieved after latch 15 is set. Furthermore, the entire detection and blocking process is completed autonomously by the hardware circuit, without relying on the operating status of the digital signal processor. Compared with traditional software blocking that relies on the interrupt response of the digital signal processor (the response time is usually on the order of microseconds), this solution improves the response speed by 1-2 orders of magnitude. It can complete the protection action before the main circuit 23 becomes magnetically saturated, effectively preventing damage to power devices. Even if the digital signal processor causes PWM abnormality due to program crash, system freeze, or communication interruption, the detection circuit can still detect and execute blocking normally.

[0092] In some embodiments, the window analysis module 13 and / or the level converter 14 are provided with a filtering unit.

[0093] The filtering unit can be an RC filtering unit.

[0094] For example, a filtering unit can be set at the input of the window analysis module 13 to perform analog filtering on the periodic count signal from the asynchronous counting module 12, filtering out high-frequency noise and preventing false over-limit signals from triggering abnormal judgment. For example, a 10Ω resistor and a 100pF capacitor connected in series to ground on the periodic count signal line form a low-pass filter with a cutoff frequency of approximately 160MHz, which can effectively suppress high-frequency interference without affecting the normal signal response speed.

[0095] Furthermore, a filter unit can be set at the input of the level converter 14 to provide hysteresis voltage characteristics and enhance the signal's anti-interference capability. For example, a Schmitt trigger input structure can be integrated at the PWM input of the level converter 14 to make it more tolerant to slowly changing or noisy input signals, outputting a clean, steep square wave signal and preventing edge oscillations from causing misjudgments in subsequent stages.

[0096] Thus, by setting up the aforementioned filtering unit, the anti-interference capability and operational stability of the detection circuit can be significantly improved while ensuring a rapid response to real faults, thus avoiding the problem of "false triggering".

[0097] In some embodiments, the detection circuit may include an edge detection module 11, an asynchronous counting module 12, a window analysis module 13, a level converter 14, and a latch 15, wherein the asynchronous counting module 12 includes a ring oscillator 121 and an asynchronous counter 122.

[0098] Since the transmission delay of the level converter 14 is ≤40ns, the response time of the edge detection module 11 is 1ns, the jitter of the ring oscillator 121 is <±200ps, the counting error of the asynchronous counter 122 is ±1LSB, and the comparison delay of the window analysis module 13 is 5ns, the detection circuit provided in this application can detect and identify quickly and accurately.

[0099] Based on the detection circuits of the above embodiments, this application also provides a waveform phase shift detection method, applied to a waveform phase shift detection system. The waveform phase shift detection system includes the detection circuits described in any of the above embodiments. See details... Figure 3 , Figure 3 This is a flowchart illustrating a first embodiment of a waveform phase shift detection method provided in this application. The waveform phase shift detection method includes the following steps:

[0100] Step 110: Obtain the PWM signal.

[0101] PWM signals can be generated using a digital signal processor.

[0102] Step 120: Perform edge detection on the PWM signal to obtain the target edge signal.

[0103] Step 130: Count the target edge signal to obtain the period count value of the PWM signal.

[0104] Step 140: Compare the cycle count value with a preset threshold to make a judgment.

[0105] Step 150: When the cycle count value is greater than the preset threshold, the PWM signal is determined to be abnormal, and an abnormality detection signal is output.

[0106] In some implementations, the preset threshold can be 80%, 85%, 90%, etc., and can be set and adjusted according to the actual situation. This application does not limit it here.

[0107] In some embodiments, the counter is reset to zero when the period count value is less than or equal to a preset threshold.

[0108] This embodiment directly detects the periodic changes of the PWM signal output by the digital signal processor by performing edge detection and period counting. Since the PWM period becomes significantly longer when waveform loss occurs, the corresponding period count value will exceed the preset maximum threshold. Based on this, the PWM period is used to determine whether waveform loss has occurred, which can achieve rapid and accurate fault identification. Secondly, the window analysis module can immediately output an abnormal detection signal within the first abnormal period when waveform loss occurs, with a response time of nanosecond level. It can quickly trigger the protection mechanism in the early stage of the fault, effectively avoiding core saturation and power device damage caused by continuous unidirectional excitation in the main circuit.

[0109] Referring to the second embodiment of the waveform phase shift detection method provided in this application, the second embodiment may include the following steps:

[0110] Step 210: Obtain the PWM signal.

[0111] Step 220: Perform edge detection on the PWM signal to obtain the target edge signal.

[0112] Step 230: Count the target edge signal to obtain the period count value of the PWM signal.

[0113] Step 240: Compare the cycle count value with a preset threshold to make a judgment.

[0114] Step 250: When the cycle count value is greater than the preset threshold, the PWM signal is determined to be abnormal, and an abnormality detection signal is output.

[0115] Step 260: In response to the anomaly detection signal, trigger the latch to be set and generate a blocking signal.

[0116] Referring to the third embodiment of the waveform phase shift detection method provided in this application, the third embodiment may include the following steps:

[0117] Step 310: Obtain the PWM signal.

[0118] Step 320: Perform level conversion on the PWM signal to obtain the converted PWM output signal;

[0119] Step 330: Perform edge detection on the converted PWM output signal to obtain the target edge signal.

[0120] Step 34: Count the target edge signal to obtain the period count value of the PWM signal.

[0121] Step 350: Compare the cycle count value with a preset threshold to make a judgment.

[0122] Step 360: When the cycle count value is greater than the preset threshold, the PWM signal is determined to be abnormal, and an abnormality detection signal is output.

[0123] Referring to the fourth embodiment of the waveform phase shift detection method provided in this application, the fourth embodiment may include the following steps:

[0124] Step 410: Obtain the PWM signal.

[0125] Step 420: Perform edge detection on the PWM signal to obtain the target edge signal.

[0126] Step 430: Count the target edge signal to obtain the period count value of the PWM signal.

[0127] Step 440: Compare the cycle count value with a preset threshold to make a judgment.

[0128] Step 450: When the cycle count value is greater than the preset threshold, the PWM signal is determined to be abnormal, and an abnormality detection signal is output.

[0129] When the period count value is greater than the preset threshold, it indicates an abnormal situation such as pulse loss or excessive length. Therefore, an abnormality detection signal can be output.

[0130] Step 460: In response to the anomaly detection signal, trigger the latch to be set and generate a blocking signal.

[0131] Step 470: Based on the blocked signal, perform hardware blocking and / or software blocking processing.

[0132] Specifically, the latch-generated blocking signal, such as a high-level signal, is sent to the level converter. Since the level converter has an enable protection function, in the default state, when a low-level signal is given, the PWM signal is output normally. When a high-level signal is given, the output stops. Therefore, when the level converter detects a high level, it immediately enters a disabled state, cutting off the transmission path of the PWM signal. At this time, even if the digital signal processor is still outputting the PWM signal, the subsequent drive circuit cannot receive a valid control signal. The drive circuit (such as the isolation driver or gate driver IC) stops outputting, the power devices (such as MOSFETs or IGBTs) are turned off, and the energy transmission of the main circuit is forcibly interrupted. In this way, the blocking between hardware is achieved, the drive circuit has no output, and the main circuit stops working.

[0133] In addition, when the software detects a blocking signal generated by the latch, such as a high level, the software blocks the signal and issues an alarm signal.

[0134] For example, software wave blocking can refer to the following process:

[0135] 1) The high-level blocking signal output by the latch is simultaneously fed back to the GPIO input pin of the digital signal processor;

[0136] 2) After the digital signal processor detects this high-level signal through polling or interrupt, it determines it to be a serious fault;

[0137] 3) The software will immediately perform the following actions:

[0138] 3-1) Disable the output enable of the relevant ePWM module;

[0139] 3-2) Enter fault protection mode;

[0140] 3-3) Record the fault type and timestamp;

[0141] 3-4) Send a fault alarm signal to the host computer or human-machine interface;

[0142] 3-5) Wait for manual reset or execute the automatic restart process.

[0143] In this way, the hardware blocking completes its action within the first cycle of an anomaly, preventing the main circuit from experiencing a sharp rise in current due to magnetic saturation and avoiding damage to power devices; while the software blocking performs fault confirmation, log recording, and alarm output after the hardware action, making it easier for maintenance personnel to locate the problem; through the collaborative mechanism of hardware and software blocking, multi-level, highly reliable system protection can be achieved, ensuring both response speed and enhancing the maintainability and security of the system.

[0144] Based on the above embodiments, the waveform phase shift detection circuit provided in this application was compared with the traditional current detection circuit, and the results are shown in Table 2 below.

[0145] Table 2:

[0146]

[0147]

[0148] Corresponding to the above-described waveform phase shift detection method, this application also provides a waveform phase shift detection device. This waveform phase shift detection device includes a unit for performing the above-described waveform phase shift detection method, and can be configured in a desktop computer, tablet computer, laptop computer, or other terminal.

[0149] like Figure 4 As shown in the figure, this application provides a computer device including a processor 111, a communication interface 112, a memory 113, and a communication bus 114, wherein the processor 111, the communication interface 112, and the memory 113 communicate with each other through the communication bus 114.

[0150] Memory 113 is used to store computer programs;

[0151] In one embodiment of this application, when the processor 111 executes the program stored in the memory 113, it implements the waveform phase shift detection method provided in any of the foregoing method embodiments, including:

[0152] Obtain the PWM signal;

[0153] Edge detection is performed on the PWM signal to obtain the target edge signal;

[0154] The target edge signal is counted to obtain the period count value of the PWM signal;

[0155] The period count value is compared with a preset threshold to determine the result.

[0156] When the cycle count value is greater than the preset threshold, the PWM signal is determined to be abnormal, and an abnormality detection signal is output.

[0157] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program may be stored in a storage medium, which is a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0158] Therefore, embodiments of this application also provide a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the waveform phase shift detection method provided in any of the foregoing method embodiments, including:

[0159] Obtain the PWM signal;

[0160] Edge detection is performed on the PWM signal to obtain the target edge signal;

[0161] The target edge signal is counted to obtain the period count value of the PWM signal;

[0162] The period count value is compared with a preset threshold to determine the result.

[0163] When the cycle count value is greater than the preset threshold, the PWM signal is determined to be abnormal, and an abnormality detection signal is output.

[0164] The storage medium is a physical, non-transient storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk, or any other physical storage medium capable of storing program code. The computer-readable storage medium can be non-volatile or volatile.

[0165] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0166] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0167] The steps in the methods of this application embodiment can be adjusted, merged, or deleted according to actual needs. The units in the apparatus of this application embodiment can be merged, divided, or deleted according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0168] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0169] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0170] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Since these modifications and variations fall within the scope of the claims and their equivalents, this application also intends to include these modifications and variations.

[0171] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A waveform phase shift detection circuit, characterized in that, The detection circuit, applied in a phase-shifting frequency converter control system, includes: An edge detection module is configured in the PWM output circuit connected to the phase-shift frequency conversion control system to extract the target edge signal from the PWM output circuit. An asynchronous counting module, connected to the edge detection module, is used to count the target edge signal to obtain the period count value of the PWM signal; A window analysis module, connected to the asynchronous counting module, is used to output an anomaly detection signal based on the comparison result between the periodic count value and a preset threshold.

2. The detection circuit according to claim 1, characterized in that, The detection circuit also includes a level converter, which is disposed between the PWM output circuit and the edge detection module, and is used to perform level conversion on the PWM signal output by the digital signal processor.

3. The detection circuit according to claim 1, characterized in that, The asynchronous counting module includes a ring oscillator and an asynchronous counter connected together. The ring oscillator provides an independent counting clock for the asynchronous counter. The asynchronous counter is also connected to the edge detection module and is used to count the target edge signal according to the clock generated by the ring oscillator to obtain the period count value of the PWM signal.

4. The detection circuit according to claim 2, characterized in that, The detection circuit includes a latch connected to the window analysis module, which is set when the abnormal detection signal is received and outputs a blocking signal.

5. The detection circuit according to claim 4, characterized in that, The level converter has an enable control terminal, which is connected to the output terminal of the latch and is used to control the on / off state of the PWM signal according to the signal output by the latch.

6. The detection circuit according to claim 2, characterized in that, The window analysis module and / or the level converter are equipped with a filtering unit.

7. A method for detecting waveform phase shift, characterized in that, A waveform phase shift detection system, the waveform phase shift detection system comprising the detection circuit as described in any one of claims 1-5, the method comprising: Obtain the PWM signal; Edge detection is performed on the PWM signal to obtain the target edge signal; The target edge signal is counted to obtain the period count value of the PWM signal; The period count value is compared with a preset threshold to determine the result. When the cycle count value is greater than the preset threshold, the PWM signal is determined to be abnormal, and an abnormality detection signal is output.

8. The method according to claim 7, characterized in that, After outputting the anomaly detection signal, the method further includes: In response to the anomaly detection signal, the latch is set, generating a blocking signal.

9. The method according to claim 7, characterized in that, The step of edge detection of the PWM signal to obtain the target edge signal includes: The PWM signal is level-converted to obtain the converted PWM output signal; The converted PWM output signal is subjected to edge detection to obtain the target edge signal.

10. The method according to claim 8, characterized in that, After generating the sealing signal, the method further includes: Based on the blocked signal, hardware blocking and / or software blocking processing are performed.

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