Software and hardware combined key on-off circuit

Abstract

The invention discloses a software and hardware combined key on-off circuit, which belongs to the technical field of circuits, and comprises a power switch tube, a pull-up resistor, a key, a one-way conduction element, a main processor and a state latch switch tube, a switch control end of the power switch tube is connected to a control node ENG, an input end of the power switch tube is connected with a power input end POWERIN, and an output end of the power switch tube is connected with a system power output end SYSPOWER; one end of the pull-up resistor is connected with the power supply input end POWERIN, and the other end of the pull-up resistor is connected with the control node ENG; one end of the key is grounded, the other end of the key is connected with the first end of the one-way conduction element, and the second end of the one-way conduction element is connected with the control node ENG. According to the invention, by multiplexing the port and software logic of the main system processor, the material cost is obviously reduced on the premise of maintaining the programmable delay startup and shutdown and soft shutdown functions.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a hardware and software integrated push-button power switch circuit. Background Technology

[0002] In the field of power management for existing electronic products, common technical solutions for user power on / off control can be mainly divided into two categories.

[0003] The first type is the mechanical hard-switching solution, such as... Figure 2 As shown, this scheme connects a physical switch directly in series in the device's main power signal path, allowing the user to manually close or open the switch to directly connect or disconnect the system power supply. The advantages of this scheme are its simple circuit structure and low cost. However, it has significant limitations: First, it cannot implement software-defined power-on / off logic with delay characteristics, such as pressing and holding for a specific duration (e.g., 3 seconds) to turn on or off, resulting in limited functionality; second, its power-off operation is a direct power-off, without notifying the system to perform any data saving or safe exit procedures before cutting off the power. This abrupt power-off method may lead to data loss or file system corruption, posing a potential risk of damage to some smart devices that require orderly power-off.

[0004] The second category is processor-based pure software switching solutions, such as... Figure 3 As shown, in this scheme, the physical buttons do not directly control the power supply. Instead, they are connected to a general-purpose input / output (GPIO) port, where a processor monitors the voltage level changes in real time and interprets them as power on / off commands. This scheme allows for flexible setting of power on / off durations and enables soft shutdown (i.e., the system software safely shuts down the application and operating system before cutting off the power), resulting in a better user experience. However, to implement continuous monitoring of button signals and power control logic, this scheme requires an additional, constantly powered coprocessor (e.g., a dedicated microcontroller MCU) in addition to the main system processor. This increases system cost, standby power consumption, and system complexity due to the introduction of an additional processor and supporting circuitry, thereby reducing the overall reliability and stability of the scheme. Summary of the Invention

[0005] One of the objectives of this invention is to provide a hardware and software integrated button power switch circuit, so as to overcome the shortcomings of high cost, high power consumption and system complexity of soft switching while retaining the flexibility and safety of soft switching.

[0006] This invention is achieved through the following technical solution: a hardware and software combined push-button power switch circuit, comprising:

[0007] Power switching transistors, pull-up resistors, buttons, unidirectional conduction components, main processor, and status latching switching transistors;

[0008] The switching control terminal of the power switch is connected to a control node EN_G, the input terminal of the power switch is connected to the power input terminal POWER_IN, and the output terminal of the power switch is connected to the system power output terminal SYS_POWER.

[0009] One end of the pull-up resistor is connected to the power input terminal POWER_IN, and the other end of the pull-up resistor is connected to the control node EN_G;

[0010] One end of the button is grounded, the other end of the button is connected to the first end of the unidirectional conduction element, and the second end of the unidirectional conduction element is connected to the control node EN_G;

[0011] The power supply terminal of the main processor is used to receive power from the system power output terminal SYS_POWER. The signal detection terminal of the main processor is connected to the connection node between the button and the unidirectional conduction element. The state control terminal of the main processor is connected to the latching control terminal of the state latching switch.

[0012] The first path terminal of the state latching switch is connected to the control node EN_G, and the second path terminal of the state latching switch is grounded.

[0013] Furthermore, the power switch is a P-channel MOSFET, and the gate, source, and drain of the P-channel MOSFET constitute the switch control terminal, input terminal, and output terminal, respectively.

[0014] Furthermore, the absolute value of the gate threshold voltage of the P-channel MOSFET is less than the voltage value at the power input terminal.

[0015] Furthermore, the unidirectional conducting element is a diode, and the anode and cathode of the diode constitute the first terminal and the second terminal, respectively.

[0016] Furthermore, the voltage value at the power input terminal minus the forward voltage drop of the diode is less than the absolute value of the gate threshold voltage of the P-channel MOSFET.

[0017] Furthermore, the state latching switch is an NPN transistor, and the base, collector, and emitter of the NPN transistor constitute the latching control terminal, the first path terminal, and the second path terminal, respectively.

[0018] Furthermore, it also includes a current-limiting resistor and a pull-down resistor. One end of the current-limiting resistor is connected to the status control terminal of the main processor, and the other end is connected to the base of the NPN transistor. One end of the pull-down resistor is connected to the base of the NPN transistor, and the other end is grounded.

[0019] Furthermore, the voltage value at the power input terminal minus the collector saturation voltage drop of the NPN transistor is less than the absolute value of the gate threshold voltage of the P-channel MOS transistor.

[0020] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0021] This invention replaces the resident coprocessor required in traditional soft-switching solutions by reusing the ports and software logic of the main system processor. While maintaining programmable delay power-on and soft-shutdown functions, it significantly reduces material costs and reduces standby power consumption in the fully powered-off state to the microampere level or even the theoretical zero power consumption level, greatly improving the battery life of battery-powered devices.

[0022] This invention combines a direct hardware triggering path consisting of a button and a unidirectional conduction element with a hardware state locking path controlled by the processor through a state latching switch. This not only realizes complex user interaction logic such as long press to power on and long press to power off, ensuring data security during system shutdown, but also simplifies the hardware structure and reduces potential failure points by eliminating the complex coprocessing subsystem, thereby significantly improving the reliability and anti-interference capability of the entire power control circuit. Attached Figure Description

[0023] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0024] Figure 1 This is a structural diagram of a hardware and software combined push-button power switch circuit according to the present invention.

[0025] Figure 2 This is a structural diagram of a traditional mechanical hard switch solution.

[0026] Figure 3 This is a structural diagram of a traditional processor-based pure soft switching scheme. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Example 1

[0029] This invention proposes a hardware and software integrated button power on / off circuit. This circuit does not require a separate coprocessor, but instead utilizes the general-purpose input / output ports of the device's main processor (MCU / SOC / CPU) and a simplified peripheral circuit to work together to achieve intelligent power on / off control that is both flexible and low-cost.

[0030] like Figure 1 As shown, the circuit in this embodiment includes:

[0031] Power switch QP1, pull-up resistor R1, button SW1, unidirectional conduction element D1, main processor and status latch switch Q1;

[0032] The switching control terminal of the power switch transistor QP1 is connected to a control node EN_G, the input terminal of the power switch transistor QP1 is connected to the power input terminal POWER_IN, and the output terminal of the power switch transistor QP1 is connected to the system power output terminal SYS_POWER.

[0033] One end of the pull-up resistor R1 is connected to the power input terminal POWER_IN, and the other end of the pull-up resistor R1 is connected to the control node EN_G;

[0034] One end of the button SW1 is grounded, the other end of the button SW1 is connected to the first end of the unidirectional conduction element D1, and the second end of the unidirectional conduction element D1 is connected to the control node EN_G.

[0035] The power supply terminal of the main processor is used to receive power from the system power output terminal SYS_POWER. The signal detection terminal of the main processor is connected to the connection node between the button SW1 and the unidirectional conduction element D1. The state control terminal of the main processor is connected to the latching control terminal of the state latching switch Q1.

[0036] The first path terminal of the state latching switch Q1 is connected to the control node EN_G, and the second path terminal of the state latching switch Q1 is grounded.

[0037] The core of the technical solution of this invention lies in constructing a power control network with the control node EN_G as the hub. The control node EN_G gathers the outputs of the pull-up resistor R1, the unidirectional conduction element D1 and the state latching switch Q1, which together determine the switching state of the power switch QP1. Through the main processor's detection of port GPIO-A and control of port GPIO-B, a complete hardware and software collaborative power-on and power-off logic is realized.

[0038] Specifically, the control node EN_G is directly connected to the switching control terminal of the power switch QP1 to control the on / off state of the power switch QP1. The input terminal of the power switch QP1 is connected to the power input terminal POWER_IN, and its output terminal is connected to the system power output terminal SYS_POWER, thus forming a controlled main power supply path. The system power output terminal SYS_POWER is connected to the input terminal of a power module. This power module may contain a linear regulator (LDO), a switching regulator (DC-DC), or a combination thereof, to convert the voltage of the system power output terminal SYS_POWER into one or more stable power supplies with different voltage values ​​(VCC1, VCC2, VCC3… as shown in the figure). At least one power supply (e.g., VCC1) directly supplies the power pin of the main processor to ensure that the main processor can work normally after the system is powered on; the other power supplies are used to power other peripheral circuits such as memory, sensors, and communication modules.

[0039] Pull-up resistor R1 is connected between the power input terminal POWER_IN and the control node EN_G. It is used to pull the control node EN_G high when there is no valid trigger, ensuring that the power switch QP1 is reliably turned off and the system is in a determined fully powered-off state.

[0040] The button SW1 and the unidirectional conduction element D1 form a hardware trigger path. One end of the button SW1 is grounded, and the other end is connected to the first end of the unidirectional conduction element D1. The second end of the unidirectional conduction element D1 is connected to the control node EN_G. The unidirectional conduction element D1 is used to reversely block the signal detection port GPIO-A level and the control node EN_G. That is, when the product is in operation and the button is not pressed, the signal detection port GPIO-A is at a high level and will not pull the control node EN_G low. When the button SW1 is pressed, the control node EN_G is pulled low, thereby turning on the power switch QP1.

[0041] The system's main processor has two ports: a signal detection port GPIO-A and a status control port GPIO-B. The signal detection port GPIO-A is configured as an input and connected to the junction of button SW1 and the first terminal of unidirectional conduction element D1 to detect the button's pressed state. The system's main processor's status control port GPIO-B is configured as an output and connected to the latch control terminal of status latch switch Q1 through a current-limiting resistor R3 to output a power sustaining signal.

[0042] The first path of the state latching switch Q1 is connected to the control node EN_G, and the second path is grounded. Its latching control terminal is connected to the state control port GPIO-B via a current-limiting resistor R3, thus accepting software control from the main processor. When the state control port GPIO-B outputs a high level, the state latching switch Q1 is turned on, locking the control node EN_G at a low level, thereby maintaining system power supply. Furthermore, a pull-down resistor R4 is connected between the latching control terminal of the state latching switch Q1 and ground. This is used to reliably pull the potential of the latching control terminal of the state latching switch Q1 low when the state control port GPIO-B outputs a low level or is in a high-impedance state, ensuring reliable cutoff and preventing malfunctions.

[0043] To ensure reliable circuit operation, the selection of key components must meet the following electrical requirements:

[0044] The pull-up resistor R1 is preferably in the range of 1kΩ to 1MΩ to achieve a balance between low static power consumption and reliable level control. Its specific value is determined based on the overall power consumption index of the device.

[0045] The power switch QP1 is a P-channel MOSFET. The gate (G), source (S), and drain (D) of the P-channel MOSFET correspond to the switching control terminal, input terminal, and output terminal of the power switch QP1, respectively. The absolute value of its gate threshold voltage must be less than the voltage of the power input terminal POWER_IN to ensure reliable conduction when triggered by a button. Its rated drain current must be greater than the maximum operating current of the system, such as AO3407.

[0046] The state latching switch Q1 is an NPN transistor. The base, collector, and emitter of the NPN transistor correspond to the latching control terminal, the first path terminal, and the second path terminal of the state latching switch Q1, respectively. The NPN transistor needs to have sufficient current amplification to ensure that it can be driven to the saturation conduction state by the current provided by the current limiting resistor R3 through the main processor's state control port GPIO-B. For example, MMBT3904.

[0047] The unidirectional conducting element D1 is a diode. The anode and cathode of the diode correspond to the first and second terminals of the unidirectional conducting element D1, respectively. Its selection must meet the following requirements: First, when the button is not pressed, its reverse cutoff characteristic should ensure that the POWER_IN level at the power input terminal does not interfere with the signal detection port GPIO-A of the main processor, allowing this port to remain stably within an acceptable high-level range. Second, when the button is pressed, its forward voltage drop must be less than the absolute value of the gate threshold voltage of the power switch QP1. Through the combined effect of these component parameters, the realization of circuit functionality and the stability of performance are guaranteed.

[0048] Example 2

[0049] This embodiment is based on the hardware and software combined button power-on / off circuit described in Embodiment 1, and details its power-on process.

[0050] The power-on process begins in a completely powered-off state, where the system has no power supply and the main processor is not working. Pull-up resistor R1 pulls the control node EN_G up to the high potential of the power input terminal POWER_IN, so that the voltage between the switching control terminal (i.e., gate G) and the input terminal (i.e., source S) of the power switch QP1 is lower than its turn-on threshold, and the power switch QP1 is in the off state.

[0051] When the user presses button SW1, the anode of the unidirectional conduction element D1 is grounded, and the cathode of the unidirectional conduction element D1, i.e., the EN_G node, is pulled low to a low level (approximately ground potential). This low level causes the voltage between the switching control terminal (i.e., gate G) and the input terminal (i.e., source S) of the power switch QP1 to meet its conduction threshold, and the power switch QP1 is then turned on. The power input terminal POWER_IN is connected to the system power output terminal SYS_POWER, the system starts to receive power, the power management module starts to work, and supplies power to the main processor and other circuits.

[0052] After the main processor receives power, it starts up and initializes its ports. At this time, its signal detection terminal GPIO-A is pulled low because button SW1 is pressed, and its status control terminal GPIO-B is initially at a low level, so that the status latch switch Q1 is in the off state because there is insufficient current at the latch control terminal (i.e., the base).

[0053] The software program inside the main processor continuously monitors the button status through its signal detection terminal GPIO-A. When the duration of the detected low level reaches a preset power-on threshold (e.g., 1 second), the software determines it as a valid power-on command. Subsequently, the main processor outputs a high-level signal through the status control terminal GPIO-B. This high-level signal drives the status latch switch Q1 into a saturated conduction state through the current-limiting resistor R3.

[0054] After the state latching switch Q1 is turned on, a low-impedance path is formed between its first path terminal (collector) and second path terminal (emitter), forcibly pulling the control node EN_G low again and maintaining it. At this point, even if the user releases button SW1, due to the unidirectional conductivity of the unidirectional conducting element D1, the level of the control node EN_G is no longer affected by button SW1, but is maintained at a low level by the turned-on state latching switch Q1. Therefore, the power switch QP1 remains on, the system power supply SYS_POWER continues, and the circuit enters a stable operating state, thus completing the power-on process triggered by hardware, judged by software, and ultimately locked by the hardware circuit.

[0055] Example 3

[0056] This embodiment is based on the hardware and software combined button power-on / off circuit described in Embodiment 1, and details its power-off process.

[0057] The shutdown process begins with the system in operation. In a stable operating state, the main processor's status control port GPIO-B outputs a high level, the status latch switch Q1 is in the on state, the control node EN_G is locked to a low level, and the power switch QP1 is in the on state.

[0058] When the user presses button SW1, the main processor's signal detection port GPIO-A is pulled low. The main processor's software program then monitors this low-level state and begins timing the duration of the low-level state. When the software detects that the duration of the low-level state of port GPIO-A reaches a preset shutdown threshold (e.g., 3 seconds), the software determines it as a valid shutdown command.

[0059] Subsequently, the main processor begins executing a system soft shutdown operation, including saving running data, closing running processes, and uninstalling drivers. Just before the main processor enters hibernation or shuts down, its software control status control port GPIO-B outputs a low level. This low level, combined with the pull-down resistor R4 connected to the base of the state latch switch Q1, causes the latch control terminal (i.e., the base) of state latch switch Q1 to lose its driving current, and state latch switch Q1 transitions from a saturated conduction state to a cutoff state. The first path terminal (i.e., collector) and the second path terminal (i.e., emitter) of state latch switch Q1 become high impedance, no longer pulling the control node EN_G low.

[0060] Since the state latch switch Q1 is off and the button SW1 is released (the unidirectional conducting element D1 is reverse-biased off), the control node EN_G is no longer forcibly pulled low by any path. The pull-up resistor R1 pulls the potential of the control node EN_G up to the high level of the power input terminal POWER_IN. This causes the voltage difference between the switching control terminal (i.e., gate G) and the input terminal (i.e., source S) of the power switch QP1 to fall below its conduction threshold. The power switch QP1 is immediately turned off, and the path between the power input terminal POWER_IN and the system power output terminal SYS_POWER is cut off. The system is thus completely powered down, and the circuit returns to its initial zero-power shutdown state.

[0061] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A hardware and software integrated push-button power switch circuit, characterized in that, include: Power switching transistors, pull-up resistors, buttons, unidirectional conduction components, main processor, and status latching switching transistors; The switching control terminal of the power switch is connected to a control node EN_G, the input terminal of the power switch is connected to the power input terminal POWER_IN, and the output terminal of the power switch is connected to the system power output terminal SYS_POWER. One end of the pull-up resistor is connected to the power input terminal POWER_IN, and the other end of the pull-up resistor is connected to the control node EN_G; One end of the button is grounded, the other end of the button is connected to the first end of the unidirectional conduction element, and the second end of the unidirectional conduction element is connected to the control node EN_G; The power supply terminal of the main processor is used to receive power from the system power output terminal SYS_POWER. The signal detection terminal of the main processor is connected to the connection node between the button and the unidirectional conduction element. The state control terminal of the main processor is connected to the latching control terminal of the state latching switch. The first path terminal of the state latching switch is connected to the control node EN_G, and the second path terminal of the state latching switch is grounded.

2. The hardware and software combined push-button power switch circuit according to claim 1, characterized in that, The power switch is a P-channel MOSFET, and the gate, source, and drain of the P-channel MOSFET constitute the switch control terminal, input terminal, and output terminal, respectively.

3. The hardware and software combined push-button power switch circuit according to claim 2, characterized in that, The absolute value of the gate threshold voltage of the P-channel MOS transistor is less than the voltage value at the power input terminal.

4. The hardware and software combined push-button power switch circuit according to claim 1, characterized in that, The unidirectional conducting element is a diode, and the anode and cathode of the diode constitute the first terminal and the second terminal, respectively.

5. A hardware and software combined button power switch circuit according to claims 2 and 4, characterized in that, The voltage value at the power input terminal minus the forward voltage drop of the diode is less than the absolute value of the gate threshold voltage of the P-channel MOSFET.

6. The hardware and software combined push-button power switch circuit according to claim 1, characterized in that, The state latching switch is an NPN transistor, and the base, collector, and emitter of the NPN transistor constitute the latching control terminal, the first path terminal, and the second path terminal, respectively.

7. The hardware and software combined push-button power switch circuit according to claim 6, characterized in that, It also includes a current-limiting resistor and a pull-down resistor. One end of the current-limiting resistor is connected to the status control terminal of the main processor, and the other end is connected to the base of the NPN transistor. One end of the pull-down resistor is connected to the base of the NPN transistor, and the other end is grounded.

8. A hardware and software combined push-button power switch circuit according to claims 2 and 6, characterized in that, The voltage value at the power input terminal minus the collector saturation voltage drop of the NPN transistor is less than the absolute value of the gate threshold voltage of the P-channel MOS transistor.

Images