Data encryption method and device, equipment and medium

Abstract

The invention discloses a data encryption method and device, equipment and a medium, and relates to the field of data encryption, in order to reduce waste of hardware resources and improve the utilization rate of the hardware resources, the data encryption method comprises the steps that message blocks of to-be-encrypted data are acquired, and any message block comprises an original message word; extending the message block by operating double adders in parallel and combining an SHA-256 algorithm to generate an extended message word, and performing iterative compression on the original message word and the generated extended message word in sequence to generate a target hash value corresponding to the message block; wherein the extension of the message block and the compression of the original message word and the generated extended message word are performed in parallel.

Description

Technical Field

[0001] This invention relates to the field of data encryption, and more particularly to a data encryption method, apparatus, device, and medium. Background Technology

[0002] The SHA-256 algorithm is a secure hash algorithm that maps messages or messages of arbitrary length to a 256-bit digest. This process is irreversible and has high security. Therefore, this algorithm is widely used in cryptography, blockchain, digital signatures and other fields.

[0003] The SHA-256 algorithm is mainly divided into three parts: data padding, data expansion, and data compression. In order to improve the running speed of the algorithm, the traditional hardware implementation method adopts a multi-adder independent architecture in the data expansion and data compression parts.

[0004] Data expansion and data compression are the core components of the SHA-256 algorithm. Data expansion aims to expand the original 16 32-bit message words of each message block into 64 32-bit extended message words to meet the iterative computation requirements of the compression phase. Data compression involves performing 64 iterative compression iterations on the 64 extended message words, progressively updating the data in the eight 32-bit registers, ultimately outputting a 256-bit hash value.

[0005] However, the traditional SHA-256 algorithm adopts a multi-adder independent architecture, designing the data expansion module and compression module independently. The expansion module and compression module together require 5 to 7 32-bit adders. Since the expansion module and compression module work serially, the adders in different modules are idle during non-working periods, resulting in wasted hardware resources and low utilization, making it unsuitable for resource-constrained scenarios such as embedded systems and the Internet of Things.

[0006] Therefore, how to reduce hardware resource waste and improve hardware resource utilization has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of the above-mentioned technological status, the present invention provides a data encryption method, apparatus, device and medium to reduce hardware resource waste and improve hardware resource utilization.

[0008] To achieve the above objectives, the present invention provides the following technical solution: A data encryption method includes: acquiring a message block of data to be encrypted, wherein any message block includes an original message word; expanding the message block by running a dual adder in parallel and combining it with the SHA-256 algorithm to generate an extended message word; and iteratively compressing the original message word and the generated extended message word sequentially to generate a target hash value corresponding to the message block; wherein the expansion of the message block and the compression of the original message word and the generated extended message word are performed in parallel.

[0009] In one optional embodiment of this application, the step of expanding the message block using the SHA-256 algorithm to generate an extended message word includes: using the SHA-256 algorithm, sequentially performing cyclic right shift, bitwise XOR, and addition operations on each original message word to generate the extended message word.

[0010] In one optional embodiment of this application, the step of iteratively compressing the original message word and the generated extended message word to generate the target hash value corresponding to the message block includes: updating the state register according to the initial hash value of the state register; compressing the first message word of the message block using the SHA-256 algorithm through the first adder and / or the second adder, combined with the updated register state, to generate the first intermediate state of the register for the first iteration of compression; compressing the t-th message word of the message block using the SHA-256 algorithm through the first adder and / or the second adder, combined with the intermediate state of the register, to generate the t-th intermediate state of the state register, until all message words are traversed to generate the target state of the state register; and generating the target hash value of the message block according to the initial hash value of the register and the target state of the state register.

[0011] In one optional embodiment of this application, updating the status register according to the initial hash value of the register includes: determining whether the message block is the first message block of the data to be encrypted; if the data to be encrypted is the first message block, updating the status register according to the preset initial hash value; if the data to be encrypted is an intermediate message block or a tail message block, updating the status register by using the hash value corresponding to the previous message block as the initial hash value.

[0012] In one optional embodiment of this application, generating the target hash value of the message block based on the initial hash value of the register and the target state of the status register includes: generating the target hash value of the message block by correspondingly adding the target state of the status register and the initial hash value of the register through parallel execution of a double adder.

[0013] In one optional embodiment of this application, the step of using the SHA-256 algorithm, combined with the updated register state, to compress the first message word of the message block and generate the first intermediate state of the state register for the first iteration of compression includes: using the SHA-256 algorithm, based on the initial hash value of the register, calling a double adder to alternately execute the compression operation of the SHA-256 algorithm to complete the compression of the first message word of the message block and generate the first intermediate state of the state register for the first iteration of compression.

[0014] In one optional embodiment of this application, obtaining the message block of the data to be encrypted includes: according to the SHA-256 standard, sequentially performing padding operations such as adding padding identifiers, padding with zero bits, and concatenating padding operations to the original length of the data to be encrypted to generate data to be encrypted that is a multiple of 512 bits; splitting the data to be encrypted that is a multiple of 512 bits to obtain N 512-bit message blocks.

[0015] Compared with the prior art, the present invention provides...

[0016] The data encryption method provided by this invention breaks through the architectural limitations of the traditional SHA-256 hardware implementation, which involves the serial execution of message expansion and compression. Through a dual-adder parallel operation mechanism, the expansion process of the message block is synchronized with the iterative compression process of the original message word and the expanded message word. While generating the expanded message word, the corresponding message word compression iteration is completed simultaneously, eliminating the need to wait for the entire expansion to be completed before starting compression. This significantly reduces the overall processing cycle of a single message block, thereby improving the overall encryption rate of the data to be encrypted and meeting the needs of high-throughput data encryption scenarios. Furthermore, the dual-adder multiplexing design allows two adders to simultaneously perform expansion and compression operations, eliminating the need for separate adder arrays for the expansion and compression modules. Compared to existing SHA-256 hardware designs, this reduces the number of adders and chip area, minimizing hardware resource waste.

[0017] The present invention also provides a data encryption device, comprising: A data acquisition unit is used to acquire message blocks of data to be encrypted, wherein any message block includes an original message word.

[0018] The compression iteration unit is used to expand the message block by running a dual adder in parallel and combining it with the SHA-256 algorithm to generate an extended message word, and to iteratively compress the original message word and the generated extended message word in sequence to generate the target hash value corresponding to the message block; wherein, the expansion of the message block and the compression of the original message word and the generated extended message word are executed in parallel.

[0019] Compared with the prior art, the beneficial effects of the data encryption device provided by the present invention are the same as those of the data encryption method described in the above technical solutions, and will not be repeated here.

[0020] The present invention also provides an electronic device, comprising: a processor; a memory for storing processor-executable instructions; the processor being configured to execute the above-described data encryption method by running the instructions in the memory.

[0021] Compared with the prior art, the beneficial effects of the electronic device provided by the present invention are the same as those of the data encryption method described in the above technical solution, and will not be repeated here.

[0022] The present invention also provides a computer storage medium storing instructions that, when executed, implement the above-described data encryption method.

[0023] Compared with the prior art, the beneficial effects of the computer storage medium provided by the present invention are the same as those of the data encryption method described in the above technical solutions, and will not be repeated here. Attached Figure Description

[0024] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, are illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention.

[0025] Figure 1 A flowchart illustrating the data encryption method provided in this application embodiment.

[0026] Figure 2 This is a structural diagram of a data encryption system provided in an embodiment of this application.

[0027] Figure 3 This is a schematic diagram illustrating the updating of a hash value, as provided in an embodiment of this application.

[0028] Figure 4 This is a structural diagram of a data encryption device provided in an embodiment of this application.

[0029] Figure 5 This is a schematic diagram of an electronic device structure provided in an embodiment of this application. Detailed Implementation

[0030] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0031] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0032] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0033] The SHA-256 algorithm is a secure hash algorithm that maps messages or messages of arbitrary length to a 256-bit digest. This process is irreversible and has high security. Therefore, this algorithm is widely used in cryptography, blockchain, digital signatures and other fields.

[0034] The SHA-256 algorithm is mainly divided into three parts: data padding, data expansion, and data compression. In order to improve the running speed of the algorithm, the traditional hardware implementation method adopts a multi-adder independent architecture in the data expansion and data compression parts.

[0035] Data expansion and data compression are the core components of the SHA-256 algorithm.

[0036] The goal of data expansion is to expand the 16 original 32-bit message words of each message block into 64 extended 32-bit message words to meet the iterative operation requirements of the compression stage.

[0037] The extended parts are shown in the following formulas (1) to (3): (1); (2); (3); in, This represents the expanded message word; This represents the t-th 32-bit message word of the i-th message block after data padding. This means circularly shifting the message word x to the right by n bits; This means shifting the message word x to the right by n bits.

[0038] Based on the above formulas (1) to (3), it can be seen that for the expansion of each message block, three 32-bit addition operations are required, and the entire expansion process requires a total of 48 × 3 additions. In this process, traditional algorithms usually set up 2 to 3 independent 32-bit adders to complete the expansion of the message word.

[0039] Data compression is achieved by performing 64 iterative compression cycles on 64 extended message words, progressively compressing the initial state of eight 32-bit compression status registers, and finally outputting a 256-bit hash value.

[0040] The iterative compression process uses eight 32-bit compression status registers (a, b, c, d, e, f, g, h) and 64 32-bit fixed constants. (t is a natural number less than or equal to 63) is compressed, and the compressed part is as follows: Formula group (4), and formulas (5) to (8): (4); Where t is a natural number less than or equal to 63; a, b, c, d, e, f, g, and h represent the data in each register, respectively; , , , This indicates an intermediate state of message block compression.

[0041] (5); (6); (7); (8); As can be seen from the above formula group (4), each compression requires 7 additions, and the entire compression process involves 64 extended message words, that is, the entire compression process requires a total of 64×7 additions. In order to achieve the compression of extended message words, the existing technology usually sets up 3 to 4 independent 32-bit adders.

[0042] Based on the above introduction to data expansion and compression, it can be seen that the traditional SHA-256 algorithm adopts a multi-adder independent architecture, designing the data expansion module and compression module independently. The expansion module and compression module together require 5 to 7 32-bit adders. Since the expansion module and compression module work serially, the adders in different modules are idle during non-working periods, resulting in wasted hardware resources and low utilization, making it unsuitable for resource-constrained scenarios such as embedded systems and the Internet of Things.

[0043] Therefore, how to reduce hardware resource waste and improve hardware resource utilization has become a technical problem that urgently needs to be solved by those skilled in the art.

[0044] To address the aforementioned technical problems, this application provides a data encryption method, apparatus, device, and medium, which will be described in detail in the following embodiments.

[0045] Please refer to Figure 1 , Figure 1 A flowchart illustrating the data encryption method provided in this application embodiment.

[0046] like Figure 1 As shown, the data encryption method includes the following S101 and S102.

[0047] S101, Obtain the message block of the data to be encrypted, wherein any message block includes the original message word.

[0048] The data to be encrypted refers to the original data that needs to be hashed using the SHA-256 algorithm. In this embodiment, the data to be encrypted can be a binary data stream of arbitrary length and format. The purpose of the SHA-256 algorithm is to generate a unique hash value corresponding to the data to be encrypted through irreversible hash operations, for use in scenarios such as data integrity correction, identity verification, and digital signatures. In practical applications, the data to be encrypted can be image data, audio data, video data, etc., and this application does not impose any restrictions on this.

[0049] Specifically, S101 includes: according to the SHA-256 standard, sequentially performing padding operations such as adding padding identifiers, filling zero bits, and concatenating padding operations to the data to be encrypted to generate data to be encrypted that is a multiple of 512 bits; splitting the data to be encrypted that is a multiple of 512 bits to obtain N 512-bit message blocks.

[0050] Specifically, the step of sequentially performing padding operations on the data to be encrypted, including adding padding markers, filling with zero bits, and concatenating the original length of the data to be encrypted, includes: First, determine the length L of the data to be encrypted; second, add a padding marker (1 bit "1") to the end of the data; then, fill in K bits of "0" until... (That is, the total number of L+1+K is divided by 512, and the remainder is 448); Finally, the length L of the original data to be encrypted is converted into a 64-bit unsigned integer and padded to the end of the data to be encrypted after "padding K bits of '0'", thus generating data to be encrypted that is a multiple of 512 bits.

[0051] In one optional embodiment of this application, the data encryption method can be as follows: Figure 2 The hardware module shown is implemented.

[0052] Please refer to Figure 2 , Figure 2 This is a structural diagram of a data encryption system provided in an embodiment of this application.

[0053] like Figure 2 As shown, the data encryption system includes: a message preprocessing module 201 and an extended compression module 202.

[0054] The above-mentioned S101 is implemented by the message preprocessing module 201.

[0055] The message preprocessing module 201 includes: a counting control unit, a block filling unit, and a mark handshake control unit.

[0056] The message preprocessing module 201 receives the data to be encrypted and sends it to the counting control unit so that the counting control unit can count the length of the data to be encrypted; it starts the block padding unit to pad the data according to the SHA-256 standard so that the length of the data to be encrypted is an integer multiple of 512 bits, and then splits the padded data into N 512-bit message blocks.

[0057] After the block filling unit completes the block division, the mark handshake control unit sends the start signal and the message block containing block marks (including three types: first message block, middle message block and tail message block) to the extended compression module 202, so that the extended compression module 202 can complete the following S102.

[0058] S102, by running dual adders in parallel and combining them with the SHA-256 algorithm to expand the message block and generate an extended message word, and by iteratively compressing the original message word and the generated extended message word in sequence, the target hash value corresponding to the message block is generated; wherein, the expansion of the message block and the compression of the original message word and the generated extended message word are performed in parallel.

[0059] Unlike existing technologies that use multiple independent adders to perform message block expansion and compression separately, the dual adder in this application includes two adders: a first adder and a second adder, which perform addition operations in parallel to complete message block expansion and compression.

[0060] Specifically, the message block is expanded using the SHA-256 algorithm to generate an extended message word, including: using the SHA-256 algorithm, each original message word is sequentially processed by cyclic right shift, bitwise XOR, and addition operations to generate the extended message word.

[0061] Further, the original message word and the generated extended message word are iteratively compressed sequentially to generate the target hash value corresponding to the message block, including: updating the state register according to the initial hash value of the state register; compressing the first message word of the message block using the SHA-256 algorithm through the first adder and / or the second adder, combined with the updated register state, to generate the first intermediate state of the state register for the first iteration of compression; compressing the t-th message word of the message block using the SHA-256 algorithm through the first adder and / or the second adder, combined with the intermediate register state, to generate the t-th intermediate state of the state register, until all message words are traversed to generate the target state of the state register; and generating the target hash value of the message block according to the initial hash value of the state register and the target state of the state register.

[0062] The process of updating the register state includes: determining whether the message block is the first message block of the data to be encrypted; if the data to be encrypted is the first message block, updating the state register according to a preset initial hash value; if the data to be encrypted is an intermediate message block or a tail message block, updating the state register using the target hash value corresponding to the previous message block as the initial hash value.

[0063] The step of compressing the first message word of the message block using the SHA-256 algorithm through the first adder and / or the second adder, combined with the updated register state, to generate the first intermediate state of the state register for the first iteration of compression includes: using the SHA-256 algorithm, based on the initial hash value of the state register, calling the dual adders to alternately execute the SHA-256 algorithm compression operation to complete the compression of the first message word of the message block and generate the first intermediate state of the state register for the first iteration of compression.

[0064] The step of generating the target hash value of the message block based on the initial hash value of the status register and the target state of the status register includes: generating the target hash value of the message block by correspondingly adding the target state of the status register and the initial hash value of the status register through parallel execution of a double adder.

[0065] For more details, please refer to the following information. Figure 2 The following is based on Figure 2 The expansion and compression of message words are described. The expansion and compression module 202 includes: a control module, a message buffer, a first adder, a second adder, a fixed constant array, a register group, and a hash value.

[0066] The control module is specifically a finite state machine (FSM) responsible for scheduling hardware components such as two adders, register sets, and message buffers.

[0067] After receiving the aforementioned start signal and the original message block containing the block marker, the control module transitions from the idle state to the initialization state.

[0068] In practical applications, upon receiving a message block Then, firstly, it is determined whether the message block is the first message block of the data to be encrypted; if the determination result is the first message block, the SHA-256 standard initial hash value (i.e., the preset initial hash value) is loaded into the compression status register to update the initial state of the status register.

[0069] The compressed status registers include: status registers a, b, c, d, e, f, g, and h. The register group also includes: intermediate register m.

[0070] In one optional embodiment of this application, the initial hash value is: ; ; ; ; ; ; ; .

[0071] Loading the initial hash value specifically involves the above... to Load them into status registers a, b, c, d, e, f, g, and h respectively.

[0072] If the result of the judgment is an intermediate message block or a tail message block, then load the previous message block. The compressed hash values ​​are stored in status register groups a, b, c, d, e, f, g, h.

[0073] In practical applications, for each 512-bit message block, the message block is first divided into 16 32-bit original message words in sequence, denoted as... to Message block expansion refers to performing 48 data expansion operations using the SHA-256 algorithm on the original message word to generate 48 32-bit extended message words, denoted as... to Compression of message blocks involves compressing each message word in the order of the original message word and the generated extended message word, and finally generating the target hash value corresponding to the message block.

[0074] However, it should be noted that in the embodiments of this application, the expansion and compression of the message block are performed simultaneously. During the expansion and compression process, two adders are run simultaneously to execute the SHA-256 algorithm.

[0075] Specifically, the algorithms used for message block expansion and compression are basically the same as those in formulas (1) to (8) above. However, since message block expansion occurs only 48 times and message block compression occurs 64 times, expansion and compression can be performed simultaneously in the first 48 rounds of adder scheduling, while compression is performed only for the last 16 expanded message words in the last 16 rounds of adder scheduling.

[0076] First, in the first 48 rounds of adder scheduling, in order to implement the SHA-256 algorithm as shown in formulas (1) to (8) above, each round of adder scheduling includes 6 scheduling cycles.

[0077] The algorithm corresponding to scheduling period 1 is as follows: ; .

[0078] Scheduling cycle 1 is part of message word compression, in which, ; ; h, f, and g represent the data corresponding to the status register.

[0079] This indicates that the data in the status register h and the t-th message word will be... The calculation is performed by the first adder, and the result is then stored in the status register h.

[0080] This indicates the result of a bitwise XOR operation after the data in the status register e is cyclically right-shifted by 6 bits, 11 bits, and 25 bits respectively.

[0081] This represents the result of a bitwise AND operation between the data in status registers e and f; This represents the result of bitwise ANDing the inverted bits in status register e with the 32-bit data in status register g. Indicates will and The result of bitwise XOR.

[0082] , indicating that and The calculation is performed in the second adder, and the result is then stored in the intermediate register m.

[0083] The algorithm corresponding to scheduling period 2 is as follows: ; .

[0084] (Right now, (), is part of message word compression, indicating that the data in status register h and status register m are scheduled to the first adder for calculation, and then the calculation result is stored in status register h.

[0085] It is part of the message block extension, t is greater than or equal to 16. In the first round of adder scheduling, t equals 16. At this time, , This indicates that the 15th message word will be... The results of bitwise XOR operations performed after circularly shifting right by 7 bits, 18 bits, and 3 bits respectively; This indicates the 10th message character. .

[0086] Indicates will and The operation is scheduled to the second adder, and the result is stored in the status register m.

[0087] The algorithm corresponding to scheduling period 3 is as follows: ; .

[0088] (Right now, (), is part of message word compression, representing the compression of the data in the status register h and the t-th fixed constant in the fixed constant array. The calculation is performed in the first adder, and the result is then stored in the status register h.

[0089] (Right now, + ) is part of the message block extension; t is greater than or equal to 16. In the first round of adder scheduling, t equals 16. At this time, , This indicates that the second message word The results of bitwise XOR operations after circular right shifts of 17, 19, and 10 bits.

[0090] This indicates that the data in the status register m and The operation is scheduled to the second adder and the result is stored in the status register m.

[0091] The algorithm corresponding to scheduling period 4 is as follows: ; .

[0092] (Right now, () is part of message word compression, indicating that the data in status register h and status register d are scheduled to the first adder for calculation, and then the calculation result is stored in status register h.

[0093] (Right now, + + ) is part of the message block extension; t is greater than or equal to 16. In the first round of adder scheduling, t equals 16. At this time, .

[0094] This means that the data in the status register m and the data of the (t-16th)th message word are scheduled to the second adder for operation, and the result is stored in the status register m.

[0095] The algorithm corresponding to scheduling period 5 is as follows: .

[0096] As shown in formula (6) mentioned above ,in, This indicates the result of a bitwise XOR operation after the data in status register a is cyclically right-shifted by 2 bits, 13 bits, and 22 bits respectively.

[0097] (Right now, +S0) is part of message word compression, indicating that the data in the status register h and S0 are scheduled to the first adder or the second adder for operation, and the result is stored in the status register h.

[0098] The algorithm corresponding to scheduling period 6 is as follows: .

[0099] As shown in formula (8) above. .in, This represents the result of a bitwise AND operation between the data in status register a and status register f; This represents the result of a bitwise AND operation between the data in status register a and status register f; This represents the result of a bitwise AND operation between the data in status register b and status register c. Indicates will , , The result of performing a bitwise XOR operation.

[0100] (Right now, +S0+ This is the last part of message word compression, thus completing the compression of a message word (i.e., the compression of the message word as shown in formula (4)). This means that the data in the status register h and The operation is scheduled to the first adder or the second adder, and the result is stored in the status register h.

[0101] Since the message block is expanded only 48 times, after scheduling the first 48 rounds of adders, all the extended message words can be generated, and the compression of the first 48 original message words and extended message words can be completed.

[0102] In the last 16 rounds of adder scheduling, message block expansion is no longer performed.

[0103] Specifically, the scheduling of each adder in the last 16 rounds involves a total of 4 scheduling cycles.

[0104] The algorithm corresponding to scheduling period 1 is as follows: ; Where t is greater than or equal to 48.

[0105] This means scheduling the data in the status register h and the t-th message block to the first adder for operation, and storing the result in the status register h; Indicates will and The operation is scheduled to the second adder and the result is stored in the status register m.

[0106] The algorithm corresponding to scheduling period 2 is as follows: ; .

[0107] (Right now, This means that the data in status register h and status register m are scheduled to the first adder for operation, and the result is stored in status register h. Indicates will and The operation is scheduled to the first adder and the result is stored in the status register m.

[0108] The algorithm corresponding to scheduling period 3 is as follows: Where t is greater than or equal to 48.

[0109] (Right now, This indicates that the data in the status register h and the t-th fixed constant are combined. The calculation is performed in the first adder, and the result is then stored in the status register h.

[0110] The algorithm corresponding to scheduling period 4 is as follows: h; .

[0111] h (i.e., This means that the data in status register h and status register d are scheduled to the first adder for operation, and the result is stored in status register d. (Right now, This means that the data in the status register h and the data in the status register m are scheduled to the second adder for operation, and the result is stored in the status register h.

[0112] Thus, completing the aforementioned 64 rounds of adder scheduling completes the expansion and compression of this message block.

[0113] In the process of expanding and compressing the next message block, the status registers are first updated.

[0114] In the embodiments of this application, the updates of each status register follow the following rules: a→b, b→c, c→d, d→f, f→e, e→g, g→h, h→a.

[0115] After updating the status register, the adder is scheduled in the same manner as described above to complete the expansion and compression of the next message block.

[0116] After each expansion and compression of a message block, the hash values ​​of each status register need to be updated.

[0117] For the first message block, the hash value can be updated using the preset initial hash value and the target state of each status register after the first message block is compressed.

[0118] For intermediate or tail message blocks, the hash value can be updated using the hash value updated in the previous message block and the target state of each status register after the message block is compressed. Finally, by traversing each message block, a 256-bit hash value is generated.

[0119] For details, please refer to Figure 3 , Figure 3 This is a schematic diagram illustrating the updating of a hash value, as provided in an embodiment of this application.

[0120] like Figure 3 As shown, Figure 3 Includes hash value , , , , , , , Status registers a, b, c, d, e, f, g, h; updated hash value , , , , , , , .

[0121] The hash value update is also based on the first and second adders. Specifically, a total of four rounds of adder scheduling are designed in the hash value update process.

[0122] The first round of adder scheduling includes: ; .

[0123] That is, the hash value The target state of status register a is scheduled to the first adder to complete the hash value. Update; change the hash value The target state of status register b is scheduled to the second adder to complete the hash value. Update.

[0124] The second round of adder scheduling includes: ; .

[0125] That is, the hash value The target state of the status register c is scheduled to the first adder to complete the hash value. Update; change the hash value The target state of the status register d is scheduled to the second adder to complete the hash value. Update.

[0126] The third round of adder scheduling includes: ; .

[0127] That is, the hash value The target state of the status register e is scheduled to the first adder to complete the hash value. Update; change the hash value The target state of the status register f is scheduled to the second adder to complete the hash value. Update.

[0128] The fourth round of adder scheduling includes: ; .

[0129] That is, the hash value The target state of the status register g is scheduled to the first adder to complete the hash value. Update; change the hash value The target state of the status register h is scheduled to the second adder to complete the hash value. Update.

[0130] After updating the hash value of each expanded and compressed message block in sequence, the final output 256-bit hash value can be obtained.

[0131] In summary, the data encryption method provided by this invention in the embodiments of this application breaks through the architectural limitations of the serial execution of message expansion and compression in traditional SHA-256 hardware implementations. Through a dual-adder parallel operation mechanism, the expansion process of the message block is synchronized with the iterative compression process of the original message word and the expanded message word. While generating the expanded message word, the corresponding message word compression iteration is completed simultaneously, eliminating the need to wait for the entire expansion to be completed before starting compression. This significantly reduces the overall processing cycle of a single message block, thereby improving the overall encryption rate of the data to be encrypted and meeting the needs of high-throughput data encryption scenarios. Furthermore, the dual-adder multiplexing design allows two adders to simultaneously perform expansion and compression operations, eliminating the need to configure separate adder arrays for the expansion and compression modules. Compared to existing SHA-256 hardware designs, this reduces the number of adders and chip area, minimizing hardware resource waste.

[0132] This application also provides a data encryption device, please refer to... Figure 4 , Figure 4 This is a structural diagram of a data encryption device provided in an embodiment of this application.

[0133] like Figure 4 As shown, the data encryption device includes: The data acquisition unit 401 is used to acquire message blocks of data to be encrypted, wherein any message block includes the original message word.

[0134] The compression iteration unit 402 is used to expand the message block by running a dual adder in parallel and combining it with the SHA-256 algorithm to generate an extended message word, and to iteratively compress the original message word and the generated extended message word in sequence to generate the target hash value corresponding to the message block; wherein, the expansion of the message block and the compression of the original message word and the generated extended message word are executed in parallel.

[0135] In one optional embodiment of this application, the step of expanding the message block using the SHA-256 algorithm to generate an extended message word includes: using the SHA-256 algorithm, sequentially performing cyclic right shift, bitwise XOR, and addition operations on each original message word to generate the extended message word.

[0136] In one optional embodiment of this application, the step of iteratively compressing the original message word and the generated extended message word to generate the target hash value corresponding to the message block includes: updating the state register according to the initial hash value of the state register; compressing the first message word of the message block using the SHA-256 algorithm through the first adder and / or the second adder, combined with the updated register state, to generate the first intermediate state of the register for the first iteration of compression; compressing the t-th message word of the message block using the SHA-256 algorithm through the first adder and / or the second adder, combined with the intermediate state of the register, to generate the t-th intermediate state of the state register, until all message words are traversed to generate the target state of the state register; and generating the target hash value of the message block according to the initial hash value of the register and the target state of the state register.

[0137] In one optional embodiment of this application, updating the status register according to the initial hash value of the register includes: determining whether the message block is the first message block of the data to be encrypted; if the data to be encrypted is the first message block, updating the status register according to the preset initial hash value; if the data to be encrypted is an intermediate message block or a tail message block, updating the status register by using the hash value corresponding to the previous message block as the initial hash value.

[0138] In one optional embodiment of this application, generating the target hash value of the message block based on the initial hash value of the register and the target state of the status register includes: generating the target hash value of the message block by correspondingly adding the target state of the status register and the initial hash value of the register through parallel execution of a double adder.

[0139] In one optional embodiment of this application, the step of using the SHA-256 algorithm, combined with the updated register state, to compress the first message word of the message block and generate the first intermediate state of the state register for the first iteration of compression includes: using the SHA-256 algorithm, based on the initial hash value of the register, calling a double adder to alternately execute the compression operation of the SHA-256 algorithm to complete the compression of the first message word of the message block and generate the first intermediate state of the state register for the first iteration of compression.

[0140] In one optional embodiment of this application, obtaining the message block of the data to be encrypted includes: according to the SHA-256 standard, sequentially performing padding operations such as adding padding identifiers, padding with zero bits, and concatenating padding operations to the original length of the data to be encrypted to generate data to be encrypted that is a multiple of 512 bits; splitting the data to be encrypted that is a multiple of 512 bits to obtain N 512-bit message blocks.

[0141] The device embodiment provided in this example belongs to the same application concept as the method embodiment of this application, and can execute the data encryption method provided in any of the above embodiments of this application, possessing the corresponding functional modules and beneficial effects for executing the data encryption method. Technical details not described in detail in this example can be found in the specific processing content of the data encryption method provided in the above embodiments of this application, and will not be repeated here.

[0142] It should be understood that the units in the above device can be implemented by a processor calling software. For example, the device includes a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above methods or to implement the functions of each unit in the device. The processor can be a general-purpose processor, such as a CPU or microprocessor, and the memory can be internal or external to the device. Alternatively, the units in the device can be implemented as hardware circuits. By designing the hardware circuits, some or all of the unit functions can be implemented. The hardware circuits can be understood as one or more processors. For example, in one implementation, the hardware circuit is an ASIC, and the functions of some or all of the above units are implemented by designing the logical relationships between the components within the circuit. In another implementation, the hardware circuit can be implemented using a PLD, such as an FPGA, which can include a large number of logic gates. The connection relationships between the logic gates are configured through configuration files to implement the functions of some or all of the above units. All units in the above device can be implemented entirely by a processor calling software, entirely by hardware circuits, or partially by a processor calling software with the remaining parts implemented by hardware circuits.

[0143] In this application embodiment, a processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction reading and execution capabilities, such as a CPU, microprocessor, GPU, or DSP. In another implementation, the processor can implement certain functions through the logical relationships of hardware circuits. These logical relationships are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the processor loading instructions to implement the functions of some or all of the above units. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as an NPU, TPU, or DPU.

[0144] As can be seen, each unit in the above device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0145] Furthermore, the units in the above devices can be integrated in whole or in part, or they can be implemented independently. In one implementation, these units are integrated together and implemented in the form of a System-on-Chip (SoC). The SoC may include at least one processor for implementing any of the above methods or implementing the functions of the units in the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0146] This application also provides an electronic device, such as... Figure 5 As shown, Figure 5 This is a schematic diagram of an electronic device structure provided in an embodiment of this application.

[0147] like Figure 5 As shown, the electronic device includes: Processor 210.

[0148] Memory 200 for storing executable instructions of the processor 210.

[0149] The processor 210 is configured to execute the data encryption method disclosed in any of the above embodiments by running instructions in the memory 200.

[0150] The processor 210, memory 200, communication interface 220, input device 230, and output device 240 are interconnected via a bus. Among them: A bus can include a pathway for transmitting information between various components of a computer system.

[0151] Processor 210 can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0152] Processor 210 may include a main processor, as well as a baseband chip, modem, etc.

[0153] The memory 200 stores a program that executes the technical solution of this invention, and may also store an operating system and other key business functions. Specifically, the program may include program code, which includes computer operation instructions. More specifically, the memory 200 may include read-only memory (ROM), other types of static storage devices capable of storing static information and instructions, random access memory (RAM), other types of dynamic storage devices capable of storing information and instructions, disk storage, flash memory, etc.

[0154] Input device 230 may include a device for receiving user input data and information, such as a keyboard, mouse, camera, scanner, touch screen, etc.

[0155] Output device 240 may include devices that allow information to be output to a user, such as a display screen, printer, speaker, etc.

[0156] The communication interface 220 may include a device that uses any transceiver to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0157] The processor 210 executes the program stored in the memory 200 and calls other devices, and can be used to implement each step of any of the data encryption methods provided in the above embodiments of this application.

[0158] In addition to the methods and devices described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the data encryption methods of various embodiments of this application.

[0159] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0160] Furthermore, embodiments of this application may also be storage media storing a computer program thereon, the computer program being executed by a processor of the steps in the data encryption methods of various embodiments of this application.

[0161] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0162] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0163] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0164] The modules and sub-modules in the apparatus and terminal in the various embodiments of this application can be merged, divided, and deleted according to actual needs.

[0165] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0166] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data encryption method, characterized in that, include: Obtain a message block containing the data to be encrypted, wherein any of the message blocks includes the original message word; The message block is expanded by running a dual adder in parallel, combined with the SHA-256 algorithm, to generate an extended message word. The original message word and the generated extended message word are then iteratively compressed sequentially to generate the target hash value corresponding to the message block. The expansion of the message block and the compression of the original message word and the generated extended message word are performed in parallel.

2. The data encryption method according to claim 1, characterized in that, The step of expanding the message block using the SHA-256 algorithm to generate an extended message word includes: By combining the SHA-256 algorithm, the extended message word is generated by sequentially performing a right circular shift, bitwise XOR, and addition operation on each original message word.

3. The data encryption method according to claim 1, characterized in that, The step of iteratively compressing the original message word and the generated extended message word sequentially to generate the target hash value corresponding to the message block includes: Update the status register based on its initial hash value. Using the first adder and / or the second adder, the SHA-256 algorithm is employed, combined with the updated register state, to compress the first message word of the message block, generating the first intermediate register state for the first iteration of compression. Using the first adder and / or the second adder, the SHA-256 algorithm is employed, combined with the intermediate state of the register, to compress the t-th message word of the message block, thereby generating the t-th intermediate state of the state register, until each message word is traversed to generate the target state of the state register. The target hash value of the message block is generated based on the initial hash value of the register and the target state of the status register.

4. The data encryption method according to claim 3, characterized in that, The step of updating the status register based on the initial hash value of the register includes: Determine whether the message block is the first message block of the data to be encrypted; If the data to be encrypted is the first message block, the status register is updated according to the preset initial hash value. If the data to be encrypted is an intermediate message block or a tail message block, the hash value corresponding to the previous message block is used as the initial hash value to update the status register.

5. The data encryption method according to claim 3, characterized in that, The step of generating the target hash value of the message block based on the initial hash value of the register and the target state of the status register includes: By running a dual adder in parallel, the target state of the status register and the initial hash value of the register are accumulated to generate the target hash value of the message block.

6. The data encryption method according to claim 3, characterized in that, The method employs the SHA-256 algorithm, combined with the updated register state, to compress the first message word of the message block, generating the first intermediate state of the state register for the first iteration of compression, including: Using the SHA-256 algorithm, based on the initial hash value of the register, the dual adders are called to alternately perform the compression operation of the SHA-256 algorithm to complete the compression of the first message word of the message block and generate the first intermediate state of the state register of the first iteration compression.

7. The data encryption method according to claim 1, characterized in that, The message block for obtaining the data to be encrypted includes: According to the SHA-256 standard, the data to be encrypted is sequentially subjected to the following operations: adding padding flags, padding with zero bits, and concatenating the padding operations to the original length of the data to be encrypted, so as to generate data to be encrypted that is a multiple of 512 bits. The data to be encrypted that is a multiple of 512 bits is split into N 512-bit message blocks.

8. A data encryption device, characterized in that, include: A data acquisition unit is used to acquire message blocks of data to be encrypted, wherein any message block includes an original message word; The compression iteration unit is used to expand the message block by running a dual adder in parallel and combining it with the SHA-256 algorithm to generate an extended message word, and to iteratively compress the original message word and the generated extended message word in sequence to generate the target hash value corresponding to the message block; wherein, the expansion of the message block and the compression of the original message word and the generated extended message word are executed in parallel.

9. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the data encryption method according to any one of claims 1 to 7 by running instructions in the memory.

10. A computer storage medium, characterized in that, The computer storage medium stores instructions that, when executed, implement the data encryption method according to any one of claims 1 to 7.

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