Symbol and timing recovery devices and related methods

Abstract

The invention relates to symbol and timing recovery devices and related methods. An example apparatus (102) includes: a feed-forward equalizer (FFE) (122) having an FFE output; an adder circuit (124) having a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output; a multiplexer (MUX) (126) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output; a decision feedback equalizer (DFE) (130) having a DFE output coupled to the second adder input; and a timing error detector (TED) (136) having a first TED input coupled to the MUX output.

Description

[0001] Information related to divisional application This invention is a divisional application of the invention patent application filed on September 1, 2021, with application number 202180054154.7 and title "Symbol and Timing Recovery Device and Related Method". Technical Field

[0002] This instruction generally relates to symbolic and timed recovery, and more specifically to symbolic and timed recovery devices and related methods. Background Technology

[0003] Some wireless and wired receivers (such as Ethernet physical layer (PHY)) implement symbol and timing recovery techniques to facilitate communication between devices. Some Ethernet PHYs are oversampling systems that use robust clock synchronization techniques to achieve robust timing loop synchronization performance, a parameter associated with improved link-on time and bit error rate (BER) performance. Some Ethernet PHYs utilize a one-sample-per-symbol system architecture to reduce costs in terms of area and power. Some of these Ethernet PHYs do not have robust timing loop synchronization performance. Summary of the Invention

[0004] For symbol and timing recovery devices and related methods, an example device includes: a feedforward equalizer (FFE) having an FFE output; an adder circuit having a first adder input, a second adder input, and a first adder output, the first adder input being coupled to the FFE output; a multiplexer (MUX) having a first MUX input, a second MUX input, and a MUX output, the first MUX input being coupled to the first adder output, and the second MUX input being coupled to the FFE output; a decision feedback equalizer (DFE) having a DFE output coupled to the second adder input; and a timing error detector (TED) having a first TED input coupled to the MUX output. Attached Figure Description

[0005] Figure 1 This is a block diagram of an example implementation of a communication system utilizing a digital signal processor (DSP), which includes a timing error detector (TED) capable of implementing symbol and timing recovery techniques.

[0006] Figure 2 yes Figure 1 A block diagram of an example implementation of TED.

[0007] Figure 3 It is possible to be Figure 1 DSP and / or Figure 1The TED execution of 2 and / or 2 is used to execute the first instance symbol and the first timing diagram and instance pseudocode of the timing recovery technique.

[0008] Figure 4 It is possible to be Figure 1 DSP and / or Figure 1 The TED execution of 2 and / or 2 is used to execute the second instance symbol and the second timing diagram and instance pseudocode of the timing recovery technique.

[0009] Figure 5 It is possible to be Figure 1 DSP and / or Figure 1 The TED execution of 2 and / or 2 is used to execute the third timing diagram and instance pseudocode of the third instance symbol and timed recovery technique.

[0010] Figure 6 It is a first graph containing the first instance waveform of the first instance frequency-locking operation used to depict different symbols and timing recovery techniques.

[0011] Figure 7 It is a second graph containing a second instance waveform used to depict the instance frequency-locking operation of different symbols and timing recovery techniques.

[0012] Figure 8 yes Figure 1 A block diagram of another implementation scheme for a communication system.

[0013] Figure 9 yes Figure 8 A graph showing the inter-symbol interference of a DSP instance operation.

[0014] Figure 10 yes Figure 8 The time loop convergence curve of the DSP instance operation.

[0015] Figure 11 yes Figure 8 The timing error of the DSP instance operation relative to the gain is plotted.

[0016] Figure 12 This is a flowchart illustrating an example process that can be executed using machine-readable instructions and / or hardware, which are configured to implement... Figure 1 Instance DSPs and / or (more generally) instance Ethernet PHY devices are used to perform the symbol and timing recovery techniques described herein.

[0017] Figure 13 This is a flowchart illustrating an example process that can be executed using machine-readable instructions and / or hardware, which are configured to implement... Figure 1 Instance DSPs and / or (more generally) instance Ethernet PHY devices to perform Figure 3The first symbol and timed recovery technology.

[0018] Figure 14 This is a flowchart illustrating an example process that can be executed using machine-readable instructions and / or hardware, wherein the machine-readable instructions are executable and / or the hardware is configured to implement... Figure 1 Instance DSPs and / or (more generally) instance Ethernet PHY devices to perform Figure 4 The second symbol and timed recovery technology.

[0019] Figure 15 This is a flowchart illustrating an example process that can be executed using machine-readable instructions and / or hardware, wherein the machine-readable instructions are executable and / or the hardware is configured to implement... Figure 1 Instance DSPs and / or (more generally) instance Ethernet PHY devices to perform Figure 5 The third symbol and timed recovery technology.

[0020] Use the same reference numerals or other reference symbols in the diagrams to indicate features that are the same or similar (in function and / or structure). Detailed Implementation

[0021] Digital communication systems can use modulation techniques such as pulse amplitude modulation (PAM) to transmit data between devices (e.g., communication devices). PAM uses symbols to transmit data. A symbol can refer to a waveform that represents one or more bits. For example, a symbol can be one or more pulses in a pulse train, and one (or more) pulses (i.e., the symbol) can be mapped to one or more data bits.

[0022] The transmitted or received symbols used in PAM technology represent different possible levels based on the amplitude of the transmitted or received pulses. Different PAM techniques exist and are defined based on modulation level identifiers (e.g., PAM3, PAM5, PAM16, etc.). For example, PAM3 may use a symbol representing one of three levels: -1, 0, or +1. In some such instances, the value -1 is assigned and / or otherwise corresponds to a first amplitude (or voltage), the value 0 is assigned and / or otherwise corresponds to a second amplitude (or voltage), and the value +1 is assigned and / or otherwise corresponds to a third amplitude (or voltage). In some such instances, the third amplitude is greater than the second amplitude, and the second amplitude is greater than the first amplitude.

[0023] Some digital communication systems operate based on the Ethernet communication protocol. For example, an Ethernet PHY device is a transceiver that receives and / or transmits data according to the Ethernet communication protocol. Some digital communication systems use Mueller-Muller (M&M) timing synchronization technology to achieve symbol and timing recovery of received data. For example, a first Ethernet PHY device can transmit data by placing symbols on the communication channel at a fixed and known symbol rate, and a second Ethernet PHY device can receive data by detecting the symbol sequence to reconstruct the transmitted data. The second Ethernet PHY device can use M&M timing synchronization technology to reconstruct the transmitted data.

[0024] M&M technology relies on inter-symbol interference (ISI) present at the output of the analog-to-digital converter (ADC) in digital communication systems. ISI is a form of signal distortion where one symbol interferes with subsequent symbols. M&M technology balances the ISI of the symbol after the cursor (P+1) and the symbol before the cursor (P-1) to the same level to achieve timing synchronization. M&M technology seeks to achieve timing synchronization with the optimal eye opening point of an eye diagram, which can be generated by superimposing different portions of the waveform representing different symbols. However, M&M-based digital communication systems rely on ISI for locking (e.g., loop locking, timing loop locking, etc.). For communication channels with low ISI, M&M-based digital communication systems may experience unstable link opening for extended periods until locking is achieved, which reduces the efficiency and / or performance of such systems.

[0025] The examples described herein include communication devices, such as transceivers (e.g., Ethernet PHY devices), that implement improved symbol and timing recovery techniques. In some of the described examples, the communication device may implement improved symbol and timing recovery techniques to achieve faster loop-locked performance independent of channel length or ISI distribution. For example, the communication device may implement the first symbol and timing recovery technique described herein to utilize PAM symbol transitions to determine timing errors. The communication device may use the timing error to generate a timing error signal, which may be incorporated into the timing-locked loop for synchronization purposes. In response to the timing error signal, the communication device may adjust the sampling rate, phase (e.g., timing phase), etc., of the clock (e.g., clock signal, sampling clock, etc.) of the communication device's ADC.

[0026] In some of the described instances, the communication device may perform a second symbol and timing recovery technique to interpolate neighboring samples, which can be used to generate approximate differential samples. As used herein, interpolation refers to constructing new data points based on a set of discrete known data points within a certain range. For example, the communication device may use transitions between sampled PAM symbols to determine new samples (e.g., differential outputs), which can be used to determine timing errors and corresponding timing error signals. In some such instances, the communication device may identify transitions as peak symbol point transitions or valley symbol point transitions to perform interpolation.

[0027] In some of the described instances, the communication device may perform third-symbol and timing recovery techniques to interpolate samples to the median or midpoint value of the sampled PAM symbols, comparing the transitions between sampled PAM symbols with the expected median or midpoint value. For example, the communication device may use the transitions between PAM symbols to determine the timing error and the direction of the corresponding timing error signal to perform interpolation.

[0028] Figure 1 This is a block diagram of an example communication system (e.g., a digital communication system) 100 including an example digital signal processor (DSP) 102. In some examples, the DSP 102 and / or (more generally) the communication system 100 may be an Ethernet PHY device. The communication system 100 includes an example high-pass filter (HPF) 104, an example low-pass filter (LPF) 106, an example analog-to-digital converter (ADC) 108, and an example phase interpolator circuit 110. In some examples, the LPF 106 may be an amplifier, such as a programmable gain amplifier or a variable gain amplifier. The HPF 104 is coupled to a communication channel (e.g., an Ethernet cable) to receive an example receive (RX) input 112. For example, the RX input 112 may be an analog communication signal based on an Ethernet communication protocol.

[0029] DSP 102 includes instance DC cancellation circuitry 114 (e.g., for DC voltage and / or DC current cancellation), instance coded automatic gain controller (CAGC) 116, instance digital automatic gain controller (DAGC) 118, instance de-equalizer (identified by DEQ) (e.g., de-equalizer circuitry) 120, instance feedforward equalizer (FFE) 122, instance adder circuitry 124, instance multiplexer 126, instance slicer circuitry (e.g., data slicer circuitry) 128, instance decision feedback equalizer (DFE) 130, instance gain loop circuitry 132, instance mean square error circuitry 134, instance timing error detector (TED) (e.g., TED circuitry) 136, instance loop filter 138, instance numerically controlled oscillator (NCO) 140, and instance sequencer circuitry 142. Alternatively, DSP 102 may include more than Figure 1 The examples depict fewer or more hardware components than those shown in the DSP 102. For example, although the HPF 104, LPF 106, ADC 108, and phase interpolator circuit 110 are depicted as separate from the DSP 102, in some instances, at least one of the HPF 104, LPF 106, ADC 108, or phase interpolator circuit 110 may be included in the DSP 102. In this example, the DSP 102 and / or (more generally) the communication system 100 implement a phase-locked loop (PLL) (e.g., a PLL circuit) 144. The PLL 144 includes the phase interpolator circuit 110, a loop filter 138, and an NCO 140. Alternatively, the PLL 144 may include more than Figure 1 The examples depict fewer or more hardware components.

[0030] exist Figure 1 In the illustrated example, the input of HPF 104 is coupled to a terminal adapted to receive RX input 112. The output of HPF 104 is coupled to the input of LPF 106. The output of LPF 106 is coupled to the input of ADC 108 (e.g., ADC input). The output of ADC 108 (e.g., ADC output) is coupled to the input of DC removal circuit 114, the input of CAGC 116, and / or (more generally) the input of DSP 102. The output of CAGC 116 is coupled to circuitry external to DSP 102. The output of DC removal circuit 114 is coupled to the input of DAGC 118. The output of DAGC 118 is coupled to the input of DEQ 120. The output of DEQ 120 is coupled to the input of FFE 122 (e.g., FFE input). The output of FFE 122 (e.g., FFE output) is coupled to the input of adder circuit 124 (e.g., adder input, adder circuit input, etc.) and the second input of multiplexer 126. The output of adder circuit 124 (e.g., adder output, adder circuit output, etc.) is coupled to the first input of multiplexer 126, the input of slicer circuit 128, the input of DFE 130, the input of gain loop circuit 132, and the input of MSE 134 circuit. The output of multiplexer 126 is coupled to the input of TED 136 (e.g., TED input). Alternatively, DSP 102 may not include multiplexer 126. For example, the outputs of FFE 122 and / or adder circuit 124 may be coupled to the input of TED 136.

[0031] The output of slicer circuit 128 (e.g., slicer output) is coupled to circuitry external to DSP 102. For example, the output of slicer circuit 128 may be coupled to a memory (and / or a memory controller) to store decisions (e.g., data slicing decisions) in the memory, which may be accessed by one or more processors. The output of slicer circuit 128 is coupled to the input of DFE 130 (e.g., DFE input), the input of gain loop circuit 132, the input of MSE circuit 134, and the input of TED 136. The output of DFE 130 (e.g., DFE output) is coupled to the input of adder circuit 124. The output of gain loop circuit 132 is coupled to the input of DAGC 118. The output of TED 136 (e.g., TED output) is coupled to the input of loop filter 138 (e.g., loop filter input) and / or (more generally) the input of PLL 144 (e.g., PLL input). The output of loop filter 138 (e.g., loop filter output) is coupled to the input of NCO 140 (e.g., NCO input). The output of NCO 140 (e.g., NCO output) is coupled to the input of phase interpolator circuit 110 (e.g., phase detector input, phase interpolator input, etc.). The output of phase interpolator circuit 110 (e.g., phase detector output, phase interpolator output, etc.) and / or (more generally) the output of PLL 144 (e.g., PLL output) is coupled to the input of ADC 108.

[0032] The DSP 102 and / or (more generally) the communication system 100 can perform the instance symbol and timing recovery techniques described herein. In instance operation, the HPF 104 (which may be implemented, for example, as a digital or analog filter) receives and / or otherwise obtains the RX input 112. For example, the HPF 104 may receive the RX input 112 from another device (e.g., a communication device, an Ethernet PHY device, etc.). The HPF 104 attenuates frequencies of the RX input 112 below a first cutoff frequency of the HPF 104. The HPF 104 passes frequencies of the RX input 112 above the first cutoff frequency to the LPF 106 (which may be implemented, for example, as a digital or analog filter). The LPF 106 attenuates frequencies of the RX input 112 above a second cutoff frequency of the LPF 106 and passes frequencies of the RX input 112 below the second cutoff frequency to the ADC 108. In an alternative embodiment, the RF sampling ADC (e.g., a delay-based ADC) can be directly connected to the RX input 112, and filtering can be performed using a digital filter after the RX input 112 has been converted from analog to digital. ADC 108 converts the filtered RX input 112 into a digital signal. In this example, ADC 108 samples the RX input 112 at a sampling rate of approximately one sample per second (e.g., one symbol per sample). Alternatively, ADC 108 can sample the RX input 112 at any other sampling rate. CAGC 116 amplifies the digital signal to output an amplified digital signal. For example, CAGC 116 can determine the power of the digitized signal and adjust the analog gain accordingly (e.g., by changing the attenuation or gain of HPF 104 or LPF 106) to bring the digitized signal to the desired level at the input of ADC 108, thereby increasing and / or otherwise maximizing the signal-to-noise ratio (SNR). DC removal circuitry 114 can be one or more filters to remove DC bias from the output of ADC 108. DAGC 118 can generate the output to DEQ 120 based on the multiplication (or product) of the output from DC removal circuit 114 and the output from gain loop circuit 132. For example, DAGC 118 can amplify a digital signal to a predetermined level at the input of slicer circuit 128. DEQ 120 can include one or more filters to filter the output from DAGC 118.

[0033] In a typical operation, FFE 122 equalizes the communication channel of communication system 100. FFE 122 recovers data from RX input 112. For example, FFE 122 can generate a first instance symbol 146 (identified by x(n)) based on the output from DEQ 120. Adder circuit 124 can generate a second instance symbol 148 (identified by y(n)) based on the difference between the first symbol 146 and the output of DFE 130. For example, FFE 122 can generate the first symbol 146 as an uncorrected symbol, and adder circuit 124 can generate the second symbol 148 as a corrected symbol.

[0034] In practical operation, DFE 130 can predict, identify, and / or otherwise determine the noise level of the communication channel based on previous samples (e.g., previous values ​​of the first symbol 146 and / or the second symbol 148). For example, DFE 130 can output a noise error (e.g., a noise error signal) to adder circuit 124 to correct the second symbol 148, thereby generating a DFE-corrected symbol. Advantageously, adder circuit 124 can subtract the predicted noise level output from DFE 130 from the first symbol 146. Slicer circuit 128 performs slicing on the second symbol 148 using one or more thresholds (e.g., one or more threshold values). For example, slicer circuit 128 can generate a first output (also referred to as a decision, data decision, symbol decision, etc.) in response to determining that the amplitude of the second symbol 148 is greater than a first threshold, and generate a second output, etc., in response to determining that the amplitude is greater than a second threshold. In some such instances, slicer circuit 128 may generate a third instance symbol 150 based on the determination. (n). For example, slicer circuit 128 can generate third symbol 150 as one of the PAM levels (e.g., the levels of PAM3 -1, 0, +1).

[0035] In a typical operation, gain loop circuit 132 may output gain (e.g., a voltage, signal, etc. representing a gain value) to DAGC 118 to adjust and / or otherwise modify the input to DEQ 120. For example, gain loop circuit 132 may output gain based on second symbol 148 and / or third symbol 150. MSE circuit 134 may output MSE (e.g., a voltage, signal, etc. representing an MSE). For example, MSE circuit 134 may determine the difference between the input to slicer circuit 128 and the output of slicer circuit 128 to determine noise associated with DSP 102, such as noise in a communication channel processed by DSP 102. In some such instances, MSE circuit 134 may determine whether a desired SNR at the input to slicer circuit 128 meets a threshold (e.g., an SNR threshold, a noise energy threshold, etc.). For example, in response to an SNR at the input to slicer circuit 128 being less than a threshold, sequencer circuit 142 may advance to a subsequent state. In some instances, in response to an SNR greater than a threshold at the input of slicer circuit 128, sequencer circuit 142 can revert to a previous state to achieve reconvergence of timing lock. In some instances, the threshold can be user-defined (e.g., through pre-programming, configuration, etc., before DSP 102 processes the communication channel). In some instances, the threshold can be dynamically adjusted by sequencer circuit 142. For example, sequencer circuit 142 can adjust the threshold based on the DSP's historical SNR (e.g., the SNR of DSP 102 within one or more previous clock cycles).

[0036] In practice, multiplexer 126 selects whether to output a first symbol 146 or a second symbol 148 to TED 136. In some instances, inputs to multiplexer 126 (e.g., control or selection inputs) are coupled to the output of sequencer circuit 142 (e.g., sequencer output). In some instances, sequencer circuit 142 may be logic circuitry, machine-readable instructions, a hardware-implemented state machine, processing circuitry, and / or any other combination thereof. For example, sequencer circuit 142 may be one or more analog and / or digital circuits. In some instances, in response to determining that PLL 144 has not implemented timing lock, sequencer circuit 142 may instruct multiplexer 126 to select the first symbol 146. In some instances, in response to determining that PLL 144 has implemented timing lock (e.g., timing loop lock), sequencer circuit 142 may instruct multiplexer 126 to select the second symbol 148. In some instances, TED 136 can determine a first timing error based on an uncorrected symbol (e.g., first symbol 146) before timing lock is achieved by PLL 144, and a second timing error based on a corrected symbol (e.g., second symbol 148) in response to timing lock being achieved by PLL 144. Advantageously, after timing lock is achieved by PLL 144, the output from DFE 130 converges to a steady state or a stable value. In response to the convergence of the output of DFE 130, TED 136 can be switched to use a DFE-corrected symbol (or a partially corrected DFE symbol) to achieve improved noise variance (e.g., lower noise variance).

[0037] In practical operation, the TED 136 outputs timing errors (e.g., voltage, timing error signals, etc.) based on a first symbol 146, a second symbol 148, and / or a third symbol 150. For example, the TED 136 can output timing errors by utilizing one or more symbols and the timing recovery techniques described herein. In some instances, the inputs of the TED 136 (e.g., control inputs, selection inputs, etc.) are coupled to the output of the sequencer circuit 142. For example, the sequencer circuit 142 can instruct the TED 136 to generate timing errors using the first symbol 146, the second symbol 148, and / or the third symbol 150. The loop filter 138 can filter the timing errors and provide the filtered timing errors to the NCO 140.

[0038] In some instances, NCO 140 may be an accumulator (e.g., a digital phase accumulator). For example, the accumulator may increment or decrement the accumulator value from an initial value (e.g., 0 or zero) and generate an instance control signal 152 (identified by phase rise / fall) in response to the accumulator value satisfying a threshold. In some instances, NCO 140 may generate control signal 152 to increase or decrease the phase of the clock that samples the RX input 112 by the ADC 108. In some instances, phase interpolator circuit 110 may be a phase detector. For example, phase interpolator circuit 110 may detect the phase of control signal 152 and, based on the detected phase of control signal 152, instruct ADC 108 to increase the phase of a clock that may be a portion of the clock of ADC 108. In some instances, phase interpolator circuit 110 may instruct ADC 108 to decrease the phase of the clock based on control signal 152.

[0039] Figure 2 This is a block diagram of an example of TED 200. In some instances, TED 200 can be implemented. Figure 1 The TED 136. The TED200 includes an instance multiplexer 202 and an instance latch 204. The latch 204 is a D flip-flop. Alternatively, the latch 204 can be a set-reset (SR) flip-flop, a JK flip-flop, or a T flip-flop. In some instances, the first input (identified by x(n-1)) and the second input (identified by -x(n-1)) of the multiplexer 202 can be coupled to Figure 1 The output of the multiplexer 126 (e.g., multiplexer output, MUX output, etc.). For example, x(n-1) and -x(n-1) can be the previous symbols. In some such instances, x(n-1) can be... Figure 1 The previous value of the first symbol 146, the previous value of the second symbol 148, etc. The third input of multiplexer 202 (e.g., multiplexer input, MUX input, etc.) is coupled to the output of latch 204 (e.g., latch output), such that the input of multiplexer 202 can be the previous output of multiplexer 202. In some instances, the control or selection input of multiplexer 202 (e.g., MUX control input) (identified by mux_sel) is coupled to... Figure 1 The output of sequencer circuit 142. The output of multiplexer 202 is coupled to the input of latch (e.g., latch input). The clock input of latch 204 can be adapted to receive a clock signal, which can be obtained from... Figure 1 The sequencer circuit 142 outputs. The output of multiplexer 202 (identified by ted(n)) is coupled to... Figure 1 The input of the loop filter 138 and / or (more generally) the input of the PLL 144.

[0040] In a practical application, when the TED 200 does not detect a timing error, it outputs "0" as the instance timing error 206 (identified by ted(n)). If the TED 200 detects a timing error, it outputs timing error 206 to ensure that the ADC 108 samples to the left or right of the desired sampling point. Accordingly, the TED 200 outputs timing error 206 with direction (e.g., whether sampling is to the left or right of the desired sampling point).

[0041] The illustrated example TED 200 can perform one or more symbol and timing recovery techniques to produce a timing error 206. For example, the timing error 206 could represent the time difference between a previously detected symbol and the currently detected symbol. When a -1, 0, or +1 symbol transition is detected at RX input 112 (e.g., ...), the timing error 206 is generated. (n-2) = -1, (n-1) = 0, When (n) = +1), the TED 200 instruction multiplexer 202 selects 1. For example, multiplexer 202 can output the positive value of a previously detected symbol. When a +1, 0, -1 symbol transition is detected at RX input 112 (e.g., ...), the multiplexer selects 1. (n-2) = +1, (n-1) = 0, When (n) = -1), TED 200 can instruct multiplexer 202 to select 2. For example, multiplexer 202 can output the negative value of the previously detected symbol. In other cases, TED 200 can instruct multiplexer 202 to select 0. Alternatively, TED 200 can use other than Figure 2 Any other logic depicted in the instance to control the multiplexer 202.

[0042] Figure 3 Depicting the corresponding Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The first timing diagram 300 for the instance operation of DSP 102. Figure 3 The text further describes the first instance pseudocode 302 and the second instance pseudocode 304, which can be derived from... Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1The DSP 102 executes the code. In some instances, the first pseudocode 302 and / or the second pseudocode 304 can be implemented by the DSP 102 to perform the first symbol and timing recovery technique. For example, the first symbol and timing recovery technique can be a constellation-based TED technique.

[0043] The first timing diagram 300 includes an example analog signal waveform 306 and an example pulse waveform 308. In some instances, the analog signal waveform 306 may be... Figure 1 The RX input is 112. In some instances, the pulse waveform 308 can be... Figure 1 The output of slicer circuit 128. For example, pulse waveform 308 can be a symbol generated by slicer circuit 128 (e.g., Figure 1 The third symbol 150).

[0044] In the example operation, Figure 1 TED 136 and / or Figure 2 The TED 200 can implement the first pseudocode 302 to determine the timing error (ted(n)). For example, the sequencer circuit 142 can determine... Figure 1 The current decision of the slicer circuit 128 (e.g., the current slicer decision). (n) is +1, the first previous slicer decision ( (n-1)) is 0, and the second previous slicer decision ( (n-2)) is -1. In response to the detection of -1, 0, and +1 sign transitions based on the aforementioned determination, TED 200 can be... Figure 2 The multiplexer 202's mux_sel produces a value of 1, causing the multiplexer 202 to select x(n-1). For example, the sequencer circuit 142 can select the input of TED 200. In some such instances, the sequencer circuit 142 can select either the first symbol 146 or the second symbol 148 based on the state of the sequencer circuit 142 (e.g., the sequencer state). Figure 1 TED 136 and / or Figure 2 The TED 200. Advantageously, the sequencer circuit 142 can select the first symbol 146 before the PLL 146 achieves timing lock, and select the second symbol 148 after the PLL 146 achieves timing lock to reduce noise after timing lock is achieved. Advantageously, the sequencer circuit 142 can instruct TED 136 and / or TED 200 to use the second symbol 148 after timing lock to reduce noise caused by ISI. In some instances, the timing error can be determined based on an example of the following equation (1):

[0045] equation (1)

[0046] For example, in response to the determination of a positive or negative slope, the TED 200 can determine that the current timing error is the same as the previous slicer input. The TED 200 can determine a positive slope based on the sign transitions of -1, 0, and +1 (e.g., negative one, zero, and positive one values). The TED 200 can determine a negative slope based on the sign transitions of +1, 0, and -1 (e.g., positive one, zero, and negative one values). For example, x(n-1) can represent the timing error generated by the TED 200 in response to detecting a positive slope based on the sign transitions of -1, 0, and +1. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error x(n-1) to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being described by reference numeral 310.

[0047] In the illustrated example, sequencer circuit 142 determines the current slicer decision of slicer circuit 128. (n) is -1, the first previous slicer decision ( (n-1)) is 0, and the second previous slicer decision ( (n-2)) is +1. In response to the detection of +1, 0, and -1 sign transitions based on the aforementioned determination, TED 200 can be... Figure 2 The multiplexer 202's mux_sel produces a value of 2, causing the multiplexer 202 to select -x(n-1). For example, the timing error can be determined based on an instance of equation (1) above. In some such instances, -x(n-1) can be the negative of the timing error generated by TED 200 in response to the detection of a negative slope based on the +1, 0, -1 sign transition. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on -x(n-1) to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being described by reference number 312.

[0048] In some instances, when the symbol transition referenced above is not detected, TED 200 can be... Figure 2 The multiplexer 202's mux_sel produces a value of 0, causing the multiplexer 202 to output a value of 0 when executing the first pseudocode 302. In some instances, TED 200 can be used when the symbol transition referenced above is not detected. Figure 2 The multiplexer 202's mux_sel produces a value of 0, causing the multiplexer 202 to output the previously generated timing error (identified by ted(n-1)) when executing the second pseudocode 304. Advantageously, in some such instances, maintaining the previous timing error value improves... Figure 1 TED136 and / or Figure 1 The gain of the TED 200, and will improve Figure 1 The locking capability of the PLL 144 (e.g., by locking faster). Advantageously, Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP 102 can determine timing errors by executing the first pseudocode 302 and / or the second pseudocode 304 using PAM sign transitions.

[0049] Figure 4 Depicting the corresponding Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The second timing diagram 400 for the instance operation of DSP 102. Figure 4 The text further describes the first instance pseudocode 402 and the second instance pseudocode 404, which can be derived from... Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP 102 is used to execute this. In some instances, the first pseudocode 402 and / or the second pseudocode 404 can be implemented by the DSP 102 to perform a second symbol and timing recovery technique. For example, the second symbol and timing recovery technique could be a pseudo maximum likelihood (ML) technique. In some such instances, Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP 102 can perform pseudo-ML techniques to interpolate samples to determine approximate difference samples based on an example of equation (2) below:

[0050] equation (2)

[0051] In the example of equation (2) above, ted ML ( n It is possible that it is caused by Figure 1 TED 136 and / or Figure 2 The timing error generated by the TED 200. In the example of equation (2) above, x ( n ) is a currently uncorrected symbol (e.g. Figure 1 The first symbol 146), and It is the derivative of the currently uncorrected sign. For example, in response to the detection of a peak sign point transition (e.g., a -1, +1, -1 sign point transition) or a valley sign point transition (e.g., a +1, -1, +1 sign point transition), the timing error is 0 because the derivative at the peak or valley sign point transition is 0. In other cases, the derivative is non-zero, which makes the timing error non-zero, and thus the TED 200 can indicate the direction of the timing error.

[0052] The second timing diagram 400 depicts an example analog signal waveform 406 and an example pulse waveform 408. In some instances, the analog signal waveform 406 may be... Figure 1 The RX input is 112. In some instances, the pulse waveform 408 can be... Figure 1 The output of slicer circuit 128. For example, pulse waveform 408 can be a symbol generated by slicer circuit 128 (e.g., Figure 1 The third symbol 150).

[0053] In the example operation, Figure 1 TED 136 and / or Figure 2 The TED 200 can implement the first pseudocode 402 to determine the timing error (ted). pML (n)). For example, sequencer circuit 142 can determine Figure 1 The current slicer decision of slicer circuit 128 ( (n) is -1, the first previous slicer decision ( (n-1)) is +1, and the second previous slicer decision ( (n-2)) is -1. In response to the detection of peak sign point transitions based on -1, +1, -1 sign transitions, TED 136 and / or TED 200 can generate timing errors based on instances of the following equation (3):

[0054] equation (3)

[0055] In the example of equation (3) above, x L ( n -1) and x E ( n The difference between -1) is x ( n -1) An approximation of the derivative, and therefore the output of the differential. Alternatively, one or more filters can be used to determine the differential output. In some instances, x L This can represent the approximate value of the first timing error at the first instance point 410 of the analog signal waveform 406, and xE This can represent the second timing error approximation at the second instance point 412 of the analog signal waveform 406. Differential output. x L and x E This can be determined based on examples of equations (4) and (5) contained in the second pseudocode 404 below:

[0056] equation (4)

[0057] equation (5)

[0058] In the example of equation (4) above, the value of μ can be controlled to determine the interpolation rate of the sign. In the example operation, Figure 1 The sequencer circuit 142 can be determined Figure 1 The current slicer decision of slicer circuit 128 ( (n) is +1, the first previous slicer decision ( (n-1)) is -1, and the second previous slicer decision ( (n-2)) is +1. In response to the detection of a valley sign point transition based on the sign transitions of -1, +1, and -1, TED 136 and / or TED 200 can generate timing errors based on instances of the following equation (6):

[0059] equation (6)

[0060] In some instances, TED 136 and / or TED 200 can determine that neither peak sign point transitions nor valley sign point transitions are detected. In some such instances, when executing the second pseudocode 402, TED 136 and / or TED 200 can output the previously generated timing error (by...). ted pML ( n -1) Identification). Advantageously, in some such instances, maintaining the previous timing error value improves the gain of the TED 136 and / or TED 200, and also improves... Figure 1 The locking capability of the PLL 144 (e.g., by locking faster). Advantageously, Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP102 can determine timing errors by executing the first pseudocode 302 and / or the second pseudocode 304 using PAM symbol transitions.

[0061] Figure 5 Depicting the corresponding Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The third timing diagram 500 for the instance operation of DSP 102. Figure 5 The example pseudocode 502 is further described, which can be derived from... Figure 2 TED 200 Figure 1 TED 136 and / or (more generally) Figure 1 The DSP 102 is used to execute this. In some instances, the DSP 102 can utilize pseudocode 502 to execute a third symbol and timing recovery technique. For example, the third symbol and timing recovery technique could be the intermediate symbol TED technique. In some such instances, TED 136 and / or TED 200 can utilize pseudocode 502 to interpolate samples to the middle or midpoint of a symbol and compare the interpolation with the expected midpoint. Under these conditions, the comparison can be based on the PAM symbol transition. Alternatively, one or more filters can be used to determine the midpoint.

[0062] The third timing diagram 500 depicts an example analog signal waveform 504 and an example pulse waveform 506. In some instances, the analog signal waveform 504 may be... Figure 1 The RX input is 112. In some instances, the pulse waveform 506 can be... Figure 1 The output of slicer circuit 128. For example, pulse waveform 506 can be a symbol generated by slicer circuit 128 (e.g., Figure 1 The third symbol 150).

[0063] In the example operation, Figure 1 TED 136 and / or Figure 2 The TED 200 can execute pseudocode 502 to determine timing error (TED). midsym (n)). For example, sequencer circuit 142 can determine Figure 1 The current slicer decision of slicer circuit 128 ( (n) is +1, and the previous slicer decision ( (n-1)) is -1. For example, sequencer circuit 142 can determine the sign transition pair based on -1, +1. Figure 1 The third symbol 150 is a prediction or estimate of +1 that can indicate... Figure 1 The second symbol 148 is at the 0 symbol. Under these conditions, TED 136 and / or TED 200 can determine that the second symbol 148 is located at the first instance symbol position 508. In response to identifying the first symbol position 508, TED 136 and / or TED 200 can determine the second symbol 148 based on x. midsymThe difference between x and 0 produces a timing error, which is then used to determine the timing error as x. midsym In some instances, the timing error signal can be a waveform with an amplitude (e.g., voltage) representing the timing error. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being represented by the first symbol position 508.

[0064] In some instances, the sequencer circuit 142 can determine Figure 1 The current slicer decision of slicer circuit 128 ( (n) is -1, and the previous slicer decision ( (n-1)) is +1. For example, sequencer circuit 142 can determine the sign transition pair based on +1, -1. Figure 1 The third symbol 150 is a prediction or estimate of -1 that can indicate Figure 1 The second symbol 148 is at the 0 symbol. Under these conditions, TED 136 and / or TED 200 can determine that the second symbol 148 is located at the second instance symbol position 510. In response to identifying the second symbol position 510, TED 136 and / or TED 200 can determine the second symbol 148 based on x. midsym The negative difference between 0 and 0 is used to generate the timing error, and the timing error is determined to be -x. midsym In some instances, the timing error signal can be a waveform with an amplitude (e.g., voltage) representing the timing error. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being represented by the second symbol position 510.

[0065] In the practical operation, the sequencer circuit 142 can be determined. Figure 1 The current slicer decision of slicer circuit 128 ( (n) is +1, and the previous slicer decision ( (n-1)) is 0. In response to the detection of a 0, +1 sign transition based on the determination, TED 136 and / or TED 200 are based on x midsym The difference between the coefficient and 0.5 produces a timing error. Alternatively, the coefficient can be any other value. Under these conditions, TED 136 and / or TED 200 can determine the timing error based on the 0, +1 sign transition pair. Figure 1 The third symbol 150 is a prediction or estimate of +1 that can indicate... Figure 1The second symbol 148 is located between symbols (e.g., between a mid-symbol or intermediate symbol, between the first symbol 0 and the second symbol +1, etc.). Under these conditions, TED 136 and / or TED 200 can determine that the second symbol 148 is located at the third instance symbol position 512. In this instance, the third symbol position 512 is an intermediate symbol position. In response to identifying the third symbol position 512, TED 136 and / or TED 200 can determine the timing error as (x midsym - 0.5). In some instances, the timing error signal can be a waveform with an amplitude (e.g., voltage) representing the timing error. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112, which are 0 symbols, in the correct phase.

[0066] In the practical operation, the sequencer circuit 142 can be determined. Figure 1 The current slicer decision of slicer circuit 128 ( (n) is 0, and the previous slicer decision ( (n-1)) is +1. In response to the detection of a +1, 0 sign transition based on the determination, TED 136 and / or TED 200 are based on x midsym A negative difference between the coefficient and 0.5 introduces a timing error. Alternatively, the coefficient can be any other value. Under these conditions, TED 136 and / or TED 200 can determine the timing error based on the +1, 0 sign transition pair. Figure 1 The third symbol 150 is a prediction or estimate of 0 that can indicate Figure 1 The second symbol 148 is located between symbols (e.g., between a mid-symbol or intermediate symbol, between the first symbol +1 and the second symbol 0, etc.). Under these conditions, TED 136 and / or TED 200 can determine that the second symbol 148 is located at the fourth instance symbol position 514. In this instance, the fourth symbol position 514 is an intermediate symbol position. In response to identifying the fourth symbol position 514, TED 136 and / or TED 200 can determine the timing error as -(x midsym - 0.5). In some instances, the timing error signal can be a waveform with an amplitude (e.g., voltage) representing the timing error. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being the +1 symbols preceding the fourth symbol position 514.

[0067] In the practical operation, the sequencer circuit 142 can be determined. Figure 1 The current slicer decision of slicer circuit 128 ( (n) is -1, and the previous slicer decision ( (n-1)) is 0. In response to the detection of a 0, -1 sign transition based on the determination, TED 136 and / or TED 200 are based on x midsym The negative sum between the coefficient 0.5 and the coefficient 0.5 produces a timing error. Alternatively, the coefficient can be any other value. Under these conditions, TED 136 and / or TED 200 can determine the timing error based on the 0, -1 sign transition pair. Figure 1 The third symbol 150 is a prediction or estimate of -1 that can indicate Figure 1 The second symbol 148 is located between symbols (e.g., between a mid-symbol or intermediate symbol, between the first symbol 0 and the second symbol -1, etc.). Under these conditions, TED 136 and / or TED 200 can determine that the second symbol 148 is located at the fifth instance symbol position 516. In this instance, the fifth symbol position 516 is an intermediate symbol position. In response to identifying the fifth symbol position 516, TED 136 and / or TED 200 can base their analysis on x. midsym The timing error is generated by the sum of the negatives of x and 0.5, and the timing error is determined to be -(x) / x. midsym +0.5). In some instances, the timing error signal can be a waveform with an amplitude (e.g., voltage) representing the timing error. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being 0 symbols before the fifth symbol position 516.

[0068] In the practical operation, the sequencer circuit 142 can be determined. Figure 1 The current slicer decision of slicer circuit 128 ( (n) is 0, and the previous slicer decision ( (n-1)) is -1. In response to the detection of a -1, 0 sign transition based on the determination, TED 136 and / or TED 200 are based on x midsym The negative sum of the coefficient 0.5 produces a timing error. Alternatively, the coefficient can be any other value. Under these conditions, TED 136 and / or TED 200 can determine the timing error based on the -1, 0 sign transition pair. Figure 1 The third symbol 150 is a prediction or estimate of 0 that can indicate Figure 1The second symbol 148 is located between symbols (e.g., between a mid-symbol or intermediate symbol, between the first symbol -1 and the second symbol 0, etc.). Under these conditions, TED 136 and / or TED 200 can determine that the second symbol 148 is located at the sixth instance symbol position 518. In this instance, the sixth symbol position 518 is an intermediate symbol position. In response to identifying the sixth symbol position 518, TED 136 and / or TED 200 can base their analysis on x. midsym The timing error is generated by the sum of the negatives of x and 0.5, and the timing error is determined to be -(x) / x. midsym +0.5). In some instances, the timing error signal can be a waveform with an amplitude (e.g., voltage) representing the timing error. Advantageously, Figure 1 The PLL 144 can adjust the phase of the ADC 108 based on the timing error signal to sample subsequent symbols of the RX input 112 in the correct phase, the symbols being -1 symbols before the sixth symbol position 518.

[0069] Figure 6 This is a graph 600 containing example waveforms 602, 604, 606, and 608 used to depict example frequency-locking operations associated with different symbols and timing recovery techniques. The x-axis (for graph 600) represents the number of symbols, and the y-axis is the value of the timing loop (Tloop) frequency arm accumulator. Waveforms 602, 604, 606, and 608 include a first example waveform 602 generated based on the Müller-Muller (MM) TED technique, a second example waveform 604 generated based on the constellation-based TED technique, a third example waveform 606 generated based on the pseudo-ML TED technique, and a fourth example waveform 608 generated based on the intermediate symbol TED technique. For example, the second waveform 604 can respond to... Figure 1 TED 136 and / or Figure 2 TED 200 Executive Figure 3 The first pseudocode 302 and / or the second pseudocode 304 are used to generate it. In some instances, the third waveform 606 can be generated in response to... Figure 1 TED 136 and / or Figure 2 TED200 Executive Figure 4 The first pseudocode 402 and / or the second pseudocode 404 are used to generate it. In some instances, the fourth waveform 608 can be generated in response to... Figure 1 TED 136 and / or Figure 2 TED 200 Executive Figure 5 It is generated by pseudocode 502.

[0070] Figure 600 depicts the frequency locking operation (e.g., implementing) of different waveforms 602, 604, 606, and 608 relative to a certain number of detected symbols. Figure 1 (PLL 144's timing lockout, timing loop lockout, etc.). For example, different waveforms 602, 604, 606, and 608 can respond to the timing loop frequency accumulator (e.g., Figure 1 Locking is achieved when the value of NCO 140 meets the instance threshold (e.g., the value of the lock threshold) 610. In some instances, the threshold 610 can be user-defined (e.g., in...). Figure 1 Before the DSP 102 processes the communication channel, it is pre-programmed, configured, etc. In some instances, the threshold 610 can be dynamically adjusted by the sequencer circuit 142. For example, the sequencer circuit 142 can adjust the threshold 610 based on the DSP's historical SNR (e.g., the SNR of DSP 102 in one or more previous clock cycles).

[0071] In some instances, Figure 600 may depict frequency-locking operation for relatively short communication channels (e.g., cables of lengths such as 0.5 meters and 1.0 meter), which presents challenging situations due to the low ISI of short communication channels. Advantageously, in the illustrated examples, in low ISI instances, constellation-based TED and pseudo-ML TED techniques offer improved frequency-locking operation compared to MM-TED techniques. Advantageously, in some instances, constellation-based TED and pseudo-ML TED techniques offer improved frequency-locking operation compared to MM-TED techniques that are independent of and / or otherwise disregard channel length or the ISI present in the channel.

[0072] Figure 7 This is a graph 700 containing example waveforms 702, 704, 706, and 708 depicting example frequency-locking operations associated with different symbols and timing recovery techniques. The x-axis (for graph 700) represents the number of symbols, and the y-axis is the value of the timing loop (Tloop) frequency arm accumulator. Waveforms 702, 704, 706, and 708 include a first example waveform 702 generated based on the Müller-Muller (MM) TED technique, a second example waveform 704 generated based on the constellation-based TED technique, a third example waveform 706 generated based on the pseudo-ML TED technique, and a fourth example waveform 708 generated based on the pseudo-ML TED technique with a differential filter. For example, the second waveform 704 can respond to... Figure 1 TED 136 and / or Figure 2 TED 200 Executive Figure 3 The first pseudocode 302 and / or the second pseudocode 304 are used to generate it. In some instances, the third waveform 706 can be generated in response to... Figure 1 TED136 and / or Figure 2TED 200 Executive Figure 4 The first pseudocode 402 and / or the second pseudocode 404 are used to generate it. In some instances, the fourth waveform 708 can be generated in response to... Figure 1 TED 136 and / or Figure 2 The TED 200 is generated by executing the first pseudocode 402 and / or one or more filters to produce a differential output, as described above. Figure 4 As described. In some such instances, one or more filters may be implemented. Figure 4 The second pseudocode 404 is used to generate the differential output.

[0073] Figure 700 depicts different waveforms 702, 704, 706, and 708 with respect to a certain number of detected symbols (e.g., implementing...). Figure 1 (e.g., timing lockout, timing loop lockout, etc. of PLL 144). For example, different waveforms 702, 704, 706, and 708 can respond to the timing loop frequency accumulator (e.g., ...). Figure 1 Locking is achieved when the value of NCO 140 satisfies the instance threshold (e.g., the value of the locking threshold) 710. In some instances, Figure 700 may depict frequency locking operation for relatively short communication channels (e.g., cables of lengths such as 0.5 meters and 1.0 meters), which presents challenging conditions due to low ISI. Advantageously, in the illustrated examples, in low ISI instances, constellation-based TED, pseudo-ML TED, and pseudo-ML TED with differential filters offer improved frequency locking operation compared to MM-TED. Advantageously, in some instances, constellation-based TED, pseudo-ML TED, and pseudo-ML TED with differential filters offer improved frequency locking operation compared to MM-TED, which is independent of and / or otherwise disregards channel length or the ISI present in the channel.

[0074] Figure 8 This is a block diagram of an example communication system (e.g., a digital communication system) 800 that includes an example digital signal processor (DSP) 802. In some examples, the DSP 802 and / or (more generally) the communication system 800 may be an Ethernet PHY device. The communication system 800 includes... Figure 1 The circuit includes RX input 112, HPF 104, LPF 106, ADC 108, and phase interpolator circuit 110.

[0075] DSP 802 includes Figure 1The circuits include DC cancellation circuit 114, CAGC 116, DAGC 118, DEQ 120, FFE 122, adder circuit 124, slicer circuit 128, DFE 130, gain loop circuit 132, MSE circuit 134, loop filter 138, NCO 140, and PLL 144. Figure 8 The text further describes Figure 1 The first symbol 146, the second symbol 148, and the third symbol 150, as well as the control signal 152. The DSP 802 includes additional instances of the TED 804 and the sequencer circuit 806.

[0076] In some instances, the DSP 802, TED 804, sequencer circuit 806, and / or (more generally) communication system 800 perform M&M timing synchronization techniques to adjust the phase of ADC 108. For example, the operation of DSP 802 may depend on the ISI of the channel of communication system 800 to achieve timing lock. In some such instances, DSP 802 may utilize M&M timing synchronization techniques to balance the post-cursor ISI (P+1) and pre-cursor ISI (P-1) to achieve lock. In some instances, DSP 802 may utilize M&M timing synchronization techniques to achieve timing lock using a DFE-corrected symbol (e.g., second symbol 148). By using M&M timing synchronization techniques, the timing loop of PLL 144 and the output from DFE 130 must converge, which may result in a longer lock time, or in some instances, instability in the timing loop. In some such instances, the timing loop controlled by PLL 144 may not converge in systems with low ISI.

[0077] Advantageously, in low ISI systems, DSP 102 and / or (more generally) Figure 1 The communication system 100 can achieve more than Figure 8 The DSP 802 offers faster timing lock-up, thereby reducing timing loop instability. Advantageously, the DSP 102 and / or (more generally) Figure 1 The communication system 100 can perform Figure 3 The first symbol and timing recovery techniques described in the text (such as constellation-based TED techniques) Figure 4 The second symbol and timed recovery techniques described in the text (such as pseudo-ML TED techniques) or Figure 5 At least one of the third symbol and timed recovery techniques (such as intermediate symbol TED technique) described herein.

[0078] Figure 9 Is with Figure 8The graph 900 shows the inter-symbol interference (ISI) associated with the instance operation of the DSP 802. Graph 900 has an x-axis for the symbols and a y-axis for the channel impulse response. Graph 900 depicts the instance ISI behavior that occurs when symbol 11 is sampled with different channel lengths (e.g., 0.5 m and 24 m). For example, the channel impulse response of symbols other than symbol 11 depicted in graph 900 represents the signal generated by the DSP 802. Figure 1 The communication system 100 implements the communication channel ISI.

[0079] As depicted in graph 900, a longer channel length results in an improved channel impulse response compared to a shorter channel length. Thus, the DSP 802 may exhibit reduced performance at low ISI levels. For example, a reduced ISI may exist in communication channels with shorter channel lengths, while an increased ISI may exist in communication channels with longer channel lengths. In graph 900, the ISI is low at a channel length of 0.5, and TED (e.g., using conventional M&M timing synchronization techniques) is also low. Figure 8 The TED 804 may have difficulty detecting symbols with low ISI (e.g., symbol 11 in graph 900) because conventional M&M timing synchronization techniques rely on higher ISI levels for detectability. Advantageously, with Figure 8 Compared to the DSP 802, Figure 1 The DSP 102 and / or (more generally) Figure 1 The communication system 100 exhibits improved performance independent of channel length at low ISI levels. For example, Figure 1 TED 136 and / or Figure 2 The TED 200 can implement one or more of the symbol and timing recovery techniques described herein, which demonstrate improved detectability of symbols at shorter channel lengths and thereby overcome the limitations of conventional M&M timing synchronization techniques at low ISI levels.

[0080] Figure 10 Is with Figure 8 Graph 1000 illustrates the time loop convergence associated with an instance operation of the DSP 802. The x-axis (for graph 1000) represents the number of symbols, and the y-axis is the value of the timing loop (Tloop) frequency arm accumulator. Graph 1000 depicts the first time loop convergence for a channel length of 0.5 meters (e.g., a cable of 0.5 meters) and the second time loop convergence for a channel length of 21 meters (e.g., a cable of 21 meters). As depicted in graph 1000, the DSP 802 did not achieve time loop convergence at the lower channel lengths. Advantageously, Figure 1 The DSP 102 achieves time loop convergence at a relatively low channel length, which is in Figure 7 The examples illustrated in the diagrams and / or 8 are shown, and the DSP 102 is therefore related to... Figure 8 It achieves improved performance compared to the DSP802.

[0081] Figure 11 Is with Figure 8 The timing error versus gain associated with an example operation of the DSP 802 is plotted in graph 1100. Graph 1100 has an x-axis for the timing error in symbols and a y-axis for the TED S curve. Graph 1100 depicts a first gain relative to the timing error in symbols for a first channel length of 0.5 meters and a second gain relative to the timing error in symbols for a second channel length of 21 meters. As plotted in graph 1100, a longer channel length has an improved gain response compared to a shorter channel length. Thus, the DSP 802 may have reduced performance at shorter channel lengths because the DSP 800 relies on a higher ISI level to achieve symbol detectability. Advantageously, with Figure 8 Compared to the DSP802, Figure 1 The DSP 102 and / or (more generally) Figure 1 The communication system 100 has improved performance over shorter channel lengths because its symbol detectability performance is independent of the ISI level, whereas conventional M&M timing synchronization technology is not independent of the ISI level, but instead relies on the ISI level to achieve symbol detectability.

[0082] Figure 12-15 The demonstration showed that the configuration can be used for implementation. Figure 1 TED 136, sequencer circuit 142, DSP 102, communication system device 100 and / or Figure 2 The flowchart describes the instance hardware logic, instance machine-readable instructions (e.g., hardware-readable instructions), instance hardware-implemented state machine, and / or any combination thereof executed by the TED 200 instance process. The instance machine-readable instructions may be one or more executable programs or portions thereof, which are intended to be executed by a programmable processor (e.g., a programmable microprocessor), programmable controller, GPU, DSP, ASIC, PLD, and / or FPLD. The program may be a software embodiment stored on a non-transitory computer-readable storage medium (e.g., electrically erasable programmable read-only memory (EEPROM), non-volatile memory, volatile memory, etc.), but the entire program and / or portions thereof may alternatively be executed by any other device (e.g., a programmable device) and / or embodied in firmware or dedicated hardware. Furthermore, although referenced... Figure 12-15 The illustrated flowchart describes an example program, but alternative implementations can be used. Figure 1TED 136, sequencer circuit 142, DSP 102, communication system device 100 and / or Figure 2 Many other methods and / or techniques of TED 200. For example, the execution order of blocks can be changed, and / or some of the described blocks can be changed, deleted, or combined. Additionally or alternatively, any or all blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuits, field-programmable logic devices (e.g., field-programmable gate arrays (FPGAs)), application-specific integrated circuits (ASICs), comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform the corresponding operations without executing software or firmware.

[0083] The machine-readable instructions described herein may be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and packaged format. The machine-readable instructions described herein may be stored as data suitable for creating, manufacturing, and / or producing machine-executable instructions (e.g., portions of instructions, code, representations of code, etc.). For example, machine-readable instructions may be segmented and stored on one or more storage devices. Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, etc., so that they can be directly read, interpreted, and / or executed by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and stored on separate computing devices, wherein these parts, when decrypted, decompressed, and combined, form a set of executable instructions that implement programs such as those described herein.

[0084] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: assembly language, C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0085] As described above, Figure 12-15The instance process can be implemented using executable instructions (e.g., computer, machine, and / or hardware-readable instructions) stored on a non-transitory computer- and / or machine-readable medium, such as flash memory, read-only memory, cache memory, random access memory, and / or any other storage device or storage disk in which information can be stored for any duration (e.g., extended time period, permanent, transient, temporary buffered, and / or cached storage information). As used herein, the terms non-transitory computer-readable medium, non-transitory machine-readable medium, and / or non-transitory hardware-readable medium are explicitly defined as including any type of computer, machine, and / or hardware-readable storage device and / or storage disk, but excluding propagation and transmission media.

[0086] Figure 12 This is a flowchart representing instance process 1200, which can be executed to perform the symbolic and timed recovery techniques described herein. Figure 12 Example process 1200 begins at block 1202, where communication system 100 receives a receiver (RX) input signal at a wired receiver. For example, HPF 104 can receive RX input 112 from a terminal of a wired receiver (e.g., the receiver of an Ethernet PHY device).

[0087] At block 1204, communication system 100 samples the RX input signal and converts it into a digital input signal. For example, ADC 108 may sample the RX input 112 at a sampling rate of one sample per second, which can be used to recover one symbol per second. In some such instances, ADC 108 samples the RX input 112 to convert the RX input 112 into a digital input signal.

[0088] At block 1206, communication system 100 adjusts the amplitude of the digital input signal to produce a scaled digital input signal. For example, CAGC 116 can adjust the amplitude of the output from ADC 108.

[0089] At block 1208, communication system 100 adjusts the gain of the scaled digital input signal to produce an output signal. For example, DAGC 118 can use the output from gain loop circuit 132 to adjust the gain of the output from DC removal circuit 114.

[0090] At block 1210, the communication system 100 generates a decision feedback equalizer (DFE) output based on one or more decisions associated with previous symbols. For example, slicer circuit 128 may generate a third symbol 150 based on a first symbol 146 and / or a second symbol 148. In some such instances, DFE 130 may generate a noise error signal, which adder circuit 124 may use to generate DFE-corrected symbols.

[0091] At block 1212, communication system 100 determines whether timing loop lock-up has been achieved. For example, sequencer circuit 142 may determine that PLL 144 has been locked in response to the value of the accumulator of NCO 140 meeting a threshold (e.g., a lock-up threshold, a timing lock-up threshold, or a timing loop lock-up threshold). If, at block 1212, communication system 100 determines that timing loop lock-up has not been achieved, then control proceeds to block 1218 to generate a timing error based on the uncorrected symbol. For example, TED 136 may generate a timing error (e.g., a timing error signal) based on the first symbol 146. In response to the timing error generated at block 1218 based on the uncorrected symbol, communication system 100 adjusts the phase of the sampling operation at block 1220 based on the timing error. For example, NCO 140 may generate a control signal 152 based on the timing error from TED 136. In some of these instances, the phase interpolator circuit 110 can adjust the phase of the ADC 108 to control the timing of the ADC 108 sampling the RX input 112.

[0092] If, at block 1212, the communication system 100 determines that timing loop locking has been achieved, then at block 1214, the communication system 100 switches to DFE-corrected symbols. For example, in response to PLL 144 achieving locking, sequencer circuit 142 can instruct multiplexer 126 to switch from providing uncorrected symbols (e.g., first symbol 146) to TED 136 to providing DFE-corrected symbols (e.g., second symbol 148) to TED 136.

[0093] At block 1216, communication system 100 generates a timing error based on the DFE-corrected symbol. For example, TED 136 may generate a timing error (e.g., a timing error signal) based on the second symbol 148 and / or the third symbol 150. In response to generating the timing error based on the DFE-corrected symbol at block 1216, communication system 100 adjusts the phase of the sampling operation at block 1220 based on the timing error. For example, NCO 140 may generate a control signal 152 based on the timing error from TED 136. In some such instances, phase interpolator circuit 110 may adjust the phase of ADC 108 to control the timing of ADC 108 sampling RX input 112.

[0094] In response to adjusting the phase of the sampling operation based on timing error at block 1220, communication system 100 determines at block 1222 whether to continue monitoring the wired receiver. For example, DSP 102 may determine that another RX input is available at the wired receiver to continue data communication between the devices (e.g., wired transmitter and wired receiver). If communication system 100 determines at block 1222 to continue monitoring the wired receiver, then control returns to block 1202; otherwise... Figure 12 The instance process 1200 has ended.

[0095] Figure 13 This is a flowchart representing instance process 1300, which can be executed to perform constellation-based TED technology. Figure 13 The instance process 1300 begins at block 1302, where the communication system 100 determines the current (N) slicer decision based on one or more previously detected symbols. For example, slicer circuit 128 may determine a third symbol 150 as the current slicer decision based on one or more previously detected symbols. In some such instances, slicer circuit 128 may determine the current slicer decision as +1.

[0096] At block 1304, communication system 100 determines the previous (N-1) slicer decision. For example, TED 136 and / or TED 200 may determine that the previous slicer decision was 0. In some such instances, the previous slicer decision may be stored in the memory of DSP 102, TED 136, and / or TED 200. In some instances, TED 136 and / or TED 200 may query slicer circuitry 128 for the previous slicer decision.

[0097] At block 1306, communication system 100 determines the penultimate (N-2) slicer decision. For example, TED 136 and / or TED 200 may determine the previous slicer decision as -1. In some such instances, the previous slicer decision may be stored in the memory of DSP 102, TED 136, and / or TED 200. In some instances, TED 136 and / or TED 200 may query slicer circuitry 128 for the previous slicer decision.

[0098] At box 1308, communication system 100 detects the presence of a negative slope based on slicer decisions. For example, TED 136 and / or TED 200 can detect negative slopes based on the N-2, N-1, N sign transitions of +1, 0, and -1. In some such instances, TED 136 and / or TED 200 can detect zero-crossing transitions (e.g., zero-crossing sign transitions) based on the detection of +1, 0, and -1 sign transitions.

[0099] If, at box 1308, communication system 100 detects a negative slope based on a slicer decision, then at box 1310, communication system 100 generates a timing error as the negative of the previous timing error corresponding to the previously detected symbol. For example, TED 136 and / or TED 200 could output the timing error of the current symbol (N) based on the negative of the timing error of the previously detected symbol (N-1), as described above. Figure 3 As described. In response to a timing error generated at block 1310, control proceeds to block 1320 to adjust the phase based on the timing error. For example, phase interpolator circuit 110 and / or (more generally) PLL 144 can adjust the phase of ADC 108 to improve the sampling window for detecting the symbol of RX input 112.

[0100] If, at block 1308, the communication system 100 does not detect a negative slope based on the slicer decision, then control proceeds to block 1312 to detect the presence of a positive slope based on the slicer decision. For example, TED 136 and / or TED 200 can detect a positive slope based on the N-2, N-1, N sign transitions of -1, 0, and +1. In some such instances, TED 136 and / or TED 200 can detect zero-crossing transitions (e.g., zero-crossing sign transitions) based on the detection of -1, 0, and +1 sign transitions.

[0101] If, at box 1312, communication system 100 detects a positive slope based on the slicer decision, then at box 1314, communication system 100 generates a timing error as a positive value corresponding to the previous timing error of the previously detected symbol. For example, TED 136 and / or TED 200 could output the timing error of the current symbol (N) based on the positive value of the timing error of the previously detected symbol (N-1), as described above. Figure 3 As described. In response to a timing error generated at block 1314, control proceeds to block 1320 to adjust the phase based on the timing error. For example, phase interpolator circuit 110 and / or (more generally) PLL 144 can adjust the phase of ADC 108 to improve the sampling window for detecting the symbol of RX input 112.

[0102] If, at block 1312, communication system 100 fails to detect a positive slope based on the slicer decision, control proceeds to block 1316 to determine whether communication system 100 failed to detect a positive or negative slope based on the slicer decision. For example, TED136 and / or TED200 may fail to detect either a positive or negative slope based on the slicer decision. In some such instances, TED136 and / or TED200 may fail to detect zero-crossing transitions. In some such instances, TED136 and / or TED200 may output a previously determined timing error to improve the locking capability of PLL 144.

[0103] If, at box 1316, the communication system 100 can detect a positive or negative slope based on the slicer decision, then Figure 13 The process 1300 ends. If, at block 1316, the communication system 100 cannot detect a positive or negative slope based on the slicer decision, then at block 1318, the communication system 100 generates a timing error based on a previous timing error. For example, TED 136 and / or TED 200 can generate a timing error as a previously determined timing error (e.g., timing error of a previously detected symbol). In some such instances, in response to the timing error from TED 136 and / or TED 200, NCO 140 can output the stored value of the accumulator of NCO 140. In response to the timing error generated at block 1318, control proceeds to block 1320 to adjust the phase based on the timing error. For example, phase interpolator circuit 110 and / or (more generally) PLL 144 can adjust the phase of ADC 108 to improve the sampling window for detecting symbols of RX input 112. In response to adjusting the phase based on the timing error, Figure 13 The process ended at 1300.

[0104] Figure 14 This is a flowchart representing instance process 1400, which can be executed to perform pseudo-ML TED technology. Figure 14 The instance process 1400 begins at block 1402, where the communication system 100 determines the current (N) slicer decision based on one or more previously detected symbols. For example, slicer circuit 128 may determine a third symbol 150 as the current slicer decision based on one or more previously detected symbols. In some such instances, slicer circuit 128 may determine the current slicer decision as -1.

[0105] At block 1404, communication system 100 determines the previous (N-1) slicer decision and the penultimate (N-2) slicer decision. For example, TED 136 and / or TED 200 may determine the previous slicer decision as +1 and the penultimate slicer decision as -1. In some such instances, the previous slicer decision and / or penultimate slicer decision may be stored in the memory of DSP 102, TED 136, and / or TED 200. In some instances, TED 136 and / or TED 200 may query slicer circuitry 128 for the previous slicer decision and / or penultimate slicer decision.

[0106] At box 1406, the communication system 100 detects the presence of a peak sign point transition based on slicer decisions. For example, TED 136 and / or TED 200 can detect the peak sign point transition based on the N-2, N-1, N sign transitions of -1, +1, and -1.

[0107] If, at box 1406, communication system 100 detects a peak symbol point transition based on a slicer decision, then at box 1408, communication system 100 generates a timing error based on differential samples associated with the peak symbol point transition. For example, TED136 and / or TED 200 could be differentials to generate a timing error for the current symbol (N), as described above. Figure 4 As described. In some such instances, the differencer can perform... Figure 4 The second pseudocode 404. In response to a timing error occurring at block 1408, control proceeds to block 1418 to adjust the phase based on the timing error. For example, phase interpolator circuit 110 and / or (more generally) PLL 144 can adjust the phase of ADC 108 to improve the sampling window for detecting the symbol of RX input 112.

[0108] If, at block 1406, the communication system 100 does not detect a peak sign point transition based on the slicer decision, then control proceeds to block 1410 to detect the presence of a valley sign point transition based on the slicer decision. For example, TED 136 and / or TED 200 can detect valley sign point transitions based on +1, -1, +1, N-2, N-1, N sign transitions.

[0109] If, at box 1410, communication system 100 detects a valley sign point transition based on a slicer decision, then at box 1412, communication system 100 generates a timing error based on differential samples associated with the valley sign point transition. For example, TED136 and / or TED 200 could be differentials to generate a timing error for the current symbol (N), as described above. Figure 4 As described. In some such instances, the differencer can perform... Figure 4The second pseudocode 404. In response to a timing error occurring at block 1412, control proceeds to block 1418 to adjust the phase based on the timing error. For example, phase interpolator circuit 110 and / or (more generally) PLL 144 can adjust the phase of ADC 108 to improve the sampling window for detecting the symbol of RX input 112.

[0110] If, at block 1410, communication system 100 fails to detect a valley sign point transition based on the slicer decision, control proceeds to block 1414 to determine whether communication system 100 failed to detect a peak or valley sign point transition based on the slicer decision. For example, TED 136 and / or TED 200 may fail to detect either a peak or valley sign point transition based on the slicer decision. In some such instances, TED 136 and / or TED 200 may output a previously determined timing error to improve the locking capability of PLL 144.

[0111] If, at box 1414, the communication system 100 is able to detect a change in the sign point of a peak or valley based on a slicer decision, then... Figure 14 The process 1400 ends. If, at block 1414, the communication system 100 cannot detect a peak or valley symbol point transition based on the slicer decision, then at block 1416, the communication system 100 generates a timing error based on a previous timing error. For example, TED 136 and / or TED 200 can generate a timing error as a previously determined timing error (e.g., timing error of a previously detected symbol). In some such instances, in response to the timing error from TED 136 and / or TED 200, NCO 140 can output the stored value of the accumulator of NCO 140. In response to the timing error generated at block 1416, control proceeds to block 1418 to adjust the phase based on the timing error. For example, phase interpolator circuit 110 and / or (more generally) PLL 144 can adjust the phase of ADC 108 to improve the sampling window for detecting symbols at RX input 112. In response to adjusting the phase based on the timing error, Figure 14 The process ended at 1400.

[0112] Figure 15 This is a flowchart representing instance process 1500, which can be executed to perform intermediate symbol TED technology. Figure 15 The instance process 1500 begins at block 1502, where the communication system 100 determines the current (N) slicer decision based on one or more previously detected symbols. For example, slicer circuit 128 may determine a third symbol 150 as the current slicer decision based on one or more previously detected symbols. In some such instances, slicer circuit 128 may determine the current slicer decision as -1.

[0113] At block 1504, communication system 100 determines the previous (N-1) slicer decision. For example, TED 136 and / or TED 200 may determine that the previous slicer decision was 0. In some such instances, the previous slicer decision may be stored in the memory of DSP 102, TED 136, and / or TED 200. In some instances, TED 136 and / or TED 200 may query slicer circuitry 128 for the previous slicer decision.

[0114] At box 1506, communication system 100 detects the presence of an intermediate symbol based on slicer decisions of ((N-1) = -1) and (N = +1). For example, TED 136 and / or TED 200 may detect the first symbol position 508 based on the N-1, N symbol transitions of -1 and +1. If communication system 100 detects an intermediate symbol at box 1506 based on ((N-1) = -1) and (N = +1), then at box 1508, communication system 100 generates a timing error based on the difference between the intermediate symbol and the coefficient. For example, TED 136 and / or TED 200 may detect the first symbol position 508 based on the slicer decisions of ((N-1) = -1) and (N = +1). Figure 5 Pseudocode 502 generates a timing error. In response to the timing error generated at block 1508 based on the difference between the intermediate value and the coefficient, control proceeds to block 1522 to adjust the phase based on the timing error. For example, phase interpolator circuit 110 and / or (more generally) PLL 144 may adjust the phase of ADC 108 (e.g., increase or decrease the phase) to adjust and / or otherwise shift the sampling window in which the sign of RX input 112 is detected.

[0115] If, at box 1506, communication system 100 does not detect an intermediate symbol based on ((N-1) = -1) and (N = +1), then communication system 100 detects the presence of an intermediate symbol at box 1510 based on ((N-1) = +1) and (N = -1). For example, TED 136 and / or TED 200 can detect intermediate symbols based on the N-1, N symbol transitions of +1 and -1. If, at box 1510, communication system 100 detects an intermediate symbol based on ((N-1) = +1) and (N = -1), then at box 1512, communication system 100 generates a timing error based on the difference between the intermediate value and the coefficient. For example, TED 136 and / or TED 200 can detect intermediate symbols based on... Figure 5The pseudocode 502 generates a timing error. In some such instances, the coefficient may be 0. In response to the timing error generated at block 1512 based on the difference between the intermediate sign and the coefficient, control proceeds to block 1522 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) the PLL 144 may adjust the phase of the ADC 108 (e.g., increase or decrease the phase) to adjust and / or otherwise shift the sampling window in which the sign of the RX input 112 is detected.

[0116] If, at box 1510, the communication system 100 does not detect an intermediate symbol based on ((N-1) = +1) and (N = -1), then at box 1514, the communication system 100 detects the presence of an intermediate symbol based on ((N-1) = 0) and (N = +1). For example, TED 136 and / or TED 200 can detect intermediate (or mid) symbols based on the N-1, N symbol transitions of 0 and +1. If, at box 1514, the communication system 100 detects an intermediate symbol based on ((N-1) = 0) and (N = +1), then at box 1516, the communication system 100 generates a timing error based on the difference between the intermediate symbol and the coefficient. For example, TED 136 and / or TED 200 can generate a timing error based on the difference between the intermediate symbol and the coefficient. Figure 5 Pseudocode 502 generates a timing error. In response to the timing error generated at block 1516 based on the difference between the intermediate sign and the coefficient, control proceeds to block 1522 to adjust the phase based on the timing error. For example, phase interpolator circuit 110 and / or (more generally) PLL 144 may adjust the phase of ADC 108 (e.g., increase or decrease the phase) to adjust and / or otherwise shift the sampling window in which the sign of RX input 112 is detected.

[0117] If, at box 1514, communication system 100 does not detect an intermediate symbol based on ((N-1) = 0) and (N = +1), then communication system 100 detects the presence of an intermediate symbol at box 1518 based on ((N-1) = +1) and (N = 0). For example, TED136 and / or TED 200 can detect intermediate symbols based on the N-1, N symbol transitions of +1 and 0. If, at box 1518, communication system 100 detects an intermediate symbol based on ((N-1) = +1) and (N = 0), then at box 1520, communication system 100 generates a timing error based on the difference between the intermediate symbol and the coefficient. For example, TED 136 and / or TED 200 can generate a timing error based on the difference between the intermediate symbol and the coefficient. Figure 5The pseudocode 502 generates a timing error. In response to the timing error generated at block 1520 based on the difference between the intermediate sign and the coefficient, control proceeds to block 1522 to adjust the phase based on the timing error. For example, the phase interpolator circuit 110 and / or (more generally) PLL 144 can adjust the phase of the ADC 108 (e.g., increase or decrease the phase) to adjust and / or otherwise shift the sampling window in which the sign of the RX input 112 is detected. In response to the phase adjustment based on the timing error at block 1522, Figure 15 The process ends at 1500.

[0118] In this description, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, and C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A, B, and C. Similarly, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an embodiment that includes any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0119] The example systems, methods, apparatuses, and articles described herein include symbol and timing recovery techniques to achieve improved timing loop locking performance independent of channel length or ISI present in the channel. The example systems, methods, apparatuses, and articles described herein include constellation-based TED techniques to determine timing errors based on zero-crossing transitions. The example systems, methods, apparatuses, and articles described herein include pseudo-ML TED techniques to determine timing errors based on the detection of peak or valley symbol transitions. The example systems, methods, apparatuses, and articles described herein include intermediate symbol TED techniques to determine timing errors based on sample interpolation comparing the symbol midpoint with the expected midpoint. The example systems, methods, apparatuses, and articles described herein include a combination of constellation-based TED techniques and pseudo-ML TED techniques to improve TED gain, as both techniques utilize complementary symbol transitions. The example systems, methods, apparatuses, and articles described herein include a differential unit that utilizes one or more filters to perform pseudo-ML TED techniques. The example systems, methods, apparatuses, and articles described herein include an interpolation operation that uses one or more filters to perform pseudo-ML TED techniques. The example systems, methods, apparatus, and articles of art described herein include symbol and timing recovery techniques that enable a TED (Timing Error Detection) to carry forward a previous timing error value when a specified or expected symbol transition is not detected. Advantageously, the symbol and timing recovery techniques described herein can be implemented by any wired receiver, transmitter, transceiver, etc. (e.g., an Ethernet PHY device) to achieve reduced hardware costs and power consumption.

[0120] This document describes example methods, devices, systems, and artifacts for symbol and timing recovery, as well as related methods. Further examples and combinations thereof include the following:

[0121] Example 1 includes a device comprising: a feedforward equalizer (FFE) having an FFE output; an adder circuit having a first adder input, a second adder input, and a first adder output, the first adder input being coupled to the FFE output; a multiplexer (MUX) having a first MUX input, a second MUX input, and a MUX output, the first MUX input being coupled to the first adder output, and the second MUX input being coupled to the FFE output; a decision feedback equalizer (DFE) having a DFE output coupled to the second adder input; and a timing error detector (TED) having a first TED input coupled to the MUX output.

[0122] Example 2 includes the device of Example 1, wherein the adder circuit has a second adder output, the DFE has a DFE input, the TED has a second TED input, and the device further includes a slicer circuit having a slicer input, a first slicer output, and a second slicer output, the slicer input being coupled to the second adder output, the first slicer output being coupled to the DFE input, and the second slicer output being coupled to the second TED input.

[0123] Example 3 includes the device of Example 1, wherein the MUX is a first MUX, the MUX output is a first MUX output, the DFE has a first DFE output and a second DFE output, and the TED includes: a second MUX having a third MUX input, a fourth MUX input, a fifth MUX input, and a second MUX output, the third MUX input being coupled to the first DFE output, the fourth MUX input being coupled to the second DFE output; and a latch having a latch input and a latch output, the latch input being coupled to the second MUX output, and the latch output being coupled to the fifth MUX input.

[0124] Example 4 includes the device of Example 3, wherein the first MUX has a first MUX control input, the second MUX has a second MUX control input, and the device further includes a sequencer circuit having a first sequencer output coupled to the first MUX control input and a second sequencer output coupled to the second MUX control input.

[0125] Example 5 includes the device of Example 3, wherein the second MUX has a third MUX output, and the device further includes a phase-locked loop (PLL) having a PLL input coupled to the third MUX output.

[0126] Example 6 includes the device of Example 1, wherein the TED has a TED output, and the device further includes: a loop filter having a loop filter input and a loop filter output, the loop filter input being coupled to the TED output; a numerically controlled oscillator (NCO) having an NCO input and an NCO output, the NCO input being coupled to the loop filter output; and a phase detector having a phase detector input coupled to the NCO output.

[0127] Example 7 includes the device of Example 6, wherein the phase detector has a phase detector output, and the device further includes: an analog-to-digital converter (ADC) having a first ADC input and a second ADC input, the first ADC input being coupled to the phase detector output; a low-pass filter having a first filter input and a first filter output, the first filter output being coupled to the second ADC input; a high-pass filter having a second filter input and a second filter output, the second filter output being coupled to the first filter input; and a terminal coupled to the second filter input.

[0128] Example 8 includes the device of Example 1, wherein the FFE has an FFE input, the TED has a TED output, and the device further includes: a phase-locked loop (PLL) having a PLL input and a PLL output, the PLL input being coupled to the TED output; an analog-to-digital converter (ADC) having an ADC input and an ADC output, the ADC input being coupled to the PLL output; a DC removal circuit having a first input and a first output, the first input being coupled to the ADC output; a digital automatic gain control (AGC) circuit having a second input and a second output, the second input being coupled to the first output; and a deequalizer circuit having a third input and a third output, the third input being coupled to the second output, the third output being coupled to the FFE input.

[0129] Example 9 includes a receiver operable to receive a communication signal comprising a plurality of symbols, the receiver comprising: a memory containing instructions stored in the memory; a processor coupled to the memory and operable to execute the instructions to at least: detect one or more first symbols in the plurality of symbols in the communication signal based on a first phase of a sampling clock; determine a second symbol in the plurality of symbols in the communication signal based on the one or more first symbols; generate a voltage corresponding to a timing phase offset, the voltage being based on the second symbol; generate a control signal based on the second symbol in response to the voltage satisfying a threshold; and adjust the first phase to a second phase based on the control signal.

[0130] Example 10 includes the receiver of Example 9, wherein the processor is used to identify timing loop lock based on the voltage satisfying the threshold.

[0131] Example 11 includes the receiver of Example 9, wherein one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, and the processor is configured to: determine that the third symbol corresponds to a positive one value; determine that the fourth symbol corresponds to a zero value; determine that the fifth symbol corresponds to a negative one value; and detect a zero-crossing transition based on the determination.

[0132] Example 12 includes the receiver of Example 11, wherein the third symbol is the current decision of the slicer circuit, the timing phase offset is the second timing phase offset, and the processor is configured to, in response to the detection of the zero-crossing transition, determine the second symbol as the product of the sign of the current decision and the first timing phase offset corresponding to the fourth symbol.

[0133] Example 13 includes the receiver of Example 9, wherein one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, and the processor is configured to: determine that the third symbol corresponds to a negative one value; determine that the fourth symbol corresponds to a zero value; determine that the fifth symbol corresponds to a positive one value; and detect a zero-crossing transition based on the determination.

[0134] Example 14 includes the receiver of Example 13, wherein the third symbol is the current decision of the slicer circuit, the timing phase offset is the second timing phase offset, and the processor is configured to, in response to the detection of the zero-crossing transition, determine the second symbol as the product of the sign of the current decision and the first timing phase offset corresponding to the fourth symbol.

[0135] Example 15 includes the receiver of Example 9, wherein the processor is configured to: determine the value of a corresponding symbol among the one or more first symbols; and in response to determining that no zero-crossing transition was detected based on the value, determine that the second symbol is a zero value.

[0136] Example 16 includes the receiver of Example 9, wherein the timing phase offset is a second timing phase offset determined at a second time, and the processor is configured to: determine the value of a corresponding symbol among the one or more first symbols; and in response to determining that no zero-crossing transition was detected based on the value, determine that the second symbol is a first timing phase offset determined at a first time prior to the second time.

[0137] Example 17 includes the receiver of Example 9, wherein one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, and the processor is configured to: determine that the third symbol corresponds to a negative one value; determine that the fourth symbol corresponds to a positive one value; determine that the fifth symbol corresponds to a negative one value; and detect a peak symbol point transition based on the determination.

[0138] Example 18 includes the receiver of Example 17, wherein the third symbol is the current decision of the slicer circuit, the timing phase offset is the second timing phase offset, and the processor is configured to, in response to the detection of the peak symbol point transition: determine the difference between the first differential output and the second differential output; and determine the second symbol as the product of the difference and the first timing phase offset corresponding to the fourth symbol.

[0139] Example 19 includes the receiver of Example 9, wherein one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, and the processor is configured to: determine that the third symbol corresponds to a positive one value; determine that the fourth symbol corresponds to a negative one value; determine that the fifth symbol corresponds to a positive one value; and detect a peak symbol point transition based on the determination.

[0140] Example 20 includes the receiver of Example 19, wherein the third symbol is the current decision of the slicer circuit, the timing phase offset is the second timing phase offset, and the processor is configured to, in response to the detection of the peak symbol point transition: determine the difference between the first differential output and the second differential output; and determine the second symbol as a negative one value, the product of the difference and the first timing phase offset corresponding to the fourth symbol.

[0141] Example 21 includes the receiver of Example 9, wherein one or more first symbols include a third symbol and a fourth symbol, and the processor is configured to: determine that the third symbol corresponds to a first value; determine that the fourth symbol corresponds to a second value; detect a fifth symbol having a third value between the first value and the second value; and determine the second symbol based on the difference between the third value and the fourth value, the fourth value being based on half of the sum of the first value and the second value.

[0142] Example 22 includes at least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause a processor to at least: detect one or more first symbols of a digital signal based on a first phase of a sampling clock; determine a second symbol based on the one or more first symbols; generate a voltage corresponding to a timing phase offset, the voltage being based on the second symbol; generate a control signal based on the second symbol in response to the voltage satisfying a threshold; and adjust the first phase to a second phase based on the control signal.

[0143] Example 23 includes at least one non-transitory computer-readable storage medium of Example 22, wherein the one or more first symbols include a third symbol and a fourth symbol, the timing phase offset is a second timing phase offset, and the instruction, when executed, causes the processor to: detect a zero-crossing transition of the digital signal based on the one or more first symbols; and, in response to the detection of the zero-crossing transition, determine that the second symbol is the product of the sign of the third symbol and the first timing offset corresponding to the fourth symbol.

[0144] Example 24 includes at least one non-transitory computer-readable storage medium of Example 22, wherein the one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, the timing phase offset is a second timing phase offset, and the instructions, when executed, cause the processor to: detect a peak or valley symbol point transition of the digital signal based on the one or more first symbols; determine, in response to the detection of the peak or valley symbol point transition, a difference between a first differential output associated with the third symbol and a second differential output associated with the fifth symbol; and determine the second symbol as the product of the difference and the first timing phase offset corresponding to the fourth symbol.

[0145] Example 25 includes at least one non-transitory computer-readable storage medium of Example 22, wherein one or more first symbols include a third symbol, a fourth symbol, and a fifth symbol, the timing phase offset is a second timing phase offset, and the instruction, when executed, causes the processor to: determine that the fourth symbol is between the third symbol and the fifth symbol; and determine the second symbol based on the difference between a first value and a second value corresponding to the fourth symbol, the second value being based on half the sum of the third value corresponding to the third symbol and the fourth value corresponding to the fifth symbol.

[0146] The term "coupled" is used throughout this specification. The term may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then in a first instance, device A is coupled to device B; or in a second instance, if the intervening component C substantially does not alter the functional relationship between device A and device B such that device B is controlled by device A via control signals provided by device A, then device A is coupled to device B via the intervening component C.

[0147] A device “configured” to perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform the function, and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. The configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnections, or a combination thereof.

[0148] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnections or endpoints between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0149] The circuits or devices described herein that include certain components may alternatively be adapted to be coupled to those components to form the described circuits or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., semiconductor dies and / or integrated circuit (IC) packages) and may be adapted to be coupled to at least some of the said passive elements and / or sources during or after manufacturing, e.g., by an end user and / or a third party, to form the described structure.

[0150] The circuits described herein can be reconfigured to include replaced components, thereby providing functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can be replaced by multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can be replaced by multiple resistors or capacitors coupled in series with a single resistor or capacitor between the same two nodes.

[0151] Unless otherwise stated, “approximately,” “around,” or “substantially” before a value means + / - 10% of the value.

[0152] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are also possible.

Claims

1. A receiver operable to receive a communication signal comprising a plurality of symbols, the receiver comprising: A memory containing instructions stored in the memory; A processor, coupled to the memory, and operable to execute the instructions to at least: Detect one or more first symbols among the plurality of symbols in the communication signal based on the first phase of the sampling clock; Determine the second symbol among the plurality of symbols in the communication signal based on the one or more first symbols; A voltage corresponding to a timing phase offset is generated, the voltage being based on the second symbol; In response to the voltage meeting the threshold, a control signal is generated based on the second symbol; and The first phase is adjusted to the second phase based on the control signal.

2. The receiver of claim 1, wherein the processor is configured to identify timing loop lock based on the voltage satisfying the threshold.

3. The receiver of claim 1, wherein the one or more first symbols comprise a third symbol, a fourth symbol, and a fifth symbol, and the processor is configured to: The third symbol is determined to correspond to a positive one value; It is determined that the fourth symbol corresponds to a zero value; It is determined that the fifth symbol corresponds to a negative one value; and Zero-crossing transitions are detected based on the determination mentioned above.

4. The receiver of claim 3, wherein the third symbol is the current decision of the slicer circuit, the timing phase offset is the second timing phase offset, and the processor is configured to determine, in response to the detection of the zero-crossing transition, that the second symbol is the product of the sign of the current decision and the first timing phase offset corresponding to the fourth symbol.

5. The receiver of claim 1, wherein the one or more first symbols comprise a third symbol, a fourth symbol, and a fifth symbol, and the processor is configured to: The third symbol is determined to correspond to a negative one value; It is determined that the fourth symbol corresponds to a zero value; It is determined that the fifth symbol corresponds to a positive one value; and Zero-crossing transitions are detected based on the determination mentioned above.

6. The receiver of claim 5, wherein the third symbol is the current decision of the slicer circuit, the timing phase offset is the second timing phase offset, and the processor is configured to determine, in response to the detection of the zero-crossing transition, that the second symbol is the product of the sign of the current decision and the first timing phase offset corresponding to the fourth symbol.

7. The receiver of claim 1, wherein the processor is configured to: Determine the value of the corresponding symbol among the one or more first symbols; and In response to determining that no zero-crossing transition was detected based on the value, the second symbol is determined to be a zero value.

8. The receiver of claim 1, wherein the timing phase offset is a second timing phase offset determined at a second time, and the processor is configured to: Determine the value of the corresponding symbol among the one or more first symbols; and In response to determining that no zero-crossing transition was detected based on the value, the second symbol is determined to be a first timing phase offset determined at a first time prior to the second time.

9. The receiver of claim 1, wherein the one or more first symbols comprise a third symbol, a fourth symbol, and a fifth symbol, and the processor is configured to: The third symbol is determined to correspond to a negative one value; The fourth symbol is determined to correspond to a positive one value; It is determined that the fifth symbol corresponds to a negative one value; and The peak sign point transition is detected based on the determination.

10. The receiver of claim 9, wherein the third symbol is the current decision of the slicer circuit, the timing phase offset is a second timing phase offset, and the processor is configured to respond to the detection of the peak symbol point transition: Determine the difference between the outputs of the first and second differential converters; and The second symbol is determined to be the product of the difference and the first timing phase offset corresponding to the fourth symbol.

11. The receiver of claim 1, wherein the one or more first symbols comprise a third symbol, a fourth symbol, and a fifth symbol, and the processor is configured to: The third symbol is determined to correspond to a positive one value; The fourth symbol is determined to correspond to a negative one value; It is determined that the fifth symbol corresponds to a positive one value; and The peak sign point transition is detected based on the determination.

12. The receiver of claim 11, wherein the third symbol is the current decision of the slicer circuit, the timing phase offset is the second timing phase offset, and the processor is configured to respond to the detection of the peak symbol point transition: Determine the difference between the outputs of the first and second differential converters; and The second symbol is determined to be a negative one, and the difference is the product of the first timing phase offset corresponding to the fourth symbol.

13. The receiver of claim 1, wherein the one or more first symbols comprise a third symbol and a fourth symbol, and the processor is configured to: It is determined that the third symbol corresponds to the first value; It is determined that the fourth symbol corresponds to the second value; Detect a fifth symbol having a third value between the first and second values; and The second symbol is determined based on the difference between the third and fourth values, wherein the fourth value is based on half the sum of the first and second values.

14. At least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause a processor to at least: One or more first symbols of a digital signal are detected based on the first phase of the sampling clock; The second symbol is determined based on one or more of the first symbols; A voltage corresponding to a timing phase offset is generated, the voltage being based on the second symbol; In response to the voltage meeting the threshold, a control signal is generated based on the second symbol; and The first phase is adjusted to the second phase based on the control signal.

15. The at least one non-transitory computer-readable storage medium of claim 14, wherein the one or more first symbols comprise a third symbol and a fourth symbol, the timing phase offset is a second timing phase offset, and the instruction, when executed, causes the processor to: The zero-crossing transition of the digital signal is detected based on one or more first symbols; and In response to the detection of the zero-crossing transition, the second symbol is determined to be the product of the sign of the third symbol and the first timing offset corresponding to the fourth symbol.

16. The at least one non-transitory computer-readable storage medium of claim 14, wherein the one or more first symbols comprise a third symbol, a fourth symbol, and a fifth symbol, the timing phase offset is a second timing phase offset, and the instruction, when executed, causes the processor to: Based on the one or more first symbols, the peak or valley sign point transition of the digital signal is detected; Detection in response to the peak sign point transition or the valley sign point transition: Determine the difference between the first differential output associated with the third symbol and the second differential output associated with the fifth symbol; and The second symbol is determined to be the product of the difference and the first timing phase offset corresponding to the fourth symbol.

17. The at least one non-transitory computer-readable storage medium of claim 14, wherein the one or more first symbols comprise a third symbol, a fourth symbol, and a fifth symbol, the timing phase offset is a second timing phase offset, and the instruction, when executed, causes the processor to: The fourth symbol is determined to be between the third symbol and the fifth symbol; and The second symbol is determined based on the difference between a first value and a second value corresponding to the fourth symbol, wherein the second value is based on half the sum of a third value corresponding to the third symbol and a fourth value corresponding to the fifth symbol.

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