Variable rate frequency shift keying (FSK) modulation and demodulation method, device and system based on field programmable gate array (FPGA)

Abstract

The invention discloses a variable-rate FSK (Frequency Shift Keying) modulation and demodulation method, device and system based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of FSK modulation and demodulation. Based on the FPGA, the method comprises the following steps of: controlling selection of a frequency word according to data to be sent during signal transmission, controlling updating of the frequency word according to a preset symbol rate, controlling a DDS (Direct Digital Synthesizer) to generate FSK modulation signals with different modulation orders by the frequency word; the operation frequency of the DDS is a modulation signal sampling rate; when a signal is received, a variable multiple CIC decimation filter is firstly used for decimation according to integral multiples, the sampling rate of the received signal is reduced, then Farrow structure fractional multiple decimation filtering is used for adjusting the sampling rate to a first symbol rate, and FSK demodulation and bit synchronization recover data in the adjusted signal. According to the invention, the transmission rate can be dynamically adjusted according to the channel state, the spectrum resource utilization rate is improved, and the transmission performance is improved.

Description

Technical Field

[0001] This invention relates to the field of FSK modulation and demodulation technology, and more specifically, to a variable rate FSK modulation and demodulation method, apparatus and system based on FPGA implementation. Background Technology

[0002] The existing FPGA-based FSK modulation and demodulation technology mostly adopts a fixed symbol rate scheme according to the communication system, which has the following drawbacks: (1) It cannot dynamically adjust the transmission rate according to the channel status, resulting in low spectrum resource utilization or deterioration of transmission performance; (2) It relies on multiple modulation channels when switching rates, resulting in high system complexity and high cost; (3) Traditional interpolation / decimation filters are difficult to balance computational efficiency and signal integrity when adjusting rates over a wide range. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a variable rate FSK modulation and demodulation method, device and system based on FPGA, which can dynamically adjust the transmission rate according to the channel state, improve the utilization of spectrum resources and enhance transmission performance.

[0004] The objective of this invention is achieved through the following solution: A variable rate FSK modulation and demodulation method implemented on FPGA, comprising the following steps performed on FPGA: When transmitting a signal, the frequency word is selected according to the data to be transmitted, and the frequency word is updated according to the preset symbol rate. The frequency word controls the DDS to generate an FSK modulated signal of the modulation order. The DDS operates at the sampling rate of the modulation signal. During signal reception, a variable-multiple CIC decimation filter is first used to decimate the signal by integer multiples to reduce the sampling rate of the received signal. Then, a Farrow structure fractional decimation filter is used to adjust the sampling rate to the first symbol rate. FSK demodulation and bit synchronization are then used to recover the data from the adjusted signal.

[0005] Furthermore, the generation of FSK modulation signals with different modulation orders specifically generates FSK / 4FSK / 8FSK modulation signals.

[0006] Furthermore, the reduction in the received signal sampling rate is specifically reduced to near the first symbol rate; the first symbol rate includes 8 times the symbol rate, so the adjusted signal includes 8 times the number of samples.

[0007] Furthermore, the step of controlling the selection of the frequency word based on the data to be transmitted and controlling the update of the frequency word based on the preset symbol rate specifically includes the following sub-steps: During transmission, the DDS and accumulator operate at a frequency of f clk It runs under the clock; The DDS outputs modulated waves of different frequencies based on the input frequency word. The FTW calculation formula for the frequency word is Equation (1): (1); in, f dst For the target frequency, N Frequency word width; The accumulator accumulates based on the rate control word, and the rate control word RTW is calculated using formula (2). (2); in, R s For the target symbol rate, M This refers to the accumulator bit width. The data to be modulated is stored in a FIFO. When the FIFO is determined to be non-empty, it is read according to the modulation order. n The data is processed in bits, and the corresponding modulation frequency word is selected based on the data. When the accumulator overflows, the frequency word of the DDS is updated. This process is repeated until all data is transmitted.

[0008] Furthermore, the step of first using a variable-multiple CIC decimation filter to decimate in integer multiples specifically includes the following sub-steps: configuring the CIC decimation multiple, where the CIC level is 4 and the decimation multiple is... R cic When the value is a power of 2, equation (3) is used to directly truncate the output; when the value is not a power of 2, equation (4) is used to first compensate the output result and then truncate it. (3) (4); Indicates the original CIC output. This indicates that the CIC truncation output is used when the extraction factor is a power of 2. This indicates that the CIC truncation output is used when the extraction multiple is not a power of 2.

[0009] Furthermore, the step of adjusting the sampling rate to the first symbol rate using the Farrow structure fractional decimation filter specifically includes the following sub-steps: The Farrow filter structure consists of two modules: a timing control module and a polynomial interpolation module. The timing control module is controlled by a counter-controlled oscillator (NCO). The polynomial interpolation module is used for the values ​​within the interval... t ∈[ m k T s , ( m k +1) T sinterpolation point y ( t ),use x [ m k The surrounding I Interpolate for each sample point: (5); in, , The base point is y ( kT i The most recent preceding one on the objective timeline x ( mT s The position of the decimal is ) and the decimal interval is . y ( kT i The most recent preceding one on the objective timeline x ( m k T s The position of ) That is to h ( t According to the interval T s Discrete filter coefficients obtained after sampling h ( i ) index; if I If it is even, then , ,like I If it is an odd number, then , ; k is the index of the current sample point to be interpolated. The sampling interval for the output signal. Let I be the sampling interval of the input signal, I be the number of samples used in each interpolation calculation, and x be the input signal. Here, m represents the interpolation coefficients, and m is the index of the input signal sample point. According to the Lagrange interpolation formula: (6); For the Farrow interpolation structure, where t i = ( m k - i ) T s , t = ( m k + u k ) Ts Substituting, we get: (7); for I Piecewise second-order parabolic interpolation of = 4, the interpolation calculation formula is as follows: y ( k ) = [ v (2) u k + v (1)] u k + v (0), where: (8); This yields a second-order parabolic interpolation Farrow filter, which is used to adjust the sampling rate to the first symbol rate.

[0010] Furthermore, the FSK demodulation and bit synchronization recover data from the adjusted signal, specifically including the following sub-steps: The data to be demodulated is stored in a shift register according to the clock. The shift register value is correlated with the reference frequency component. Then, the sum of squares of the in-phase and quadrature components is calculated. Finally, the maximum value of each branch is found to obtain the demodulation result. The FSK / 4FSK / 8FSK signals with different frequency intervals are detected by dynamically adjusting the reference frequency component value.

[0011] Further, the shift register value is correlated with the reference frequency component, then the sum of squares of the in-phase and quadrature components is calculated, and finally the maximum value is found by comparing each branch to obtain the demodulation result. This process specifically includes the following sub-steps: Considering that FSK includes two frequencies f 1 and f 2. Corresponding angular frequency ω 1 = 2 πf 1 and ω 2 = 2 πf 2. The symbol period is T The received signal is as shown in equation (9), where, s i ( t () is the signal being sent. i = 1, 2, n ( t It is additive white noise; r ( t ) = s i ( t ) + n ( t (9); For each frequency f i Set in-phase and quadrature reference signals. Used for normalizing energy: (10); For the received signal r ( t Correlation operations are performed with each reference signal to obtain I and Q channel outputs, for frequency... f i I and Q channel outputs: (11); The energy of each frequency branch is calculated as shown in equation (12), where z i 2 Indicates frequency as f i Signal energy: (12); Finally, the energies of the two frequency branches are compared to determine the corresponding frequencies, as shown in equation (13): (13); By increasing the number of frequency branches and selecting the maximum z i 2 The corresponding frequency can be extended to 4FSK / 8FSK demodulation.

[0012] A variable rate FSK modulation and demodulation device based on FPGA includes a processor and a memory, wherein the memory stores a computer program that executes the method described in any of the preceding methods when the computer program is loaded by the processor.

[0013] A variable rate FSK modulation and demodulation system based on FPGA includes the variable rate FSK modulation and demodulation device based on FPGA as described above.

[0014] The beneficial effects of this invention include: This invention can dynamically adjust the transmission rate according to the channel state, thereby improving the utilization of spectrum resources and enhancing transmission performance. Furthermore, it can balance computational efficiency and signal integrity when adjusting the rate over a wide range, reducing system complexity and cost. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of the variable rate FSK / 4FSK / 8FSK modulation and demodulation process in the method of this embodiment of the invention; Figure 2 This is a diagram illustrating the variable rate transmission process in the method of this embodiment of the invention; Figure 3 This is a schematic diagram of Farrow polynomial interpolation calculation in the method of an embodiment of the present invention; Figure 4 This refers to the Farrow polynomial interpolation structure in the method of this embodiment of the invention; Figure 5 This is a diagram of the FSK / 4FSK / 8FSK demodulation structure in the method of this embodiment of the invention. Detailed Implementation

[0017] All features disclosed in all embodiments of this specification, or steps in all methods or processes implied in the disclosure, may be combined and / or extended or replaced in any way, except for mutually exclusive features and / or steps.

[0018] The specific implementation process of this invention is as follows: In a preferred embodiment of the present invention, a variable rate FSK / 4FSK / 8FSK modulation and demodulation method based on FPGA is specifically proposed, the main process of which is as follows: Figure 1 As shown, the process includes the following steps: selecting the frequency word according to the data to be transmitted, updating the frequency word according to the preset symbol rate, and using the frequency word to control the DDS to generate FSK / 4FSK / 8FSK modulated signals. The operating frequency of the DDS is the sampling rate of the modulated signal. During reception, a variable multiple CIC decimation filter is first used to decimate the signal in integer multiples to reduce the sampling rate of the received signal to approximately 8 times the symbol rate. Then, a Farrow structure fractional decimation filter is used to adjust the sampling rate to 8 times the symbol rate. FSK demodulation and bit synchronization recover the data from the signal with 8 times the number of samples.

[0019] In other, more specific embodiments, the present invention includes a variable-rate transmission process, such as... Figure 2 As shown, the following steps are performed: During transmission, the DDS and accumulator operate at a frequency of f clkOperating under the clock, the DDS outputs modulated waves of different frequencies based on the input frequency word. The frequency word (FTW) is calculated using Equation 1, where... f dst For the target frequency, N The frequency word width is specified; the accumulator accumulates based on the rate control word, and the rate control word (RTW) calculation formula uses Equation 2, where... R s For the target symbol rate, M The accumulator bit width is specified; the data to be modulated is stored in the FIFO, and when the FIFO is not empty, it is read according to the modulation order. n The data is processed in bits, and the corresponding modulation frequency word is selected based on the data. When the accumulator overflows, the frequency word of the DDS is updated. This process is repeated until all data is transmitted.

[0020] (1); (2); The embodiment of this invention also includes a variable rate reception process, which mainly reduces the sampling rate of the ADC sampled data to 8 times the symbol rate for demodulation processing and frame synchronization. Specifically, it includes the following steps: integer multiple CIC decimation filter processing and fractional multiple Farrow structure decimation filter processing. The CIC decimation factor can be configured online, and the CIC processing gain changes accordingly when the decimation factor changes. To maintain a constant output gain, when the CIC stage number is 4 and the decimation factor is... R cic When the value is a power of 2, the output is directly truncated, as shown in Equation 3, where... Indicates the original CIC output. This indicates that the CIC output is truncated when the extraction multiple is a power of 2; for multiples other than powers of 2, the output result is first compensated and then truncated, as shown in Equation 4, where... This indicates that the CIC truncation output is used when the extraction multiple is not a power of 2.

[0021] (3) (4); Indicates the original CIC output. This indicates that the CIC truncation output is used when the extraction factor is a power of 2. This indicates that the CIC truncation output is used when the extraction multiple is not a power of 2.

[0022] In this embodiment, the Farrow filter architecture is essentially a digitally efficient implementation of Lagrange polynomial interpolation. The Farrow filter structure mainly consists of two modules: a timing control module and a polynomial interpolation module. The timing control module is controlled by a counter-controlled oscillator (NCO). The polynomial interpolation calculation is as follows: Figure 3 As shown, for those located in the interval t ∈[ m k T s , ( m k +1) T s interpolation point y ( t ),use x [ m k The surrounding I Interpolate for each sample point: (5); in, , The base point is y ( kT i The most recent preceding one on the objective timeline x ( mT s The position of the decimal is ) and the decimal interval is . y ( kT i The most recent preceding one on the objective timeline x ( m k T s The position of ) That is to h ( t According to the interval T s Discrete filter coefficients obtained after sampling h ( i ) index; if I If it is even, then , ,like I If it is an odd number, then , ; k is the index of the current sample point to be interpolated. The sampling interval for the output signal. Let I be the sampling interval of the input signal, I be the number of samples used in each interpolation calculation, and x be the input signal. Here, m represents the interpolation coefficients, and m is the index of the input signal sample point. According to the Lagrange interpolation formula: (6); For the Farrow interpolation structure, where t i = ( m k - i ) T s , t = ( m k + u k ) T s Substituting the values, we get: (7); for I Piecewise second-order parabolic interpolation of = 4, the interpolation calculation formula is as follows: y ( k ) = [ v (2) u k + v (1)] u k + v (0), where: (8); Therefore, the structure of the Farrow filter for second-order parabolic interpolation within the FPGA can be obtained as follows: Figure 4 As shown, its structure is simple and can save a lot of computing resources.

[0023] The embodiments of this invention use an energy-decision-based incoherent detection method for FSK / 4FSK / 8FSK demodulation, considering that FSK contains two frequencies. f 1 and f 2 (corresponding angular frequency) ω 1 = 2 πf 1 and ω 2 = 2 πf 2) Symbol period is T The received signal is as shown in Equation 9, where, s i ( t ) is the signal sent ( i = 1, 2), n ( t ) is additive white noise.

[0024] r ( t ) = s i (t ) + n ( t (9); For each frequency f i Set in-phase and quadrature reference signals ( (used for normalizing energy) (i=1,2)(10); For the received signal r ( t Correlation operations are performed with each reference signal to obtain I and Q channel outputs, for frequency... f i I and Q channel outputs: (11); To eliminate phase effects, the energy of each frequency branch is calculated as shown in Equation 12, where z i 2 Indicates frequency as f i The signal energy.

[0025] (12); Finally, the energies of the two frequency branches are compared to determine the corresponding frequency, as shown in Equation 13.

[0026] (13); By increasing the number of frequency branches and selecting the maximum z i 2 The corresponding frequency can be extended to 4FSK / 8FSK demodulation.

[0027] In this embodiment of the invention, the sampling rate of the signal to be demodulated is reduced to 8 times the symbol rate by CIC and Farrow filters. FSK / 4FSK / 8FSK demodulation can be achieved by discretizing the reference frequency signal into 8 samples and performing correlation calculations with the received signal. Figure 5 As shown, the data to be demodulated is stored in a shift register according to the clock cycle. The shift register value is correlated with the reference frequency component, and then the sum of squares of the in-phase and quadrature components is calculated. Finally, the maximum value of each branch is compared to obtain the demodulation result. The reference frequency component is generated in the same way as FSK modulation, except that the modulation sampling rate is changed to 8 times the symbol rate. By dynamically adjusting the reference frequency component value, FSK / 4FSK / 8FSK signals with different frequency intervals can be detected.

[0028] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0029] According to one aspect of the present invention, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0030] In another aspect, embodiments of the present invention also provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods described in the above embodiments.

Claims

1. A variable rate FSK modulation and demodulation method based on FPGA implementation, characterized in that, The following steps are performed based on the FPGA: When transmitting a signal, the frequency word is selected according to the data to be transmitted, and the frequency word is updated according to the preset symbol rate. The frequency word controls the DDS to generate FSK modulated signals of different modulation orders. The operating frequency of the DDS is the sampling rate of the modulation signal. During signal reception, a variable-multiple CIC decimation filter is first used to decimate the signal by integer multiples to reduce the sampling rate of the received signal. Then, a Farrow structure fractional decimation filter is used to adjust the sampling rate to the first symbol rate. FSK demodulation and bit synchronization are then used to recover the data from the adjusted signal.

2. The variable rate FSK modulation and demodulation method based on FPGA implementation according to claim 1, characterized in that, The generation of FSK modulation signals with different modulation orders specifically generates FSK / 4FSK / 8FSK modulation signals.

3. The variable rate FSK modulation and demodulation method based on FPGA implementation according to claim 1, characterized in that, The reduction in the received signal sampling rate is specifically reduced to near the first symbol rate; the first symbol rate includes 8 times the symbol rate, so the adjusted signal includes 8 times the number of samples.

4. The variable rate FSK modulation and demodulation method based on FPGA implementation according to claim 1, characterized in that, The step of controlling the selection of frequency words based on the data to be transmitted and controlling the updating of frequency words based on a preset symbol rate specifically includes the following sub-steps: During transmission, the DDS and accumulator operate at a frequency of f clk It runs under the clock; The DDS outputs modulated waves of different frequencies based on the input frequency word. The FTW calculation formula for the frequency word is Equation (1): (1)； in, f dst For the target frequency, N Frequency word width; The accumulator accumulates based on the rate control word, and the rate control word RTW is calculated using formula (2). (2)； in, R s For the target symbol rate, M This refers to the accumulator bit width. The data to be modulated is stored in a FIFO. When the FIFO is determined to be non-empty, it is read according to the modulation order. n The data is processed in bits, and the corresponding modulation frequency word is selected based on the data. When the accumulator overflows, the frequency word of the DDS is updated. This process is repeated until all data is transmitted.

5. The variable rate FSK modulation and demodulation method based on FPGA implementation according to claim 1, characterized in that, The first step involves using a variable-multiple CIC decimation filter to decimate in integer multiples, specifically including the following sub-steps: configuring the CIC decimation multiple, with a CIC level of 4 and a decimation multiple of... R cic When the value is a power of 2, equation (3) is used to directly truncate the output; when the value is not a power of 2, equation (4) is used to first compensate the output result and then truncate it. ；(3) (4)； Indicates the original CIC output. This indicates that the CIC truncation output is used when the extraction factor is a power of 2. This indicates that the CIC truncation output is used when the extraction multiple is not a power of 2.

6. The variable rate FSK modulation and demodulation method based on FPGA implementation according to claim 1, characterized in that, The step of adjusting the sampling rate to the first symbol rate using the Farrow structure fractional decimation filter specifically includes the following sub-steps: The Farrow filter structure consists of two modules: a timing control module and a polynomial interpolation module. The timing control module is controlled by a counter-controlled oscillator (NCO). The polynomial interpolation module is used for the values ​​within the interval... t ∈[ m k T s , ( m k +1) T s interpolation point y ( t ),use x [ m k The surrounding I Interpolate for each sample point: (5)； in, , The base point is y ( kT i The most recent preceding one on the objective timeline x ( mT s The position of the decimal is ) and the decimal interval is . y ( kT i The most recent preceding one on the objective timeline x ( m k T s The position of ) That is to h ( t According to the interval T s Discrete filter coefficients obtained after sampling h ( i ) index; if I If it is even, then , ,like I If it is an odd number, then , ; k is the index of the current sample point to be interpolated. The sampling interval for the output signal. Let I be the sampling interval of the input signal, I be the number of samples used in each interpolation calculation, and x be the input signal. Here, m represents the interpolation coefficients, and m is the index of the input signal sample point. According to the Lagrange interpolation formula: (6)； For the Farrow interpolation structure, where t i = ( m k - i ) T s , t = ( m k + u k ) T s Substituting, we get: (7)； for I Piecewise second-order parabolic interpolation of = 4, the interpolation calculation formula is as follows: y ( k ) = [ v (2) u k + v (1)] u k + v (0), where: (8)； This yields a second-order parabolic interpolation Farrow filter, which is used to adjust the sampling rate to the first symbol rate.

7. The variable rate FSK modulation and demodulation method based on FPGA implementation according to claim 2, characterized in that, The FSK demodulation and bit synchronization recover data from the adjusted signal, specifically including the following sub-steps: The data to be demodulated is stored in a shift register according to the clock. The shift register value is correlated with the reference frequency component. Then, the sum of squares of the in-phase and quadrature components is calculated. Finally, the maximum value of each branch is found to obtain the demodulation result. The FSK / 4FSK / 8FSK signals with different frequency intervals are detected by dynamically adjusting the reference frequency component value.

8. The variable rate FSK modulation and demodulation method based on FPGA implementation according to claim 7, characterized in that, The shift register value is correlated with the reference frequency component, then the sum of squares of the in-phase and quadrature components is calculated, and finally the maximum value of each branch is found to obtain the demodulation result. This process includes the following sub-steps: Considering that FSK includes two frequencies f 1 and f 2. Corresponding angular frequency ω 1 = 2 πf 1 and ω 2 = 2 πf 2. The symbol period is T The received signal is as shown in equation (9). in, s i ( t () is the signal being sent. i = 1, 2, n ( t It is additive white noise; r ( t ) = s i ( t ) + n ( t )(9)； For each frequency f i Set in-phase and quadrature reference signals. Used for normalizing energy: (10)； For the received signal r ( t Correlation operations are performed with each reference signal to obtain I and Q channel outputs, for frequency... f i I and Q channel outputs: (11)； The energy of each frequency branch is calculated as shown in equation (12), where z i 2 Indicates frequency as f i Signal energy: (12)； Finally, the energies of the two frequency branches are compared to determine the corresponding frequencies, as shown in equation (13): (13)； By increasing the number of frequency branches and selecting the maximum z i 2 The corresponding frequency can be extended to 4FSK / 8FSK demodulation.

9. A variable rate FSK modulation and demodulation device based on FPGA, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that, when loaded by the processor, executes the method as described in any one of claims 1 to 8.

10. A variable rate FSK modulation and demodulation system based on FPGA, characterized in that, Includes the FPGA-based variable rate FSK modulation and demodulation device as described in claim 9.

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