FPGA video daughter card based on SlimSAS interface and transmission method
By adopting the SlimSAS interface and related circuit design, the FMC interface dependency and transmission mode compatibility issues were resolved, achieving low-cost and high-stability FPGA video transmission. It supports automatic switching between TMDS and FRL dual modes, improving device interoperability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-12
- Publication Date
- 2026-03-13
AI Technical Summary
In existing FPGA systems, the FMC interface relies on specific motherboard hardware support, which is costly, has a long transmission path that is prone to signal attenuation and interference, and lacks compatible design for TMDS and FRL transmission modes, thus limiting device interoperability.
The SlimSAS interface is used to replace the FMC interface. By combining the SlimSAS interface module, heavy driver, multiplexer, level conversion circuit and independent power supply system, automatic compatibility between TMDS and FRL dual modes is achieved. The transmission mode is automatically identified by the FPGA internal switching mechanism and the external MUX circuit.
It reduces interface costs, expands applicable scenarios, improves signal transmission stability and anti-interference capabilities, and enables seamless switching and device interoperability between TMDS and FRL modes.
Smart Images
Figure CN121664938A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic interface technology, and more specifically, to an FPGA video daughter card and transmission method based on the SlimSAS interface. Background Technology
[0002] FPGA systems often use the FMC (FPGA Mezzanine Card) interface to extend HDMI functionality. All data, clock, and power signals are transmitted through the FMC connector, a typical implementation being the HDMI daughter card from ChipEasy Electronics. This design is feasible in standard scenarios, but it has inherent limitations: the FMC interface relies on specific hardware support on the motherboard, making it unusable on motherboards without an FMC interface; additionally, the FMC interface is expensive, and its long transmission path is prone to signal attenuation and interference. Furthermore, existing solutions lack compatibility with both TMDS (Transition Minimized Differential Signaling) and FRL (Fixed Rate Link) transmission modes (TMDS for HDMI 2.0 and below, and FRL for HDMI 2.1 and above), limiting interoperability with different versions of devices. Summary of the Invention
[0003] To address the aforementioned technical problems in related technologies, this invention proposes an FPGA video daughter card based on the SlimSAS interface, comprising:
[0004] The SlimSAS interface module is used to provide the SlimSAS physical interface.
[0005] The first driver connects to the SlimSAS interface module at one end and to the HDMI interface module at the other end to provide an HDMI signal transmission channel.
[0006] The second driver is connected to the SlimSAS interface module at one end and to the HDMI interface module at the other end, and is used to provide an HDMI signal receiving channel.
[0007] A first multiplexer, one end of which is connected to the SlimSAS interface module, and the other end of which is connected to the second driver;
[0008] A second multiplexer, one end of which is connected to the SlimSAS interface module, and the other end of which is connected to a level conversion circuit;
[0009] Level conversion circuit, used to convert the levels of CEC and HPD signals;
[0010] HDMI interface module, used to provide HDMI physical interface.
[0011] Specifically, the SlimSAS interface module is a standard SFF-8654 connector.
[0012] Specifically, the first and second drivers are ONSEMI's NB7NQ621M.
[0013] Specifically, the first and second multiplexers are MAXIN's MAX3841.
[0014] Specifically, the level conversion circuit is a TXS0108E level conversion chip.
[0015] Specifically, it also includes: a power module, including a local DC-DC converter and a filtering circuit; it is connected to the 12V power supply on the motherboard via an ATX 4PIN power connector, and then supplies power to the FPGA video daughter card through the DC-DC conversion circuit.
[0016] Specifically, it also includes: an I2C level conversion circuit I2CSW, wherein the I2C level conversion circuit is a TCA9617 chip, used for level conversion of I2C signals.
[0017] Secondly, another embodiment of the present invention discloses an FPGA video transmission method based on the SlimSAS interface for use in the aforementioned FPGA video daughter card based on the SlimSAS interface, comprising the following steps:
[0018] S1, the FPGA detects the clock frequency or LTP of the input signal;
[0019] S2, if TMDS characteristics are detected, enable the TMDS link and use low-power differential signal processing; if FRL is detected, switch to the FRL link and activate multi-channel fixed-rate transmission.
[0020] Specifically, the detected TMDS feature is the detection of a stable clock; the detected LTP negotiation sequence is the detection of the FRL bit.
[0021] Specifically, step S2 involves the FPGA selecting either the TMDS or FRL path via the MODE_SEL signal of the first multiplexer.
[0022] This invention uses SlimSAS instead of FMC, employing the standard SlimSAS (SFF-8654) interface as the main connector. Its cost is significantly lower than that of the FMC connector, making it more common in servers and industrial motherboards and applicable to a wider range of scenarios. Furthermore, this embodiment achieves automatic compatibility between TMDS and FRL modes. Utilizing the FPGA's internal switching mechanism in conjunction with an external MUX switching circuit, the FPGA analyzes the input signal characteristics (clock frequency or LTP training sequence) in real time, automatically identifying and switching to the corresponding mode (TMDS or FRL). Furthermore, it employs independent power supply, resulting in more independent and stable power delivery and stronger anti-interference capabilities. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of an FPGA video daughter card structure based on the SlimSAS interface provided in an embodiment of the present invention;
[0025] Figure 2 This is a schematic diagram illustrating the specific working process of the FPGA video daughter card with the SlimSAS interface provided in this embodiment of the invention.
[0026] Figure 3 This is a schematic diagram of mode switching provided in an embodiment of the present invention. Detailed Implementation
[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.
[0028] Example 1
[0029] refer to Figure 1 This embodiment discloses an FPGA video daughter card based on the SlimSAS interface, which includes:
[0030] The SlimSAS interface module provides a physical connection interface for high-speed serial signal input and output. It uses a standard SFF-8654 connector and supports 8 channels of differential signal transmission (4 channels for transmit TXP / N<0:3>, 4 channels for receive RXP / N<0:3>). The channel bandwidth supports 12Gbps / channel, with a total bandwidth of up to 96Gbps, meeting the transmission requirements of HDMI 2.1 FRL mode (up to 48Gbps). The physical layer directly interfaces with the FPGA's SerDes port, reducing intermediate conversion circuits, shortening signal path length, and minimizing signal attenuation.
[0031] In this embodiment, the SlimSAS interface module is connected to the FPGA PHY controller.
[0032] The first driver, Redriver1, is connected to the SlimSAS interface module at one end to enhance the 4-channel transmit signal TXP / N<0:3>; the other end is connected to the HDMI interface module to provide the HDMI transmit signal channel.
[0033] The second driver, Redriver2, connects to the SlimSAS interface module on one end to enhance the 4-channel received signal RXP / N<0:3>; and to the HDMI interface module on the other end to provide an HDMI received signal channel.
[0034] The Redriver chips (Redriver1 and Redriver2) use ONSEMI's NB7NQ621M as the HDMI signal redriver, supporting adaptive equalization and de-emphasis to ensure signal eye diagram integrity. Redriver1 is used to enhance the transmit path signal, and Redriver2 is used to enhance the receive path signal.
[0035] The first multiplexer (MUX) is connected at one end to the SlimSAS interface module and at the other end to the second driver. The first multiplexer uses MAXIN's MAX3841 as a high-speed analog switch, which selects the TMDS or FRL path according to the MODE_SEL signal.
[0036] One end of the second multiplexer (MUX) is connected to the SlimSAS, and the other end is connected to the level conversion circuit. The second multiplexer is used to provide CEC and HPD signal channels.
[0037] The second multiplexer uses MAXIN's MAX3841.
[0038] A level conversion circuit is used to convert the levels of CEC and HPD signals.
[0039] The TI (TEXAS INSTRUMENTS) TXS0108E level conversion chip is used to handle the level conversion of single-ended signals such as CEC (Consumer Electronics Control) and HPD (Hot Plug Detect) (e.g., 3.3V↔5V).
[0040] CEC and HPD are control signals for interaction between the HDMI device and the FPGA. The HDMI device uses a 5V level, while the FPGA requires a 3.3V level. Therefore, this embodiment provides a level conversion circuit to realize the level conversion between HDMI and FPGA.
[0041] The I2C level conversion circuit I2CSW in this embodiment uses TI's TCA9617 chip for I2C signal level conversion.
[0042] HDMI interface module: Connects to downstream display devices to complete signal output.
[0043] The HDMI interface module in this embodiment provides HDMI transmit signal HDMI-TX and HDMI receive signal HDMI-RX. The HDMI-TX port is used to send processed TMDS or FRL signals to the display, and the HDMI-RX port is used to acquire external video signals.
[0044] The power module employs an independent power supply system, including a local DC-DC converter and filtering circuit, to provide stable, low-noise power to the system. It connects to the motherboard's 12V power supply via an ATX 4-pin power connector, and then powers the FPGA video daughter card (using the SlimSAS interface in this example) through a DC-DC conversion circuit.
[0045] Reference Appendix Figure 2 The specific working process of the SlimSAS interface FPGA video daughter card in this embodiment is as follows:
[0046] 1) Signal Input: The upstream video source (such as an HDMI source device) outputs a video signal (including TMDS_RXP / N<0:3>, CEC, HPD, and I2C signals) to the HDMI-RX port, which is then transmitted to the SlimSAS interface. TMDS_RXP / N<0:3> is the TMDS differential receive signal output by the HDMI source device, containing 3 data signals (RXP / N...). <0> RXP / N <1> RXP / N <2> ) and 1 clock signal (RXP / N) <3> (This signal is a clock signal in TMDS mode and a data signal in FRL mode). RXP / N<0:3> is a differential receive signal adapted to the SlimSAS interface after signal processing, while TMDS_RXP / N<0:3> is the original input signal of RXP / N<0:3>. Both are essentially differential signals, but the former is the standard HDMI signal format, while the latter is the signal format adapted to the SlimSAS interface.
[0047] 2) Signal Reception and Enhancement: After receiving the signal via the SlimSAS interface, Redriver2 performs signal enhancement processing on TMDS_RXP / N<0:3> to compensate for attenuation during transmission, improve signal integrity, and output RXP / N<0:3> after processing. Here, RXP / N<0:2> represents three differential data signals used to transmit the red, green, and blue components of video data and control information; RXP / N<3> represents the differential clock signal (in TMDS mode) used to synchronize video data transmission.
[0048] 3) Signal Conversion and Switching: RXP / N<0:2> is directly transmitted to the FPGA. RXP / N<3> is converted by the MUX unit (MAX3841) to RXP / N3 (data signal in FRL mode) or CLKP / N (differential clock signal). CLKP / N is an independent differential clock signal used for internal clock synchronization within the FPGA, ensuring precise alignment between the data signal and the clock signal and avoiding data transmission errors. The reason for this conversion by the MUX unit is that the transmission mechanisms of TMDS and FRL are different. Routing RXP / N<3> in two paths can satisfy the signal transmission and clock synchronization requirements of both modes respectively.
[0049] 4) FPGA Processing: The FPGA parses signals through its internal PHY (Physical Layer) controller while simultaneously monitoring signal characteristics (clock frequency or LTP sequence) in real time. If the source device only supports TMDS mode (such as HDMI 2.0 devices), the FPGA directly processes the TMDS data; if the source device supports FRL mode (such as HDMI 2.1 devices), the FPGA switches to the FRL high-speed link. Furthermore, CEC and HPD signals are converted to FPGA-compatible levels via a level conversion circuit (TXS0108E), and I2C signals are converted by a TCA9617 before being transmitted to the FPGA, enabling device interaction control and status detection.
[0050] 5) Signal Output Conversion: The signal output after FPGA processing is TXP / N<0:3> (differential transmit signal adapted to the SlimSAS interface), CEC, HPD, and SCL / SDA (serial clock and serial data for I2C signals). TXP / N<0:3> is the differential transmit signal output from the FPGA adapted to the SlimSAS interface, which is enhanced by Redriver1 and converted to TMDS_TXP / N<0:3> (HDMI standard transmit signal); the CEC and HPD signals are restored to HDMI standard levels after level conversion; SCL / SDA is used for parameter configuration between the FPGA and the HDMI device (such as reading EDID information), and is adapted to the I2C interface of the HDMI device after level conversion.
[0051] 6) Output and display: The processed signal is directly output from the FPGA to the downstream display device (such as a monitor) to complete the video rendering.
[0052] Introduction to the mode switching mechanism (see appendix for details) Figure 3 ):
[0053] 1) Detection Phase: The FPGA PHY controller monitors signal characteristics in real time through internal circuitry. For example, during initialization, it detects the clock frequency or LTP (Link Training Pattern) sequence of the input signal: the typical clock frequency for TMDS mode is ≤340MHz, while FRL mode uses the LTP negotiation sequence (such as the 16b / 18b encoding defined in the HDMI 2.1 specification).
[0054] 2) Switching Logic: If TMDS (stable clock) characteristics are detected, the controller enables the TMDS link and uses low-power differential signal processing; if FRL (LTP sequence) characteristics are detected, the controller switches to the FRL link and activates multi-channel fixed-rate transmission (up to 48Gbps). The switching time is short, allowing for seamless adaptation to different devices.
[0055] 3) Fault tolerance: Built-in error detection circuit (such as CRC check) ensures that the signal is not interrupted during the switching process.
[0056] This embodiment uses SlimSAS instead of FMC, employing the standard SlimSAS (SFF-8654) interface as the main connector. Its cost is significantly lower than FMC connectors, and it is more commonly found on servers and industrial motherboards, making it suitable for a wider range of applications. Furthermore, this embodiment achieves automatic compatibility between TMDS and FRL modes. Utilizing the FPGA's internal switching mechanism in conjunction with an external MUX switching circuit, the FPGA analyzes the input signal characteristics (clock frequency or LTP training sequence) in real time, automatically identifying and switching to the corresponding mode (TMDS or FRL). Additionally, it employs independent power supply, resulting in more independent and stable power delivery and stronger anti-interference capabilities.
[0057] Example 2
[0058] This embodiment discloses an FPGA video transmission method based on the SlimSAS interface, which is applied to the FPGA video daughter card based on the SlimSAS interface in Embodiment 1, and includes the following steps:
[0059] S1, the FPGA detects the clock frequency or LTP of the input signal;
[0060] S2, if TMDS characteristics are detected, enable the TMDS link and use low-power differential signal processing; if FRL is detected, switch to the FRL link and activate multi-channel fixed-rate transmission.
[0061] Specifically, the detected TMDS feature is the detection of a stable clock; the detected LTP negotiation sequence is the detection of the FRL bit.
[0062] The specific step S2 is as follows: The FPGA selects the TMDS or FRL path through the MODE_SEL signal of the first multiplexer.
[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An FPGA video daughter card based on the SlimSAS interface, characterized in that: include: The SlimSAS interface module is used to provide the SlimSAS physical interface. The first driver connects to the SlimSAS interface module at one end and to the HDMI interface module at the other end to provide an HDMI signal transmission channel. The second driver is connected to the SlimSAS interface module at one end and to the HDMI interface module at the other end, and is used to provide an HDMI signal receiving channel. A first multiplexer, one end of which is connected to the SlimSAS interface module, and the other end of which is connected to the second driver; The second multiplexer has one end connected to the SlimSAS interface module and the other end connected to the level conversion circuit. A level conversion circuit, which is used to convert the levels of CEC and HPD signals; HDMI interface module, used to provide HDMI physical interface.
2. The FPGA video daughter card based on the SlimSAS interface according to claim 1, characterized in that: The SlimSAS interface module is a standard SFF-8654 connector.
3. The FPGA video daughter card based on the SlimSAS interface according to claim 1, characterized in that: The first and second drivers are ONSEMI's NB7NQ621M.
4. The FPGA video daughter card based on the SlimSAS interface according to claim 1, characterized in that: The first and second multiplexers are MAXIN's MAX3841.
5. The FPGA video daughter card based on the SlimSAS interface according to claim 1, characterized in that: The level conversion circuit is a TXS0108E level conversion chip.
6. The FPGA video daughter card based on the SlimSAS interface according to claim 1, characterized in that: Also includes: The power module includes a local DC-DC converter and a filtering circuit; it is connected to the 12V power supply on the motherboard via an ATX 4PIN power connector, and then supplies power to the FPGA video daughter card through the DC-DC conversion circuit.
7. The FPGA video daughter card based on the SlimSAS interface according to claim 1, characterized in that: Also includes: The I2C level conversion circuit I2CSW is a TCA9617 chip used for level conversion of I2C signals.
8. A video transmission method based on an FPGA video daughter card with a SlimSAS interface according to any one of claims 1-7, characterized in that: It includes the following steps: S1, the FPGA detects the clock frequency or LTP of the input signal; S2, if TMDS characteristics are detected, enable the TMDS link and use low-power differential signal processing; if FRL is detected, switch to the FRL link and activate multi-channel fixed-rate transmission.
9. The video transmission method according to claim 8, characterized in that: The detected TMDS feature is the detection of a stable clock; the FRL bit between the two bits detects the LTP negotiation sequence.
10. The video transmission method according to claim 8, characterized in that: Step S2 specifically involves the FPGA selecting either the TMDS or FRL path via the MODE_SEL signal of the first multiplexer.