Baseband processing system

Abstract

A baseband processing system is configured by using a first processor, a first accelerator device, and a second accelerator device, and baseband processing steps respectively executed by the first accelerator device and the second accelerator device are configured on the basis of the first processor, a series of baseband processing steps of data can be jointly completed by the first accelerator device and the second accelerator device. Therefore, a series of baseband processing steps are allocated to the plurality of accelerator devices to be executed, so that each accelerator device only focuses on executing specific baseband processing steps as few as possible, the specificity of the accelerator devices is improved, efficient cooperation among different accelerator devices is realized, and the overall energy consumption of the baseband processing system is further reduced. Moreover, a plurality of accelerator devices which can be configured by the processor are arranged in the baseband processing system, so that the accelerator devices can be flexibly configured or expanded based on an actual scene, the flexibility of the baseband processing system is improved, and the cloudization requirement of a base station is favorably met.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a baseband processing system. Background Technology

[0002] Mobile communication technology is constantly evolving to meet people's ever-growing demand for wireless communication. 5G (5th generation mobile networks or 5th generation wireless systems) is the latest generation of mobile communication technology currently in commercial use and is gradually becoming more widespread.

[0003] As the most important component of a 5G network, the function of a 5G base station can be divided into three parts: Centralized Unit (CU), Distributed Unit (DU), and Radio Unit (RU). Currently, in a 5G network, a DU typically connects to one or more RUs, thereby processing uplink and downlink messages associated with one or more RUs.

[0004] For DUs (Data Controllers), because they need to process a large number of uplink and downlink packets related to RUs (Remote Roots), and each packet requires a series of complex baseband processing steps, the hardware in DUs is usually highly specialized to ensure that they can quickly and efficiently complete the complex processing of packets. In cloud-based baseband solutions, due to the need to support higher flexibility and resource sharing capabilities, more general-purpose computing power needs to be introduced, which often leads to higher energy consumption for DUs in cloud-based baseband solutions. Summary of the Invention

[0005] This application provides a baseband processing system that can reduce the overall energy consumption of the baseband processing system and improve the flexibility of the baseband processing system, which is conducive to meeting the cloudification requirements of base stations.

[0006] Firstly, a baseband processing system is provided, comprising: a first processor, a first accelerator device, and a second accelerator device. A communication link exists between the first and second accelerator devices, supporting direct communication between them. In other words, the communication link between the first and second accelerator devices is essentially a peer-to-peer communication bus, meaning data transmission between them can be directly completed based on this bus without needing to pass through a centralized control node (such as the first processor).

[0007] The first processor is used to configure the first accelerator device to perform a first baseband processing step and to configure the second accelerator device to perform a second baseband processing step. The first accelerator device is used to perform the first baseband processing step on the input first data and send the processed data to the second accelerator device; the second accelerator device is used to perform the second baseband processing step on the data sent by the first accelerator device to obtain the target data.

[0008] In other words, both the first and second accelerators are only a part of a series of baseband processing steps for the message data, and the processing steps performed by the first and second accelerators do not overlap. Furthermore, after completing the configured first baseband processing steps on the input first data, the first accelerator directly sends the processed data to the second accelerator without needing to be relayed through other components (such as a processor or host memory), ensuring the efficiency of the joint baseband processing by the first and second accelerators.

[0009] In this solution, a baseband processing system is constructed using a first processor, a first accelerator, and a second accelerator. The baseband processing steps executed by the first and second accelerators are configured based on the first processor, enabling the first and second accelerators to jointly complete a series of baseband processing steps. Furthermore, the first and second accelerators are connected via a communication link supporting direct communication, ensuring direct data interaction between them. By distributing a series of baseband processing steps in the message data processing flow to multiple accelerators, the required baseband processing steps can be allocated according to the computing power characteristics of each accelerator. The direct communication capability of the peer-to-peer communication bus enables efficient collaboration between different accelerators, thereby reducing the overall energy consumption of the baseband processing system. Moreover, setting multiple accelerators configurable by the processor in the baseband processing system allows for flexible configuration or expansion of the accelerators based on actual scenarios, improving the flexibility of the baseband processing system and facilitating the cloudification requirements of base stations.

[0010] In one possible implementation, the first accelerator is further configured to trigger the execution of a first baseband processing step on the first data after receiving a first task start signal, according to the configuration of the first processor; the first accelerator is further configured to send a second task start signal to the second accelerator after sending the processed data to the second accelerator; the second accelerator is further configured to trigger the execution of a second baseband processing step on the data sent by the first accelerator after receiving the second task start signal, according to the configuration of the first processor.

[0011] In other words, the first processor configures the first accelerator device to perform the first baseband processing step on the first data upon receiving the first task start signal, and configures the first accelerator device to send the second task start signal to the second accelerator device after sending the second data. Furthermore, the first processor also configures the second accelerator device to perform the second baseband processing step on the second data upon receiving the second task start signal. Thus, based on the configuration of the first and second accelerator devices by the first processor, close cooperation between the first and second accelerator devices can be achieved to realize baseband data processing.

[0012] In one possible implementation, the first data resides in the memory used by the first processor, and the first acceleration device is further configured to retrieve the first data from the memory after receiving a first task start signal. That is, the first acceleration device is also connected to the memory used by the first processor via a peer-to-peer communication link. In this way, the first acceleration device can directly read data from the memory used by the first processor based on the peer-to-peer communication link.

[0013] In this solution, by having the first accelerator device directly read input data from the memory used by the first processor, the step of the first processor forwarding input data to the first accelerator device can be eliminated, thereby improving the efficiency of data processing and reducing the processing pressure on the first processor.

[0014] In one possible implementation, the baseband processing system further includes: a second processor; the first processor and the first accelerator are located on the first device, and the second processor and the second accelerator are located on the second device; a data exchange device is connected between the first device and the second device, and the data exchange device supports a direct communication link across devices; the first accelerator sends the processed data to the second accelerator through the data exchange device.

[0015] In one possible implementation, the first processor is specifically used to negotiate with the second processor to configure the second acceleration device to perform the second baseband processing steps.

[0016] In other words, the first accelerator and the second accelerator are actually located on different devices and are managed by different processors. Therefore, in order to enable the accelerators on different devices to jointly perform baseband processing, the processors on the two devices can first negotiate to determine how the first accelerator and the second accelerator should coordinate to perform baseband processing.

[0017] In one possible implementation, the baseband processing system further includes: a network interface card (NIC); the NIC is used to receive fronthaul data and write the first data, which includes in-phase quadrature (IQ) IQ signals, into the memory of the first acceleration device, so that the first acceleration device can retrieve the first data from the memory.

[0018] In other words, the first processor can configure the network card to write received data into the memory of the first acceleration device. For example, the first processor sends configuration information to the network card, which indicates that the storage address for uplink data is the memory address in the first acceleration device.

[0019] In one possible implementation, the network interface card (NIC) and the first acceleration device are separate. The first processor is configured to configure the NIC to write the forward data containing IQ signals into the memory address of the first acceleration device via a direct communication link after receiving the forward data containing IQ signals.

[0020] In one possible implementation, the network interface card (NIC) is integrated into the first acceleration device. That is, the NIC and the first acceleration device are combined into one unit, which can also be understood as the first acceleration device also having fronthaul data transmission and reception capabilities. The first acceleration device is used to perform a first baseband processing step on the data containing IQ signals received through the NIC after it meets the rules configured by the first processor.

[0021] That is, when the network card and the first acceleration device are integrated into one unit, the first processor can be configured to start the first baseband processing step on the data including the IQ signal after the first acceleration device has received data including the IQ signal of one symbol or one slot of the air interface through the network card, without needing to trigger the first acceleration device to execute the first baseband processing step through a task start signal.

[0022] In one possible implementation, the baseband processing system further includes a third acceleration device. The network interface card (NIC) is also used to write the second data, according to the configuration of the first processor, into the memory of the third acceleration device via a communication link; the third acceleration device is used to perform baseband processing steps on the second data.

[0023] In other words, the network interface card (NIC) actually sends different data to different acceleration devices for processing based on the configuration of the primary processor. This achieves load balancing among the acceleration devices and allows for the selection of the appropriate acceleration device for different baseband data processing steps. Thus, by configuring the NIC to send data to different acceleration devices, multiple acceleration devices in the baseband processing system can be flexibly configured to process various types of data based on actual needs, improving the flexibility of the solution.

[0024] In one possible implementation, the source address of the fronthaul data to which the first data belongs is a first address, which is the fronthaul link address of the first cell; the source address of the fronthaul data to which the second data belongs is a second address, which is the fronthaul link address of the second cell; the first processor is also configured to configure the network card to send fronthaul data with the source address of the first address to the first acceleration device, and to send fronthaul data with the source address of the second address to the third acceleration device.

[0025] In other words, by configuring a network card on the first processor to send data from different source addresses to different acceleration devices, it is possible to achieve data splitting processing for different source addresses, thereby splitting the fronthaul data of different cells to different acceleration devices for processing, so as to meet the cloudification requirements of baseband processing in practical applications.

[0026] In one possible implementation, the fronthaul data to which the first data belongs is first type of fronthaul data, and the fronthaul data to which the second data belongs is second type of fronthaul data; the first processor is also configured to configure the network card to send the first data to the first acceleration device and to send the second data to the third acceleration device.

[0027] In other words, the first processor can be configured to process different types of fronthaul data to different acceleration devices, thereby enabling different types of fronthaul data to be distributed to different acceleration devices for processing.

[0028] In one possible implementation, the first type of fronthaul data is used to transmit data for one type of air interface signal or air interface channel, and the second type of fronthaul data is used to transmit data for another type of air interface signal or air interface channel. Since different air interface signals or channels may require different baseband processing flows, offloading the data from different air interface signals or channels to different acceleration devices for different baseband processing improves the energy efficiency of baseband processing.

[0029] In one possible implementation, the network interface card, the first accelerator, and the second accelerator are located on the first device, and the third accelerator is located on the second device. A data exchange device is connected between the first device and the second device, and the data exchange device supports direct communication links across devices.

[0030] In this solution, different types of data are forwarded by the network interface card (NIC) to acceleration devices on different equipment for processing. This enables independent processing of different data, and the acceleration devices operate independently without affecting each other, facilitating flexible upgrades of the acceleration devices. For example, if a processing function upgrade is performed for a certain type of data (such as data from a specific cell), this data can be offloaded to new acceleration devices for processing, ensuring that the original business data processing is not affected.

[0031] In one possible implementation, the baseband processing system further includes a second processor; the first processor is specifically configured to negotiate with the second processor to configure a third acceleration device to perform baseband processing steps.

[0032] In one possible implementation, the first processor is specifically configured at a first time node to configure the first accelerator device to execute the first baseband processing step and to configure the second accelerator device to execute the second baseband processing step; the first processor is further configured at a second time node to configure the first accelerator device to execute the third baseband processing step and to configure the second accelerator device to execute the fourth baseband processing step; wherein the processing steps included in the third baseband processing step are different from the processing steps included in the first baseband processing step, and the processing steps included in the fourth baseband processing step are different from the processing steps included in the second baseband processing step.

[0033] That is, the first processor can flexibly configure the baseband processing steps actually executed by each acceleration device, so that each acceleration device can execute different baseband processing steps at different time points to meet the actual application requirements.

[0034] In one possible implementation, the first acceleration device is further configured to perform a third baseband processing step on the input third data after acquiring the third task start signal, which is acquired after the second time node.

[0035] In one possible implementation, the amount of data that the first accelerator needs to process at the first time point is different from the amount of data that needs to be processed at the second time point.

[0036] In one possible implementation, the baseband processing system further includes: a fourth accelerator device, which is added to the system after the first processor configures the first accelerator device to perform the first baseband processing step and configures the second accelerator device to perform the second baseband processing step; the first processor is also configured to reconfigure the first accelerator device and / or the second accelerator device, as well as the baseband processing steps performed by the fourth accelerator device, based on the capabilities of the fourth accelerator device.

[0037] In one possible implementation, the first processor is further configured to send a capability query request to the fourth accelerator and receive a capability query response returned by the fourth accelerator to obtain the capabilities of the fourth accelerator.

[0038] In one possible implementation, the first accelerator and the second accelerator are hardware devices with different structures; or, the first accelerator and the second accelerator are hardware devices with the same structure.

[0039] In one possible implementation, the first and second accelerator devices are Field Programmable Gate Array (FPGA) chips, Application-Specific Integrated Circuit (ASIC) chips, Networking Processor (NP) chips, CPUs, Graphics Processing Units (GPUs), Neural-network Processing Units (NPUs), or Tensor Processing Units (TPUs). Attached Figure Description

[0040] Figure 1 A schematic diagram of the architecture of a 5G network access network device provided in this application;

[0041] Figure 2 This application provides a schematic diagram of the structure of a baseband processing system;

[0042] Figure 3 A schematic diagram illustrating a series of baseband processing steps jointly performed by a first accelerator device and a second accelerator device, as provided in this application;

[0043] Figure 4 A schematic diagram illustrating the process of a first accelerator device and a second accelerator device performing baseband processing based on a configuration of a first processor, provided in this application;

[0044] Figure 5 A schematic diagram of another baseband processing system provided in this application;

[0045] Figure 6 A schematic diagram of another baseband processing system provided in this application;

[0046] Figure 7 A schematic diagram of a process for performing baseband processing based on a configuration of a first accelerator device and a second accelerator device located on different devices, provided for this application;

[0047] Figure 8 A schematic diagram of another baseband processing system provided in this application;

[0048] Figure 9 A schematic diagram illustrating a network interface card, a first accelerator, and a second accelerator jointly performing a series of baseband processing steps, provided in this application;

[0049] Figure 10 A schematic diagram illustrating the process of a network interface card, a first accelerator device, and a second accelerator device completing baseband processing based on the configuration of a first processor, provided in this application;

[0050] Figure 11 A schematic diagram of another baseband processing system provided in this application;

[0051] Figure 12A A schematic diagram of the network card forwarding the first and second data provided in this application;

[0052] Figure 12B This application provides a schematic diagram of a network interface card (NIC) forwarding first and second data.

[0053] Figure 12C This application provides another schematic diagram of a network interface card (NIC) forwarding first and second data.

[0054] Figure 12D A schematic diagram of the format of a fronthaul eCPRI data packet provided for this application;

[0055] Figure 13 A schematic diagram of another baseband processing system provided in this application;

[0056] Figure 14 A schematic diagram showing a change in the baseband processing steps performed by an acceleration device provided in this application;

[0057] Figure 15 A schematic diagram of another baseband processing system provided in this application;

[0058] Figure 16 A schematic diagram of the structure of the network device provided in this application. Detailed Implementation

[0059] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0060] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0061] In current communication networks, communication between access network devices and terminal devices follows a specific protocol layer structure. This protocol layer can be divided into a control plane protocol layer and a user plane protocol layer. The control plane protocol layer may include at least one of the following: radio resource control (RRC) layer, packet data convergence protocol (PDCP) layer, radio link control (RLC) layer, media access control (MAC) layer, and physical (PHY) layer. The user plane protocol layer may include at least one of the following: service data adaptation protocol (SDAP) layer, PDCP layer, RLC layer, MAC layer, and physical layer.

[0062] For example, please refer to Figure 1 , Figure 1 This application provides a schematic diagram of the architecture of an access network device for a 5G network. Figure 1 As shown, the access network equipment in a 5G network includes CU, DU, and RU. A CU is typically connected to one or more DUs, and a DU is typically connected to one or more RUs.

[0063] CU and DU implement different protocol layer functions of the wireless network: for example, CU is configured to implement the functions of the PDCP layer and above (such as the RRC layer and / or SDAP layer); DU is configured to implement the functions of the protocol layers below the PDCP layer (such as the RLC layer, MAC layer, and / or PHY layer).

[0064] The RU is typically configured to handle the transmission and reception of air interface radio electromagnetic waves, including antenna, radio frequency, and some PHY layer functions.

[0065] DU and RU can cooperate to implement the functions of the PHY layer. A DU can be connected to one or more RUs. The functions of DU and RU can be configured in various ways depending on the design. For example, a DU can be configured to implement baseband functions, and an RU can be configured to implement RF functions. Another example is that a DU can be configured to implement higher-level functions in the PHY layer, and an RU can be configured to implement lower-level functions in the PHY layer, or both lower-level and RF functions. Higher-level functions in the physical layer can include a portion of the physical layer's functions that are closer to the MAC layer, while lower-level functions in the physical layer can include another portion of the physical layer's functions that are closer to the mid-RF side.

[0066] The connection between the CU and DU is called the midhaul. The connection between the DU and RU is called the fronthaul. The fronthaul primarily transmits in-phase quadrature (IQ) signals, requiring low latency and high bandwidth. The one-way latency requirement is 100–250 µs; the bandwidth requirement is several times the air interface data rate. For example, when the fronthaul uses the evolved Common Public Radio Interface (eCPRI) protocol, the fronthaul bandwidth requirement is approximately 4–5 times the air interface rate.

[0067] In recent years, as operators have increased their requirements for the flexibility of wireless networks in terms of construction, deployment and operation and maintenance, cloud technology has been introduced into the field of Radio Access Network (RAN). Through the cloud-based deployment of CU and DU, namely Cloud RAN, the flexibility and deployment speed of RAN are improved, more flexible resource scheduling and load balancing are achieved, thereby reducing deployment and operation and maintenance costs.

[0068] However, for DUs (Dedicated Units), because they need to process a large number of uplink and downlink packets related to RUs (Remote Roots), and each packet requires a series of complex baseband processing steps, DUs currently typically use dedicated hardware to perform these steps. This dedicated hardware is highly specialized and can complete all baseband processing steps for uplink and downlink packets efficiently and promptly. However, if a single dedicated hardware unit performs all the baseband processing steps for a packet in a DU, it is often difficult to achieve flexible scalability, making cloud deployment of the DU challenging. On the other hand, if a cloud-deployed DU uses general-purpose hardware to complete the complex processing of uplink and downlink packets, it will result in high power consumption.

[0069] In view of this, this application provides a baseband processing system, which is constructed by employing a first processor, a first accelerator, and a second accelerator. The baseband processing steps executed by the first and second accelerators are configured based on the first processor, enabling the first and second accelerators to jointly complete a series of baseband processing steps for data. Furthermore, a communication link supports direct communication between the first and second accelerators, ensuring direct data interaction between them. By distributing a series of baseband processing steps in the message data processing flow to multiple accelerators, each accelerator can focus on executing specific baseband processing steps, improving the specialization of the accelerators. Moreover, the accelerators send data through a peer-to-peer communication link, achieving efficient collaboration between different accelerators and reducing the overall energy consumption of the baseband processing system. Furthermore, by setting multiple accelerators configurable by the processor in the baseband processing system, the configuration or expansion of the accelerators can be flexibly adjusted based on actual scenarios, improving the flexibility of the baseband processing system and helping to meet the flexibility requirements of cloud-based base stations.

[0070] Please see Figure 2 , Figure 2 This is a schematic diagram of a baseband processing system provided in this application. Figure 2 As shown, the baseband processing system includes a first processor, a first accelerator device, and a second accelerator device. A communication link exists between the first and second accelerator devices to support direct communication between them. In other words, the communication link between the first and second accelerator devices is a peer-to-peer communication bus, meaning data transmission between them can be completed directly via this bus without needing to pass through a centralized control node (such as the first processor). For example, the communication link between the first and second accelerator devices could be a Unified Bus (UB), an Ultra Accelerator Link (UALink) bus, an Nvlink bus, or a Compute Express Link (CXL) bus.

[0071] In addition, there are communication links between the first processor and the first accelerator device, as well as between the first processor and the second accelerator device, to support interaction between the first processor and the first accelerator device and the second accelerator device.

[0072] In the baseband processing system, the first processor is used to configure the first acceleration device to perform the first baseband processing step and to configure the second acceleration device to perform the second baseband processing step.

[0073] The first accelerator device performs a first baseband processing step on the input first data and sends the processed data to the second accelerator device. The second accelerator device performs a second baseband processing step on the data sent by the first accelerator device to obtain the target data. The first baseband processing step may include one or more baseband processing steps, and the second baseband processing step may include another one or more baseband processing steps.

[0074] In other words, by configuring the first and second accelerator devices using a first processor, the first and second accelerator devices can jointly complete a series of baseband processing steps for message data. Each accelerator device only performs a portion of these baseband processing steps, and the processing steps performed by the first and second accelerator devices do not overlap. Furthermore, after completing the configured first baseband processing steps on the input first data, the first accelerator device directly sends the processed data to the second accelerator device without needing to pass through other components (such as a processor or host memory), ensuring the efficiency of the joint baseband processing by the first and second accelerator devices.

[0075] For example, please refer to Figure 3 , Figure 3 This is a schematic diagram illustrating how a first accelerating device and a second accelerating device jointly perform a series of baseband processing steps, as provided in this application. Figure 3 As shown, taking the joint processing of data from the Physical Uplink Shared Channel (PUSCH) by the first and second accelerator devices as an example, the first baseband processing steps performed by the first accelerator device on the input first data (i.e., PUSCH data) include RE demapping, channel estimation, and receiver equalization. The second baseband processing steps performed by the second accelerator device on the data transmitted by the first accelerator device include demodulation, descrambling, rate matching dematching, LDPC decoding, and transport block (TB) generation.

[0076] It should be noted that, Figure 3 This section uses the joint processing of PUSCH data by the first and second accelerator devices as an example to illustrate the baseband processing steps performed by the first and second accelerator devices respectively. When the first and second accelerator devices process other types of data, the baseband processing steps performed by them may be other types of steps, which are not specifically limited here. In general, the first processor can be configured to execute the baseband processing steps by the first and second accelerator devices when processing various types of data.

[0077] Furthermore, the above describes the baseband processing of data using a first accelerator and a second accelerator in conjunction. In practical applications, the first processor can be configured with two or more accelerators to jointly complete the baseband processing. That is, in addition to the first and second accelerators, the baseband processing system can also include other accelerators. In this case, the target data obtained by the second accelerator in performing the second baseband processing step can be further sent to other accelerators for processing.

[0078] The first processor mentioned above can be, for example, a central processing unit (CPU). The first and second accelerator devices can be FPGA chips, application-specific integrated circuit (ASIC) chips, network processors (NP), CPUs, graphics processing units (GPUs), neural network processing units (NPUs), or tensor processing units (TPUs).

[0079] Furthermore, the first accelerator and the second accelerator can be hardware with different structures (e.g., the first accelerator is a GPU and the second accelerator is an ASIC chip). Alternatively, the first accelerator and the second accelerator can be hardware with the same structure (e.g., both the first accelerator and the second accelerator are ASIC chips).

[0080] Optionally, the first processor, the first accelerator, and the second accelerator described above may be deployed on the same device, such as on the same base station device or server.

[0081] Optionally, in some scenarios, depending on the differences in processing steps, the first accelerator device can have more general-purpose computing power, such as a GPU, while the second accelerator device can have higher energy efficiency, such as a more specialized ASIC chip. Generally speaking, the more specialized the accelerator device, the fewer types of baseband tasks it can handle, but the higher its energy efficiency. In this way, by configuring a first accelerator device with strong general-purpose computing power and a second accelerator device with strong specialized capabilities to jointly complete baseband processing, the baseband processing system can be guaranteed to have both strong versatility and energy efficiency, facilitating flexible configuration of the accelerator devices in the future.

[0082] For example, please refer to Figure 4 , Figure 4This application provides a schematic diagram illustrating the process of a first accelerator device and a second accelerator device performing baseband processing based on a first processor configuration. (See attached diagram.) Figure 4 As shown, the process by which the first accelerator device and the second accelerator device perform baseband processing based on the configuration of the first processor includes the following steps 401-408.

[0083] Step 401: The first processor configures the first acceleration device to perform the first baseband processing step, and configures the second acceleration device to perform the second baseband processing step.

[0084] Specifically, the first processor may send configuration information to the first accelerator device and the second accelerator device respectively to configure the first accelerator device to perform the first baseband processing steps and configure the second accelerator device to perform the second baseband processing steps. For example, the first processor may configure the first accelerator device to perform three baseband processing steps: RE demapping, channel estimation, and receiver equalization, and configure the second accelerator device to perform five baseband processing steps: demodulation, descrambling, rate matching de-matching, LDPC decoding, and TB generation.

[0085] Furthermore, to ensure that the first and second accelerator devices can successfully complete baseband processing, the first processor can also configure the input data address (including PUSCH data and a description of the data format), task start signal, output address of processed data, and task end signal (including the receiving object and signal value) for each of the first and second accelerator devices. Specifically, the first processor configures the memory address of the second accelerator device as the output address of the processed data from the first accelerator device. Additionally, the first processor configures the first task start signal as the start signal for the first accelerator device, and configures the first accelerator device to send a second task start signal to the second accelerator device after completing data output. Furthermore, the first processor configures the second task start signal as the start signal for the second accelerator device.

[0086] Step 402: The first acceleration device receives the first task start signal.

[0087] After the baseband processing system acquires the data to be processed, it can trigger the first acceleration device to process the data, causing the first acceleration device to receive a first task start signal. This first task start signal can be, for example, a signal sent by the first processor or a clock interrupt signal.

[0088] Step 403: The first acceleration device obtains input data from the configured address and executes the first baseband processing step.

[0089] After receiving the first task start signal, the first acceleration device obtains the input data (i.e., the first data mentioned above) from the address configured by the first processor (such as the memory address within the first acceleration device, where the input data to be processed has already been written into the memory space within the acceleration device), and executes the configured first baseband processing step.

[0090] Optionally, in some scenarios, the first data may be located in the memory used by the first processor. In this case, after receiving the first task start signal, the first acceleration device retrieves the first data from the memory used by the first processor (i.e., the address of the input data configured by the first processor is the address in the memory used by the first processor). Please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of another baseband processing system provided in this application. Figure 5 As shown, in the baseband processing system, the first accelerator and the second accelerator are also connected to the memory used by the first processor via a communication link. In this way, the first accelerator can directly read data from the memory used by the first processor via the communication link, and the second accelerator can also directly write data to the memory used by the first processor via the communication link.

[0091] In this solution, by having the first accelerator device directly read input data from the memory used by the first processor, the step of the first processor forwarding input data to the first accelerator device can be eliminated, thereby improving the efficiency of data processing and reducing the processing pressure on the first processor.

[0092] Step 404: The first acceleration device sends the processed data to the second acceleration device.

[0093] After performing the first baseband processing step on the input data, the first accelerator device obtains the data processed after the first baseband processing step (hereinafter referred to as the processed data). Therefore, the first accelerator device sends the processed data to the second accelerator device according to the output address of the processed data configured by the first processor. Specifically, the output address of the processed data configured by the first processor for the first accelerator device can be the address of the memory of the second accelerator device. Therefore, the first accelerator device can write the processed data to the address of the memory of the second accelerator device through a peer-to-peer communication bus, thereby realizing the sending of the processed data to the second accelerator device.

[0094] Step 405: The first acceleration device sends a second task start signal to the second acceleration device.

[0095] After the processed data is written to the memory of the second accelerator, the first accelerator can send a second task start signal to the second accelerator according to the configuration of the first processor.

[0096] Step 406: The second acceleration device obtains the processed data sent by the first acceleration device from the configured address and executes the second baseband processing step.

[0097] Specifically, for the second accelerator device, the second task start signal sent by the first accelerator device is the same task start signal configured by the first processor for the second accelerator device. Therefore, after receiving the second task start signal, the second accelerator device triggers the retrieval of the processed data sent by the first accelerator device from the configured address and executes the second baseband processing step.

[0098] Step 407: The second accelerator device outputs the target data obtained by performing the second baseband processing step.

[0099] After completing the second baseband processing step, the second acceleration device can output the obtained target data according to the configuration of the first processor, such as sending the target data to the first processor so that the first processor can continue to execute subsequent processing steps or forward the target data to other components.

[0100] Alternatively, when the first processor is configured with a first accelerator, a second accelerator, and other accelerators to jointly complete the baseband processing of the data, the second accelerator can continue to send the obtained target data to the other accelerators so that the other accelerators can continue to complete the baseband processing.

[0101] Step 408: The second acceleration device sends a task completion signal.

[0102] After the second accelerator outputs the target data, it can send a task completion signal to a designated object (such as the first processor or other accelerator) to trigger further processing of the target data by the designated object.

[0103] Optionally, the baseband processing system further includes a second processor. The first processor and the first accelerator are located on the first device, and the second processor and the second accelerator are located on the second device. Specifically, the first processor is used to negotiate with the second processor to configure the first accelerator to perform the first baseband processing step and to configure the second accelerator to perform the second baseband processing step.

[0104] In other words, the first accelerator and the second accelerator are actually located on different devices and are managed by different processors. Therefore, in order to enable the accelerators on different devices to jointly perform baseband processing, the processors on the two devices can first negotiate to determine how the first accelerator and the second accelerator should coordinate to perform baseband processing.

[0105] Optional, please refer to Figure 6 , Figure 6This is a schematic diagram of another baseband processing system provided in this application. Figure 6 As shown, a data exchange device connects the first device and the second device. The first accelerator is used to send processed data to the second accelerator through the data exchange device. The data exchange device can be, for example, a switch, router, or hub. Furthermore, the data exchange device needs to support direct communication links across devices; for example, it needs to support a peer-to-peer communication bus protocol, so that the first accelerator can directly send processed data to the second accelerator through the data exchange device.

[0106] For example, please refer to Figure 7 , Figure 7 This application provides a schematic diagram illustrating the process of a first accelerator device and a second accelerator device located on different devices performing baseband processing based on a configuration of a first processor. (See attached diagram.) Figure 7 As shown, the process by which the first accelerator device and the second accelerator device perform baseband processing based on the configuration of the first processor includes the following steps 701-709.

[0107] Step 701: The first processor and the second processor negotiate to jointly perform baseband processing using the first accelerator and the second accelerator.

[0108] Specifically, the content negotiated by the first processor and the second processor may include, for example, the baseband processing steps executed by the second accelerator, the output address of the data processed by the first accelerator (i.e., the address of the input data of the second accelerator), the task completion signal of the first accelerator (i.e., the task start signal of the second accelerator), and other information.

[0109] Step 702: Configure the first acceleration device to perform the first baseband processing step, and configure the second acceleration device to perform the second baseband processing step.

[0110] After the first processor and the second processor complete the negotiation, the configuration of the first accelerator device and the second accelerator device can be executed. Specifically, in this step, the first processor can simultaneously configure the first accelerator device to perform the first baseband processing step and configure the second accelerator device to perform the second baseband processing step. Alternatively, in this step, the first processor can configure the first accelerator device to perform the first baseband processing step, and the second processor can configure the second accelerator device to perform the second baseband processing step.

[0111] Step 703: The first acceleration device receives the first task start signal.

[0112] Step 704: The first acceleration device obtains input data from the configured address and executes the first baseband processing step.

[0113] Steps 703-704 are similar to steps 402-403 above. Please refer to steps 402-403 above for details, which will not be repeated here.

[0114] Step 705: The first acceleration device sends the processed data to the second acceleration device through the data exchange device.

[0115] After receiving the data sent by the first accelerator, since the second accelerator is located on the second device, the first accelerator needs to send the output data to the second accelerator through a data exchange device, such as writing the output data directly into the memory of the second accelerator through a switch.

[0116] Step 706: The first acceleration device sends a second task start signal to the second acceleration device.

[0117] Step 707: The second acceleration device obtains the processed data sent by the first acceleration device from the configured address and executes the second baseband processing step.

[0118] Step 708: The second accelerator device outputs the target data obtained by performing the second baseband processing step.

[0119] Step 709: The second acceleration device sends a task completion signal.

[0120] Steps 706-709 are similar to steps 405-408 above. Please refer to steps 405-408 above for details, which will not be repeated here.

[0121] Optional, please refer to Figure 8 , Figure 8 A schematic diagram of another baseband processing system provided in this application. (See diagram below.) Figure 8 As shown, in addition to the first processor, the first accelerator, and the second accelerator, the baseband processing system also includes a network interface card (NIC). The NIC receives fronthaul data and writes the first data, including IQ signals, from the fronthaul data into the memory of the first accelerator, so that the first accelerator can retrieve the first data from its memory.

[0122] In other words, the first processor can configure the network card to write the first data, which includes the IQ signal, from the received fronthaul data to the memory of the first acceleration device. For example, the first processor sends configuration information to the network card, which indicates that the storage address of the first data is the memory address in the first acceleration device.

[0123] When the baseband processing system has a network card, the specific processing flow for uplink and downlink data is as follows.

[0124] Uplink data processing flow: According to the configuration of the first processor, the network card receives the fronthaul data from the fronthaul interface. After the network card performs optional fronthaul decompression processing, it directly writes the first data (such as the payload in the fronthaul data packet) including the IQ signal into the memory of the first acceleration device. The data is then processed by the first acceleration device and the second acceleration device in sequence to complete the baseband processing flow of the uplink data.

[0125] For example, please refer to Figure 9 , Figure 9 This is a schematic diagram illustrating how a network interface card (NIC), a first accelerator, and a second accelerator jointly complete a series of baseband processing steps, as provided in this application. Figure 9 As shown, for uplink fronthaul data, after the network card receives the fronthaul data packet, it performs optional fronthaul decompression processing and sends the data containing IQ signals to the first acceleration device. Then, the first acceleration device sequentially performs RE demapping, channel estimation, and receiver equalization on the data containing IQ signals, and the second acceleration device continues to perform demodulation, descrambling, derate matching, LDPC decoding, and TB generation on the data processed by the first acceleration device.

[0126] Downlink data processing flow: The baseband processing flow for downlink data is the reverse of the uplink data processing flow. Downlink TB data packets are processed sequentially by the second and first accelerator devices before being directly sent to the network card. After optional fronthaul compression, they are sent out through the fronthaul interface. For example... Figure 9 As shown, for downlink data, the second accelerator sequentially performs TB plus CRC, LDPC encoding, rate matching, scrambling, and modulation on the downlink data. Meanwhile, the first accelerator continues to perform layer mapping, precoding, and RE mapping on the output data of the second accelerator. Finally, the network interface card (NIC) performs optional fronthaul compression processing on the output data of the first accelerator and sends the processed data out through the fronthaul interface.

[0127] For example, please refer to Figure 10 , Figure 10 This application provides a schematic diagram illustrating the process of a network interface card (NIC), a first accelerator device, and a second accelerator device performing baseband processing based on a configuration of a first processor. (See attached diagram.) Figure 10 As shown, the process by which the network card, the first accelerator, and the second accelerator perform baseband processing based on the configuration of the first processor includes the following steps 1001-1010.

[0128] Step 1001: Configure the network card in the first processor.

[0129] Specifically, the first processor can send configuration information to the network card, which instructs the network card to write the forward data including the IQ signal into the memory address of the first acceleration device through the communication link after receiving the forward data including the IQ signal.

[0130] Step 1002: The first processor configures the first acceleration device to perform the first baseband processing step, and configures the second acceleration device to perform the second baseband processing step.

[0131] Step 1003: The network card writes the received forward data, including the IQ signal, into the memory of the first acceleration device.

[0132] After the network card receives the fronthaul data through the fronthaul interface, the network card can write the received fronthaul data, including the IQ signal, into the memory of the first acceleration device according to the configuration of the first processor.

[0133] Step 1004: The first acceleration device receives the first task start signal.

[0134] After the network card completes the data writing, the first acceleration device can receive a first task start signal. This first task start signal can, for example, come from the first processor or the network card.

[0135] Specifically, if the network interface card (NIC) does not have the capability to process the fronthaul protocol, it can send the header of the received fronthaul data packet to the first processor, and the payload of the fronthaul data packet to the first acceleration device. Based on the received header, the first processor determines that the uplink data for a symbol or slot has been received, and then sends a task start signal to the first acceleration device.

[0136] If the network card has the function of processing the fronthaul protocol, then the network card itself can determine whether the uplink data of a symbol or slot has been received. Therefore, the network card can directly send the first task start signal to the first acceleration device.

[0137] Step 1005: The first acceleration device obtains input data from the configured address and executes the first baseband processing step.

[0138] The input data obtained by the first acceleration device from the configured address is actually the forward transmission data sent by the network card, which includes IQ signals.

[0139] Step 1006: The first acceleration device sends the processed data to the second acceleration device.

[0140] After receiving the processed data, the first accelerator device sends the processed data directly to the second accelerator device via a peer-to-peer communication bus. If the second accelerator device is on the second device, the first accelerator device can send the processed data to the second accelerator device through a data exchange device, such as writing the processed data directly into the memory of the second accelerator device via a switch.

[0141] Step 1007: The first acceleration device sends a second task start signal to the second acceleration device.

[0142] Step 1008: The second acceleration device obtains the processed data sent by the first acceleration device from the configured address and executes the second baseband processing step.

[0143] Step 1009: The second accelerator device outputs the target data obtained by performing the second baseband processing step.

[0144] Step 1010: The second acceleration device sends a task completion signal.

[0145] Steps 1005-1010 are similar to steps 403-408 above. Please refer to steps 403-408 above for details, which will not be repeated here.

[0146] Optional, such as Figure 11 As shown, Figure 11 This is a schematic diagram of another baseband processing system provided in this application. To achieve high integration of the devices, the network card can be integrated onto the first acceleration device. That is, the network card and the first acceleration device are combined into one, which can also be understood as the first acceleration device also having the function of forward data transmission and reception.

[0147] With the network card integrated into the first acceleration device, compared to Figure 10 The interaction process between various components in the baseband processing system can differ as shown in the following steps.

[0148] Difference 1: In the configuration obtained by the first acceleration device from the first processor, the address of the input data can be omitted, that is, the address of the input data is determined by the first acceleration device itself (i.e., the address at which the forward transmission data received by the network card should be stored is determined by the first acceleration device itself).

[0149] Difference 2: In the configuration obtained by the first accelerator device from the first processor, the first task start signal is optional. That is, the first accelerator device can determine the processing start time itself according to its internal implementation, such as starting when the forward transmission data of a symbol or slot of the air interface has been written into memory, thus eliminating the need to configure a first task start signal for the first accelerator device.

[0150] For example, the first acceleration device is configured to perform a first baseband processing step on the data containing IQ signals after the data received through the network card, which includes IQ signals, satisfies the rules configured by the first processor. The rules of the first processing configuration, for example, are that the first acceleration device has received all the data containing IQ signals for one symbol or slot through the network card.

[0151] Correspondingly, for downlink data, the output data address and task completion signal can be optional in the configuration obtained by the first acceleration device from the first processor. After completing baseband processing, the first acceleration device directly sends the processed data through its integrated network card, without needing to send a task completion signal to other devices.

[0152] Please see Figure 12A , Figure 12A This is a schematic diagram illustrating the forwarding of first and second data by the network interface card provided in this application. Figure 12A As shown, the baseband processing system includes a first processor, a network interface card (NIC), a first accelerator, a second accelerator, and a third accelerator. In addition to sending received first data to the first accelerator, the NIC also receives second data and writes it to the memory of the third accelerator. The third accelerator performs baseband processing steps on the second data.

[0153] In other words, the network interface card (NIC) actually sends different data to different acceleration devices for processing based on the configuration of the primary processor, thereby achieving load sharing among the acceleration devices. In this way, by configuring the NIC to send data to different acceleration devices, multiple acceleration devices in the baseband processing system can be flexibly configured to process various types of data based on actual needs, improving the flexibility of the solution.

[0154] It should be noted that the baseband processing system may also include other acceleration devices. The third acceleration device may be used in conjunction with other acceleration devices to achieve baseband processing of the second data.

[0155] Typically, the fiber used on a single fronthaul interface (e.g., a 100Gbps bandwidth fiber) usually transmits fronthaul data from multiple cells (e.g., each cell requires 25Gbps of fronthaul bandwidth). One requirement for cloud-based base stations is the ability to support flexible deployment and scaling of cell processing resources. Therefore, in one possible example, the network interface card (NIC) includes programmable functionality, and can, depending on the configuration, offload fronthaul data from different cells to different acceleration devices for processing.

[0156] In one possible example, the source address of the fronthaul data packet to which the first data belongs is the first address, which is the fronthaul link address of the first cell; the source address of the fronthaul data packet to which the second data belongs is the second address, which is the fronthaul link address of the second cell.

[0157] The first processor is also configured to configure the network interface card (NIC) to send forward data with a source address of a first address to the first accelerator device, and to send forward data with a source address of a second address to the second accelerator device. In this way, when the NIC receives the first data and the second data, it can send the first data to the first accelerator device based on the source address of the forward data packet to which the first data belongs, and send the second data to the second accelerator device based on the source address of the forward data packet to which the second data belongs. For example, please refer to [link to relevant documentation]. Figure 12B , Figure 12B This is a schematic diagram illustrating a network interface card (NIC) forwarding first and second data, as provided in this application. Figure 12B As shown, for the first data belonging to cell 1, the network card sends the first data to the first acceleration device according to the source address of the fronthaul data packet to which the first data belongs. For the second data belonging to cell 2, the network card sends the second data to the third acceleration device according to the source address of the fronthaul data packet to which the second data belongs.

[0158] In other words, by configuring a network card on the first processor to send fronthaul data from different source addresses to different acceleration devices, it is possible to achieve the splitting of fronthaul data from different addresses, thereby splitting the fronthaul data from different cells to different acceleration devices for processing, in order to meet the cloudification requirements of base stations in practical applications.

[0159] In another possible example, the fronthaul data to which the first data belongs is first type of fronthaul data, and the fronthaul data to which the second data belongs is second type of fronthaul data; the first processor is also configured to configure the network card to send the first data to the first acceleration device and to send the second data to the third acceleration device.

[0160] In other words, the first processor can be configured to process different types of fronthaul data to different acceleration devices, thereby enabling different types of fronthaul data to be distributed to different acceleration devices for processing.

[0161] Generally, different types of fronthaul data may be processed using different methods. Therefore, by offloading different types of fronthaul data to different accelerators for processing, it is possible to ensure that the accelerators focus on processing specific types of fronthaul data, so that more specialized accelerators can be used to perform baseband processing steps, thereby improving the overall energy efficiency of the baseband processing system.

[0162] Optionally, the first type of fronthaul data is used to transmit data of one air interface signal or air interface channel, and the second type of fronthaul data is used to transmit data of another air interface signal or air interface channel. For example, the air interface signal to which the data transmitted by the first type of fronthaul data belongs is an air interface signal such as a Sounding Reference Signal (SRS) or a De-Modulation Reference Signal (DMRS), or the air interface channel to which the data transmitted by the first type of fronthaul data belongs is an air interface channel such as PUSCH, Physical Uplink Control Channel (PUCCH), or Physical Random Access Channel (PRACH). The air interface channel to which the data transmitted by the second type of fronthaul data belongs is an air interface channel such as PUSCH, PUCCH, or PRACH, or the air interface signal to which the data transmitted by the second type of fronthaul data belongs is an air interface signal such as SRS or DMRS. Alternatively, the first type of fronthaul data is used to transmit air interface data in the first frequency band (e.g., high frequency band), and the second type of fronthaul data is used to transmit air interface data in the second frequency band (e.g., low frequency band).

[0163] For example, please refer to Figure 12C , Figure 12C This is a schematic diagram illustrating another network interface card (NIC) for forwarding first and second data, as provided in this application. Figure 12C As shown, for the first data whose fronthaul data is PUSCH, the network interface card (NIC) sends the first data to the first acceleration device according to the type of fronthaul data to which the first data belongs. For the second data whose fronthaul data is SRS, the NIC sends the second data to the third acceleration device according to the type of fronthaul data to which the second data belongs.

[0164] Please see Figure 12D , Figure 12D This is a schematic diagram illustrating the format of a fronthaul eCPRI data packet provided in this application. Figure 12D As shown, the PC_ID field in the payload of the fronthaul eCPRI data packet is used to identify a set of IQ messages (such as physical channels, users, streams, or antenna ports), and the SEQ_ID field is used to identify a specific message (such as an OFDM symbol or subcarrier) within the IQ message set. Therefore, based on the values ​​of the PC_ID and SEQ_ID fields in the payload of the received fronthaul eCPRI data packet, the type of the fronthaul eCPRI data packet can be determined, and the payload in the fronthaul eCPRI data packet can then be sent to the corresponding acceleration device for processing.

[0165] Optional, please refer to Figure 13 , Figure 13 This is a schematic diagram of another baseband processing system provided in this application. Figure 13 As shown, the network interface card (NIC), the first accelerator, and the second accelerator are located on the first device, while the second processor and the third accelerator are located on the second device. Furthermore, a data exchange device connects the first and second devices, supporting direct communication links across devices. Therefore, the NIC can directly send data to the third accelerator through the data exchange device. The first processor is also used to negotiate with the second processor to configure the third accelerator to perform baseband processing steps.

[0166] In other words, the network interface card (NIC), the first accelerator, and the second accelerator are located on the same device, while the third accelerator is located on another device. The NIC sends the different data it receives to the accelerators on its own device and to the accelerators on other devices for processing.

[0167] In this solution, different types of data are forwarded by the network interface card (NIC) to acceleration devices on different equipment for processing. This enables independent processing of different data, and the acceleration devices operate independently without affecting each other, facilitating flexible upgrades of the acceleration devices. For example, if a processing function upgrade is performed for a certain type of data (such as data from a specific cell), this data can be offloaded to new acceleration devices for processing, ensuring that the original business data processing is not affected.

[0168] Optionally, in order to adaptively adjust the steps processed by the acceleration device according to the actual operating conditions during the application, the first processor can configure different baseband processing steps for the acceleration device at different time points to ensure that the acceleration device can meet the actual operating requirements during the execution of baseband processing steps.

[0169] For example, the first processor is specifically configured to configure the first accelerator device to perform a first baseband processing step and the second accelerator device to perform a second baseband processing step at a first time node. Furthermore, the first processor is also configured to configure the first accelerator device to perform a third baseband processing step and the second accelerator device to perform a fourth baseband processing step at a second time node.

[0170] The processing steps included in the third baseband processing step are different from those included in the first baseband processing step, and the processing steps included in the fourth baseband processing step are different from those included in the second baseband processing step.

[0171] In other words, at the first time point, the first accelerator device is configured to execute the first baseband processing step; at the second time point, the first accelerator device is configured to execute the third baseband processing step. At the first time point, the second accelerator device is configured to execute the second baseband processing step; at the second time point, the second accelerator device is configured to execute the fourth baseband processing step. That is, the first processor can flexibly configure the actual baseband processing steps executed by each accelerator device, so that each accelerator device can execute different baseband processing steps at different time points to meet the actual application requirements.

[0172] Optionally, the first accelerator device is further configured to perform a third baseband processing step on the input third data after acquiring the third task start signal, wherein the third task start signal is acquired after the second time node. That is, after the first processor reconfigures the first accelerator device to perform the third baseband processing step, the reconfiguration information of the first processor takes effect at the moment the first accelerator device receives the new task start signal (i.e., the third task start signal). In other words, after receiving the new task start signal, the first accelerator device performs the third baseband processing step on the input third data according to the latest configuration information of the first processor.

[0173] Generally, the computing power ratios of different acceleration devices (such as scalar, vector, tensor, and dedicated computing power) often differ. Therefore, for the same baseband processing step, the energy consumption of different acceleration devices executing that step often varies. Based on this, in practical applications, the first processor can comprehensively consider factors such as workload, energy consumption, and computing power requirements to dynamically configure acceleration devices to execute different baseband processing steps in different scenarios.

[0174] For example, the amount of traffic that the first accelerator needs to process at the first time point is different from the amount of traffic that needs to be processed at the second time point. That is, when the amount of data to be processed changes, the first processor can trigger an adjustment of the baseband processing steps performed by the first and second accelerators to meet the power consumption or throughput requirements as much as possible.

[0175] Specifically, please refer to Figure 14 , Figure 14 This is a schematic diagram illustrating the changes in the baseband processing steps performed by an acceleration device provided in this application. For example... Figure 14As shown, in low-load scenarios, the amount of data to be processed is relatively small, thus requiring less computing power for baseband processing. In this case, to reduce overall power consumption, the first processor can configure the first accelerator device to complete the three baseband processing steps: RE demapping, channel estimation, and receiver equalization (i.e., the first baseband processing steps mentioned above). The second accelerator device then completes the five baseband processing steps: demodulation, descrambling, rate matching de-matching, LDPC decoding, and TB generation (i.e., the second baseband processing steps mentioned above). Because the second accelerator device is more specialized, while the first accelerator device is more versatile, the energy consumption of the second accelerator device performing the demodulation and descrambling baseband processing steps is lower than that of the first accelerator device. Therefore, in low-load scenarios, the latter five baseband processing steps are all handled by the second accelerator device.

[0176] In high-load scenarios, the computing power required for rate matching and LDPC decoding increases significantly with the growth of traffic. In this case, the computing power of the second accelerator device may be insufficient to support it in handling the five baseband processing steps. Therefore, the first processor can configure the second accelerator device to focus on completing the three baseband processing steps of rate matching, LDPC decoding, and TB generation (i.e., the fourth baseband processing step mentioned above), and configure the first accelerator device to perform the first five baseband processing steps (i.e., the third baseband processing step mentioned above), thereby prioritizing the throughput requirements of baseband processing.

[0177] Generally, the first processor can adjust the configuration of different acceleration devices. The acceleration devices can then activate the new configuration at a specified time based on the latest received configuration, thus enabling dynamic adjustment of the acceleration task chain.

[0178] Furthermore, unlike traditional tightly coupled and integrated cloud-based baseband solutions, the baseband processing system provided in this application can be a flexibly configurable and adjustable system, meaning that the acceleration devices in the baseband processing system can be flexibly plugged in and replaced.

[0179] Optional, please refer to Figure 15 , Figure 15 This is a schematic diagram of another baseband processing system provided in this application. Figure 15As shown, the baseband processing system includes a first processor, a first accelerator device, a second accelerator device, and a fourth accelerator device. The fourth accelerator device is added to the baseband processing system after the first processor configures the first accelerator device to execute the first baseband processing step and configures the second accelerator device to execute the second baseband processing step. For example, if the baseband processing algorithm changes or the specifications of the baseband processing system need to be adjusted, a fourth accelerator device can be added to the baseband processing system. For instance, the fourth accelerator device can be directly inserted into the peer-to-peer communication bus of the baseband processing system, enabling it to communicate peer-to-peer with the first processor, the first accelerator device, and the second accelerator device.

[0180] Furthermore, after the fourth accelerator device is added to the baseband processing system, the first processor is also used to reconfigure the first and / or second accelerator devices, as well as the baseband processing steps performed by the fourth accelerator device, based on the capabilities of the fourth accelerator device. The reconfiguration of the baseband processing steps performed by each accelerator device by the first processor may involve the first, second, and fourth accelerator devices jointly completing the baseband processing of data, or it may involve the fourth accelerator device replacing the first or second accelerator device to complete the baseband processing of data (i.e., the first or second accelerator device no longer performs baseband processing of data).

[0181] For example, if the first baseband processing steps configured by the first processor for the first accelerating device include RE demapping, channel estimation, and receiver equalization, and the second baseband processing steps configured for the second accelerating device include demodulation, descrambling, rate matching de-matching, LDPC decoding, and TB generation, and if the processing algorithms for baseband processing steps such as rate matching de-matching, LDPC decoding, and TB generation change, then the first processor could be configured to have the first accelerating device perform RE demapping, channel estimation, and receiver equalization, the second accelerating device perform demodulation and descrambling, and the fourth accelerating device perform rate matching de-matching, LDPC decoding, and TB generation. In this way, when the processing algorithm of the baseband processing system is upgraded, the upgrade can be flexibly accomplished by introducing new accelerating devices, while ensuring that the original accelerating devices can still be used, thus improving the smooth upgradeability and compatibility of the baseband processing system.

[0182] Optionally, after the fourth accelerator device is added to the baseband processing system, the first processor is also used to send a capability query request to the fourth accelerator device and receive a capability query response returned by the fourth accelerator device in order to obtain the capabilities of the fourth accelerator device.

[0183] In other words, when the first processor discovers a new accelerator device introduced on the peer-to-peer communication bus, it needs to understand the capabilities of the new accelerator device in order to orchestrate the baseband processing task chain. The first processor understands the capabilities of the new accelerator device through the accelerator device capability discovery process.

[0184] Specifically, when the first processor discovers a newly added fourth accelerator device on the peer-to-peer communication bus, it sends a capability query request to the fourth accelerator device to inquire about its baseband processing capabilities. The fourth accelerator device then returns a capability query response to the first processor. This response includes one or more acceleration capability profiles supported by the fourth accelerator device, and the address of the input data corresponding to each acceleration profile. An acceleration profile is a set of one or more baseband processing steps. The address of the input data corresponding to each acceleration profile can be a memory address within the accelerator device that can be accessed via the peer-to-peer communication bus. Taking the UB bus as an example, the address of the input data corresponding to the acceleration profile is a UB memory handle, including the UB entity ID representing the UB device and the memory address within that UB device.

[0185] The above describes a baseband processing system provided in this application. The following describes a network device for deploying the processor and acceleration device in the above baseband processing system.

[0186] Please see Figure 16 , Figure 16 This is a schematic diagram of a network device provided in this application. The network device 1600 can specifically be a device in the aforementioned baseband processing system (such as the first or second device mentioned above), and is not limited thereto. Specifically, the network device 1600 includes: a receiver 1601, a transmitter 1602, a processor 1603, a memory 1604, and an acceleration device 1605. The number of processors 1603 in the network device 1600 can be one or more. Figure 16 Taking a single processor as an example; the number of accelerator devices 1605 in the network device 1600 can be one or more. Figure 16 Taking an accelerator device as an example, processor 1603 may include application processor 16031 and communication processor 16032. In some embodiments of this application, receiver 1601, transmitter 1602, processor 1603, memory 1604, and accelerator device 1605 may be connected via a peer-to-peer communication bus.

[0187] Memory 1604 may include read-only memory and random access memory, and provides instructions and data to processor 1603. A portion of memory 1604 may also include non-volatile random access memory (NVRAM). Memory 1604 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0188] Processor 1603 controls the operation of network devices. In specific applications, the various components of network devices are coupled together through a bus system, which may include not only data buses but also power buses, control buses, and status signal buses. However, for clarity, all buses in the diagram are referred to as the bus system.

[0189] The methods disclosed in the embodiments of this application can be applied to, or implemented by, processor 1603 and accelerator 1605. Processor 1603 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 1603 or by instructions in software form. Processor 1603 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. Processor 1603 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 1604. Processor 1603 reads the information in memory 1604 and, in conjunction with its hardware, completes the steps of the above method.

[0190] Receiver 1601 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of network devices. Transmitter 1602 can be used to output digital or character information through the first interface; transmitter 1602 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; transmitter 1602 may also include a display device such as a display screen.

Claims

1. A baseband processing system, characterized in that, include: A first processor, a first accelerator device, and a second accelerator device, wherein the first accelerator device and the second accelerator device have a communication link, and the communication link is used to support direct communication between the first accelerator device and the second accelerator device. The first processor is configured to configure the first acceleration device to perform a first baseband processing step and to configure the second acceleration device to perform a second baseband processing step; The first acceleration device is configured to perform the first baseband processing steps on the input first data according to the configuration of the first processor, and send the processed data to the second acceleration device through the communication link; The second acceleration device is used to perform the second baseband processing steps on the data sent by the first acceleration device according to the configuration of the first processor, so as to obtain the target data.

2. The system according to claim 1, characterized in that, The first acceleration device is also configured to trigger the execution of the first baseband processing steps on the first data after receiving the first task start signal, according to the configuration of the first processor; The first accelerator is also used to send a second task start signal to the second accelerator after sending the processed data to the second accelerator. The second acceleration device is also configured to, according to the configuration of the first processor, trigger the execution of the second baseband processing step on the data sent by the first acceleration device after obtaining the second task start signal.

3. The system according to claim 1 or 2, characterized in that, The first data is located in the memory used by the first processor, and the first acceleration device is used to retrieve the first data from the memory after receiving the first task start signal.

4. The system according to any one of claims 1-3, characterized in that, The system also includes: a second processor; The first processor and the first accelerator are located on the first device, and the second processor and the second accelerator are located on the second device; A data exchange device is connected between the first device and the second device, and the data exchange device supports direct communication links across devices; The first accelerator device sends the processed data to the second accelerator device through the data exchange device.

5. The system according to claim 4, characterized in that, The first processor is specifically used to negotiate with the second processor to configure the second acceleration device to perform the second baseband step.

6. The system according to claim 1, characterized in that, The system also includes: a network interface card; The network card is used to receive fronthaul data and write the first data, which includes the same-direction quadrature IQ signal, into the memory of the first acceleration device so that the first acceleration device can retrieve the first data from the memory.

7. The system according to claim 6, characterized in that, The first processor is configured to, after receiving fronthaul data including IQ signals, write the fronthaul data including IQ signals into the memory address of the first acceleration device through the communication link.

8. The system according to claim 6, characterized in that, The network card is integrated on the first acceleration device; The first acceleration device is used to perform the first baseband processing step on the data including IQ signals received through the network card after the data satisfies the rules configured by the first processor.

9. The system according to any one of claims 6-8, characterized in that, The system also includes: a third acceleration device; The network card is also used to write the second data into the memory of the third acceleration device through the communication link, according to the configuration of the first processor. The third accelerator device is used to perform baseband processing steps on the second data.

10. The system according to claim 9, characterized in that, The source address of the fronthaul data to which the first data belongs is the first address, and the first address is the fronthaul link address of the first cell. The source address of the fronthaul data to which the second data belongs is the second address, and the second address is the fronthaul link address of the second cell. The first processor is further configured to configure the network card to send forward data with the source address of the first address to the first acceleration device, and to send forward data with the source address of the second address to the third acceleration device.

11. The system according to claim 9 or 10, characterized in that, The first data belongs to the first type of fronthaul data, and the second data belongs to the second type of fronthaul data. The first processor is also configured to configure the network card to send the first data to the first acceleration device and to send the second data to the third acceleration device.

12. The system according to claim 11, characterized in that, The first type of fronthaul data is used to transmit one type of air interface signal or air interface channel data, and the second type of fronthaul data is used to transmit another type of air interface signal or air interface channel data.

13. The system according to any one of claims 9-12, characterized in that, The network card, the first acceleration device, and the second acceleration device are located on the first device, and the third acceleration device is located on the second device. A data exchange device is connected between the first device and the second device, and the data exchange device supports direct communication links across devices.

14. The system according to claim 13, characterized in that, The system further includes a second processor; the first processor is specifically used to negotiate with the second processor to configure the third acceleration device to perform baseband processing steps.

15. The system according to any one of claims 1-14, characterized in that, The first processor is specifically configured to configure the first acceleration device to perform the first baseband processing step and the second acceleration device to perform the second baseband processing step at a first time node; The first processor is further configured to configure the first acceleration device to perform a third baseband processing step and the second acceleration device to perform a fourth baseband processing step at a second time node; The processing steps included in the third baseband processing step are different from those included in the first baseband processing step, and the processing steps included in the fourth baseband processing step are different from those included in the second baseband processing step.

16. The system according to claim 15, characterized in that, The first acceleration device is also used to perform the third baseband processing step on the input third data after acquiring the third task start signal, wherein the third task start signal is acquired after the second time node.

17. The system according to any one of claims 15-16, characterized in that, The system further includes a fourth acceleration device, which is added to the system after the first processor configures the first acceleration device to perform the first baseband processing step and configures the second acceleration device to perform the second baseband processing step. The first processor is also configured to reconfigure the first accelerator and / or the second accelerator based on the capabilities of the fourth accelerator, as well as the baseband processing steps performed by the fourth accelerator.

18. The system according to claim 17, characterized in that, The first processor is further configured to send a capability query request to the fourth accelerator and receive a capability query response returned by the fourth accelerator to obtain the capabilities of the fourth accelerator.

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