Stacked semiconductor device and operating method thereof

Abstract

The invention relates to a stacked semiconductor device and an operating method thereof. A stacked memory device includes a base chip, a first sharded chip stacked over the base chip, and a second sharded chip stacked over the first sharded chip. The base chip includes a sharding control circuit configured to control the first sharding chip and the second sharding chip such that when a refresh memory bank signal for refreshing memory banks included in the first sharding chip and the second sharding chip is generated, the first sharding chip and the second sharding chip generate a refresh memory bank signal for refreshing memory banks included in the first sharding chip and the second sharding chip. And executing a refreshing operation according to the refreshing mode of the first fragment chip and the refreshing mode of the second fragment chip.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0118863, filed with the Korean Intellectual Property Office on September 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor memory device, including but not limited to a stacked memory device. Background Technology

[0004] Stacked memory systems, such as high-bandwidth memory (HBM) devices, are widely used in a variety of applications due to their considerable bandwidth. A stacked memory system comprises a stacked memory device consisting of a base chip interconnected via through-silicon vias (TSVs) and multiple shard chips. The stacked memory device includes a physical interface (e.g., a physical layer for communicating with a processor), and the physical layer is configured for high-speed data transfer and efficient communication.

[0005] Each of the multiple shards in a stacked storage device comprises multiple storage cells for storing data. Since the data stored in the storage cells within a shard disappears over time, refresh operations are used to rewrite the data into the storage cells at regular intervals. Summary of the Invention

[0006] In one embodiment, a stacked memory device may include a base chip, a first shard chip stacked on the base chip, and a second shard chip stacked on the first shard chip. The base chip may include a shard control circuit configured to control the first and second shard chips such that when a refresh memory bank signal is generated to refresh the memory banks included in the first and second shard chips, a refresh operation is performed according to the refresh mode of the first and second shard chips.

[0007] In one embodiment, a stacked memory device may include a base chip, a first shard chip stacked on the base chip, and a second shard chip stacked on the first shard chip. The base chip may include: control circuitry configured to generate a clock signal that switches when a refresh memory bank signal is generated to refresh the memory banks included in the first and second shard chips; and a first shard refresh control circuitry configured to select a refresh mode for the first shard chip based on the clock signal, a reset signal, and a shard identifier (ID).

[0008] In one embodiment, a method may include: when a refresh memory bank signal is generated to refresh the memory banks included in a first shard chip and a second shard chip of a stacked memory device, a shard control circuit for the first shard chip and the second shard chip controls the first shard chip to perform a refresh operation according to a refresh mode of the first shard chip; and when a refresh memory bank signal is generated to refresh the memory banks included in the first shard chip and the second shard chip, the shard control circuit controls the second shard chip to perform a refresh operation according to a refresh mode of the second shard chip. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a stacked storage device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a block diagram illustrating a segmentation control circuit according to an embodiment of the present disclosure.

[0011] Figure 3 This is a circuit diagram illustrating a first mode control signal generation circuit according to an embodiment of the present disclosure.

[0012] Figure 4 It is a table of data during operation of a first mode control signal generation circuit according to an embodiment of the present disclosure.

[0013] Figure 5 This is a circuit diagram illustrating a second mode control signal generation circuit according to an embodiment of the present disclosure.

[0014] Figure 6 It is a table of data during operation of the second mode control signal generation circuit according to an embodiment of the present disclosure.

[0015] Figure 7 This is a circuit diagram illustrating a third-mode control signal generation circuit according to an embodiment of the present disclosure.

[0016] Figure 8 It is a table of data during operation of a third mode control signal generation circuit according to an embodiment of the present disclosure.

[0017] Figure 9 This is a circuit diagram illustrating a fourth mode control signal generation circuit according to an embodiment of the present disclosure.

[0018] Figure 10 It is a table of data during operation of a fourth mode control signal generation circuit according to an embodiment of the present disclosure.

[0019] Figure 11 This is a circuit diagram illustrating a first refresh mode selection signal generation circuit according to an embodiment of the present disclosure.

[0020] Figure 12 It is a table of data during the operation of a first refresh mode selection signal generation circuit according to an embodiment of the present disclosure.

[0021] Figure 13 This is a circuit diagram illustrating a second refresh mode selection signal generation circuit according to an embodiment of the present disclosure.

[0022] Figure 14 It is a table of data during operation of a second refresh mode selection signal generation circuit according to an embodiment of the present disclosure.

[0023] Figure 15 This is a circuit diagram illustrating a third refresh mode selection signal generation circuit according to an embodiment of the present disclosure.

[0024] Figure 16 It is a table of data during operation of a third refresh mode selection signal generation circuit according to an embodiment of the present disclosure.

[0025] Figure 17 This is a circuit diagram illustrating a fourth refresh mode selection signal generation circuit according to an embodiment of the present disclosure.

[0026] Figure 18 It is a table of data during operation of a fourth refresh mode selection signal generation circuit according to an embodiment of the present disclosure.

[0027] Figure 19 This is a circuit diagram illustrating a first refresh control circuit according to an embodiment of the present disclosure.

[0028] Figure 20 This is a timing diagram of a refresh mode performed for a plurality of sharded chips according to embodiments of the present disclosure.

[0029] Figure 21 and Figure 22 This is a block diagram illustrating an example of a stacked storage system according to this disclosure. Detailed Implementation

[0030] Terms such as "first" and "second" are used to distinguish multiple elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be called the second element, while in another example, the second element may be called the first element.

[0031] When one element is referred to as "connected" to another element, these elements can be directly connected or connected through one or more intermediate elements between the elements. When two elements are referred to as "directly connected," one element is directly connected to the other element, and there are no intermediate elements between the two elements.

[0032] When one element is identified as being "above" or "above" another element, the two elements can be in direct contact with each other, or an intermediate element can be placed between the elements.

[0033] Terms such as “above,” “over,” “high,” “low,” “column,” “row,” “horizontal,” and other terms that suggest relative spatial relationships or orientation are used for ease of description or reference to the accompanying drawings and have no other limiting effect.

[0034] The term "bit group" refers to a combination of logic levels of the bits contained in a signal. The bit group of a signal differs when the logic levels of the bits in the signal change. For example, when a signal includes a first combination of two bits, the signal's logical bit group is the first bit group, and when the signal includes a second combination of two bits, the signal's bit group is the second bit group.

[0035] Embodiments of this disclosure have been described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustratively illustrate the concepts disclosed in this application. Examples or embodiments of the concepts may be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0036] The refresh operation is performed in several ways, in which the number of memory cells included in a shard chip and refreshed together is varied. When all shard chips in a stacked memory device are refreshed in the same way, current consumption increases rapidly as the number of shard chips refreshed together increases.

[0037] Figure 1 This is a block diagram illustrating a stacked storage device 10 according to an embodiment of the present disclosure.

[0038] like Figure 1As shown, the stacked memory device 10 includes a base chip 100, a first shard chip 110-1, a second shard chip 110-2, a third shard chip 110-3, and a fourth shard chip 110-4. The first shard chip 110-1 is stacked on top of the base chip 100, the second shard chip 110-2 is stacked on top of the first shard chip 110-1, the third shard chip 110-3 is stacked on top of the second shard chip 110-2, and the fourth shard chip 110-4 is stacked on top of the third shard chip 110-3. The number L of shard chips stacked on top of the base chip 100 can be, for example, one of 8, 12, 16, etc., where L is a positive integer. Each of the base chip 100, the first shard chip 110-1, the second shard chip 110-2, the third shard chip 110-3, and the fourth shard chip 110-4 has a through-silicon via (TSV). Through-silicon vias (TSVs) penetrate the base chip 100, the first chip 110-1, the second chip 110-2, the third chip 110-3, and the fourth chip 110-4, and are electrically connected vias, for example, microbumps. Therefore, signals and data are transmitted at high speed between the base chip 100, the first chip 110-1, the second chip 110-2, the third chip 110-3, and the fourth chip 110-4 vias.

[0039] The base chip 100 includes a slice control circuit (SLICE CTR) 120. The slice control circuit 120 receives a command address CA from an external device (not shown). The external device can be implemented using a processor, for example... Figure 21 The processor 3300 or Figure 22 The processor 4310 in the chip. The slice control circuit 120 sets a refresh mode or procedure for each of the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4 based on the command address CA. For simplicity, the term "mode" herein includes the implementation of procedures within a mode, as well as the implementation of procedures outside of a mode. Refresh memory bank signals (e.g., ...) are used to refresh the memory banks (not shown) included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. Figure 2When the REF-BK is generated, the sharding control circuit 120 controls the first shard chip 110-1, the second shard chip 110-2, the third shard chip 110-3, and the fourth shard chip 110-4, so that a refresh operation is performed according to the refresh mode of each of the first shard chip 110-1, the second shard chip 110-2, the third shard chip 110-3, and the fourth shard chip 110-4. A memory bank refers to the logical or physical partitioning of memory cells that perform independent operations in the first shard chip 110-1, the second shard chip 110-2, the third shard chip 110-3, and the fourth shard chip 110-4.

[0040] The sharding control circuit 120 controls the first shard chip 110-1 such that when a refresh signal for refreshing the memory included in the first shard chip 110-1 is generated, refresh operations according to a first refresh mode, a second refresh mode, a third refresh mode, and a fourth refresh mode are executed sequentially and repeatedly. The first refresh mode is configured such that an automatic refresh operation for the memory included in the first shard chip 110-1 is executed, and subsequently, the automatic refresh operation for the memory included in the first shard chip 110-1 is executed repeatedly. Therefore, when a refresh signal for refreshing the memory included in the first shard chip 110-1 is generated, for example, after the initialization operation of the stacked storage device 10, the automatic refresh operation for the memory included in the first shard chip 110-1 is executed twice. The second refresh mode is configured such that when a refresh signal for refreshing the memory included in the first shard chip 110-1 is generated, for example, after the first refresh mode, an intelligent refresh operation for the memory included in the first shard chip 110-1 is executed. The intelligent refresh operation includes, for example, performing a refresh operation on word lines adjacent to frequently accessed target word lines among the word lines connected to the memory banks included in the first slice chip 110-1. A third refresh mode is configured such that when a refresh memory bank signal for refreshing the memory banks included in the first slice chip 110-1 is generated, for example after a second refresh mode, an automatic refresh operation for the memory banks included in the first slice chip 110-1 is performed. A fourth refresh mode is configured such that when a refresh memory bank signal for refreshing the memory banks included in the first slice chip 110-1 is generated, for example after a third refresh mode, a refresh operation for the memory banks included in the first slice chip 110-1 is not performed or is skipped.

[0041] The sharding control circuit 120 controls the second shard chip 110-2 such that when a refresh memory signal is generated to refresh the memory included in the second shard chip 110-2, refresh operations according to the second refresh mode, the third refresh mode, the fourth refresh mode, and the first refresh mode are executed sequentially and repeatedly. The second refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the second shard chip 110-2, for example, after the initialization operation of the stacked storage device 10, an intelligent refresh operation for the memory included in the second shard chip 110-2 is executed. The third refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the second shard chip 110-2, for example, after the second refresh mode, an automatic refresh operation for the memory included in the second shard chip 110-2 is executed. The fourth refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the second shard chip 110-2, for example, after the third refresh mode, a refresh operation for the memory included in the second shard chip 110-2 is not executed or is skipped. The first refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the second slicing chip 110-2 after, for example, a fourth refresh mode, the automatic refresh operation for the memory included in the second slicing chip 110-2 is performed twice.

[0042] The sharding control circuit 120 controls the third shard chip 110-3 such that when a refresh memory signal is generated to refresh the memory included in the third shard chip 110-3, refresh operations according to the third refresh mode, the fourth refresh mode, the first refresh mode, and the second refresh mode are executed sequentially and repeatedly. The third refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the third shard chip 110-3, for example, after the initialization operation of the stacked storage device 10, an automatic refresh operation for the memory included in the third shard chip 110-3 is executed. The fourth refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the third shard chip 110-3, for example, after the third refresh mode, a refresh operation for the memory included in the third shard chip 110-3 is not executed or is skipped. The first refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the third shard chip 110-3, for example, after the fourth refresh mode, the automatic refresh operation for the memory included in the third shard chip 110-3 is executed twice. The second refresh mode is configured such that when a refresh memory signal is generated, for example after the first refresh mode, the smart refresh operation for the memory included in the third slice chip 110-3 is performed.

[0043] The slicing control circuit 120 controls the fourth slicing chip 110-4 such that when a refresh memory signal is generated to refresh the memory included in the fourth slicing chip 110-4, refresh operations according to the fourth refresh mode, the first refresh mode, the second refresh mode, and the third refresh mode are executed sequentially and repeatedly. The fourth refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the fourth slicing chip 110-4, for example, after the initialization operation of the stacked storage device 10, refresh operations for the memory included in the fourth slicing chip 110-4 are not executed or are skipped. The first refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the fourth slicing chip 110-4, for example, after the fourth refresh mode, automatic refresh operations for the memory included in the fourth slicing chip 110-4 are executed twice. The second refresh mode is configured such that intelligent refresh operations for the memory included in the fourth slicing chip 110-4 are executed when a refresh memory signal is generated to refresh the memory included in the fourth slicing chip 110-4, for example, after the first refresh mode. The third refresh mode is configured such that when a refresh memory signal is generated to refresh the memory included in the fourth slicing chip 110-4 after, for example, the second refresh mode, an automatic refresh operation for the memory included in the fourth slicing chip 110-4 is performed.

[0044] Figure 2 A block diagram illustrating a segmentation control circuit 120 according to an embodiment of the present disclosure is provided. Figure 2 As shown, the segmentation control circuit 120 includes a mode selection control circuit 130, a first segmentation refresh control circuit 131, a second segmentation refresh control circuit 132, a third segmentation refresh control circuit 133, and a fourth segmentation refresh control circuit 134.

[0045] The mode selection control circuit 130 includes a command address decoder (CA DEC) 130-1, a refresh memory signal generation circuit (REF-BK GEN) 130-2, and a clock signal generation circuit (MS-CLK GEN) 130-3.

[0046] Command address decoder 130-1 decodes command address CA to generate a refresh command REF-CMD for refresh operations. Command address CA may include multiple bits, and the number of bits in the bit group included in the command address CA that generates the refresh command REF-CMD may vary depending on the embodiment. Although refresh command REF-CMD is represented singularly, refresh command REF-CMD may, depending on the embodiment, include an all-memory refresh command for refreshing all memory banks and a per-memory refresh command for refreshing each memory bank. The all-memory refresh command is generated to simultaneously perform refresh operations on all memory banks included in each of the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The per-memory refresh command is generated such that each memory bank included in each of the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4 performs a refresh operation independently of the other memory banks.

[0047] The refresh memory bank signal generation circuit 130-2 is connected to the command address decoder 130-1 to receive the refresh command REF-CMD from the command address decoder 130-1. Based on the refresh command REF-CMD, the refresh memory bank signal generation circuit 130-2 generates a refresh memory bank signal REF-BK, which selects at least one memory bank to perform a refresh operation. The refresh memory bank signal generation circuit 130-2 also generates a refresh memory bank signal REF-BK that selects all memory banks simultaneously when performing a refresh operation on all memory banks, and a refresh memory bank signal REF-BK that selects each memory bank sequentially when performing a refresh operation on each memory bank.

[0048] Clock signal generation circuit 130-3 is connected to refresh memory bank signal generation circuit 130-2 to receive refresh memory bank signal REF-BK from refresh memory bank signal generation circuit 130-2. Clock signal generation circuit 130-3 generates clock signal MS-CLK when refreshing the refresh memory bank signal REF-BK included in the first slice chip 110-1, second slice chip 110-2, third slice chip 110-3, and fourth slice chip 110-4. In one example, each of the first slice chip 110-1, second slice chip 110-2, third slice chip 110-3, and fourth slice chip 110-4 includes 16 memory banks, and the refresh memory bank signal REF-BK includes a group of bits corresponding to the 16 memory banks. The clock signal generation circuit 130-3 receives the refresh memory signal REF-BK to generate a clock signal MS-CLK, which is switched to select the memory included in the first slicing chip 110-1, the second slicing chip 110-2, the third slicing chip 110-3, and the fourth slicing chip 110-4 for the refresh operation.

[0049] The first segment refresh control circuit 131 includes a first mode control signal generation circuit (MCNT GEN(1)) 131-1, a first refresh mode selection signal generation circuit (REF-MD GEN(1)) 131-2 and a first refresh control circuit (REF CNT(1)) 131-3.

[0050] The first mode control signal generation circuit 131-1 is connected to the clock signal generation circuit 130-3 to receive the clock signal MS-CLK from the clock signal generation circuit 130-3. The first mode control signal generation circuit 131-1 generates a first mode control signal MCNT(1) based on the clock signal MS-CLK, the reset signal RST, and the slice ID SID. When the reset signal RST is generated at a logic high level to start the initialization operation of the stacked memory device 10, the first mode control signal generation circuit 131-1 generates a first mode control signal MCNT1 according to the slice ID SID, which controls the refresh operation performed on the first slice chip 110-1 during the initial refresh mode. The reset signal RST and the slice ID SID can be provided from outside the stacked memory device 10 or generated internally. The reset signal RST is generated at a predetermined logic high level for a short pulse or extended time period, for example until the refresh operation is completed. The predetermined logic high level of the reset signal RST can be a logic high level or a logic low level to start or trigger the initialization operation. When the refresh memory bank signal REF-BK is generated and the clock signal MS-CLK is generated at a logic high level, the first mode control signal generation circuit 131-1 generates a first mode control signal MCNT1 based on the slice ID SID. This first mode control signal MCNT1 controls the refresh operation performed on the first slice chip 110-1 during the changing refresh modes. For example, when the reset signal RST is generated, the first mode control signal generation circuit 131-1 generates a first mode control signal MCNT1 based on the slice ID SID to control the refresh operation performed on the first slice chip 110-1 during the first refresh mode (i.e., the initial refresh mode). When the clock signal MS-CLK is generated at a logic high level, the first mode control signal MCNT1 generates a first mode control signal MCNT1 based on the slice ID SID to control the refresh operation performed on the first slice chip 110-1 repeatedly in the order of the second refresh mode, the third refresh mode, the fourth refresh mode, and the first refresh mode.

[0051] The first refresh mode selection signal generation circuit 131-2 is connected to the first mode control signal generation circuit 131-1 to receive the first mode control signal MCNT1 from the first mode control signal generation circuit 131-1. The first refresh mode selection signal generation circuit 131-2 generates a first refresh mode selection signal REF-MD1 to set the refresh mode of the first slice chip 110-1 based on the first mode control signal MCNT1. The first refresh mode selection signal generation circuit 131-2 decodes the first mode control signal MCNT1 to generate the first refresh mode selection signal REF-MD1 to set the refresh mode of the first slice chip 110-1 according to the bit bits of the bit group contained in the first mode control signal MCNT1. For example, when the bit bits contained in the first mode control signal MCNT1 are in the first bit group, the first refresh mode selection signal generation circuit 131-2 generates the first refresh mode selection signal REF-MD1 to control the refresh operation performed on the first slice chip 110-1 during the first refresh mode. For example, when a bit in the first mode control signal MCNT1 is in the second bit group, the first refresh mode selection signal generation circuit 131-2 generates a first refresh mode selection signal REF-MD1 to control the refresh operation performed on the first slice chip 110-1 during the second refresh mode. For example, when a bit in the first mode control signal MCNT1 is in the third bit group, the first refresh mode selection signal generation circuit 131-2 generates a first refresh mode selection signal REF-MD1 to control the refresh operation performed on the first slice chip 110-1 during the third refresh mode. For example, when a bit in the first mode control signal MCNT1 is in the fourth bit group, the first refresh mode selection signal generation circuit 131-2 generates a first refresh mode selection signal REF-MD1 to control the refresh operation performed on the first slice chip 110-1 during the fourth refresh mode.

[0052] The first refresh control circuit 131-3 is connected to the refresh memory bank signal generation circuit 130-2 and the first refresh mode selection signal generation circuit 131-2 to receive the refresh memory bank signal REF-BK from the refresh memory bank signal generation circuit 130-2, and to receive the first refresh mode selection signal REF-MD1 from the first refresh mode selection signal generation circuit 131-2. The first refresh control circuit 131-3 controls the first shard chip 110-1 to perform a refresh operation in refresh mode based on the refresh memory bank signal REF-BK and the first refresh mode selection signal REF-MD1. For example, the first refresh control circuit 131-3 controls the first shard chip 110-1 to perform two automatic refresh operations on the memory bank contained in the first shard chip 110-1 selected by the refresh memory bank signal REF-BK when the first refresh mode selection signal REF-MD1 is received to control the refresh operation performed on the first shard chip 110-1 during the first refresh mode. For example, the first refresh control circuit 131-3 controls the first shard chip 110-1 such that when the first refresh mode selection signal REF-MD1 is received to control the refresh operation performed on the first shard chip 110-1 during a second refresh mode, a smart refresh operation is performed on the memory bank included in the first shard chip 110-1 selected by the refresh memory bank signal REF-BK. For example, the first refresh control circuit 131-3 controls the first shard chip 110-1 such that when the first refresh mode selection signal REF-MD1 is received to control the refresh operation performed on the first shard chip 110-1 during a third refresh mode, an automatic refresh operation is performed on the memory bank included in the first shard chip 110-1 selected by the refresh memory bank signal REF-BK. For example, the first refresh control circuit 131-3 controls the first shard chip 110-1 such that when the first refresh mode selection signal REF-MD1 is received to control the refresh operation performed on the first shard chip 110-1 during the fourth refresh mode, the refresh operation is not performed or is skipped on the memory bank included in the first shard chip 110-1 selected by the refresh memory bank signal REF-BK.

[0053] The second segment refresh control circuit 132 includes a second mode control signal generation circuit (MCNT GEN(2)) 132-1, a second refresh mode selection signal generation circuit (REF-MD GEN(2)) 132-2, and a second refresh control circuit (REF CNT(2)) 132-3.

[0054] The second mode control signal generation circuit 132-1 is connected to the clock signal generation circuit 130-3 to receive the clock signal MS-CLK from the clock signal generation circuit 130-3. The second mode control signal generation circuit 132-1 generates a second mode control signal MCNT2 based on the clock signal MS-CLK, the reset signal RST, and the slice ID SID. When the reset signal RST is generated at a logic high level to begin the initialization operation of the stacked memory device 10, the second mode control signal generation circuit 132-1 generates the second mode control signal MCNT2 according to the slice ID SID to control the refresh operation performed on the second slice chip 110-2 during the initial refresh mode. When a refresh memory bank signal is generated to refresh the memory banks included in the second slice chip 110-2 and the clock signal MS-CLK is generated at a logic high level, the second mode control signal generation circuit 132-1 generates the second mode control signal MCNT2 according to the slice ID SID to control the refresh operation performed on the second slice chip 110-2 during the changing refresh mode. For example, when the reset signal RST is generated, the second mode control signal generation circuit 132-1 generates a second mode control signal MCNT2 based on the slice ID SID to control the refresh operation performed on the second slice chip 110-2 during the second refresh mode (i.e., the initial refresh mode). When the clock signal MS-CLK is generated at a logic high level, the second mode control signal MCNT2 is generated based on the slice ID SID to control the refresh operation repeatedly performed on the second slice chip 110-2 in the order of the third refresh mode, the fourth refresh mode, the first refresh mode, and the second refresh mode.

[0055] The second refresh mode selection signal generation circuit 132-2 is connected to the second mode control signal generation circuit 132-1 to receive the second mode control signal MCNT2 from the second mode control signal generation circuit 132-1. The second refresh mode selection signal generation circuit 132-2 generates a second refresh mode selection signal REF-MD2 to set the refresh mode of the second slice chip 110-2 based on the second mode control signal MCNT2. The second refresh mode selection signal generation circuit 132-2 decodes the second mode control signal MCNT2 to generate the second refresh mode selection signal REF-MD2 to set the refresh mode of the second slice chip 110-2 according to the bit bits of the bit group contained in the second mode control signal MCNT2. For example, when the bit bits contained in the second mode control signal MCNT2 are in the second bit group, the second refresh mode selection signal generation circuit 132-2 generates the second refresh mode selection signal REF-MD2 to control the refresh operation performed on the second slice chip 110-2 during the second refresh mode. For example, when a bit in the second mode control signal MCNT2 is in the third bit group, the second refresh mode selection signal generation circuit 132-2 generates a second refresh mode selection signal REF-MD2 to control the refresh operation performed on the second slice chip 110-2 during the third refresh mode. For example, when a bit in the second mode control signal MCNT2 is in the fourth bit group, the second refresh mode selection signal generation circuit 132-2 generates a second refresh mode selection signal REF-MD2 to control the refresh operation performed on the second slice chip 110-2 during the fourth refresh mode. For example, when a bit in the second mode control signal MCNT2 is in the first bit group, the second refresh mode selection signal generation circuit 132-2 generates a second refresh mode selection signal REF-MD2 to control the refresh operation performed on the second slice chip 110-2 during the first refresh mode.

[0056] The second refresh control circuit 132-3 is connected to the refresh memory bank signal generation circuit 130-2 and the second refresh mode selection signal generation circuit 132-2 to receive the refresh memory bank signal REF-BK from the refresh memory bank signal generation circuit 130-2 and the second refresh mode selection signal REF-MD2 from the second refresh mode selection signal generation circuit 132-2. The second refresh control circuit 132-3 controls the second shard chip 110-2 based on the refresh memory bank signal REF-BK and the second refresh mode selection signal REF-MD2, causing a refresh operation to be performed in refresh mode. For example, when the second refresh mode selection signal REF-MD2 is received to control the refresh operation performed on the second shard chip 110-2 during the second refresh mode, the second refresh control circuit 132-3 controls the second shard chip 110-2 to perform a smart refresh operation on the memory bank contained in the second shard chip 110-2 selected by the refresh memory bank signal REF-BK. For example, when the second refresh mode selection signal REF-MD2 is received to control the refresh operation performed on the second shard chip 110-2 during the third refresh mode, the second refresh control circuit 132-3 controls the second shard chip 110-2 to perform an automatic refresh operation on the memory banks included in the second shard chip 110-2 selected by the refresh memory bank signal REF-BK. For example, when the second refresh mode selection signal REF-MD2 is received to control the refresh operation performed on the second shard chip 110-2 during the fourth refresh mode, the second refresh control circuit 132-3 controls the second shard chip 110-2 to not perform a refresh operation or skip the refresh operation on the memory banks included in the second shard chip 110-2 selected by the refresh memory bank signal REF-BK. For example, when the second refresh mode selection signal REF-MD2 is received to control the refresh operation performed on the second shard chip 110-2 during the first refresh mode, the second refresh control circuit 132-3 controls the second shard chip 110-2 to perform two automatic refresh operations on the memory bank included in the second shard chip 110-2 selected by the refresh memory bank signal REF-BK.

[0057] The third segment refresh control circuit 133 includes a third mode control signal generation circuit (MCNT GEN(3)) 133-1, a third refresh mode selection signal generation circuit (REF-MD GEN(3)) 133-2, and a third refresh control circuit (REF-CNT(3)) 133-3.

[0058] The third mode control signal generation circuit 133-1 is connected to the clock signal generation circuit 130-3 to receive the clock signal MS-CLK from the clock signal generation circuit 130-3. The third mode control signal generation circuit 133-1 generates a third mode control signal MCNT3 based on the clock signal MS-CLK, the reset signal RST, and the slice ID SID. When the reset signal RST is generated at a logic high level to begin the initialization operation of the stacked memory device 10, the third mode control signal generation circuit 133-1 generates the third mode control signal MCNT3 according to the slice ID SID to control the refresh operation performed on the third slice chip 110-3 during the initial refresh mode. When a refresh memory bank signal is generated to refresh the memory banks included in the third slice chip 110-3 and the clock signal MS-CLK is generated at a logic high level, the third mode control signal generation circuit 133-1 generates the third mode control signal MCNT3 according to the slice ID SID to control the refresh operation performed on the third slice chip 110-3 during the changing refresh mode. For example, when the reset signal RST is generated, the third mode control signal generation circuit 133-1 generates a third mode control signal MCNT3 based on the slice IDSID to control the refresh operation performed on the third slice chip 110-3 during the third refresh mode, which is the initial refresh mode. When the clock signal MS-CLK is generated at a logic high level, the third mode control signal MCNT3 is generated based on the slice IDSID to control the refresh operation repeatedly performed on the third slice chip 110-3 in the order of the fourth refresh mode, the first refresh mode, the second refresh mode, and the third refresh mode.

[0059] The third refresh mode selection signal generation circuit 133-2 is connected to the third mode control signal generation circuit 133-1 to receive the third mode control signal MCNT3 from the third mode control signal generation circuit 133-1. The third refresh mode selection signal generation circuit 133-2 generates a third refresh mode selection signal REF-MD3 to set the refresh mode of the third slice chip 110-3 based on the third mode control signal MCNT3. The third refresh mode selection signal generation circuit 133-2 decodes the third mode control signal MCNT3 to generate the third refresh mode selection signal REF-MD3 to set the refresh mode of the third slice chip 110-3 according to the bit groups contained in the third mode control signal MCNT3. For example, when the bit contained in the third mode control signal MCNT3 is in the third bit group, the third refresh mode selection signal generation circuit 133-2 generates the third refresh mode selection signal REF-MD3 to control the refresh operation performed on the third slice chip 110-3 during the third refresh mode. For example, when a bit in the third mode control signal MCNT3 is in the fourth bit group, the third refresh mode selection signal generation circuit 133-2 generates a third refresh mode selection signal REF-MD3 to control the refresh operation performed on the third slice chip 110-3 during the fourth refresh mode. For example, when a bit in the third mode control signal MCNT3 is in the first bit group, the third refresh mode selection signal generation circuit 133-2 generates a third refresh mode selection signal REF-MD3 to control the refresh operation performed on the third slice chip 110-3 during the first refresh mode. For example, when a bit in the third mode control signal MCNT3 is in the second bit group, the third refresh mode selection signal generation circuit 133-2 generates a third refresh mode selection signal REF-MD3 to control the refresh operation performed on the third slice chip 110-3 during the second refresh mode.

[0060] The third refresh control circuit 133-3 is connected to the refresh memory signal generation circuit 130-2 and the third refresh mode selection signal generation circuit 133-2 to receive the refresh memory signal REF-BK from the refresh memory signal generation circuit 130-2 and the third refresh mode selection signal REF-MD3 from the third refresh mode selection signal generation circuit 133-2. The third refresh control circuit 133-3 controls the third shard chip 110-3 to perform a refresh operation in refresh mode based on the refresh memory signal REF-BK and the third refresh mode selection signal REF-MD3. For example, when the third refresh mode selection signal REF-MD3 is received to control the refresh operation performed on the third shard chip 110-3 during the third refresh mode, the third refresh control circuit 133-3 controls the third shard chip 110-3 to perform an automatic refresh operation on the memory bank included in the third shard chip 110-3 selected by the refresh memory signal REF-BK. For example, when the third refresh mode selection signal REF-MD3 is received to control the refresh operation performed on the third shard chip 110-3 during the fourth refresh mode, the third refresh control circuit 133-3 controls the third shard chip 110-3 so that refresh operations are not performed or are skipped on the memory banks included in the third shard chip 110-3 selected by the refresh memory bank signal REF-BK. For example, when the third refresh mode selection signal REF-MD3 is received to control the refresh operation performed on the third shard chip 110-3 during the first refresh mode, the third refresh control circuit 133-3 controls the third shard chip 110-3 so that two automatic refresh operations are performed on the memory banks included in the third shard chip 110-3 selected by the refresh memory bank signal REF-BK. For example, when the third refresh mode selection signal REF-MD3 is received to control the refresh operation performed on the third shard chip 110-3 during the second refresh mode, the third refresh control circuit 133-3 controls the third shard chip 110-3 to perform a smart refresh operation on the memory bank included in the third shard chip 110-3 selected by the refresh memory bank signal REF-BK.

[0061] The fourth slice refresh control circuit 134 includes a fourth mode control signal generation circuit (MCNT GEN(4)) 134-1, a fourth refresh mode selection signal generation circuit (REF-MD GEN(4)) 134-2, and a fourth refresh control circuit (REFCNT(4)) 134-3.

[0062] The fourth mode control signal generation circuit 134-1 is connected to the clock signal generation circuit 130-3 to receive the clock signal MS-CLK from the clock signal generation circuit 130-3. The fourth mode control signal generation circuit 134-1 generates a fourth mode control signal MCNT4 based on the clock signal MS-CLK, the reset signal RST, and the slice ID SID. When the reset signal RST is generated at a logic high level to begin the initialization operation of the stacked memory device 10, the fourth mode control signal generation circuit 134-1 generates the fourth mode control signal MCNT4 according to the slice ID SID to control the refresh operation performed on the fourth slice chip 110-4 during the initial refresh mode. When the refresh memory bank signal REF-BK for refreshing the memory banks included in the fourth slice chip 110-4 is generated and the clock MS-CLK is generated at a logic high level, the fourth mode control signal generation circuit 134-1 generates the fourth mode control signal MCNT4 according to the slice ID SID to control the refresh operation performed on the fourth slice chip 110-4 during the changing refresh mode. For example, when the reset signal RST is generated, the fourth mode control signal generation circuit 134-1 generates the fourth mode control signal MCNT4 based on the slice ID SID to control the refresh operation performed on the fourth slice chip 110-4 during the fourth refresh mode, which is the initial refresh mode. When the clock signal MS-CLK is generated at a logic high level, the fourth mode control signal MCNT4 is generated based on the slice ID SID to control the refresh operation repeatedly performed on the fourth slice chip 110-4 in the order of the first refresh mode, the second refresh mode, the third refresh mode, and the fourth refresh mode.

[0063] The fourth refresh mode selection signal generation circuit 134-2 is connected to the fourth mode control signal generation circuit 134-1 to receive the fourth mode control signal MCNT4 from the fourth mode control signal generation circuit 134-1. The fourth refresh mode selection signal generation circuit 134-2 generates a fourth refresh mode selection signal REF-MD4 to set the refresh mode of the fourth slice chip 110-4 based on the fourth mode control signal MCNT4. The fourth refresh mode selection signal generation circuit 134-2 decodes the fourth mode control signal MCNT4 to generate the fourth refresh mode selection signal REF-MD4 to set the refresh mode of the fourth slice chip 110-4 according to the bit groups contained in the fourth mode control signal MCNT4. For example, when the bit contained in the fourth mode control signal MCNT4 is in the fourth bit group, the fourth refresh mode selection signal generation circuit 134-2 generates the fourth refresh mode selection signal REF-MD4 to control the refresh operation performed on the fourth slice chip 110-4 during the fourth refresh mode. For example, when the bits included in the fourth mode control signal MCNT4 are in the first bit group, the fourth refresh mode selection signal generation circuit 134-2 generates a fourth refresh mode selection signal REF-MD4 to control the refresh operation performed on the fourth slice chip 110-4 during the first refresh mode. For example, when the bits included in the fourth mode control signal MCNT4 are in the second bit group, the fourth refresh mode selection signal generation circuit 134-2 generates a fourth refresh mode selection signal REF-MD4 to control the refresh operation performed on the fourth slice chip 110-4 during the second refresh mode. For example, when the bits included in the fourth mode control signal MCNT4 are in the third bit group, the fourth refresh mode selection signal generation circuit 134-2 generates a fourth refresh mode selection signal REF-MD4 to control the refresh operation performed on the fourth slice chip 110-4 during the third refresh mode.

[0064] The fourth refresh control circuit 134-3 is connected to the refresh memory bank signal generation circuit 130-2 and the fourth refresh mode selection signal generation circuit 134-2 to receive the refresh memory bank signal REF-BK from the refresh memory bank signal generation circuit 130-2 and the fourth refresh mode selection signal REF-MD4 from the fourth refresh mode selection signal generation circuit 134-2. The fourth refresh control circuit 134-3 controls the fourth shard chip 110-4 based on the refresh memory bank signal REF-BK and the fourth refresh mode selection signal REF-MD4, causing a refresh operation to be performed in refresh mode. For example, when the fourth refresh mode selection signal REF-MD4 is received to control the refresh operation performed on the fourth shard chip 110-4 during the fourth refresh mode, the fourth refresh control circuit 134-3 controls the fourth shard chip 110-4 so that refresh operations are not performed or are skipped on the memory banks included in the fourth shard chip 110-4 selected by the refresh memory bank signal REF-BK. For example, when the fourth refresh mode selection signal REF-MD4 is received to control the refresh operation performed on the fourth shard chip 110-4 during the first refresh mode, the fourth refresh control circuit 134-3 controls the fourth shard chip 110-4 to perform two automatic refresh operations on the memory banks included in the fourth shard chip 110-4 selected by the refresh memory bank signal REF-BK. For example, when the fourth refresh mode selection signal REF-MD4 is received to control the refresh operation performed on the fourth shard chip 110-4 during the second refresh mode, the fourth refresh control circuit 134-3 controls the fourth shard chip 110-4 to perform a smart refresh operation on the memory banks included in the fourth shard chip 110-4 selected by the refresh memory bank signal REF-BK. For example, when the fourth refresh mode selection signal REF-MD4 is received to control the refresh operation performed on the fourth shard chip 110-4 during the third refresh mode, the fourth refresh control circuit 134-3 controls the fourth shard chip 110-4 to perform an automatic refresh operation on the memory bank included in the fourth shard chip 110-4 selected by the refresh memory bank signal REF-BK.

[0065] Figure 3 This is a circuit diagram showing a first mode control signal generation circuit 131-1 according to an embodiment of the present disclosure, and Figure 4 It is a table that includes data during the operation of the first mode control signal generation circuit 131-1.

[0066] like Figure 3As shown, the first mode control signal generation circuit 131-1 includes flip-flops 211-1 and 211-2, inverters 213-1 and 213-2, and selectors 215-1 and 215-2. When the reset signal RST is generated at a logic high level to start the initialization operation, flip-flop 211-1 outputs the first pre-control signal PCNT1 at a logic low level through the output terminal Q. When the refresh memory bank signal for refreshing the memory bank included in the first slicing chip 110-1 is generated and the clock signal MS-CLK is generated at a logic low level and then at a logic high level (e.g., a pulse, hereinafter referred to as "clock signal MS-CLK switching"), flip-flop 211-1 receives and latches the signal from the inverted output terminal QB as feedback through the input terminal D, and outputs the signal from the inverted output terminal QB through the output terminal Q. When the refresh memory bank signal for refreshing the memory bank included in the first slicing chip 110-1 is generated and the clock signal MS-CLK switches, flip-flop 211-1 inverts the logic level of the first pre-control signal PCNT1. Inverter 213-1 inverts and buffers the first pre-control signal PCNT1 to output the inverted and buffered signal of the first pre-control signal PCNT1. Selector 215-1 selects the first bit SID of the fragment ID. <0> The first pre-control signal PCNT1 or the output signal of inverter 213-1 is output as the first bit MCNT1 of the first mode control signal. <0> In order to select the refresh mode of the first slice chip 110-1, selector 215-1 selects the slice ID based on the first bit SID, which is at a logic low level. <0> Output the first pre-control signal PCNT1 as the first bit of the first mode control signal MCNT1 <0> When the reset signal RST is generated at a logic high level to begin the initialization operation, flip-flop 211-2 outputs the signal through output terminal Q at a logic low level. In the first bit of the first mode control signal MCNT1... <0> When a logic high level is generated, flip-flop 211-2 receives and latches the signal from the inverting output terminal QB as feedback through input terminal D, and outputs the signal from the inverting output terminal QB through output terminal Q. Therefore, when the first bit of the first mode control signal MCNT1... <0> When a logic high level is generated, flip-flop 211-2 inverts the logic level of its output terminal Q. Inverter 213-2 inverts and buffers the output signal of flip-flop 211-2 to output the inverted and buffered signal from the output of flip-flop 211-2. Selector 215-2 uses the second bit SID of the fragment ID. <1> The output signal of flip-flop 211-2 or the output signal of inverter 213-2 is used as the second bit of the first mode control signal MCNT1. <1> .In order to select the refresh mode of the first slice chip 110-1, selector 215-2 uses the second bit SID of the slice ID. <1> The output signal of flip-flop 211-2 is used as the second bit of the first mode control signal, MCNT1. <1> .

[0067] refer to Figure 3 and Figure 4 Describe the operation of the first mode control signal generation circuit 131-1. When the first bit of the fragment ID is SID... <0> and the second bit of the fragment ID, SID <1> When the logic level is low to select the refresh mode of the first slice chip 110-1, the operation of the first mode control signal generation circuit 131-1 is executed.

[0068] like Figure 3 and Figure 4 As shown in the first data line, when the reset signal RST is generated at a logic high level H to begin the initialization operation, flip-flop 211-1 outputs a first pre-control signal PCNT1 at a logic low level L. Selector 215-1 then outputs the first bit SID based on the logic low level L of the fragment ID. <0> The first bit of the logic low level L of the first mode control signal output is MCNT1. <0> The selector 215-2 determines the second bit SID based on the logic low level L of the fragment ID. <1> The second bit of the logic low level L of the first mode control signal output is MCNT1. <1> .

[0069] like Figure 3 and Figure 4 As shown in the second data line, after the initialization operation, when the refresh memory bank signal for refreshing the memory bank included in the first slice chip 110-1 is generated and the clock signal MS-CLK switches for the first time, the flip-flop 211-1 outputs the first pre-control signal PCNT1 with a logic high level H, and the selector 215-1 outputs the first bit SID according to the first bit of the logic low level L of the slice ID. <0> The first bit of the logic high level H outputting the first mode control signal is MCNT1. <0> The selector 215-2 determines the first bit SID based on the logic low level L of the fragment ID. <1> The second bit of the logic low level L outputting the first mode control signal is MCNT1. <1> .

[0070] like Figure 3 and Figure 4As shown in the third data line, when the refresh memory bank signal for refreshing the memory bank included in the first slicing chip 110-1 is generated and the clock signal MS-CLK switches for the second time, the flip-flop 211-1 outputs the first pre-control signal PCNT1 with a logic low level L, and the selector 215-1 outputs the first bit SID according to the logic low level L of the slicing ID. <0> The first bit of the logic low level L outputting the first mode control signal is MCNT1. <0> The selector 215-2 determines the first bit SID based on the logic low level L of the fragment ID. <1> The second bit of the logic high level H outputting the first mode control signal is MCNT1. <1> .

[0071] like Figure 3 and Figure 4 As shown in the fourth data line, when the refresh memory bank signal for refreshing the memory bank included in the first slicing chip 110-1 is generated and the clock signal MS-CLK switches for the third time, the flip-flop 211-1 outputs the first pre-control signal PCNT1 with a logic high level H, and the selector 215-1 sets the first bit SID to a logic low level L according to the slicing ID setting. <0> The first bit of the logic high level H outputting the first mode control signal is MCNT1. <0> The selector 215-2 determines the second bit SID based on the logic low level L of the fragment ID. <1> The second bit of the logic high level H outputting the first mode control signal is MCNT1. <1> .

[0072] Figure 5 This is a circuit diagram showing the second mode control signal generation circuit 132-1 according to an embodiment of the present disclosure, and Figure 6 It is a table of data during operation of the second mode control signal generation circuit 132-1 according to an embodiment of the present disclosure.

[0073] like Figure 5As shown, the second mode control signal generation circuit 132-1 includes flip-flops 221-1 and 221-2, inverters 223-1 and 223-2, and selectors 225-1 and 225-2. When the reset signal RST is generated at a logic high level to start the initialization operation, flip-flop 221-1 outputs the second pre-control signal PCNT2 at a logic low level through the output terminal Q. When the refresh memory bank signal for refreshing the memory bank included in the second slicing chip 110-2 is generated and the clock signal MS-CLK switches, flip-flop 221-1 receives and latches the signal from the inverted output terminal QB as feedback through the input terminal D, and outputs the signal from the inverted output terminal QB through the output terminal Q. Therefore, when the refresh memory bank signal for refreshing the memory bank included in the second slicing chip 110-2 is generated and the clock signal MS-CLK switches, flip-flop 221-1 inverts the logic level of the second pre-control signal PCNT2. Inverter 223-1 inverts and buffers the second pre-control signal PCNT2 to output the inverted buffered signal of the second pre-control signal PCNT2. Selector 225-1 selects the signal based on the first bit SID of the fragment ID. <0> The output of the second pre-control signal PCNT2 or the output signal of inverter 223-1 is used as the first bit of the second mode control signal MCNT2. <0> To select the refresh mode of the second shard chip 110-2, selector 225-1 uses the first bit of the shard ID, SID. <0> The output signal of the output inverter 223-1 is used as the first bit of the second mode control signal MCNT2. <0> When the reset signal RST is generated at a logic high level to begin the initialization operation, flip-flop 221-2 outputs a signal through output terminal Q at a logic low level. In the first bit of the second mode control signal MCNT2... <0> When a logic high level is generated, flip-flop 221-2 receives and latches the signal from the inverting output terminal QB as feedback through input terminal D, and outputs the signal from the inverting output terminal QB through output terminal Q. Therefore, when the first bit of the second mode control signal MCNT2 is MCNT2 <0> When a logic high level is generated, flip-flop 221-2 inverts the logic level of its output terminal Q. Inverter 223-2 inverts and buffers the output signal of flip-flop 221-2 to output an inverted and buffered signal from the output of flip-flop 221-2. Selector 225-2 uses the second bit SID of the fragment ID. <1> The output signal of the output flip-flop 221-2 or the output signal of the inverter 223-2 is used as the second bit of the second mode control signal MCNT2. <1> To select the refresh mode of the second shard chip 110-2, selector 225-2 uses the second bit SID of the shard ID. <1> The output signal of the output flip-flop 221-2 serves as the second bit of the second mode control signal MCNT2. <1> .

[0074] refer to Figure 5 and Figure 6 Describe the operation of the second mode control signal generation circuit 132-1. When the first bit of the fragment ID is SID... <0> The first bit of the fragment ID, SID, is at a logic high level. <1> When the logic level is low to select the refresh mode of the second slicing chip 110-2, the operation of the second mode control signal generation circuit 132-1 is executed.

[0075] like Figure 5 and Figure 6 As shown in the first data line, when the reset signal RST is generated at a logic high level H to begin the initialization operation, flip-flop 221-1 outputs a second pre-control signal PCNT2 at a logic low level L. Selector 225-1 then selects the first bit SID based on the logic high level H of the fragment ID. <0> The first bit of the logic high level H of the output second mode control signal, MCNT2. <0> The selector 225-2 determines the second bit SID based on the logic low level L of the fragment ID. <1> The second bit of the logic low level L of the output second mode control signal, MCNT2. <1> .

[0076] like Figure 5 and Figure 6 As shown in the second data line, after the initialization operation, when the refresh memory bank signal for refreshing the memory bank included in the second shard chip 110-2 is generated and the clock signal MS-CLK switches for the first time after the initialization operation, the flip-flop 221-1 outputs the second pre-control signal PCNT2 with a logic high level H. The selector 225-1 then selects the first bit SID according to the logic high level H of the shard ID. <0> The first bit of the logic low level L outputting the second mode control signal is MCNT2. <0> The selector 225-2 determines the second bit SID based on the logic low level L of the fragment ID. <1> The second bit of MCNT outputs the logic high level H of the second mode control signal. <1> .

[0077] like Figure 5 and Figure 6 As shown in the third data line, when the refresh memory bank signal for the memory bank included in the second slicing chip 110-2 is generated and the clock signal MS-CLK switches for the second time, the flip-flop 221-1 outputs the second pre-control signal PCNT2 with a logic low level L, and the selector 225-1 outputs the first bit SID according to the logic high level H of the slicing ID. <0> The first bit of the logic high level H outputting the second mode control signal is MCNT2. <0> The selector 225-2 determines the second bit SID based on the logic low level L of the fragment ID. <1> The second bit of MCNT outputs the logic high level H of the second mode control signal. <1> .

[0078] like Figure 5 and Figure 6 As shown in the fourth data line, when the refresh memory bank signal for refreshing the memory bank included in the second slicing chip 110-2 is generated and the clock signal MS-CLK switches for the third time, the flip-flop 221-1 outputs the second pre-control signal PCNT2 with a logic high level H, and the selector 225-1 selects the first bit SID according to the logic high level H of the slicing ID. <0> The first bit of the logic low level L outputting the second mode control signal is MCNT2. <0> The selector 225-2 determines the second bit SID based on the logic low level L of the fragment ID. <1> The second bit of MCNT outputs the logic low level L of the second mode control signal. <1> .

[0079] Figure 7 This is a circuit diagram showing the third mode control signal generation circuit 133-1 according to an embodiment of the present disclosure, and Figure 8 It is a table of data during operation of the third mode control signal generation circuit 133-1 according to an embodiment of the present disclosure.

[0080] like Figure 7As shown, the third mode control signal generation circuit 133-1 includes flip-flops 231-1 and 231-2, inverters 233-1 and 233-2, and selectors 235-1 and 235-2. When the reset signal RST is generated at a logic high level to start the initialization operation, flip-flop 231-1 outputs the third pre-control signal PCNT3 through output terminal Q. When the refresh memory bank signal for refreshing the memory bank included in the third slicing chip 110-3 is generated and the clock signal MS-CLK switches, flip-flop 231-1 receives and latches the signal from the inverted output terminal QB as feedback, and outputs the signal from the inverted output terminal QB through output terminal Q. Therefore, when the refresh memory bank signal for refreshing the memory bank included in the third slicing chip 110-3 is generated and the clock signal MS-CLK switches, flip-flop 231-1 inverts the logic level of the third pre-control signal PCNT3. Inverter 233-1 buffers the inverted third pre-control signal PCNT3 to output the buffered inverted signal of the third pre-control signal PCNT3. Selector 235-1 uses the first bit of the fragment ID, SID, as the basis for selection. <0> The output of the third pre-control signal PCNT3 or the output signal of inverter 233-1 is used as the first bit of the third mode control signal MCNT3. <0> To select the refresh mode of the third slicing chip 110-3, selector 235-1 uses the first bit (SID) of the slicing ID as the basis for selection. <0> The third pre-control signal PCNT3 is output as the first bit of the third mode control signal MCNT3. <0> When the reset signal RST is generated at a logic high level to begin the initialization operation, flip-flop 231-2 outputs a signal at a logic low level through output terminal Q. In the first bit of the third mode control signal MCNT3... <0> When a logic high level is generated, flip-flop 231-2 receives and latches the signal from the inverting output terminal QB, and outputs the signal from the inverting output terminal QB through the output terminal Q. Therefore, in the first bit of the third mode control signal MCNT3 <0> When a logic high level is generated, flip-flop 231-2 inverts the logic level of its output terminal Q. Inverter 233-2 inverts and buffers the output signal of flip-flop 231-2 to output an inverted and buffered signal from the output of flip-flop 231-2. Selector 235-2 uses the second bit SID of the fragment ID. <1> The output signal of the output flip-flop 231-1 or the output signal of the inverter 233-2 is used as the second bit of the third mode control signal MCNT3. <1> .

[0081] refer to Figure 7 and Figure 8Describe the operation of the third-mode control signal generation circuit 133-1. When the first bit of the fragment ID is SID... <0> The second bit of the fragment ID, SID, is at a logic low level. <1> When the logic level is high to select the refresh mode of the third slicing chip 110-3, the operation of the third mode control signal generation circuit 133-1 is executed.

[0082] like Figure 7 and Figure 8 As shown in the first data line, when the reset signal RST is generated at a logic high level to begin the initialization operation, flip-flop 231-1 outputs a third pre-control signal PCNT3 at a logic low level L. Selector 235-1 then selects the first bit SID based on the logic low level L of the fragment ID. <0> The first bit of the logic low level L outputting the third mode control signal is MCNT3. <0> The selector 235-2 determines the second bit SID based on the logic high level H of the fragment ID. <1> The second bit of the logic high level H of the output third mode control signal is MCNT3. <1> .

[0083] like Figure 7 and Figure 8 As shown in the second data line, after the initialization operation, when the refresh memory bank signal for refreshing the memory bank included in the third slicing chip 110-3 is generated and the clock signal MS-CLK switches for the first time, the flip-flop 231-1 outputs the third pre-control signal PCNT3 with a logic high level H, and the selector 235-1 outputs the first bit SID according to the logic low level L of the slicing ID. <0> The first bit of the logic high level H of the output third mode control signal is MCNT3. <0> The selector 235-2 determines the second bit SID based on the logic high level H of the fragment ID. <1> The second bit of the logic high level H of the output third mode control signal is MCNT3. <1> .

[0084] like Figure 7 and Figure 8 As shown in the third data line, when the refresh memory bank signal for the memory bank included in the third slicing chip 110-3 is generated and the clock signal MS-CLK switches for the second time, the flip-flop 231-1 outputs the third pre-control signal PCNT3 with a logic low level L. The selector 235-1 then selects the first bit SID of the slicing ID, which is at a logic low level L. <0> The first bit of the output third mode control signal, MCNT3, is at logic low level L. <0> The selector 235-2 determines the value of the second bit SID of the fragment ID, which is at a logic high level H. <1> The second bit of the output third mode control signal MCNT3 is at logic low level L. <1> .

[0085] like Figure 7 and Figure 8As shown in the fourth data line, when the refresh memory bank signal for the memory bank included in the third slicing chip 110-3 is generated and the clock signal MS-CLK switches for the third time, the flip-flop 231-1 outputs the third pre-control signal PCNT3, which is at a logic high level H. The selector 235-1 then selects the first bit SID, which is at a logic low level L, based on the slicing ID. <0> The first bit of the output third mode control signal, MCNT3, is at logic high level H. <0> The selector 235-2 determines the value of the second bit SID of the fragment ID, which is at a logic high level H. <1> The second bit of the output third mode control signal, MCNT3, is at logic low level L. <1> .

[0086] Figure 9 This is a circuit diagram showing the fourth mode control signal generation circuit 134-1 according to an embodiment of the present disclosure, and Figure 10 It is a table of data during operation of the fourth mode control signal generation circuit 134-1 according to an embodiment of the present disclosure.

[0087] like Figure 9As shown, the fourth mode control signal generation circuit 134-1 includes flip-flops 241-1 and 241-2, inverters 243-1 and 243-2, and selectors 245-1 and 245-2. When the reset signal RST is generated at a logic high level to start the initialization operation, flip-flop 241-1 outputs the fourth pre-control signal PCNT4 at a logic low level through the output terminal Q. When the refresh memory bank signal for refreshing the memory bank included in the fourth slicing chip 110-4 is generated and the clock signal MS-CLK switches, flip-flop 241-1 receives and latches the signal from the inverted output terminal QB as feedback through the input terminal D, and outputs the signal from the inverted output terminal QB through the output terminal Q. Therefore, when the refresh memory bank signal for refreshing the memory bank included in the fourth slicing chip 110-4 is generated and the clock signal MS-CLK switches, flip-flop 241-1 inverts the logic level of the fourth pre-control signal PCNT4. Inverter 243-1 inverts and buffers the fourth pre-control signal PCNT4 to output the inverted and buffered signal of the fourth pre-control signal PCNT4. Selector 245-1 selects the first bit SID of the fragment ID. <0> The output of the fourth pre-control signal PCNT4 or the output signal of inverter 243-1 is used as the first bit of the fourth mode control signal MCNT4. <0> To select the refresh mode of the fourth slice chip 110-4, selector 245-1 uses the first bit SID, which is at a logic low level, of the slice ID. <0> The output signal of inverter 243-1 is used as the first bit of the fourth mode control signal MCNT4. <0> When the reset signal RST is generated at a logic high level to begin the initialization operation, flip-flop 241-2 outputs a signal through output terminal Q at a logic low level. In the first bit of the fourth mode control signal MCNT4... <0> When a logic high level is generated, flip-flop 241-2 receives and latches the signal from the inverting output terminal QB as feedback through input terminal D, and outputs the signal from the inverting output terminal QB through output terminal Q. Therefore, in the first bit of the fourth mode control signal MCNT4 <0> When a logic high level is generated, flip-flop 241-2 inverts the logic level of its output terminal Q. Inverter 243-2 inverts and buffers the output signal of flip-flop 241-2 to output an inverted and buffered signal from the output of flip-flop 241-2. Selector 245-2 selects the output signal based on the second bit SID of the fragment ID. <0> The output signal of the output flip-flop 241-2 or the output signal of the inverter 243-2 is used as the second bit of the fourth mode control signal MCNT4. <1> To select the refresh mode of the fourth slice chip 110-4, selector 245-2 uses the second bit SID, which is at a logic high level, of the slice ID. <0> The output signal of the output inverter 243-2 is used as the second bit of the fourth mode control signal MCNT4. <1> .

[0088] refer to Figure 9 and Figure 10 Describe the operation of the fourth mode control signal generation circuit 134-1. When the first bit of the fragment ID is SID... <0> and the second bit of the fragment ID, SID <1> When the logic level is high to select the refresh mode of the fourth slicing chip 110-4, the operation of the fourth mode control signal generation circuit 134-1 is executed.

[0089] like Figure 9 and Figure 10 As shown in the first data line, when the reset signal RST is generated at a logic high level to begin the initialization operation, flip-flop 241-1 outputs the fourth pre-control signal PCNT4 at a logic low level L. Selector 245-1 then selects the first bit SID of the segment ID, which is at a logic high level H. <0> The first bit of the logic high level H outputting the fourth mode control signal is MCNT4. <0> The selector 245-2 determines the value of the second bit SID of the fragment ID, which is at a logic high level H. <1> The second bit of MCNT4, which outputs the fourth mode control signal, is at logic high level H. <1> .

[0090] like Figure 9 and Figure 10 As shown in the second data line, after the initialization operation, when the refresh memory bank signal for refreshing the memory bank included in the fourth slicing chip 110-4 is generated and the clock signal MS-CLK switches for the first time, the flip-flop 241-1 outputs the fourth pre-control signal PCNT4 with a logic high level H. The selector 245-1 then selects the first bit SID of the slicing ID based on the logic high level H of the slicing ID. <0> The first bit of the logic low level L outputting the fourth mode control signal is MCNT4. <0> The selector 245-2 determines the value of the second bit SID of the fragment ID, which is at a logic high level H. <1> The second bit of the logic low level L outputting the fourth mode control signal is MCNT4. <1> .

[0091] like Figure 9 and Figure 10 As shown in the third data line, the refresh memory bank signal is generated to refresh the memory bank included in the fourth slicing chip 110-4, and the clock signal MS-CLK switches for the second time. Flip-flop 241-1 outputs the fourth pre-control signal PCNT4, which is at a logic low level L. Selector 245-1 selects the first bit SID, which is at a logic high level H, based on the slicing ID. <0> The first bit of the logic high level H outputting the fourth mode control signal is MCNT4. <0> The selector 245-2 determines the value of the second bit SID of the fragment ID, which is at a logic high level H. <1> The second bit MCNT4, which outputs the fourth mode control signal, is at a low logic level (L). <1> .

[0092] like Figure 9 and Figure 10 As shown in the fourth data line, the refresh memory bank signal is generated to refresh the memory bank included in the fourth slicing chip 110-4, and the clock signal MS-CLK switches for the third time. Flip-flop 241-1 outputs the fourth pre-control signal PCNT4 with a logic high level H. Selector 245-1 selects the first bit SID of the slicing ID, which is at a logic high level H. <0> The first bit of the logic low level L outputting the fourth mode control signal is MCNT4. <0> The selector 245-2 determines the value of the second bit SID of the fragment ID, which is at a logic high level H. <1> The second bit of the logic high level H outputting the fourth mode control signal is MCNT4. <1> .

[0093] Figure 11 To illustrate a circuit diagram of the first refresh mode selection signal generation circuit 131-2 according to an embodiment of the present disclosure, Figure 12 This is a table of data during operation of the first refresh mode selection signal generation circuit 131-2 according to an embodiment of this disclosure.

[0094] like Figure 11 and Figure 12 As shown, the first refresh mode selection signal generation circuit 131-2 is based on the first bit MCNT1 of the first mode control signal. <0> and the second bit of the first mode control signal MCNT1 <1> The first bit of the first refresh mode selection signal, REF-MD1, is generated to select the refresh mode of the first slice chip 110-1. <0> The second bit of the first refresh mode selection signal, REF-MD1 <1> The third bit of the first refresh mode selection signal, REF-MD1 <2> and the fourth bit of the first refresh mode selection signal, REF-MD1 <3> .

[0095] like Figure 11 and Figure 12As shown, the first refresh mode selection signal generation circuit 131-2 generates the signal based on the first bit MCNT1, which includes the first mode control signal. <0> and the second bit of the first mode control signal MCNT1 <1> The first bit group generates the first bit REF-MD1 of the first refresh mode selection signal with a logic high level H. <0> And generate the second bit REF-MD1 of the first refresh mode selection signal with a logic low level L. <1> The third bit of the first refresh mode selection signal, REF-MD1 <2> and the fourth bit of the first refresh mode selection signal, REF-MD1 <3> The first bit of the first mode control signal is MCNT1. <0> and the second bit of the first mode control signal MCNT1 <1> The logic level is low (L). This is because the first bit of the first refresh mode selection signal, REF-MD1, is low. <0> When the logic level H is high, the refresh operation of the first slice chip 110-1 is the first refresh mode. Therefore, two automatic refresh operations are performed on the memory included in the first slice chip 110-1.

[0096] like Figure 11 and Figure 12 As shown, the first refresh mode selection signal generation circuit 131-2 generates the signal based on the first bit MCNT1, which includes the first mode control signal. <0> and the second bit of the first mode control signal MCNT1 <1> The second bit group, generated by logic high level H, is the second bit REF-MD1 of the first refresh mode selection signal. <1> And generate the first bit REF-MD1 of the first refresh mode selection signal with a logic low level L. <0> The third bit of the first refresh mode selection signal, REF-MD1 <2> and the fourth bit of the first refresh mode selection signal, REF-MD1 <3> The first bit of the first mode control signal is MCNT1. <0> The logic level is high (H), and the second bit of the first mode control signal is MCNT1. <1> The logic level is low (L). This is because the second bit of the first refresh mode selection signal, REF-MD1, is... <1> When the logic level H is high, the refresh operation of the first slice chip 110-1 is the second refresh mode, so a smart refresh operation is performed on the memory included in the first slice chip 110-1.

[0097] like Figure 11 and Figure 12As shown, the first refresh mode selection signal generation circuit 131-2 generates the signal based on the first bit MCNT1, which includes the first mode control signal. <0> and the second bit of the first mode control signal MCNT1 <1> The third bit group is used to generate the third bit REF-MD1 of the first refresh mode selection signal with a logic high level H. <2> And generate the first bit REF-MD1 of the first refresh mode selection signal with a logic low level L. <0> The second bit of the first refresh mode selection signal, REF-MD1 <1> and the fourth bit of the first refresh mode selection signal, REF-MD1 <3> The first bit of the first mode control signal is MCNT1. <0> The logic level is low (L), while the second bit of the first mode control signal is MCNT1. <1> The logic level is high (H). This is because the third bit of the first refresh mode selection signal, REF-MD1, is... <2> When the logic level H is high, the refresh operation of the first slice chip 110-1 is the third refresh mode, so an automatic refresh operation is performed on the memory included in the first slice chip 110-1.

[0098] like Figure 11 and Figure 12 As shown, the first refresh mode selection signal generation circuit 131-2 generates the signal based on the first bit MCNT1, which includes the first mode control signal. <0> and the second bit of the first mode control signal MCNT1 <1> The fourth bit group is used to generate the fourth bit REF-MD1 of the first refresh mode selection signal with a logic high level H. <3> And generate the first bit REF-MD1 of the first refresh mode selection signal with a logic low level L. <0> The second bit of the first refresh mode selection signal, REF-MD1 <1> The third bit of the first refresh mode selection signal, REF-MD1 <2> The first bit of the first mode control signal is MCNT1. <0> The logic level is high (H), while the second bit of the first mode control signal is MCNT1. <1> The logic level is high (H). This is because the fourth bit of the first refresh mode selection signal, REF-MD1, is... <3> When the logic level H is high, the refresh operation of the first slice chip 110-1 is the fourth refresh mode, so the refresh operation of all memory banks included in the first slice chip 110-1 is not executed or is skipped.

[0099] Figure 13 To illustrate a circuit diagram of the second refresh mode selection signal generation circuit 132-2 according to an embodiment of the present disclosure, Figure 14 This is a table of data during operation of the second refresh mode selection signal generation circuit 132-2 according to an embodiment of the present disclosure.

[0100] like Figure 13 and Figure 14As shown, the second refresh mode selection signal generation circuit 132-2 is based on the first bit MCNT2 of the second mode control signal. <0> The second bit of the second mode control signal MCNT2 <1> The first bit of the second refresh mode selection signal, REF-MD2, is generated to select the refresh mode of the second slicing chip 110-2. <0> The second bit of the second refresh mode selection signal, REF-MD2 <1> The third bit of the second refresh mode selection signal, REF-MD2 <2> And the fourth bit of the second refresh mode selection signal, REF-MD2 <3> .

[0101] like Figure 13 and Figure 14 As shown, the second refresh mode selection signal generation circuit 132-2 generates the signal based on the first bit MCNT2-, which includes the second mode control signal. <0> The second bit of the second mode control signal MCNT2 <1> The second bit group, generated by logic high level H, is the second bit of the second refresh mode selection signal REF-MD2. <1> And generate the first bit of the second refresh mode selection signal REF-MD2 with a logic low level L. <0> The third bit of the second refresh mode selection signal, REF-MD2 <2> The fourth bit of the second refresh mode selection signal, REF-MD2 <3> The first bit of the second mode control signal is MCNT2. <0> The logic level is high (H), while the second bit of the second mode control signal is MCNT2. <1> The logic level is low (L). This is because the second bit of the second refresh mode selection signal, REF-MD2, is... <1> When the logic level H is high, the refresh operation of the second slice chip 110-2 is the second refresh mode, so a smart refresh operation is performed on the memory included in the second slice chip 110-2.

[0102] like Figure 13 and Figure 14As shown, the second refresh mode selection signal generation circuit 132-2 generates the signal based on the first bit MCNT2, which includes the second mode control signal. <0> The second bit of the second mode control signal MCNT2 <1> The third bit group, generated by logic high level H, is the third bit of the second refresh mode selection signal, REF-MD2. <2> And generate the first bit of the second refresh mode selection signal REF-MD2 with a logic low level L. <0> The second bit of the second refresh mode selection signal, REF-MD2 <1> The fourth bit of the second refresh mode selection signal, REF-MD2 <3> The first bit of the second mode control signal is MCNT2. <0> The logic level is low (L), while the second bit of the second mode control signal is MCNT2. <1> The logic level is high (H). This is because the third bit of the second refresh mode selection signal, REF-MD2, is... <2> When the logic level H is high, the refresh operation of the second chip 110-2 is the third refresh mode, so an automatic refresh operation is performed on the memory included in the second chip 110-2.

[0103] like Figure 13 and Figure 14 As shown, the second refresh mode selection signal generation circuit 132-2 generates the signal based on the first bit MCNT2-, which includes the second mode control signal. <0> The second bit of the second mode control signal MCNT2- <1> The fourth bit group is used to generate the fourth bit of the second refresh mode selection signal, REF-MD2, with a logic high level H. <3> And generate the first bit of the second refresh mode selection signal REF-MD2 with a logic low level L. <0> The second bit of the second refresh mode selection signal, REF-MD2 <1> The third bit of the second refresh mode selection signal, REF-MD2 <2> The first bit of the second mode control signal is MCNT2. <0> The logic level is high (H), while the second bit of the second mode control signal is MCNT2. <1> The logic level is high (H). This is because the fourth bit of the second refresh mode selection signal, REF-MD2, is... <3> When the logic level H is high, the refresh operation of the second chip 110-2 is in the fourth refresh mode, so the refresh operation of the memory included in the second chip 110-2 is not performed or is skipped.

[0104] like Figure 13 and Figure 14As shown, the second refresh mode selection signal generation circuit 132-2 generates the signal based on the first bit MCNT2, which includes the second mode control signal. <0> The second bit of the second mode control signal MCNT2- <1> The first bit group generates the first bit of the second refresh mode selection signal REF-MD2 with a logic high level H. <0> And generate the second bit REF-MD2 of the second refresh mode selection signal with a logic low level L. <1> The third bit of the second refresh mode selection signal, REF-MD2 <2> The fourth bit of the second refresh mode selection signal, REF-MD2 <3> The first bit of the second mode control signal is MCNT2. <0> The second bit of the second mode control signal MCNT2 <1> The logic level is low (L). This is because the first bit of the second refresh mode selection signal, REF-MD2, is low. <0> When the logic level H is high, the refresh operation of the second slice chip 110-2 is the first refresh mode, so two automatic refresh operations are performed on the memory included in the second slice chip 110-2.

[0105] Figure 15 To illustrate a circuit diagram of the third refresh mode selection signal generation circuit 133-2 according to an embodiment of the present disclosure, Figure 16 This is a table of data during operation of the third refresh mode selection signal generation circuit 133-2 according to an embodiment of this disclosure.

[0106] like Figure 15 and Figure 16 As shown, the third refresh mode selection signal generation circuit 133-2 is based on the first bit MCNT3 of the third mode control signal. <0> and the second bit of the third mode control signal MCNT3 <1> The first bit of the third refresh mode selection signal, REF-MD3, is generated to select the refresh mode of the third slicing chip 110-3. <0> The second bit of the third refresh mode selection signal, REF-MD3 <1> The third bit of the third refresh mode selection signal, REF-MD3 <2> and the fourth bit of the third refresh mode selection signal, REF-MD3 <3> .

[0107] like Figure 15 and Figure 16As shown, the third refresh mode selection signal generation circuit 133-2 generates the signal based on the first bit MCNT3, which includes the third mode control signal. <0> And the second bit of the third mode control signal MCNT3- <1> The third bit group, generated by logic high level H, is the third bit of the third refresh mode selection signal REF-MD3. <2> And generate the first bit of the third refresh mode selection signal REF-MD3 with a logic low level L. <0> The second bit of the third refresh mode selection signal, REF-MD3 <1> and the fourth bit of the third refresh mode selection signal, REF-MD3 <3> Among them, the first bit of the third mode control signal is MCNT3. <0> The logic level is low (L), while the second bit of the third mode control signal is MCNT3. <1> The logic level is high (H). This is because the third bit of the third refresh mode selection signal, REF-MD3, is at this level. <2> When the logic level H is high, the refresh operation of the third chip 110-3 is the third refresh mode, so an automatic refresh operation is performed on the memory included in the third chip 110-3.

[0108] like Figure 15 and Figure 16 As shown, the third refresh mode selection signal generation circuit 133-2 generates the signal based on the first bit MCNT3, which includes the third mode control signal. <0> and the second bit of the third mode control signal MCNT3 <1> The fourth bit group is generated by using a logic high level H to generate the fourth bit of the third refresh mode selection signal, REF-MD3. <3> And generate the first bit of the third refresh mode selection signal REF-MD3 with a logic low level L. <0> The second bit of the third refresh mode selection signal, REF-MD3 <1> and the third bit of the third refresh mode selection signal REF-MD3 <2> The first bit of the third mode control signal is MCNT3. <0> The logic level is high (H), while the second bit of the third mode control signal is MCNT3. <1> The logic level is high (H). This is because the fourth bit of the third refresh mode selection signal, REF-MD3, is at this level. <3> When the logic level H is high, the refresh operation of the third chip 110-3 is in the fourth refresh mode, so the refresh operation of the memory included in the third chip 110-3 is not performed or is skipped.

[0109] like Figure 15 and Figure 16As shown, the third refresh mode selection signal generation circuit 133-2 generates the signal based on the first bit MCNT3, which includes the third mode control signal. <0> and the second bit of the third mode control signal MCNT3 <1> The first bit group generates the first bit of the third refresh mode selection signal REF-MD3 with a logic high level H. <0> And generate the second bit of the third refresh mode selection signal REF-MD3 with a logic low level L. <1> The third bit of the third refresh mode selection signal, REF-MD3 <2> and the fourth bit of the third refresh mode selection signal, REF-MD3 <3> Among them, the first bit of the third mode control signal is MCNT3. <0> and the second bit of the third mode control signal MCNT3 <1> The logic level is low (L). This is because the first bit of the third refresh mode selection signal, REF-MD3, is low. <0> When the logic level H is high, the refresh operation of the third chip 110-3 is the first refresh mode, so two automatic refresh operations are performed on the memory included in the third chip 110-3.

[0110] like Figure 15 and Figure 16 As shown, the third refresh mode selection signal generation circuit 133-2 generates the signal based on the first bit MCNT3, which includes the third mode control signal. <0> and the second bit of the third mode control signal MCNT3 <1> The second bit group generates the second bit of the third refresh mode selection signal REF-MD3 with a logic high level H. <1> And generate the first bit of the third refresh mode selection signal REF-MD3 with a logic low level L. <0> The third bit of the third refresh mode selection signal, REF-MD3 <2> and the fourth bit of the third refresh mode selection signal, REF-MD3 <3> Among them, the first bit of the third mode control signal is MCNT3. <0> The logic level is high (H), while the second bit of the third mode control signal is MCNT3. <1> The logic level is low (L). This is due to the second bit of the third refresh mode selection signal, REF-MD3. <1> When the logic level is high (H), the refresh operation of the third chip 110-3 is in the second refresh mode, and therefore a smart refresh operation is performed on the memory included in the third chip 110-3.

[0111] Figure 17 To illustrate a circuit diagram of the fourth refresh mode selection signal generation circuit 134-2 according to an embodiment of the present disclosure, Figure 18 This is a table of data during operation of the fourth refresh mode selection signal generation circuit 134-2 according to an embodiment of this disclosure.

[0112] like Figure 17 and Figure 18As shown, the fourth refresh mode selection signal generation circuit 134-2 is based on the first bit MCNT4 of the fourth mode control signal. <0> and the second bit of the fourth mode control signal MCNT4 <1> The first bit of the fourth refresh mode selection signal (REF-MD4) is used to generate the refresh mode selection signal for the fourth slicing chip 110-4. <0> The second bit of the fourth refresh mode selection signal, REF-MD4 <1> The third bit of the fourth refresh mode selection signal, REF-MD4 <2> and the fourth bit of the fourth refresh mode selection signal REF-MD4 <3> .

[0113] like Figure 17 and Figure 18 As shown, the fourth refresh mode selection signal generation circuit 134-2 generates the signal based on the first bit MCNT4, which includes the fourth mode control signal. <0> and the second bit of the fourth mode control signal MCNT4 <1> The fourth bit group is generated by using a logic high level H to generate the fourth bit of the fourth refresh mode selection signal, REF-MD4. <3> And generate the first bit of the fourth refresh mode selection signal REF-MD4 with a logic low level L. <0> The second bit of the fourth refresh mode selection signal, REF-MD4 <1> The third bit of the fourth refresh mode selection signal, REF-MD4 <2> The first bit of the fourth mode control signal is MCNT4. <0> The logic level is high (H), while the second bit of the fourth mode control signal is MCNT4. <1> The logic level is high (H). This is because the fourth bit of the fourth refresh mode selection signal, REF-MD4, is at this level. <3> When the logic level H is high, the refresh operation of the fourth chip 110-4 is in the fourth refresh mode, so the refresh operation of the memory included in the fourth chip 110-4 is not executed or is skipped.

[0114] like Figure 17 and Figure 18As shown, the fourth refresh mode selection signal generation circuit 134-2 generates the signal based on the first bit MCNT4, which includes the fourth mode control signal. <0> and the second bit of the fourth mode control signal MCNT4 <1> The first bit group generates the first bit of the fourth refresh mode selection signal REF-MD4 with a logic high level H. <0> And the second bit of the fourth refresh mode selection signal, REF-MD4, is generated with a logic low level L. <1> The third bit of the fourth refresh mode selection signal, REF-MD4 <2> and the fourth bit of the fourth refresh mode selection signal REF-MD4 <3> The first bit of the fourth mode control signal is MCNT4. <0> and the second bit of the fourth mode control signal MCNT4 <1> The logic level is low (L). This is because the fourth bit of the fourth refresh mode selection signal, REF-MD4, is at this level. <0> When the logic level H is high, the refresh operation of the fourth chip 110-4 is the first refresh mode, so two automatic refresh operations are performed on the memory included in the fourth chip 110-4.

[0115] like Figure 17 and Figure 18 As shown, the fourth refresh mode selection signal generation circuit 134-2 generates the signal based on the first bit MCNT4, which includes the fourth mode control signal. <0> and the second bit of the fourth mode control signal MCNT4 <1> The second bit group, generated by logic high level H, is the second bit of the fourth refresh mode selection signal REF-MD4. <1> And generate the first bit of the fourth refresh mode selection signal REF-MD4 with a logic low level L. <0> The third bit of the fourth refresh mode selection signal, REF-MD4 <2> and the fourth bit of the fourth refresh mode selection signal REF-MD4 <3> The first bit of the fourth mode control signal is MCNT4. <0> The logic level is high (H), while the second bit of the fourth mode control signal is MCNT4. <1> The logic level is low (L). This is because the second bit of the fourth refresh mode selection signal, REF-MD4, is low. <1> When the logic level H is high, the refresh operation of the fourth chip 110-4 is in the second refresh mode, and therefore a smart refresh operation is performed on the memory included in the fourth chip 110-4.

[0116] like Figure 17 and Figure 18As shown, the fourth refresh mode selection signal generation circuit 134-2 generates the signal based on the first bit MCNT4, which includes the fourth mode control signal. <0> And the second bit of the fourth mode control signal MCNT4- <1> The third bit group, with a logic high level H, generates the third bit of the fourth refresh mode selection signal, REF-MD4. <2> And generate the first bit of the fourth refresh mode selection signal REF-MD4 with a logic low level L. <0> The second bit of the fourth refresh mode selection signal, REF-MD4 <1> and the fourth bit of the fourth refresh mode selection signal REF-MD4 <3> The first bit of the fourth mode control signal is MCNT4. <0> The logic level is low (L), while the second bit of the fourth mode control signal is MCNT4. <1> The logic level is high (H). This is because the third bit of the fourth refresh mode selection signal, REF-MD4, is at this level. <2> When the logic level H is high, the refresh operation of the fourth chip 110-4 is in the third refresh mode, so an automatic refresh operation is performed on the memory included in the fourth chip 110-4.

[0117] Figure 19 This is a circuit diagram illustrating a first refresh control circuit 131-3 according to an embodiment of the present disclosure. Figure 19 As shown, the first refresh control circuit 131-3 includes an automatic refresh control circuit (AR CTR) 251, an intelligent refresh control circuit (SRCTR) 253, and a memory bank (BK) 255.

[0118] The automatic refresh control circuit 251 is based on the first bit REF-MD1 of the first refresh mode selection signal. <0> The third bit of the first refresh mode selection signal, REF-MD1 <2> And the fourth bit of the first refresh mode selection signal, REF-MD1 <3> Controls whether to perform an automatic refresh operation on the memory bank 255 included in the first slice chip 110-1. For example, when the automatic refresh control circuit 251 receives the first bit REF-MD1 of the logic high level of the first refresh mode selection signal. <0> The third bit of the first refresh mode selection signal, REF-MD1, is at a logic low level. <2> And the fourth bit REF-MD1 of the logic low level of the first refresh mode selection signal. <3> When the refresh operation performed on the memory bank 255 included in the first slice chip 110-1 is in the first refresh mode, two automatic refresh operations are performed on the memory bank 255. For example, when the automatic refresh control circuit 251 receives the third bit REF-MD1 of the logic high level of the first refresh mode selection signal... <2> The first bit of the first refresh mode selection signal that is low is REF-MD1. <0> And the fourth bit REF-MD1 of the logic low level of the first refresh mode selection signal. <3> At this time, the refresh mode of the refresh operation performed on the memory bank 255 included in the first slice chip 110-1 is the third refresh mode, and an automatic refresh operation is performed on the memory bank 255. For example, when the automatic refresh control circuit 251 receives the fourth bit REF-MD1 of the logic high level of the first refresh mode selection signal. <3> The first bit of the first refresh mode selection signal that is low is REF-MD1. <0> And the third bit REF-MD1 of the logic low level of the first refresh mode selection signal. <2> At that time, the refresh mode of the refresh operation performed on the memory bank 255 included in the first chip 110-1 is the fourth refresh mode, and the automatic refresh operation is not performed on the memory bank 255.

[0119] The intelligent refresh control circuit 253 is based on the second bit REF-MD1 of the first refresh mode selection signal. <1> and the fourth bit of the first refresh mode selection signal, REF-MD1 <3> Controls whether to perform a smart refresh operation on the memory bank 255 included in the first slice chip 110-1. For example, when the smart refresh control circuit 253 receives the second bit REF-MD1 of the logic high level of the first refresh mode selection signal. <1> The fourth bit REF-MD1 of the first refresh mode selection signal is at a logic low level. <3> At this time, the refresh mode of the refresh operation performed on the memory bank 255 included in the first slice chip 110-1 is the second refresh mode, and a smart refresh operation is performed on the memory bank 255. For example, when the smart refresh control circuit 253 receives the fourth bit REF-MD1 of the logic high level of the first refresh mode selection signal... <3> The second bit REF-MD1 of the first refresh mode selection signal is at a low logic level. <1> At that time, the refresh mode of the refresh operation performed on the memory bank 255 included in the first chip 110-1 is the fourth refresh mode, and the intelligent refresh operation is not performed on the memory bank 255.

[0120] The first refresh control circuit 131-3 controls the first shard chip 110-1 based on the refresh memory signal REF-BK and the first refresh mode selection signal REF-MD1, so that the refresh operation is performed in refresh mode. The second refresh control circuit 132-3 can be configured similarly to Figure 19 The first refresh control circuit 131-3 controls the second shard chip 110-2 based on the refresh memory signal REF-BK and the second refresh mode selection signal REF-MD2, so that the refresh operation is performed in refresh mode. The third refresh control circuit 133-3 can be configured similarly to Figure 19 The first refresh control circuit 131-3 controls the third shard chip 110-3 based on the refresh memory signal REF-BK and the third refresh mode selection signal REF-MD3, so that the refresh operation is performed in refresh mode. The fourth refresh control circuit 134-3 can be configured similarly to... Figure 19 The first refresh control circuit 131-3 controls the fourth slicing chip 110-4 based on the refresh memory signal REF-BK and the fourth refresh mode selection signal REF-MD4, so that the refresh operation is performed in refresh mode.

[0121] Figure 20 It is a timing diagram for the refresh mode performed for each chip segment.

[0122] During the time period from time T11 to time T12, the reset signal RST is generated at a logic high level to initiate the initialization operation, and refresh memory bank signals are generated to refresh the memory banks included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The refresh operation for the first slice chip 110-1 is performed in the first refresh mode, the refresh operation for the second slice chip 110-2 is performed in the second refresh mode, the refresh operation for the third slice chip 110-3 is performed in the third refresh mode, and the refresh operation for the fourth slice chip 110-4 is performed in the fourth refresh mode. During the time period from time T11 to time T12, two automatic refresh operations are performed on the memory included in the first slice chip 110-1, a smart refresh operation is performed on the memory included in the second slice chip 110-2, an automatic refresh operation is performed on the memory included in the third slice chip 110-3, and no refresh operation is performed or the refresh operation is skipped on the memory included in the fourth slice chip 110-4.

[0123] During the time period from time T12 to time T13, the first pulse of the clock signal MS-CLK is generated at a logic high level (clock signal switching), and refresh memory bank signals are generated to refresh the memory banks included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The refresh operation for the first slice chip 110-1 is performed in the second refresh mode, the refresh operation for the second slice chip 110-2 is performed in the third refresh mode, the refresh operation for the third slice chip 110-3 is performed in the fourth refresh mode, and the refresh operation for the fourth slice chip 110-4 is performed in the first refresh mode. During the time period from time T12 to time T13, a smart refresh operation is performed on the memory included in the first slice chip 110-1, an automatic refresh operation is performed on the memory included in the second slice chip 110-2, no refresh operation is performed or the refresh operation is skipped on the memory included in the third slice chip 110-3, and two automatic refresh operations are performed on the memory included in the fourth slice chip 110-4.

[0124] During the time period from time T13 to time T14, the second pulse of the clock signal MS-CLK is generated at a logic high level, and refresh memory bank signals are generated to refresh the memory banks included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The refresh operation for the first slice chip 110-1 is performed in the third refresh mode, the refresh operation for the second slice chip 110-2 is performed in the fourth refresh mode, the refresh operation for the third slice chip 110-3 is performed in the first refresh mode, and the refresh operation for the fourth slice chip 110-4 is performed in the second refresh mode. During the time period from time T13 to time T14, an automatic refresh operation is performed on all memory cells included in the first slice chip 110-1, no refresh operation is performed or the refresh operation is skipped on the memory cells included in the second slice chip 110-2, two automatic refresh operations are performed on the memory cells included in the third slice chip 110-3, and a smart refresh operation is performed on the memory cells included in the fourth slice chip 110-4.

[0125] During the time period from time T14 to time T15, the third pulse of the clock signal MS-CLK is generated at a logic high level, and refresh memory bank signals are generated to refresh the memory banks included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The refresh operation for the first slice chip 110-1 is performed in the fourth refresh mode, the refresh operation for the second slice chip 110-2 is performed in the first refresh mode, the refresh operation for the third slice chip 110-3 is performed in the second refresh mode, and the refresh operation for the fourth slice chip 110-4 is performed in the third refresh mode. During the time period from time T14 to time T15, the refresh operation of the memory included in the first slice chip 110-1 is not performed or is skipped, two automatic refresh operations are performed on the memory included in the second slice chip 110-2, a smart refresh operation is performed on the memory included in the third slice chip 110-3, and an automatic refresh operation is performed on the memory included in the fourth slice chip 110-4.

[0126] During the time period from time T15 to time T16, the fourth pulse of the clock signal MS-CLK is generated at a logic high level, and refresh memory bank signals are generated to refresh the memory banks included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The refresh operation for the first slice chip 110-1 is performed in the first refresh mode, the refresh operation for the second slice chip 110-2 is performed in the second refresh mode, the refresh operation for the third slice chip 110-3 is performed in the third refresh mode, and the refresh operation for the fourth slice chip 110-4 is performed in the fourth refresh mode. During the time period from time T15 to time T16, two automatic refresh operations are performed on the memory included in the first slice chip 110-1, a smart refresh operation is performed on the memory included in the second slice chip 110-2, an automatic refresh operation is performed on the memory included in the third slice chip 110-3, and no refresh operation is performed or the refresh operation is skipped on the memory included in the fourth slice chip 110-4.

[0127] During the time period from time T16 to time T17, the fifth pulse of the clock signal MS-CLK is generated at a logic high level, and refresh memory bank signals are generated to refresh the memory banks included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The refresh operation for the first slice chip 110-1 is performed in the second refresh mode, the refresh operation for the second slice chip 110-2 is performed in the third refresh mode, the refresh operation for the third slice chip 110-3 is performed in the fourth refresh mode, and the refresh operation for the fourth slice chip 110-4 is performed in the first refresh mode. During the time period from time T16 to time T17, a smart refresh operation is performed on the memory included in the first slice chip 110-1, an automatic refresh operation is performed on the memory included in the second slice chip 110-2, no refresh operation is performed or the refresh operation is skipped on all the memory included in the third slice chip 110-3, and two automatic refresh operations are performed on all the memory included in the fourth slice chip 110-4.

[0128] During the time period from time T17 to time T18, the sixth pulse of the clock signal MS-CLK is generated at a logic high level, and refresh memory bank signals are generated to refresh the memory banks included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The refresh operation for the first slice chip 110-1 is performed in the third refresh mode, the refresh operation for the second slice chip 110-2 is performed in the fourth refresh mode, the refresh operation for the third slice chip 110-3 is performed in the first refresh mode, and the refresh operation for the fourth slice chip 110-4 is performed in the second refresh mode. During the time period from time T17 to time T18, an automatic refresh operation is performed on the memory included in the first slice chip 110-1, the refresh operation on the memory included in the second slice chip 110-2 is not performed or is skipped, two automatic refresh operations are performed on the memory included in the third slice chip 110-3, and a smart refresh operation is performed on the memory included in the fourth slice chip 110-4.

[0129] During the period following time T18, the seventh pulse of the clock signal MS-CLK is generated at a logic high level, and refresh memory bank signals are generated for the memory banks included in the first slice chip 110-1, the second slice chip 110-2, the third slice chip 110-3, and the fourth slice chip 110-4. The refresh operation for the first slice chip 110-1 is performed in the fourth refresh mode, the refresh operation for the second slice chip 110-2 is performed in the first refresh mode, the refresh operation for the third slice chip 110-3 is performed in the second refresh mode, and the refresh operation for the fourth slice chip 110-4 is performed in the third refresh mode. During the period following time T18, refresh operations for the memory banks included in the first slice chip 110-1 are not performed or are skipped; two automatic refresh operations are performed for the memory banks included in the second slice chip 110-2; a smart refresh operation is performed for the memory banks included in the third slice chip 110-3; and an automatic refresh operation is performed for the memory banks included in the fourth slice chip 110-4.

[0130] The refresh modes for refresh operations performed in the first shard chip 110-1, second shard chip 110-2, third shard chip 110-3, and fourth shard chip 110-4 of the stacked storage device 10 include a first refresh mode that performs two automatic refresh operations, a second refresh mode that performs a smart refresh operation, a third refresh mode that performs an automatic refresh operation, and a fourth refresh mode that does not perform or skips refresh operations. When refresh operations are performed in the order of the first refresh mode, third refresh mode, second refresh mode, and fourth refresh mode, the current consumed during a refresh operation decreases for each subsequent refresh operation. Among the refresh modes, the first refresh mode has the highest current consumption, the second refresh mode has the second highest current consumption, the third refresh mode has the third highest current consumption, and the fourth refresh mode has the lowest current consumption. The stacked storage device 10 uses the shard ID (SID) to assign high-current-consuming refresh modes to the first shard chip 110-1, the second shard chip 110-2, the third shard chip 110-3, and the fourth shard chip 110-4, thereby reducing the current consumption when performing refresh operations in the stacked storage device 10.

[0131] Figure 21 A block diagram illustrating a stacked storage system 3 according to an embodiment of the present disclosure. (See attached diagram.) Figure 21 As shown, the stacked storage system 3 includes a first stacked storage device 3100, a second stacked storage device 3200, a processor 3300, an interposer layer 3400, and a substrate 3500.

[0132] An interposer layer 3400 is disposed on the substrate 3500. A first stacked storage device 3100, a second stacked storage device 3200, and a processor 3300 are disposed on the interposer layer 3400. The processor 3300 is disposed between the first stacked storage device 3100 and the second stacked storage device 3200. The interposer layer 3400 electrically connects the substrate 3500, the first stacked storage device 3100, the second stacked storage device 3200, and the processor 3300. When the spacing difference between the first stacked storage device 3100, the second stacked storage device 3200, and the processor 3300 is large, the first stacked storage device 3100, the second stacked storage device 3200, and the processor 3300 are electrically connected using the interposer layer 3400, which includes various formed wires.

[0133] Processor 3300 includes a first controller 3310 for controlling a first stacked storage device 3100 and a first processor interface circuit 3320 electrically connecting the first stacked storage device 3100 to the first controller 3310. Processor 3300 also includes a second controller 3330 for controlling a second stacked storage device 3200 and a second processor interface circuit 3340 electrically connecting the second stacked storage device 3200 to the second controller 3330. Processor 3300 transmits signals including commands and addresses controlling various internal operations of the first stacked storage device 3100 to the first stacked storage device 3100 via the first processor interface circuit 3320, and receives signals from the first stacked storage device 3100 via the first processor interface circuit 3320. Processor 3300 transmits signals including commands and addresses controlling various internal operations of the second stacked storage device 3200 to the second stacked storage device 3200 via the second processor interface circuit 3340, and receives signals from the second stacked storage device 3200 via the second processor interface circuit 3340.

[0134] The first stacked storage device 3100 includes a first base chip 3110 and first core chips 3120, 3130, 3140, and 3150. The first core chips 3120, 3130, 3140, and 3150 are stacked sequentially on top of the first base chip 3110 and receive various signals from the first base chip 3110 via TSV. Figure 21 In the first stacked storage device 3100, four first core chips 3120, 3130, 3140, and 3150 are included, but it can be configured to include four, eight, sixteen, or other numbers of first core chips. For example, the first stacked storage device 3100 utilizes... Figure 1 This is achieved using the stacked storage device 10 shown.

[0135] The first base chip 3110 includes a first core interface circuit 3111. The first core interface circuit 3111 is configured to communicate with the first processor interface circuit 3320 to receive signals sent from the processor 3300 and transmit signals generated from the first core chips 3120, 3130, 3140 and 3150 to the processor 3300.

[0136] The second stacked storage device 3200 includes a second base chip 3210 and second core chips 3220, 3230, 3240, and 3250. The second core chips 3220, 3230, 3240, and 3250 are stacked sequentially on top of the second base chip 3210 and receive various signals from the second base chip 3210 via TSV. Figure 21In the second stacked storage device 3200, four second core chips 3220, 3230, 3240, and 3250 are included, but it can be configured to include four, eight, sixteen, or other numbers of second core chips. For example, the second stacked storage device 3200 uses... Figure 1 This is achieved using the stacked storage device 10 shown.

[0137] The second base chip 3210 includes a second core interface circuit 3211. The second core interface circuit 3211 is configured to communicate with the second processor interface circuit 3340 to receive signals sent from the processor 3300 and to transmit signals generated from the second core chips 3220, 3230, 3240 and 3250 to the processor 3300.

[0138] Figure 22 A block diagram illustrating a stacked storage system 4 according to an embodiment of the present disclosure. (See attached diagram.) Figure 22 As shown, the stacked storage system 4 includes a first stacked storage device 4100, a second stacked storage device 4200, a system control device 4300, a substrate 4400, and a motherboard 4500.

[0139] A substrate 4400 is mounted on a motherboard 4500, a system control device 4300 is mounted on the substrate 4400, and a first stacked storage device 4100 and a second stacked storage device 4200 are mounted on the system control device 4300. The system control device 4300 includes a processor 4310, a first controller 4320, a first processor interface circuit 4330, a second controller 4340, and a second processor interface circuit 4350.

[0140] Processor 4310 is electrically connected to first controller 4320 to control various internal operations of first stacked storage device 4100. Processor 4310 transmits signals including commands and addresses controlling various internal operations of first stacked storage device 4100 to first stacked storage device 4100 via first processor interface circuit 4330, and receives signals from first stacked storage device 4100 via first processor interface circuit 4330. Processor 4310 is electrically connected to second controller 4340 to control various internal operations of second stacked storage device 4200. Processor 4310 transmits signals including commands and addresses controlling various internal operations of second stacked storage device 4100 to second stacked storage device 4200 via second processor interface circuit 4350, and receives signals from second stacked storage device 4200 via second processor interface circuit 4350.

[0141] The first stacked storage device 4100 includes a first base chip 4110 and first core chips 4120, 4130, 4140, and 4150. The first stacked storage device 4100, for example, via... Figure 1 The stacked storage device 10 shown is used to implement this. First core chips 4120, 4130, 4140, and 4150 are sequentially stacked on top of the first base chip 4110 and receive various signals from the first base chip 4110 via TSV. Figure 22 In the first stacked storage device 4100, four first core chips 4120, 4130, 4140, and 4150 are included, but it can be configured to include four, eight, twelve, sixteen, or other numbers of first core chips. The first stacked storage device 4100 can, for example, utilize... Figure 1 This is achieved using the stacked storage device 10 shown.

[0142] The first base chip 4110 includes a first core interface circuit 4111. The first core interface circuit 4111 is configured to communicate with the first processor interface circuit 4330 to receive signals sent from the processor 4310 and to transmit signals generated from the first core chips 4120, 4130, 4140 and 4150 to the processor 4310.

[0143] The second stacked storage device 4200 includes second core chips 4210, 4220, 4230, and 4240. The second core chips 4210, 4220, 4230, and 4240 are stacked sequentially and receive various signals via a TSV. Figure 22 In the second stacked storage device 4200, four second core chips 4210, 4220, 4230, and 4240 are included, but it can be configured to include four, eight, sixteen, or other numbers of second core chips. The second stacked storage device 4200 is formed by stacking core chips without a base chip. For example, the second stacked storage device 4200 is formed by... Figure 1 This is achieved using the stacked storage device 10 shown.

[0144] The second stacked storage device 4200 is configured to communicate with the second processor interface circuit 4350 to receive signals sent from the processor 4310 and transmit signals generated from the second core chips 4210, 4220, 4230 and 4240 to the processor 4310.

[0145] The concept has been disclosed in conjunction with various examples and embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered illustratively and not restrictively. The scope of this disclosure is not limited to illustration, and all distinguishing features within the equivalent scope should be interpreted as being included in this disclosure. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A stacked storage device, comprising: Basic chips; The first chip segment is stacked on top of the base chip; and The second chip is stacked on top of the first chip. The base chip includes a slicing control circuit. When a refresh memory signal is generated to refresh the memory included in the first slicing chip and the second slicing chip, the slicing control circuit controls the first slicing chip and the second slicing chip so that the refresh operation is performed according to the refresh mode of the first slicing chip and the refresh mode of the second slicing chip.

2. The stacked storage device according to claim 1, wherein, The sharding control circuit controls the first sharding chip so that the refresh operation is performed sequentially and repeatedly according to the order of the first refresh mode, the second refresh mode, the third refresh mode and the fourth refresh mode to refresh the memory included in the first sharding chip.

3. The stacked storage device according to claim 2, wherein, The sharding control circuit controls the first sharding chip to perform two automatic refresh operations on the memory included in the first sharding chip during the first refresh mode, perform a smart refresh operation during the second refresh mode, perform the automatic refresh operation during the third refresh mode, and not perform a refresh operation during the fourth refresh mode.

4. The stacked storage device according to claim 2, wherein, The sharding control circuit controls the second sharding chip to perform refresh operations sequentially and repeatedly according to the order of the second refresh mode, the third refresh mode, the fourth refresh mode and the first refresh mode, so as to refresh the memory included in the second sharding chip.

5. The stacked storage device according to claim 4, wherein, The sharding control circuit controls the second sharding chip to perform the smart refresh operation on the memory included in the second sharding chip during the second refresh mode, to perform the automatic refresh operation during the third refresh mode, not to perform a refresh operation during the fourth refresh mode, and to perform the automatic refresh operation twice during the first refresh mode.

6. The stacked storage device of claim 1, wherein the sharding control circuit comprises: A control circuit, comprising: generating a clock signal, the clock signal being switched when a refresh memory signal is generated to refresh the memory included in the first and second shard chips; and The first slice refresh control circuit selects the refresh mode of the first slice chip based on the clock signal, the reset signal and the slice ID, where ID represents an identifier.

7. The stacked storage device according to claim 6, wherein, The control circuit includes: A command address decoder, which decodes command addresses to generate refresh commands; A refresh memory bank signal generation circuit, comprising: generating a refresh memory bank signal based on the refresh command, wherein the refresh memory bank signal selects at least one memory bank from the memory banks included in the first and second shard chips to which the refresh operation is performed; and A clock signal generation circuit generates the clock signal when generating the refresh memory signal for the memory included in the first and second shard chips.

8. The stacked storage device according to claim 7, in, The command address decoder generates the refresh command; as well as The refresh commands include: a full memory bank refresh command, which is generated to simultaneously perform the refresh operation on all memory banks included in the first shard chip and the second shard chip; and a per memory bank refresh command, which is generated to independently perform the refresh operation on each memory bank included in the first shard chip and the second shard chip.

9. The stacked storage device according to claim 6, wherein, First slice refresh control circuit: When the reset signal is generated at a predetermined logic level to start the initialization operation, the refresh operation performed on the first slice chip during the first refresh mode is controlled according to the slice ID. as well as When the clock signal switches for the first time after the initialization operation, the refresh operation is performed on the first slice chip during the second refresh mode according to the slice ID.

10. The stacked storage device according to claim 9, wherein, First slice refresh control circuit: When the clock signal switches for the second time, the refresh operation performed on the first slice chip during the third refresh mode is controlled according to the slice ID. When the clock signal switches for the third time, the refresh operation performed on the first slice chip during the fourth refresh mode is controlled according to the slice ID. as well as When the clock signal switches for the fourth time, the refresh operation performed on the first slice chip during the first refresh mode is controlled according to the slice ID.

11. The stacked storage device according to claim 6, wherein, The first fragment refresh control circuit includes: The first mode control signal generation circuit generates a first mode control signal based on the clock signal, the reset signal, and the segment ID. The first refresh mode selection signal generation circuit generates a first refresh mode selection signal based on the bit group of the first mode control signal; and A first refresh control circuit controls the refresh operation on the first shard chip and selects the refresh mode of the first shard chip based on the refresh memory signal and the first refresh mode selection signal.

12. The stacked storage device according to claim 6, wherein, The slicing control circuit further includes a second slicing refresh control circuit, which selects the refresh mode of the second slicing chip based on the clock signal, the reset signal, and the slicing ID.

13. The stacked storage device according to claim 12, wherein, Second segment refresh control circuit: When the reset signal is generated at a predetermined logic level to start the initialization operation, the refresh operation performed on the second slice chip during the second refresh mode is controlled according to the slice ID; as well as When the clock signal switches for the first time after the initialization operation, the refresh operation performed on the second slice chip during the third refresh mode is controlled according to the slice ID.

14. The stacked storage device according to claim 13, wherein, Second segment refresh control circuit: When the clock signal switches for the second time, the refresh operation performed on the second slice chip during the fourth refresh mode is controlled according to the slice ID; When the clock signal switches for the third time, the refresh operation performed on the second slice chip during the first refresh mode is controlled according to the slice ID. as well as When the clock signal switches for the fourth time, the refresh operation performed on the second slice chip during the second refresh mode is controlled according to the slice ID.

15. The stacked storage device according to claim 12, wherein, The second slice refresh control circuit includes: The second mode control signal generation circuit generates a second mode control signal based on the mode selection signal, the reset signal, and the segment ID. The second refresh mode selection signal generation circuit generates a second refresh mode selection signal based on the bit group of the second mode control signal; and The second refresh control circuit controls the refresh operation on the second shard chip and selects the refresh mode of the second shard chip based on the refresh memory signal and the second refresh mode selection signal.

16. The stacked storage device of claim 1, further comprising a third shard chip stacked on top of the second shard chip, wherein, The slicing control circuit: when the refresh memory signal for refreshing the memory included in the third slicing chip is generated, it controls the third slicing chip to perform the refresh operation according to the refresh mode of the third slicing chip.

17. The stacked storage device according to claim 16, wherein, The slicing control circuit controls the third slicing chip to sequentially and repeatedly execute the refresh operation according to the order of the third refresh mode, the fourth refresh mode, the first refresh mode, and the second refresh mode, so as to refresh the memory included in the third slicing chip.

18. The stacked storage device according to claim 17, wherein, The sharding control circuit controls the third sharding chip to perform an automatic refresh operation on the memory included in the third sharding chip during the third refresh mode, not to perform the refresh operation during the fourth refresh mode, to perform the automatic refresh operation twice during the first refresh mode, and to perform a smart refresh operation during the second refresh mode.

19. A stacked storage device, comprising: Basic chips; The first chip segment is stacked on top of the base chip; and The second chip slice is stacked on top of the first chip slice. The basic chip includes: A control circuit, comprising: generating a clock signal, the clock signal being switched during the generation of a refresh memory bank signal that refreshes the memory banks included in the first and second shard chips; and The first slice refresh control circuit selects the refresh mode of the first slice chip based on the clock signal, reset signal and slice ID, where ID represents an identifier.

20. The stacked storage device according to claim 19, wherein, The control circuit includes: A command decoder that decodes command addresses to generate refresh commands; A refresh memory bank signal generation circuit, comprising: generating a refresh memory bank signal based on the refresh command, wherein the refresh memory bank signal selects at least one memory bank from the memory banks included in the first and second shard chips to which the refresh operation is performed; and A clock signal generation circuit generates the clock signal when generating the refresh memory signal for the memory included in the first and second shard chips.

21. The stacked storage device according to claim 20, in, The command address decoder generates the refresh command; as well as The refresh commands include: a full memory bank refresh command, which is generated to simultaneously perform the refresh operation on all memory banks included in each of the first shard chip and the second shard chip; and a per memory bank refresh command, which is generated to independently perform the refresh operation on each memory bank included in each of the first shard chip and the second shard chip.

22. The stacked storage device according to claim 19, wherein, First slice refresh control circuit: When the reset signal is generated at a predetermined logic level to start the initialization operation, the refresh operation performed on the first slice chip during the first refresh mode is controlled according to the slice ID. as well as When the clock signal switches for the first time after the initialization operation, the refresh operation is performed on the first slice chip during the second refresh mode according to the slice ID.

23. The stacked storage device according to claim 22, wherein, First slice refresh control circuit: When the clock signal switches for the second time, the refresh operation performed on the first slice chip during the third refresh mode is controlled according to the slice ID. When the clock signal switches for the third time, the refresh operation performed on the first slice chip during the fourth refresh mode is controlled according to the slice ID. as well as When the clock signal switches for the fourth time, the refresh operation performed on the first slice chip during the first refresh mode is controlled according to the slice ID.

24. The stacked storage device according to claim 19, wherein, The first fragment refresh control circuit includes: The first mode control signal generation circuit generates a first mode control signal based on the clock signal, the reset signal, and the segment ID. The first refresh mode selection signal generation circuit generates a first refresh mode selection signal based on the bit group of the first mode control signal; and A first refresh control circuit controls the refresh operation of the first shard chip and selects the refresh mode of the first shard chip based on the refresh memory signal and the first refresh mode selection signal.

25. The stacked storage device according to claim 19, wherein, The slicing control circuit further includes a second slicing refresh control circuit, which selects the refresh mode of the second slicing chip based on the clock signal, the reset signal, and the slicing ID.

26. The stacked storage device according to claim 25, wherein, Second segment refresh control circuit: When the reset signal is generated at a predetermined logic level to start the initialization operation, the refresh operation performed on the second slice chip during the second refresh mode is controlled according to the slice ID; as well as When the clock signal switches for the first time after the initialization operation, the refresh operation performed on the second shard chip during the third refresh mode is controlled.

27. The stacked storage device according to claim 26, wherein, Second segment refresh control circuit: When the clock signal switches for the second time, the refresh operation performed on the second slice chip during the fourth refresh mode is controlled according to the slice ID. When the clock signal switches for the third time, the refresh operation performed on the second slice chip during the first refresh mode is controlled according to the slice ID. as well as When the clock signal switches for the fourth time, the refresh operation performed on the second slice chip during the second refresh mode is controlled according to the slice ID.

28. The stacked storage device according to claim 25, wherein, The second slice refresh control circuit includes: The second mode control signal generation circuit generates a second mode control signal based on the mode selection signal, the reset signal, and the segment ID. The second refresh mode selection signal generation circuit generates a second refresh mode selection signal based on the bit group of the second mode control signal; and The second refresh control circuit controls the refresh operation on the second shard chip and selects the refresh mode of the second shard chip based on the refresh memory signal and the second refresh mode selection signal.

29. The stacked storage device of claim 19, further comprising a third shard chip stacked on top of the second shard chip, wherein, The slicing control circuit further includes a third slicing refresh control circuit, which selects the refresh mode of the third slicing chip based on the clock signal, the reset signal, and the slicing ID.

30. The stacked storage device according to claim 29, wherein, The third segment control circuit: When the reset signal is generated at a predetermined logic level to begin the initialization operation, the refresh operation performed on the third slice chip during the third refresh mode is controlled according to the slice ID, and When the clock signal switches for the first time after the initialization operation, the refresh operation is performed on the third slice chip during the fourth refresh mode according to the slice ID.

31. The stacked storage device according to claim 30, wherein, The third segment control circuit: When the clock signal switches for the second time, the refresh operation performed on the third slice chip during the first refresh mode is controlled according to the slice ID. When the clock signal switches for the third time, the refresh operation is performed on the third slice chip during the second refresh mode according to the slice ID. as well as When the clock signal switches for the fourth time, the refresh operation performed on the third slice chip during the third refresh mode is controlled according to the slice ID.

32. The stacked storage device according to claim 29, wherein, The third segment control circuit includes: The third mode control signal generation circuit generates a third mode control signal based on the mode selection signal, the reset signal, and the segment ID. The third refresh mode selection signal generation circuit generates a third refresh mode selection signal based on the bit group of the third mode control signal; and The third refresh control circuit controls the refresh operation on the third shard chip and selects the refresh mode of the third shard chip based on the refresh memory signal and the third refresh mode selection signal.

33. A method comprising: When a refresh memory bank signal is generated for refreshing the memory banks included in the first and second shard chips of the stacked memory device, the first shard chip is controlled by the shard control circuit for the first and second shard chips, so that a refresh operation is performed according to the refresh mode of the first shard chip. as well as When a refresh memory signal is generated to refresh the memory included in the first and second shard chips, the shard control circuit controls the second shard chip to perform a refresh operation according to the refresh mode of the second shard chip.

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