Semiconductor structure, preparation method and wafer

Abstract

The invention relates to the field of semiconductor device manufacturing, and particularly provides a semiconductor structure, a preparation method and a wafer. The epitaxial layer is located on the substrate and has a first doping type; the first insulating layer is located on the epitaxial layer; the second insulating layer is located on the epitaxial layer; the first open groove and the second open groove are located in the second insulating layer and are transversely separated from each other, the first open groove is exposed out of the first insulating layer, and the second open groove is exposed out of the epitaxial layer; the metal layer is located in the first slot; and the well region is located in the second slot. According to the invention, the capacitance regulation and control range of the variable capacitance diode can be widened, the process difficulty is low, and the possible adverse effects of high-concentration ion implantation on the substrate and the dielectric layer can be remarkably reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and specifically provides a semiconductor structure, a preparation method, and a wafer. Background Technology

[0002] Varactor diodes are widely used in communication equipment (such as FM radios and wireless communication modules), television receivers (such as tuner circuits and automatic frequency control (AFC)), and radio frequency systems (such as voltage-controlled oscillators (VCOs) and tunable filters).

[0003] Varactor diodes are classified into MOS varactor diodes and junction varactor diodes. The capacitance variation range of a junction varactor diode is limited by the PN junction width under reverse bias. Although increasing the doping concentration of heteroatoms during ion implantation can expand the capacitance variation range of the varactor diode, this change not only increases the requirements for the equipment and photoresist, but also exacerbates the damage to the wafer surface caused by high-concentration ion implantation. Therefore, under current conditions, expanding the capacitance variation range of junction varactor diodes is a cumbersome and complex process.

[0004] While MOS varactor diodes have been developed, their gate oxide is typically grown using FUR (or organic vapor phase reactor) or ISSG (in-situ water vapor generation) processes. However, both processes have inherent limitations, resulting in the capacitance control range of MOS varactor diodes being consistently restricted by the thickness of the gate oxide layer, and their control precision being relatively poor. Therefore, a new semiconductor structure with varactor diode characteristics is needed, offering not only a wide capacitance variation range but also high control precision. Summary of the Invention

[0005] To overcome the above-mentioned defects, the present invention provides a semiconductor structure, a preparation method and a wafer. The capacitor constructed using the semiconductor structure of the present invention has higher capacitance regulation capability and the preparation method is simple.

[0006] In a first aspect, the present invention provides a semiconductor structure comprising: a substrate; an epitaxial layer on the substrate having a first doping type; a first insulating layer on the epitaxial layer; a second insulating layer on the epitaxial layer; a first trench and a second trench located in the second insulating layer and laterally spaced apart from each other, wherein the first trench exposes the first insulating layer and the second trench exposes the epitaxial layer; a metal layer located in the first trench; and a well region located in the second trench, the well region having a second doping type opposite to the first doping type.

[0007] Furthermore, the first insulating layer and the second insulating layer are formed separately from each other.

[0008] Furthermore, there is a boundary between the first insulating layer and the second insulating layer.

[0009] Furthermore, the first insulating layer and the second insulating layer are an integral structure.

[0010] Furthermore, the semiconductor structure further includes: a first electrode, which is in electrical contact with the well region; a second electrode, which is in electrical contact with the metal layer; and a third electrode, which is in electrical contact with the substrate.

[0011] Furthermore, the semiconductor structure further includes: a third insulating layer covering the metal junction.

[0012] The structure includes a well region and an exposed second insulating layer; a first via disposed in the third insulating layer electrically connects the first electrode and the well region; and a second via disposed in the third insulating layer electrically connects the second electrode and the metal layer.

[0013] Furthermore, the epitaxial layer is formed on the first surface of the substrate, and the third electrode is located on the second surface of the substrate, the second surface being opposite to the first surface.

[0014] Furthermore, the metal layer is annular, surrounding the well region.

[0015] Furthermore, the well region comprises a plurality of well regions that are insulated from each other, the plurality of well regions surrounding the metal layer.

[0016] Furthermore, both the second and third insulating layers are made of materials with a dielectric constant ε greater than 4.

[0017] Furthermore, the materials of the second insulating layer and / or the third insulating layer are HfO2, ZrO2, or SiON, respectively.

[0018] Furthermore, the second and third insulating layers are made of the same material.

[0019] Furthermore, the metal layer is made of copper, aluminum, or tungsten.

[0020] Furthermore, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

[0021] Furthermore, the epitaxial layer is formed on the first surface of the substrate, and the third electrode is located on the second surface of the substrate, the second surface being opposite to the first surface.

[0022] In a second aspect, the present invention provides a wafer comprising: a plurality of semiconductor structures as described in any one of the first aspects, wherein the plurality of semiconductor structures are arranged in an array.

[0023] In a third aspect, the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0024] An epitaxial layer is formed on a substrate, the epitaxial layer having a first doping type; a first insulating layer is formed on the epitaxial layer; a second insulating layer is formed, covering the first insulating layer and the epitaxial layer;

[0025] A first slot and a second slot spaced apart from each other are formed in the second insulating layer, wherein the first slot exposes the first insulating layer and the second slot exposes the epitaxial layer; a metal layer is formed in the first slot; and a well region is formed in the second slot, the well region having a second doping type opposite to the first doping type.

[0026] Furthermore, the method for manufacturing the semiconductor structure also includes forming a first electrode electrically connected to the well region; forming a second electrode electrically connected to the metal layer; and forming a third electrode electrically connected to the substrate.

[0027] In a fourth aspect, the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0028] An epitaxial layer is formed on a substrate, the epitaxial layer having a first doping type; an insulating layer is formed on the epitaxial layer; a first trench and a second trench spaced apart from each other are formed in the insulating layer, wherein the first trench does not penetrate the insulating layer, and the second trench penetrates the insulating layer to expose the epitaxial layer; a metal layer is formed in the first trench; a well region is formed in the second trench, the well region having a second doping type opposite to the first doping type; a first electrode is formed and electrically connected to the well region; a second electrode is formed and electrically connected to the metal layer; and a third electrode is formed and electrically connected to the substrate.

[0029] The above-described technical solutions of the present invention have at least one or more of the following beneficial effects:

[0030] In the technical solution of this invention, a portion of the second insulating layer, the metal layer, and the well region form a capacitor. By using the well region and the metal layer as the two plates of the capacitor, the charge amount of the capacitor plates can be changed by applying a voltage to the second electrode, thereby adjusting the carrier concentration in the well region and thus adjusting the PN junction width between the well region and the epitaxial layer. This allows for adjustment of the capacitance of the varactor diode, which includes the PN junction formed by the well region and the epitaxial layer, thereby broadening the capacitance control range of the varactor diode.

[0031] This invention utilizes a metal-constructed parallel-plate capacitor to regulate the carrier distribution in the well region, thereby reducing voltage loss applied to the capacitor terminals.

[0032] The preparation process of this invention is not only less difficult but also relatively simple, and can significantly reduce the adverse effects that high-concentration ion implantation may have on the substrate and dielectric layer.

[0033] In this invention, the capacitance value of the capacitor can also be precisely controlled by adjusting the spacing between the metal layer and the well region. Attached Figure Description

[0034] The disclosure of this invention will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this invention. Furthermore, similar numbers in the drawings are used to denote similar components, wherein:

[0035] Figure 1 This is a schematic diagram of the main structure of a semiconductor structure according to an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the main structure of a semiconductor structure prepared according to another embodiment of the present invention;

[0037] Figure 3 Is it like this? Figure 1 A schematic diagram of the main process flow for manufacturing the semiconductor structure shown.

[0038] Figures 4-7 Is it like this? Figure 3 A schematic diagram of the structural cross-sections corresponding to the key steps in the flowchart shown.

[0039] Figure 8 Is it like this? Figure 1 A schematic diagram of the main process flow for manufacturing the semiconductor structure shown.

[0040] Figures 9-12 Is it like this? Figure 8 A schematic diagram of the structural cross-sections corresponding to the key steps in the flowchart shown.

[0041] Figure 13 This is a schematic diagram of the main structure of a semiconductor structure according to one embodiment;

[0042] Figure 14 This is a top view schematic diagram of a semiconductor structure according to one embodiment;

[0043] Figure 15 This is a top view schematic diagram of a semiconductor structure according to one embodiment.

[0044] List of reference numerals :

[0045] 1: Substrate; 2: Epitaxial layer; 3: First insulating layer; 4: Second insulating layer; 5: Metal layer; 6: Well region; 7: Third insulating layer; 8: First via; 9: Second via; 10: First electrode; 11: Second electrode; 12: Third electrode; 4-1: First slot; 4-2: Second slot. Detailed Implementation

[0046] Some embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0047] Currently, the reverse-biased PN junction width of PN junction functional regions and their derived devices (such as the varactor diodes mentioned in the background section) remains fixed due to fixed ion implantation conditions. If the application requirements do not match the characteristics of the current devices, the reverse-biased PN junction width can only be adjusted by changing the carrier concentration during ion implantation. Increasing the ion implantation concentration not only increases the requirements on the equipment but also requires avoiding residual problems caused by accelerated hardening of the photoresist after high-concentration ion implantation. Existing technologies suffer from problems such as a limited adjustable range for the PN junction width and voltage loss.

[0048] To address the problems of the prior art, this invention proposes a novel semiconductor structure. In this invention, a capacitor is formed by a metal layer 5, a well region 6, and an insulating material between the metal layer 5 and the well region 6. By using the well region 6 as one of the capacitor plates, the charge on the capacitor plate can be changed by applying a voltage to the second electrode 11, thereby adjusting the carrier concentration in the well region 6 and thus adjusting the width of the PN junction between the well region 6 and the epitaxial layer 2. Consequently, the capacitance of the varactor diode, which includes the PN junction formed by the well region 6 and the epitaxial layer 2, can be adjusted, thereby broadening the capacitance control range of the varactor diode.

[0049] The specific semiconductor structure will be explained in detail below.

[0050] Reference Figure 1 The present invention relates to a semiconductor structure, comprising: a substrate 1, an epitaxial layer 2, a first insulating layer 3, a second insulating layer 4, a metal layer 5, a well region 6, a first electrode 10, a second electrode 11, and a third electrode 12.

[0051] The following explains the location and structural characteristics of each component.

[0052] Epitaxial layer 2 is located on substrate 1 (the upper surface in the figure) and has a first doping type. The first doping type is selected from either P-type doping or N-type doping.

[0053] The first insulating layer 3 is located on the epitaxial layer 2. In one embodiment, the first insulating layer 3 is formed by first forming and patterning a first insulating material.

[0054] The second insulating layer 4 is located on the epitaxial layer 2 and the first insulating layer 3. In this embodiment, the second insulating layer 4 and the first insulating layer 3 are made of different materials. In one embodiment, the second insulating layer 4 is made of a material with a dielectric constant ε greater than 4, such as HfO2, ZrO2, or SiON.

[0055] The first slot 4-1 and the second slot 4-2 are located in the second insulating layer 4 and are laterally spaced apart from each other. The first slot 4-1 exposes the first insulating layer 3, which is formed separately from the second insulating layer 4. The second slot 4-2 exposes the epitaxial layer 2.

[0056] The metal layer 5 is located on the first insulating layer 3 in the first slot. That is, the metal layer 5 fills the first slot and is separated from the epitaxial layer 2 by the first insulating layer 3. In one embodiment, the metal layer 5 is made of copper, aluminum or tungsten.

[0057] Well region 6 is located in the second trench and has a second doping type opposite to the first doping type. Well region 6 is in contact with epitaxial layer 2 to form a PN junction.

[0058] The first electrode 10 is in electrical contact with the well region 6; the second electrode 11 is in electrical contact with the metal layer 5; and the third electrode 12 is in electrical contact with the substrate 1.

[0059] The following describes the dimensional design of the main layer structure in this invention.

[0060] In one embodiment, the deposition height of the well region 6 is set within the range of 100 angstroms to 4000 angstroms. On the one hand, this ensures that the equipment used can meet the minimum time constraints required to complete this process. On the other hand, this deposition height range also meets the diffusion depth requirements typically required after ion implantation and activation, thereby ensuring the stability and reliability of device performance.

[0061] In one embodiment, the total height of the metal layer 5 and the first insulating layer 3 is approximately equal to the deposition height of the well region 6. In one embodiment, the top surfaces of the metal layer 5, the well region 6, and the second insulating layer 4 are flush with each other. In one embodiment, the spacing between the first insulating layer 3 and the well region 6 is the same as the spacing between the metal layer 5 and the well region 6.

[0062] In one embodiment, the spacing between the well region 6 and the metal layer 5 is set between 50 angstroms and 1000 angstroms.

[0063] In one embodiment, the material of the first insulating layer 3 may be SiO2, HfO2, or zirconium oxide.

[0064] In one embodiment, since the first insulating layer 3 serves as an insulator, the projected area of ​​the first insulating layer 3 on the substrate 1 is equal to or slightly larger than the projected area of ​​the metal layer 5 on the substrate 1.

[0065] The following embodiment illustrates the specific structure of the electrical contact between the first electrode 10 and the well region 6, and the electrical contact between the second electrode 11 and the metal layer 5. In this embodiment, the semiconductor structure further includes a third insulating layer 7, a first via 8, and a second via 9.

[0066] Both the first via 8 and the second via 9 are disposed within the third insulating layer 7. The third insulating layer 7 covers the metal layer 5, the well region 6, and the exposed second insulating layer 4. In one embodiment, the third insulating layer 7 is made of a material with a dielectric constant ε greater than 4, such as HfO2, ZrO2, or SiON. In another embodiment, the third insulating layer 7 and the second insulating layer 4 can be made of the same material.

[0067] The first through-hole 8 is electrically contacted with the first electrode 10 and the well region 6, respectively, thus electrically connecting the first electrode and the well region. The second through-hole 9 is electrically contacted with the second electrode 11 and the metal layer 5, respectively, thus electrically connecting the second electrode and the metal layer. The first through-hole 8 and the second through-hole 9 can be formed by creating through slots in the third insulating layer 7 and filling the slots with electrical contact material. The contact material can be a conventional material, such as tungsten or copper.

[0068] The third electrode 12 is in electrical contact with the substrate 1. In the specific example shown in the figure, the third electrode 12 is formed on the lower surface of the substrate 1.

[0069] The semiconductor structure of this invention can broaden the capacitance control range of the varactor diode. For example, when the doping type of the well region 6 is N-type, when a positive bias voltage is applied to the second electrode 11 and the positive bias voltage increases, electrons in the well region 6 will gather towards the second electrode 11 (i.e., gather upwards), and the PN junction formed between the well region 6 and the epitaxial layer 2 will be broadened, thus reducing the capacitance of the varactor diode.

[0070] By applying different voltages to the second electrode 11, the present invention changes the number of charge carriers stored in the capacitor structure consisting of the metal layer 5, the well region 6, and the insulating material between them, thereby controlling the distribution of charge carriers in the well region 6 structure and adjusting the width of the PN junction formed between the well region 6 and the epitaxial layer 2.

[0071] pass Figure 1The semiconductor structure shown illustrates that this invention uses the well region and the metal layer as the two plates of a capacitor, respectively. The metal layer 5 and the well region 6 are formed above the epitaxial layer 2, but not within it. Specifically, both are disposed within the second insulating layer 4, and the metal layer 5 and the well region 6 are separated by a portion of the second insulating layer 4. This design maintains a certain distance between the metal layer 5 in the first slot 4-1 and the well region 6 in the second slot 4-2. Compared to the conventional method of forming the dielectric layer of a capacitor through deposition or oxidation, the innovation of this invention lies in creating two slots with a certain spacing in the second insulating layer 4 to define the length of the dielectric layer between the two plates of the capacitor. This spacing can be controlled by photolithography. Compared to the gate oxide layer control scheme of MOS varactor diodes, this design allows for more precise control of the portion of the second insulating layer 4 between the metal layer 5 and the well region 6, i.e., more precise control of the length of the capacitor's dielectric layer. By precisely controlling the length of the portion of dielectric layer 4 located between metal layer 5 and well region 6, the capacitance value of the capacitor composed of metal layer 5, well region 6, and the insulating material between them can be further adjusted. This adjustment can improve the precision of carrier distribution control in well region 6, thereby significantly improving the performance of the entire semiconductor device.

[0072] Unlike existing technologies that use semiconductor-doped structures to form the electrodes of parallel-plate capacitors, this invention utilizes a metal-constructed plate of the parallel-plate capacitor to adjust the carrier distribution in the well region, thereby reducing voltage loss at the capacitor terminals. The high electron density and gapless band structure of metals determine their efficient and stable conductivity, allowing the applied voltage to be applied to the target structure with almost no loss. Furthermore, since metals conduct electricity via electrons at extremely high concentrations, trace impurity atoms mixed into the metal lattice cause very little interference to the overall free electron flow, making it difficult to significantly change the overall resistivity of the metal. Semiconductors, on the other hand, conduct electricity via doped ions, and the doping concentration is limited. Therefore, using a metal instead of a semiconductor-doped structure as the capacitor plate effectively avoids the impact of trace impurities on conductivity, thus using a metal to replace the semiconductor-doped structure improves energy utilization.

[0073] Furthermore, the use of a high dielectric constant material in this invention can improve the intrinsic breakdown voltage of the capacitor, thereby achieving a higher capacitance regulation capability in varactor diodes. Under the same voltage, a high-ε material can control a larger number of charges, indirectly improving the material's breakdown voltage characteristics.

[0074] In addition, in such Figure 2 In another embodiment shown, with Figure 1The difference in the illustrated embodiment is that the first insulating layer and the second insulating layer are made of the same material and are integrally formed. In actual processing, an insulating material can be formed, and then two slots can be formed using two masks. When forming the first slot, a certain thickness of insulating material is left as the first insulating layer by controlling the etching time, which will be described in detail in the subsequent process method description.

[0075] The present invention also provides a wafer comprising: a plurality of semiconductor structures as described above, wherein the plurality of semiconductor structures are arranged in an array.

[0076] The present invention also provides that the present invention Figure 1 or Figure 2 The fabrication method of the semiconductor structure shown is first introduced. Figure 1 The method for preparing the structure shown.

[0077] Reference Figure 3 The present invention also provides a method for manufacturing a semiconductor structure, comprising:

[0078] S30. An epitaxial layer 2 is formed on the substrate 1, the epitaxial layer 2 having a first doping type. In one embodiment, such as Figure 4 As shown, the first doping type is selected from either P-type doping or N-type doping.

[0079] S31. A first insulating layer 3 is formed on the epitaxial layer 2. In one embodiment, a first insulating material is first formed on the epitaxial layer 2, and then the first insulating material is patterned to form the first insulating layer 3, such as... Figure 4 As shown.

[0080] S32. A second insulating layer 4 is formed, which covers the first insulating layer 3 and the epitaxial layer. In this embodiment, the second insulating layer 4 and the first insulating layer 3 are formed of different materials. In one embodiment, the second insulating layer 4 is made of a material with a dielectric constant ε greater than 4, such as HfO2, ZrO2, or SiON.

[0081] S33. A first slot 4-1 and a second slot 4-2 spaced apart from each other are formed in the second insulating layer 4, wherein the first slot 4-1 exposes the first insulating layer 3 and the second slot 4-2 exposes the epitaxial layer 2.

[0082] S34. A metal layer 5 is formed in the first slot 4-1, see Figure 5 .

[0083] S35, a well region 6 is formed in the second slot 4-2, the well region 6 having a second doping type opposite to the first doping type, see Figure 5 .

[0084] It should be noted that the formation order of S34 and S35 is not fixed, and the metal layer 5 can also be formed after the formation of the trap region 6.

[0085] The top surfaces of the formed trap region 6, metal layer 5, and second insulating layer 4 can be flush with each other.

[0086] In one embodiment, the metal layer 5 is made of copper, aluminum, or tungsten.

[0087] In one embodiment, for distinction, the epitaxial layer 2 is named the first epitaxial layer. The well region 6 is formed in the second trench 4-2 by first growing the second epitaxial layer using an epitaxial process, and then using an ion implantation method to implant dopants using high-energy ions.

[0088] S36. A third insulating layer 7 is formed, which covers the metal layer 5, the well region 6, and the second insulating layer 4. See below. Figure 6 .

[0089] In one embodiment, the third insulating layer 7 is made of a material with a dielectric constant ε greater than 4, such as HfO2, ZrO2, or SiON. In another embodiment, the third insulating layer 7 is made of the same material as the second insulating layer 4.

[0090] S37, forming the first through-hole 8 and the second through-hole 9. In one embodiment, such as Figure 7 As shown, firstly, a first through-hole and a second through-hole are formed in the third insulating layer, exposing the well region 6 and the metal layer 5, respectively. Next, the first through-hole and the second through-hole are filled with a first contact material and a second contact material, respectively, thereby forming a first through-hole and a second through-hole, as shown. Figure 1 As shown. Conventional materials such as tungsten and copper can be used for contact.

[0091] S38. Forming a first electrode, a second electrode, and a third electrode. Specifically, the first electrode 10 is formed and electrically connected to the well region, the second electrode is formed and electrically connected to the metal layer, and the third electrode is formed and electrically connected to the substrate. The first electrode 10, the second electrode 11, and the third electrode 12 are in electrical contact with the first contact material, the second contact material, and the substrate 1, respectively. Thus, the first via 8 is in electrical contact with the first electrode 10 and the well region 6, and the second via 9 is in electrical contact with the second electrode 11 and the metal layer 5, respectively. See [link to documentation]. Figure 1 .

[0092] The following explanation Figure 2 The preparation method of the structure shown is as follows: Figure 8 The present invention also provides a method for manufacturing a semiconductor structure, comprising:

[0093] S80, an epitaxial layer 2 is formed on substrate 1, the epitaxial layer 2 having a first doping type.

[0094] S81, an insulating layer is formed on the epitaxial layer 2.

[0095] S82, a first slot 4-1 and a second slot 4-2 spaced apart from each other are formed in the insulating layer. The first slot 4-1 does not penetrate the insulating layer, while the second slot 4-2 penetrates the insulating layer, exposing the epitaxial layer. A material layer of a predetermined thickness is retained in the first slot 4-1, see... Figure 9 In this process, the process can be controlled, such as controlling the etching time, preventing direct etching to the bottom, so that an insulating layer of a certain thickness remains on the top surface of epitaxial layer 2. Figure 3 Compared to the method shown, this reduces the number of film deposition steps. The second groove 4-2 exposes the epitaxial layer 2, wherein the insulating layer outside the groove constitutes the second insulating layer 4, and the portion of the insulating layer below the first groove 4-1 constitutes the first insulating layer 3.

[0096] S83, a metal layer 5 is formed in the first slot 4-1.

[0097] S84, a well region 6 is formed in the second slot 4-2, the well region 6 having a second doping type opposite to the first doping type, as shown in the reference. Figure 10 .

[0098] S85, forming a third insulating layer 7, the third insulating layer 7 covering the metal layer 5, the well region 6 and the second insulating layer 4.

[0099] S86, forming the first through-hole 8 and the second through-hole 9. In one embodiment, as follows: Figure 11 As shown, firstly, a first through-hole and a second through-hole are formed in the third insulating layer, exposing the well region 6 and the metal layer 5, respectively. Next, the first through-hole and the second through-hole are filled with a first contact material and a second contact material, respectively, thereby forming a first through-hole and a second through-hole, as shown. Figure 12 As shown. Conventional materials such as tungsten and copper can be used for contact.

[0100] S87, forming the first electrode 10 to the third electrode 12. The first electrode 10 to the third electrode 12 are in electrical contact with the first contact material, the second contact material, and the substrate 1, respectively. Thus, the first via 8 is in electrical contact with the first electrode 10 and the well region 6, and the second via 9 is in electrical contact with the second electrode 11 and the metal layer 5, respectively. Therefore, the first electrode 10 is electrically connected to the well region 6, the second electrode 11 is electrically connected to the metal layer 5, and the third electrode 12 is electrically connected to the substrate 1. (See...) Figure 2 .

[0101] In one embodiment, refer to Figures 13-14The diagram illustrates an example where the metal layer 5 is ring-shaped, meaning it surrounds the well region 6 in a top view. This distribution significantly increases the area occupied by the metal layer. Along with this increase in area, the capacitance also increases, resulting in stronger regulation capability. It should be noted that a ring-shaped metal layer differs from a single-sided metal layer (…). Figure 1 and 2 Compared to other methods, the effect is more pronounced in regulating carrier distribution. This is because, under the same applied voltage, the toroidal metal layer can regulate more charge, resulting in superior electrical performance of the entire structure.

[0102] In another embodiment, refer to Figure 15 This shows that the metal layer 5 is located in the center, while four unconnected well areas 6 are arranged around it. This design layout is different from a single-sided structure (such as...). Figure 1 and 2 Unlike traditional single-sided structures, where one metal layer 5 typically corresponds to one well region 6 in a one-to-one relationship, this embodiment uses one metal layer 5 to control four well regions 6, breaking the traditional design of one metal layer 5 paired with one well region 6. Because the area of ​​the metal plate is relatively large, its capacitance value also increases accordingly, resulting in a wider control range.

[0103] Specifically, this embodiment successfully reduces the amount of metal required by using a single metal layer 5 to control four well regions 6. Traditionally, four metal layers correspond to four well regions 6, but this embodiment achieves a 1:4 ratio, significantly reducing the amount of metal material while improving overall integration. Furthermore, increasing the surface area of ​​the capacitors further enhances device integration. The core of this approach lies in using a single metal layer 5 to control multiple well regions 6, thereby achieving more efficient space utilization. This allows for more transistors to be accommodated within a limited chip area, significantly improving functional density and overall performance per unit area. This design not only saves material costs but also provides new ideas for the development of future semiconductor devices with higher integration levels.

[0104] It should be noted that the number of metal layers 5 and well regions 6 can be set as needed, and the distribution is not limited to the two embodiments described above.

[0105] In current technology, the construction of semiconductor structures with adjustable PN junction widths typically employs a gate oxide (GOX) scheme. A typical GOX semiconductor structure is used for comparison, in which the well region extends into the epitaxial layer, defining at least one well island within the well region. The doped region is then positioned within a U-shaped deep trench. An isolation layer, at least partially located between the well region and the doped region, separates them. A channel region, inversely shaped to the well region, is formed within each well island, adjacent to the isolation layer and in contact with the epitaxial layer. Fabrication requires two ion implantations: one in the well region and another in the doped region.

[0106] However, this approach has some drawbacks, such as the deep trench structure, multiple ion implantation processes, and insufficient stability of the dielectric layer. The novel semiconductor structure proposed in this invention effectively solves these problems. To more clearly illustrate the superiority of this invention, its innovative points and improvements are detailed as a comparative example.

[0107] 1. Improvement of deep trench structure

[0108] To meet the increasing integration requirements of miniaturized devices in certain applications, deep trench structures, as described above in semiconductor architectures, are commonly employed. However, the high aspect ratio of these trenches significantly increases the difficulty of chemical vapor deposition (CVD) when filling them with material. This can sometimes lead to incomplete material filling and voids within the trenches. Furthermore, the diffusion of precursor gases is difficult to precisely control during CVD. This invention constructs a specific semiconductor structure by creating at least two trenches within an insulating layer. A metal layer 5 is formed in one trench, and a well region 6 is formed in the other. This significantly reduces the difficulty of electroplating and PVD deposition compared to depositing multiple different materials within the trenches.

[0109] 2. Improvements to the multiple ion implantation process

[0110] In the semiconductor structures described above in the prior art, two ion implantations are employed: one in the doped region and the other in the well region. Simply put, ion implantation in the doped region involves implanting heteroatoms to impart conductivity to the doped region. In this invention, the doped region is a metal layer 5, which already possesses conductivity without requiring ion implantation. This invention uses only one ion implantation step when forming the well region, thus reducing the number of ion implantation steps.

[0111] Ion implantation uses high-energy plasma to bombard the wafer, which inevitably causes damage to the wafer. Even during photolithography, some areas will be damaged due to excessive exposure. Therefore, ion implantation should be minimized to reduce damage to the wafer surface.

[0112] This invention effectively reduces the negative impact of such damage by minimizing the ion implantation step during the fabrication process. Therefore, the fabrication process of this invention is not only less complex but also relatively simple, significantly reducing the potential adverse effects of high-concentration ion implantation on the substrate.

[0113] 3. Improvement of insufficient stability of the dielectric layer

[0114] In the aforementioned prior art semiconductor structure, the U-shaped isolation layer is a dielectric layer, which is a very thin and fine U-shaped structure. This structure has significant problems, which are analyzed in detail below:

[0115] 3.1 In the comparison scheme, due to the shape of the trench, it is difficult to guarantee the consistency of the dielectric layer in terms of thickness and quality when growing multilayer dielectric layers.

[0116] 3.2 The U-shaped isolation layer formed to accommodate the deep trench structure inevitably results in some heteroatoms being implanted into the dielectric layer during ion implantation. This weakens the insulation of the dielectric layer and limits the application scenarios of the device. Therefore, ion implantation weakens the breakdown voltage withstand capability of the dielectric layer.

[0117] This invention uses a metallic material, and the metal layer 5 can be prepared by electroplating, which has almost no impact on the intrinsic material. The withstand voltage depends on the thickness of the epitaxial layer 2; increasing the thickness of the epitaxial layer 2 can improve the withstand voltage. Thus, since this invention does not have a thin dielectric layer around the doped region and does not require ion implantation, damage to the dielectric layer can be reduced.

[0118] In summary, the semiconductor structure in the aforementioned prior art presents additional challenges in the actual process flow due to the proximity of the well region to the dielectric layer. Particularly in the photolithography step, limitations in photolithography precision prevent ensuring the process is confined to the specific well region. Consequently, a certain amount of heteroatoms is implanted into the dielectric layer, reducing its voltage withstand capability. Furthermore, the boundary of the photoresist is difficult to perfectly align with the wiring between the dielectric layer and the well region.

[0119] The method of this invention does not rely on precise control of the dielectric layer thickness (gate oxide control scheme), but proposes a simpler and more precise control method. Specifically, in the early stages of capacitor design, the capacitance value is precisely controlled by adjusting the spacing between the first slot 4-1 and the second slot 4-2 using techniques such as photolithography. In the actual fabrication process, this invention utilizes the capabilities of a photolithography machine to achieve precise control of the capacitor capacitance value by adjusting the device spacing designed on the photomask. That is, different slot spacings can be designed during the design phase, resulting in products with different control capabilities. Under the same voltage applied to the second electrode 11, different distances between the metal layer 5 and the well region 6 will cause changes in their ability to attract or repel charge carriers, thus affecting the ability to regulate the charge carrier distribution. In other words, when the spacing between the first slot 4-1 and the second slot 4-2 is large, or when the spacing between the metal layer 5 and the well region 6 is large, the control of the charge carrier distribution will be more refined under the same voltage conditions; while when these spacings are small, the control of the charge carrier distribution is relatively coarse. Compared to traditional methods that rely on dielectric layer thickness control, this method offers significant improvements in accuracy and controllability, addressing potential uncertainties and uncontrollable factors.

[0120] It should be noted that although the steps in the above embodiments are described in a specific order, those skilled in the art will understand that in order to achieve the effects of the present invention, different steps do not necessarily have to be executed in such an order. They can be executed simultaneously (in parallel) or in other orders, and these variations are all within the scope of protection of the present invention.

[0121] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; An epitaxial layer, located on the substrate and having a first doping type; A first insulating layer is located on the epitaxial layer; A second insulating layer is located on the epitaxial layer; A first slot and a second slot are located in the second insulating layer and are laterally spaced apart from each other, wherein the first slot exposes the first insulating layer and the second slot exposes the epitaxial layer; A metal layer is located in the first slot; A well region, located in the second slot, has a second doping type opposite to the first doping type.

2. The semiconductor structure according to claim 1, characterized in that, There is a boundary between the first insulating layer and the second insulating layer, or the first insulating layer and the second insulating layer are an integral continuous structure.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure Also includes: The first electrode is in electrical contact with the well region; The second electrode is in electrical contact with the metal layer; The third electrode is in electrical contact with the substrate.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: A third insulating layer covers the metal layer, the well region, and the second insulating layer; A first via is provided in the third insulating layer to electrically connect the first electrode and the well region. A second through-hole is provided in the third insulating layer to electrically connect the second electrode and the metal layer.

5. The semiconductor structure according to claim 3, characterized in that, The epitaxial layer is formed on the first surface of the substrate, and the third electrode is located on the second surface of the substrate, the second surface being opposite to the first surface.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The metal layer is annular and surrounds the well region.

7. The semiconductor structure according to any one of claims 1-5, characterized in that, The well region comprises a plurality of well regions that are insulated from each other, the plurality of well regions surrounding the metal layer.

8. A wafer, characterized in that, include: A plurality of semiconductor structures as described in any one of claims 1 to 7, wherein the plurality of semiconductor structures are arranged in an array.

9. A method for manufacturing a semiconductor structure, characterized in that, include: An epitaxial layer is formed on a substrate, the epitaxial layer having a first doping type; A first insulating layer is formed on the epitaxial layer; A second insulating layer is formed, covering the first insulating layer and the epitaxial layer; A first slot and a second slot spaced apart from each other are formed in the second insulating layer, wherein the first slot exposes the first insulating layer and the second slot exposes the epitaxial layer; A metal layer is formed in the first slot; A well region is formed in the second slot, the well region having a second doping type opposite to the first doping type.

10. A method for manufacturing a semiconductor structure, characterized in that, include: An epitaxial layer is formed on a substrate, the epitaxial layer having a first doping type; An insulating layer is formed on the epitaxial layer; A first slot and a second slot are formed in the insulating layer, spaced apart from each other, wherein the first slot does not penetrate the insulating layer, and the second slot penetrates the insulating layer to expose the epitaxial layer; A metal layer is formed in the first slot; A well region is formed in the second slot, the well region having a second doping type opposite to the first doping type.

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